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69c60c88 | 1 | #include <linux/export.h> |
1da177e4 | 2 | #include <linux/bitops.h> |
5cdd174f | 3 | #include <linux/elf.h> |
1da177e4 | 4 | #include <linux/mm.h> |
8d71a2ea | 5 | |
8bdbd962 | 6 | #include <linux/io.h> |
c98fdeaa | 7 | #include <linux/sched.h> |
e6017571 | 8 | #include <linux/sched/clock.h> |
4e26d11f | 9 | #include <linux/random.h> |
1da177e4 | 10 | #include <asm/processor.h> |
d3f7eae1 | 11 | #include <asm/apic.h> |
1f442d70 | 12 | #include <asm/cpu.h> |
26bfa5f8 | 13 | #include <asm/smp.h> |
42937e81 | 14 | #include <asm/pci-direct.h> |
b466bdb6 | 15 | #include <asm/delay.h> |
1da177e4 | 16 | |
8d71a2ea | 17 | #ifdef CONFIG_X86_64 |
8d71a2ea | 18 | # include <asm/mmconfig.h> |
d1163651 | 19 | # include <asm/set_memory.h> |
8d71a2ea YL |
20 | #endif |
21 | ||
1da177e4 LT |
22 | #include "cpu.h" |
23 | ||
3344ed30 TG |
24 | static const int amd_erratum_383[]; |
25 | static const int amd_erratum_400[]; | |
26 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); | |
27 | ||
cc2749e4 AG |
28 | /* |
29 | * nodes_per_socket: Stores the number of nodes per socket. | |
30 | * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX | |
31 | * Node Identifiers[10:8] | |
32 | */ | |
33 | static u32 nodes_per_socket = 1; | |
34 | ||
2c929ce6 BP |
35 | static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) |
36 | { | |
2c929ce6 BP |
37 | u32 gprs[8] = { 0 }; |
38 | int err; | |
39 | ||
682469a5 BP |
40 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
41 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
42 | |
43 | gprs[1] = msr; | |
44 | gprs[7] = 0x9c5a203a; | |
45 | ||
46 | err = rdmsr_safe_regs(gprs); | |
47 | ||
48 | *p = gprs[0] | ((u64)gprs[2] << 32); | |
49 | ||
50 | return err; | |
51 | } | |
52 | ||
53 | static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) | |
54 | { | |
2c929ce6 BP |
55 | u32 gprs[8] = { 0 }; |
56 | ||
682469a5 BP |
57 | WARN_ONCE((boot_cpu_data.x86 != 0xf), |
58 | "%s should only be used on K8!\n", __func__); | |
2c929ce6 BP |
59 | |
60 | gprs[0] = (u32)val; | |
61 | gprs[1] = msr; | |
62 | gprs[2] = val >> 32; | |
63 | gprs[7] = 0x9c5a203a; | |
64 | ||
65 | return wrmsr_safe_regs(gprs); | |
66 | } | |
67 | ||
1da177e4 LT |
68 | /* |
69 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause | |
70 | * misexecution of code under Linux. Owners of such processors should | |
71 | * contact AMD for precise details and a CPU swap. | |
72 | * | |
73 | * See http://www.multimania.com/poulot/k6bug.html | |
d7de8649 AH |
74 | * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" |
75 | * (Publication # 21266 Issue Date: August 1998) | |
1da177e4 LT |
76 | * |
77 | * The following test is erm.. interesting. AMD neglected to up | |
78 | * the chip setting when fixing the bug but they also tweaked some | |
79 | * performance at the same time.. | |
80 | */ | |
fb87a298 | 81 | |
277d5b40 | 82 | extern __visible void vide(void); |
de642faf JP |
83 | __asm__(".globl vide\n" |
84 | ".type vide, @function\n" | |
85 | ".align 4\n" | |
86 | "vide: ret\n"); | |
1da177e4 | 87 | |
148f9bb8 | 88 | static void init_amd_k5(struct cpuinfo_x86 *c) |
11fdd252 | 89 | { |
26bfa5f8 | 90 | #ifdef CONFIG_X86_32 |
11fdd252 YL |
91 | /* |
92 | * General Systems BIOSen alias the cpu frequency registers | |
6a6256f9 | 93 | * of the Elan at 0x000df000. Unfortunately, one of the Linux |
11fdd252 YL |
94 | * drivers subsequently pokes it, and changes the CPU speed. |
95 | * Workaround : Remove the unneeded alias. | |
96 | */ | |
97 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ | |
98 | #define CBAR_ENB (0x80000000) | |
99 | #define CBAR_KEY (0X000000CB) | |
100 | if (c->x86_model == 9 || c->x86_model == 10) { | |
8bdbd962 AC |
101 | if (inl(CBAR) & CBAR_ENB) |
102 | outl(0 | CBAR_KEY, CBAR); | |
11fdd252 | 103 | } |
26bfa5f8 | 104 | #endif |
11fdd252 YL |
105 | } |
106 | ||
148f9bb8 | 107 | static void init_amd_k6(struct cpuinfo_x86 *c) |
11fdd252 | 108 | { |
26bfa5f8 | 109 | #ifdef CONFIG_X86_32 |
11fdd252 | 110 | u32 l, h; |
46a84132 | 111 | int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); |
11fdd252 YL |
112 | |
113 | if (c->x86_model < 6) { | |
114 | /* Based on AMD doc 20734R - June 2000 */ | |
115 | if (c->x86_model == 0) { | |
116 | clear_cpu_cap(c, X86_FEATURE_APIC); | |
117 | set_cpu_cap(c, X86_FEATURE_PGE); | |
118 | } | |
119 | return; | |
120 | } | |
121 | ||
122 | if (c->x86_model == 6 && c->x86_mask == 1) { | |
123 | const int K6_BUG_LOOP = 1000000; | |
124 | int n; | |
125 | void (*f_vide)(void); | |
37963666 | 126 | u64 d, d2; |
11fdd252 | 127 | |
1b74dde7 | 128 | pr_info("AMD K6 stepping B detected - "); |
11fdd252 YL |
129 | |
130 | /* | |
131 | * It looks like AMD fixed the 2.6.2 bug and improved indirect | |
132 | * calls at the same time. | |
133 | */ | |
134 | ||
135 | n = K6_BUG_LOOP; | |
136 | f_vide = vide; | |
5f8a1615 | 137 | OPTIMIZER_HIDE_VAR(f_vide); |
4ea1636b | 138 | d = rdtsc(); |
11fdd252 YL |
139 | while (n--) |
140 | f_vide(); | |
4ea1636b | 141 | d2 = rdtsc(); |
11fdd252 YL |
142 | d = d2-d; |
143 | ||
144 | if (d > 20*K6_BUG_LOOP) | |
1b74dde7 | 145 | pr_cont("system stability may be impaired when more than 32 MB are used.\n"); |
11fdd252 | 146 | else |
1b74dde7 | 147 | pr_cont("probably OK (after B9730xxxx).\n"); |
11fdd252 YL |
148 | } |
149 | ||
150 | /* K6 with old style WHCR */ | |
151 | if (c->x86_model < 8 || | |
152 | (c->x86_model == 8 && c->x86_mask < 8)) { | |
153 | /* We can only write allocate on the low 508Mb */ | |
154 | if (mbytes > 508) | |
155 | mbytes = 508; | |
156 | ||
157 | rdmsr(MSR_K6_WHCR, l, h); | |
158 | if ((l&0x0000FFFF) == 0) { | |
159 | unsigned long flags; | |
160 | l = (1<<0)|((mbytes/4)<<1); | |
161 | local_irq_save(flags); | |
162 | wbinvd(); | |
163 | wrmsr(MSR_K6_WHCR, l, h); | |
164 | local_irq_restore(flags); | |
1b74dde7 | 165 | pr_info("Enabling old style K6 write allocation for %d Mb\n", |
11fdd252 YL |
166 | mbytes); |
167 | } | |
168 | return; | |
169 | } | |
170 | ||
171 | if ((c->x86_model == 8 && c->x86_mask > 7) || | |
172 | c->x86_model == 9 || c->x86_model == 13) { | |
173 | /* The more serious chips .. */ | |
174 | ||
175 | if (mbytes > 4092) | |
176 | mbytes = 4092; | |
177 | ||
178 | rdmsr(MSR_K6_WHCR, l, h); | |
179 | if ((l&0xFFFF0000) == 0) { | |
180 | unsigned long flags; | |
181 | l = ((mbytes>>2)<<22)|(1<<16); | |
182 | local_irq_save(flags); | |
183 | wbinvd(); | |
184 | wrmsr(MSR_K6_WHCR, l, h); | |
185 | local_irq_restore(flags); | |
1b74dde7 | 186 | pr_info("Enabling new style K6 write allocation for %d Mb\n", |
11fdd252 YL |
187 | mbytes); |
188 | } | |
189 | ||
190 | return; | |
191 | } | |
192 | ||
193 | if (c->x86_model == 10) { | |
194 | /* AMD Geode LX is model 10 */ | |
195 | /* placeholder for any needed mods */ | |
196 | return; | |
197 | } | |
26bfa5f8 | 198 | #endif |
11fdd252 YL |
199 | } |
200 | ||
26bfa5f8 | 201 | static void init_amd_k7(struct cpuinfo_x86 *c) |
1f442d70 | 202 | { |
26bfa5f8 BP |
203 | #ifdef CONFIG_X86_32 |
204 | u32 l, h; | |
205 | ||
206 | /* | |
207 | * Bit 15 of Athlon specific MSR 15, needs to be 0 | |
208 | * to enable SSE on Palomino/Morgan/Barton CPU's. | |
209 | * If the BIOS didn't enable it already, enable it here. | |
210 | */ | |
211 | if (c->x86_model >= 6 && c->x86_model <= 10) { | |
212 | if (!cpu_has(c, X86_FEATURE_XMM)) { | |
1b74dde7 | 213 | pr_info("Enabling disabled K7/SSE Support.\n"); |
26bfa5f8 BP |
214 | msr_clear_bit(MSR_K7_HWCR, 15); |
215 | set_cpu_cap(c, X86_FEATURE_XMM); | |
216 | } | |
217 | } | |
218 | ||
219 | /* | |
220 | * It's been determined by AMD that Athlons since model 8 stepping 1 | |
221 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx | |
222 | * As per AMD technical note 27212 0.2 | |
223 | */ | |
224 | if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { | |
225 | rdmsr(MSR_K7_CLK_CTL, l, h); | |
226 | if ((l & 0xfff00000) != 0x20000000) { | |
1b74dde7 CY |
227 | pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", |
228 | l, ((l & 0x000fffff)|0x20000000)); | |
26bfa5f8 BP |
229 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
230 | } | |
231 | } | |
232 | ||
233 | set_cpu_cap(c, X86_FEATURE_K7); | |
234 | ||
1f442d70 | 235 | /* calling is from identify_secondary_cpu() ? */ |
f6e9456c | 236 | if (!c->cpu_index) |
1f442d70 YL |
237 | return; |
238 | ||
239 | /* | |
240 | * Certain Athlons might work (for various values of 'work') in SMP | |
241 | * but they are not certified as MP capable. | |
242 | */ | |
243 | /* Athlon 660/661 is valid. */ | |
244 | if ((c->x86_model == 6) && ((c->x86_mask == 0) || | |
245 | (c->x86_mask == 1))) | |
1077c932 | 246 | return; |
1f442d70 YL |
247 | |
248 | /* Duron 670 is valid */ | |
249 | if ((c->x86_model == 7) && (c->x86_mask == 0)) | |
1077c932 | 250 | return; |
1f442d70 YL |
251 | |
252 | /* | |
253 | * Athlon 662, Duron 671, and Athlon >model 7 have capability | |
254 | * bit. It's worth noting that the A5 stepping (662) of some | |
255 | * Athlon XP's have the MP bit set. | |
256 | * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for | |
257 | * more. | |
258 | */ | |
259 | if (((c->x86_model == 6) && (c->x86_mask >= 2)) || | |
260 | ((c->x86_model == 7) && (c->x86_mask >= 1)) || | |
261 | (c->x86_model > 7)) | |
26bfa5f8 | 262 | if (cpu_has(c, X86_FEATURE_MP)) |
1077c932 | 263 | return; |
1f442d70 YL |
264 | |
265 | /* If we get here, not a certified SMP capable AMD system. */ | |
266 | ||
267 | /* | |
268 | * Don't taint if we are running SMP kernel on a single non-MP | |
269 | * approved Athlon | |
270 | */ | |
271 | WARN_ONCE(1, "WARNING: This combination of AMD" | |
7da8b6dd | 272 | " processors is not suitable for SMP.\n"); |
8c90487c | 273 | add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); |
6c62aa4a | 274 | #endif |
26bfa5f8 | 275 | } |
6c62aa4a | 276 | |
645a7919 | 277 | #ifdef CONFIG_NUMA |
bbc9e2f4 TH |
278 | /* |
279 | * To workaround broken NUMA config. Read the comment in | |
280 | * srat_detect_node(). | |
281 | */ | |
148f9bb8 | 282 | static int nearby_node(int apicid) |
6c62aa4a YL |
283 | { |
284 | int i, node; | |
285 | ||
286 | for (i = apicid - 1; i >= 0; i--) { | |
bbc9e2f4 | 287 | node = __apicid_to_node[i]; |
6c62aa4a YL |
288 | if (node != NUMA_NO_NODE && node_online(node)) |
289 | return node; | |
290 | } | |
291 | for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { | |
bbc9e2f4 | 292 | node = __apicid_to_node[i]; |
6c62aa4a YL |
293 | if (node != NUMA_NO_NODE && node_online(node)) |
294 | return node; | |
295 | } | |
296 | return first_node(node_online_map); /* Shouldn't happen */ | |
297 | } | |
298 | #endif | |
11fdd252 | 299 | |
4a376ec3 | 300 | /* |
23588c38 AH |
301 | * Fixup core topology information for |
302 | * (1) AMD multi-node processors | |
303 | * Assumption: Number of cores in each internal node is the same. | |
6057b4d3 | 304 | * (2) AMD processors supporting compute units |
4a376ec3 | 305 | */ |
c8e56d20 | 306 | #ifdef CONFIG_SMP |
148f9bb8 | 307 | static void amd_get_topology(struct cpuinfo_x86 *c) |
4a376ec3 | 308 | { |
23588c38 | 309 | u8 node_id; |
4a376ec3 AH |
310 | int cpu = smp_processor_id(); |
311 | ||
23588c38 | 312 | /* get information required for multi-node processors */ |
362f924b | 313 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
79a8b9aa | 314 | u32 eax, ebx, ecx, edx; |
6057b4d3 | 315 | |
79a8b9aa BP |
316 | cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); |
317 | ||
318 | node_id = ecx & 0xff; | |
319 | smp_num_siblings = ((ebx >> 8) & 0xff) + 1; | |
320 | ||
321 | if (c->x86 == 0x15) | |
322 | c->cu_id = ebx & 0xff; | |
b6a50cdd | 323 | |
08b25963 YG |
324 | if (c->x86 >= 0x17) { |
325 | c->cpu_core_id = ebx & 0xff; | |
326 | ||
327 | if (smp_num_siblings > 1) | |
328 | c->x86_max_cores /= smp_num_siblings; | |
329 | } | |
330 | ||
b6a50cdd YG |
331 | /* |
332 | * We may have multiple LLCs if L3 caches exist, so check if we | |
333 | * have an L3 cache by looking at the L3 cache CPUID leaf. | |
334 | */ | |
335 | if (cpuid_edx(0x80000006)) { | |
336 | if (c->x86 == 0x17) { | |
337 | /* | |
338 | * LLC is at the core complex level. | |
339 | * Core complex id is ApicId[3]. | |
340 | */ | |
341 | per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; | |
342 | } else { | |
343 | /* LLC is at the node level. */ | |
344 | per_cpu(cpu_llc_id, cpu) = node_id; | |
345 | } | |
346 | } | |
23588c38 | 347 | } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { |
6057b4d3 AH |
348 | u64 value; |
349 | ||
23588c38 | 350 | rdmsrl(MSR_FAM10H_NODE_ID, value); |
23588c38 | 351 | node_id = value & 7; |
b6a50cdd YG |
352 | |
353 | per_cpu(cpu_llc_id, cpu) = node_id; | |
23588c38 | 354 | } else |
4a376ec3 AH |
355 | return; |
356 | ||
23588c38 | 357 | /* fixup multi-node processor information */ |
cc2749e4 | 358 | if (nodes_per_socket > 1) { |
d518573d | 359 | u32 cus_per_node; |
6057b4d3 | 360 | |
23588c38 | 361 | set_cpu_cap(c, X86_FEATURE_AMD_DCM); |
ee6825c8 | 362 | cus_per_node = c->x86_max_cores / nodes_per_socket; |
9d260ebc | 363 | |
9e81509e | 364 | /* core id has to be in the [0 .. cores_per_node - 1] range */ |
8196dab4 | 365 | c->cpu_core_id %= cus_per_node; |
23588c38 | 366 | } |
4a376ec3 AH |
367 | } |
368 | #endif | |
369 | ||
11fdd252 | 370 | /* |
aa5e5dc2 | 371 | * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. |
11fdd252 YL |
372 | * Assumes number of cores is a power of two. |
373 | */ | |
148f9bb8 | 374 | static void amd_detect_cmp(struct cpuinfo_x86 *c) |
11fdd252 | 375 | { |
c8e56d20 | 376 | #ifdef CONFIG_SMP |
11fdd252 | 377 | unsigned bits; |
99bd0c0f | 378 | int cpu = smp_processor_id(); |
11fdd252 YL |
379 | |
380 | bits = c->x86_coreid_bits; | |
11fdd252 YL |
381 | /* Low order bits define the core id (index of core in socket) */ |
382 | c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); | |
383 | /* Convert the initial APIC ID into the socket ID */ | |
384 | c->phys_proc_id = c->initial_apicid >> bits; | |
99bd0c0f AH |
385 | /* use socket ID also for last level cache */ |
386 | per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; | |
23588c38 | 387 | amd_get_topology(c); |
11fdd252 YL |
388 | #endif |
389 | } | |
390 | ||
8b84c8df | 391 | u16 amd_get_nb_id(int cpu) |
6a812691 | 392 | { |
8b84c8df | 393 | u16 id = 0; |
6a812691 AH |
394 | #ifdef CONFIG_SMP |
395 | id = per_cpu(cpu_llc_id, cpu); | |
396 | #endif | |
397 | return id; | |
398 | } | |
399 | EXPORT_SYMBOL_GPL(amd_get_nb_id); | |
400 | ||
cc2749e4 AG |
401 | u32 amd_get_nodes_per_socket(void) |
402 | { | |
403 | return nodes_per_socket; | |
404 | } | |
405 | EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); | |
406 | ||
148f9bb8 | 407 | static void srat_detect_node(struct cpuinfo_x86 *c) |
6c62aa4a | 408 | { |
645a7919 | 409 | #ifdef CONFIG_NUMA |
6c62aa4a YL |
410 | int cpu = smp_processor_id(); |
411 | int node; | |
0d96b9ff | 412 | unsigned apicid = c->apicid; |
6c62aa4a | 413 | |
bbc9e2f4 TH |
414 | node = numa_cpu_node(cpu); |
415 | if (node == NUMA_NO_NODE) | |
416 | node = per_cpu(cpu_llc_id, cpu); | |
6c62aa4a | 417 | |
64be4c1c | 418 | /* |
68894632 AH |
419 | * On multi-fabric platform (e.g. Numascale NumaChip) a |
420 | * platform-specific handler needs to be called to fixup some | |
421 | * IDs of the CPU. | |
64be4c1c | 422 | */ |
68894632 | 423 | if (x86_cpuinit.fixup_cpu_id) |
64be4c1c DB |
424 | x86_cpuinit.fixup_cpu_id(c, node); |
425 | ||
6c62aa4a | 426 | if (!node_online(node)) { |
bbc9e2f4 TH |
427 | /* |
428 | * Two possibilities here: | |
429 | * | |
430 | * - The CPU is missing memory and no node was created. In | |
431 | * that case try picking one from a nearby CPU. | |
432 | * | |
433 | * - The APIC IDs differ from the HyperTransport node IDs | |
434 | * which the K8 northbridge parsing fills in. Assume | |
435 | * they are all increased by a constant offset, but in | |
436 | * the same order as the HT nodeids. If that doesn't | |
437 | * result in a usable node fall back to the path for the | |
438 | * previous case. | |
439 | * | |
440 | * This workaround operates directly on the mapping between | |
441 | * APIC ID and NUMA node, assuming certain relationship | |
442 | * between APIC ID, HT node ID and NUMA topology. As going | |
443 | * through CPU mapping may alter the outcome, directly | |
444 | * access __apicid_to_node[]. | |
445 | */ | |
6c62aa4a YL |
446 | int ht_nodeid = c->initial_apicid; |
447 | ||
7030a7e9 | 448 | if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) |
bbc9e2f4 | 449 | node = __apicid_to_node[ht_nodeid]; |
6c62aa4a YL |
450 | /* Pick a nearby node */ |
451 | if (!node_online(node)) | |
452 | node = nearby_node(apicid); | |
453 | } | |
454 | numa_set_node(cpu, node); | |
6c62aa4a YL |
455 | #endif |
456 | } | |
457 | ||
148f9bb8 | 458 | static void early_init_amd_mc(struct cpuinfo_x86 *c) |
11fdd252 | 459 | { |
c8e56d20 | 460 | #ifdef CONFIG_SMP |
11fdd252 YL |
461 | unsigned bits, ecx; |
462 | ||
463 | /* Multi core CPU? */ | |
464 | if (c->extended_cpuid_level < 0x80000008) | |
465 | return; | |
466 | ||
467 | ecx = cpuid_ecx(0x80000008); | |
468 | ||
469 | c->x86_max_cores = (ecx & 0xff) + 1; | |
470 | ||
471 | /* CPU telling us the core id bits shift? */ | |
472 | bits = (ecx >> 12) & 0xF; | |
473 | ||
474 | /* Otherwise recompute */ | |
475 | if (bits == 0) { | |
476 | while ((1 << bits) < c->x86_max_cores) | |
477 | bits++; | |
478 | } | |
479 | ||
480 | c->x86_coreid_bits = bits; | |
481 | #endif | |
482 | } | |
483 | ||
148f9bb8 | 484 | static void bsp_init_amd(struct cpuinfo_x86 *c) |
8fa8b035 | 485 | { |
26bfa5f8 BP |
486 | |
487 | #ifdef CONFIG_X86_64 | |
488 | if (c->x86 >= 0xf) { | |
489 | unsigned long long tseg; | |
490 | ||
491 | /* | |
492 | * Split up direct mapping around the TSEG SMM area. | |
493 | * Don't do it for gbpages because there seems very little | |
494 | * benefit in doing so. | |
495 | */ | |
496 | if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { | |
497 | unsigned long pfn = tseg >> PAGE_SHIFT; | |
498 | ||
1b74dde7 | 499 | pr_debug("tseg: %010llx\n", tseg); |
26bfa5f8 BP |
500 | if (pfn_range_is_mapped(pfn, pfn + 1)) |
501 | set_memory_4k((unsigned long)__va(tseg), 1); | |
502 | } | |
503 | } | |
504 | #endif | |
505 | ||
8fa8b035 BP |
506 | if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { |
507 | ||
508 | if (c->x86 > 0x10 || | |
509 | (c->x86 == 0x10 && c->x86_model >= 0x2)) { | |
510 | u64 val; | |
511 | ||
512 | rdmsrl(MSR_K7_HWCR, val); | |
513 | if (!(val & BIT(24))) | |
1b74dde7 | 514 | pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); |
8fa8b035 BP |
515 | } |
516 | } | |
517 | ||
518 | if (c->x86 == 0x15) { | |
519 | unsigned long upperbit; | |
520 | u32 cpuid, assoc; | |
521 | ||
522 | cpuid = cpuid_edx(0x80000005); | |
523 | assoc = cpuid >> 16 & 0xff; | |
524 | upperbit = ((cpuid >> 24) << 10) / assoc; | |
525 | ||
526 | va_align.mask = (upperbit - 1) & PAGE_MASK; | |
527 | va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; | |
4e26d11f HMG |
528 | |
529 | /* A random value per boot for bit slice [12:upper_bit) */ | |
530 | va_align.bits = get_random_int() & va_align.mask; | |
8fa8b035 | 531 | } |
b466bdb6 HR |
532 | |
533 | if (cpu_has(c, X86_FEATURE_MWAITX)) | |
534 | use_mwaitx_delay(); | |
8dfeae0d HR |
535 | |
536 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { | |
537 | u32 ecx; | |
538 | ||
539 | ecx = cpuid_ecx(0x8000001e); | |
540 | nodes_per_socket = ((ecx >> 8) & 7) + 1; | |
541 | } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { | |
542 | u64 value; | |
543 | ||
544 | rdmsrl(MSR_FAM10H_NODE_ID, value); | |
545 | nodes_per_socket = ((value >> 3) & 7) + 1; | |
546 | } | |
8fa8b035 BP |
547 | } |
548 | ||
148f9bb8 | 549 | static void early_init_amd(struct cpuinfo_x86 *c) |
2b16a235 | 550 | { |
11fdd252 YL |
551 | early_init_amd_mc(c); |
552 | ||
40fb1715 VP |
553 | /* |
554 | * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate | |
555 | * with P/T states and does not stop in deep C-states | |
556 | */ | |
557 | if (c->x86_power & (1 << 8)) { | |
e3224234 | 558 | set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); |
40fb1715 VP |
559 | set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); |
560 | } | |
5fef55fd | 561 | |
01fe03ff HR |
562 | /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ |
563 | if (c->x86_power & BIT(12)) | |
564 | set_cpu_cap(c, X86_FEATURE_ACC_POWER); | |
565 | ||
6c62aa4a YL |
566 | #ifdef CONFIG_X86_64 |
567 | set_cpu_cap(c, X86_FEATURE_SYSCALL32); | |
568 | #else | |
5fef55fd | 569 | /* Set MTRR capability flag if appropriate */ |
6c62aa4a YL |
570 | if (c->x86 == 5) |
571 | if (c->x86_model == 13 || c->x86_model == 9 || | |
572 | (c->x86_model == 8 && c->x86_mask >= 8)) | |
573 | set_cpu_cap(c, X86_FEATURE_K6_MTRR); | |
574 | #endif | |
42937e81 | 575 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) |
b9d16a2a AG |
576 | /* |
577 | * ApicID can always be treated as an 8-bit value for AMD APIC versions | |
578 | * >= 0x10, but even old K8s came out of reset with version 0x10. So, we | |
579 | * can safely set X86_FEATURE_EXTD_APICID unconditionally for families | |
580 | * after 16h. | |
581 | */ | |
425d8c2f BP |
582 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
583 | if (c->x86 > 0x16) | |
42937e81 | 584 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); |
425d8c2f BP |
585 | else if (c->x86 >= 0xf) { |
586 | /* check CPU config space for extended APIC ID */ | |
587 | unsigned int val; | |
588 | ||
589 | val = read_pci_config(0, 24, 0, 0x68); | |
590 | if ((val >> 17 & 0x3) == 0x3) | |
591 | set_cpu_cap(c, X86_FEATURE_EXTD_APICID); | |
592 | } | |
42937e81 AH |
593 | } |
594 | #endif | |
3b564968 | 595 | |
c1118b36 PB |
596 | /* |
597 | * This is only needed to tell the kernel whether to use VMCALL | |
598 | * and VMMCALL. VMMCALL is never executed except under virt, so | |
599 | * we can set it unconditionally. | |
600 | */ | |
601 | set_cpu_cap(c, X86_FEATURE_VMMCALL); | |
602 | ||
3b564968 | 603 | /* F16h erratum 793, CVE-2013-6885 */ |
8f86a737 BP |
604 | if (c->x86 == 0x16 && c->x86_model <= 0xf) |
605 | msr_set_bit(MSR_AMD64_LS_CFG, 15); | |
2b16a235 | 606 | |
3344ed30 TG |
607 | /* |
608 | * Check whether the machine is affected by erratum 400. This is | |
609 | * used to select the proper idle routine and to enable the check | |
610 | * whether the machine is affected in arch_post_acpi_init(), which | |
611 | * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. | |
612 | */ | |
613 | if (cpu_has_amd_erratum(c, amd_erratum_400)) | |
614 | set_cpu_bug(c, X86_BUG_AMD_E400); | |
615 | } | |
e6ee94d5 | 616 | |
26bfa5f8 BP |
617 | static void init_amd_k8(struct cpuinfo_x86 *c) |
618 | { | |
619 | u32 level; | |
620 | u64 value; | |
621 | ||
622 | /* On C+ stepping K8 rep microcode works well for copy/memset */ | |
623 | level = cpuid_eax(1); | |
624 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | |
625 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); | |
626 | ||
627 | /* | |
628 | * Some BIOSes incorrectly force this feature, but only K8 revision D | |
629 | * (model = 0x14) and later actually support it. | |
630 | * (AMD Erratum #110, docId: 25759). | |
631 | */ | |
632 | if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { | |
633 | clear_cpu_cap(c, X86_FEATURE_LAHF_LM); | |
634 | if (!rdmsrl_amd_safe(0xc001100d, &value)) { | |
635 | value &= ~BIT_64(32); | |
636 | wrmsrl_amd_safe(0xc001100d, value); | |
637 | } | |
638 | } | |
639 | ||
640 | if (!c->x86_model_id[0]) | |
641 | strcpy(c->x86_model_id, "Hammer"); | |
6f9b63a0 BP |
642 | |
643 | #ifdef CONFIG_SMP | |
644 | /* | |
645 | * Disable TLB flush filter by setting HWCR.FFDIS on K8 | |
646 | * bit 6 of msr C001_0015 | |
647 | * | |
648 | * Errata 63 for SH-B3 steppings | |
649 | * Errata 122 for all steppings (F+ have it disabled by default) | |
650 | */ | |
651 | msr_set_bit(MSR_K7_HWCR, 6); | |
652 | #endif | |
96e5d28a | 653 | set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); |
26bfa5f8 BP |
654 | } |
655 | ||
656 | static void init_amd_gh(struct cpuinfo_x86 *c) | |
657 | { | |
658 | #ifdef CONFIG_X86_64 | |
659 | /* do this for boot cpu */ | |
660 | if (c == &boot_cpu_data) | |
661 | check_enable_amd_mmconf_dmi(); | |
662 | ||
663 | fam10h_check_enable_mmcfg(); | |
664 | #endif | |
665 | ||
666 | /* | |
667 | * Disable GART TLB Walk Errors on Fam10h. We do this here because this | |
668 | * is always needed when GART is enabled, even in a kernel which has no | |
669 | * MCE support built in. BIOS should disable GartTlbWlk Errors already. | |
670 | * If it doesn't, we do it here as suggested by the BKDG. | |
671 | * | |
672 | * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 | |
673 | */ | |
674 | msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); | |
675 | ||
676 | /* | |
677 | * On family 10h BIOS may not have properly enabled WC+ support, causing | |
678 | * it to be converted to CD memtype. This may result in performance | |
679 | * degradation for certain nested-paging guests. Prevent this conversion | |
680 | * by clearing bit 24 in MSR_AMD64_BU_CFG2. | |
681 | * | |
682 | * NOTE: we want to use the _safe accessors so as not to #GP kvm | |
683 | * guests on older kvm hosts. | |
684 | */ | |
685 | msr_clear_bit(MSR_AMD64_BU_CFG2, 24); | |
686 | ||
687 | if (cpu_has_amd_erratum(c, amd_erratum_383)) | |
688 | set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); | |
689 | } | |
690 | ||
d1992996 EC |
691 | #define MSR_AMD64_DE_CFG 0xC0011029 |
692 | ||
693 | static void init_amd_ln(struct cpuinfo_x86 *c) | |
694 | { | |
695 | /* | |
696 | * Apply erratum 665 fix unconditionally so machines without a BIOS | |
697 | * fix work. | |
698 | */ | |
699 | msr_set_bit(MSR_AMD64_DE_CFG, 31); | |
700 | } | |
701 | ||
26bfa5f8 BP |
702 | static void init_amd_bd(struct cpuinfo_x86 *c) |
703 | { | |
704 | u64 value; | |
705 | ||
706 | /* re-enable TopologyExtensions if switched off by BIOS */ | |
96685a55 | 707 | if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && |
26bfa5f8 BP |
708 | !cpu_has(c, X86_FEATURE_TOPOEXT)) { |
709 | ||
710 | if (msr_set_bit(0xc0011005, 54) > 0) { | |
711 | rdmsrl(0xc0011005, value); | |
712 | if (value & BIT_64(54)) { | |
713 | set_cpu_cap(c, X86_FEATURE_TOPOEXT); | |
96685a55 | 714 | pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); |
26bfa5f8 BP |
715 | } |
716 | } | |
717 | } | |
718 | ||
719 | /* | |
720 | * The way access filter has a performance penalty on some workloads. | |
721 | * Disable it on the affected CPUs. | |
722 | */ | |
723 | if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { | |
ae8b7875 | 724 | if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { |
26bfa5f8 | 725 | value |= 0x1E; |
ae8b7875 | 726 | wrmsrl_safe(MSR_F15H_IC_CFG, value); |
26bfa5f8 BP |
727 | } |
728 | } | |
729 | } | |
730 | ||
148f9bb8 | 731 | static void init_amd(struct cpuinfo_x86 *c) |
1da177e4 | 732 | { |
8e8da023 | 733 | u32 dummy; |
7d318d77 | 734 | |
2b16a235 AK |
735 | early_init_amd(c); |
736 | ||
fb87a298 PC |
737 | /* |
738 | * Bit 31 in normal CPUID used for nonstandard 3DNow ID; | |
16282a8e | 739 | * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway |
fb87a298 | 740 | */ |
16282a8e | 741 | clear_cpu_cap(c, 0*32+31); |
fb87a298 | 742 | |
12d8a961 | 743 | if (c->x86 >= 0x10) |
6c62aa4a | 744 | set_cpu_cap(c, X86_FEATURE_REP_GOOD); |
0d96b9ff YL |
745 | |
746 | /* get apicid instead of initial apic id from cpuid */ | |
747 | c->apicid = hard_smp_processor_id(); | |
11fdd252 YL |
748 | |
749 | /* K6s reports MCEs but don't actually have all the MSRs */ | |
750 | if (c->x86 < 6) | |
751 | clear_cpu_cap(c, X86_FEATURE_MCE); | |
26bfa5f8 BP |
752 | |
753 | switch (c->x86) { | |
754 | case 4: init_amd_k5(c); break; | |
755 | case 5: init_amd_k6(c); break; | |
756 | case 6: init_amd_k7(c); break; | |
757 | case 0xf: init_amd_k8(c); break; | |
758 | case 0x10: init_amd_gh(c); break; | |
d1992996 | 759 | case 0x12: init_amd_ln(c); break; |
26bfa5f8 BP |
760 | case 0x15: init_amd_bd(c); break; |
761 | } | |
11fdd252 | 762 | |
281b6221 RM |
763 | /* |
764 | * Enable workaround for FXSAVE leak on CPUs | |
765 | * without a XSaveErPtr feature | |
766 | */ | |
767 | if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) | |
9b13a93d | 768 | set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); |
1da177e4 | 769 | |
27c13ece | 770 | cpu_detect_cache_sizes(c); |
3dd9d514 | 771 | |
11fdd252 | 772 | /* Multi core CPU? */ |
6c62aa4a | 773 | if (c->extended_cpuid_level >= 0x80000008) { |
11fdd252 | 774 | amd_detect_cmp(c); |
6c62aa4a YL |
775 | srat_detect_node(c); |
776 | } | |
faee9a5d | 777 | |
6c62aa4a | 778 | #ifdef CONFIG_X86_32 |
11fdd252 | 779 | detect_ht(c); |
6c62aa4a | 780 | #endif |
39b3a791 | 781 | |
04a15418 | 782 | init_amd_cacheinfo(c); |
3556ddfa | 783 | |
12d8a961 | 784 | if (c->x86 >= 0xf) |
11fdd252 | 785 | set_cpu_cap(c, X86_FEATURE_K8); |
de421863 | 786 | |
054efb64 | 787 | if (cpu_has(c, X86_FEATURE_XMM2)) { |
dc39f26b TL |
788 | unsigned long long val; |
789 | int ret; | |
790 | ||
bde94319 TL |
791 | /* |
792 | * A serializing LFENCE has less overhead than MFENCE, so | |
793 | * use it for execution serialization. On families which | |
794 | * don't have that MSR, LFENCE is already serializing. | |
795 | * msr_set_bit() uses the safe accessors, too, even if the MSR | |
796 | * is not present. | |
797 | */ | |
798 | msr_set_bit(MSR_F10H_DECFG, | |
799 | MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); | |
800 | ||
dc39f26b TL |
801 | /* |
802 | * Verify that the MSR write was successful (could be running | |
803 | * under a hypervisor) and only then assume that LFENCE is | |
804 | * serializing. | |
805 | */ | |
806 | ret = rdmsrl_safe(MSR_F10H_DECFG, &val); | |
807 | if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { | |
808 | /* A serializing LFENCE stops RDTSC speculation */ | |
809 | set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); | |
810 | } else { | |
811 | /* MFENCE stops RDTSC speculation */ | |
812 | set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); | |
813 | } | |
11fdd252 | 814 | } |
6c62aa4a | 815 | |
e9cdd343 BO |
816 | /* |
817 | * Family 0x12 and above processors have APIC timer | |
818 | * running in deep C states. | |
819 | */ | |
820 | if (c->x86 > 0x11) | |
b87cf80a | 821 | set_cpu_cap(c, X86_FEATURE_ARAT); |
5bbc097d | 822 | |
8e8da023 | 823 | rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); |
a930dc45 BP |
824 | |
825 | /* 3DNow or LM implies PREFETCHW */ | |
826 | if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) | |
827 | if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) | |
828 | set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); | |
61f01dd9 | 829 | |
def9331a JG |
830 | /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ |
831 | if (!cpu_has(c, X86_FEATURE_XENPV)) | |
832 | set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); | |
1da177e4 LT |
833 | } |
834 | ||
6c62aa4a | 835 | #ifdef CONFIG_X86_32 |
148f9bb8 | 836 | static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) |
1da177e4 LT |
837 | { |
838 | /* AMD errata T13 (order #21922) */ | |
839 | if ((c->x86 == 6)) { | |
8bdbd962 AC |
840 | /* Duron Rev A0 */ |
841 | if (c->x86_model == 3 && c->x86_mask == 0) | |
1da177e4 | 842 | size = 64; |
8bdbd962 | 843 | /* Tbird rev A1/A2 */ |
1da177e4 | 844 | if (c->x86_model == 4 && |
8bdbd962 | 845 | (c->x86_mask == 0 || c->x86_mask == 1)) |
1da177e4 LT |
846 | size = 256; |
847 | } | |
848 | return size; | |
849 | } | |
6c62aa4a | 850 | #endif |
1da177e4 | 851 | |
148f9bb8 | 852 | static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) |
b46882e4 BP |
853 | { |
854 | u32 ebx, eax, ecx, edx; | |
855 | u16 mask = 0xfff; | |
856 | ||
857 | if (c->x86 < 0xf) | |
858 | return; | |
859 | ||
860 | if (c->extended_cpuid_level < 0x80000006) | |
861 | return; | |
862 | ||
863 | cpuid(0x80000006, &eax, &ebx, &ecx, &edx); | |
864 | ||
865 | tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; | |
866 | tlb_lli_4k[ENTRIES] = ebx & mask; | |
867 | ||
868 | /* | |
869 | * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB | |
870 | * characteristics from the CPUID function 0x80000005 instead. | |
871 | */ | |
872 | if (c->x86 == 0xf) { | |
873 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
874 | mask = 0xff; | |
875 | } | |
876 | ||
877 | /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
d1393367 BP |
878 | if (!((eax >> 16) & mask)) |
879 | tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; | |
880 | else | |
b46882e4 | 881 | tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; |
b46882e4 BP |
882 | |
883 | /* a 4M entry uses two 2M entries */ | |
884 | tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; | |
885 | ||
886 | /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ | |
887 | if (!(eax & mask)) { | |
888 | /* Erratum 658 */ | |
889 | if (c->x86 == 0x15 && c->x86_model <= 0x1f) { | |
890 | tlb_lli_2m[ENTRIES] = 1024; | |
891 | } else { | |
892 | cpuid(0x80000005, &eax, &ebx, &ecx, &edx); | |
893 | tlb_lli_2m[ENTRIES] = eax & 0xff; | |
894 | } | |
895 | } else | |
896 | tlb_lli_2m[ENTRIES] = eax & mask; | |
897 | ||
898 | tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; | |
899 | } | |
900 | ||
148f9bb8 | 901 | static const struct cpu_dev amd_cpu_dev = { |
1da177e4 | 902 | .c_vendor = "AMD", |
fb87a298 | 903 | .c_ident = { "AuthenticAMD" }, |
6c62aa4a | 904 | #ifdef CONFIG_X86_32 |
09dc68d9 JB |
905 | .legacy_models = { |
906 | { .family = 4, .model_names = | |
1da177e4 LT |
907 | { |
908 | [3] = "486 DX/2", | |
909 | [7] = "486 DX/2-WB", | |
fb87a298 PC |
910 | [8] = "486 DX/4", |
911 | [9] = "486 DX/4-WB", | |
1da177e4 | 912 | [14] = "Am5x86-WT", |
fb87a298 | 913 | [15] = "Am5x86-WB" |
1da177e4 LT |
914 | } |
915 | }, | |
916 | }, | |
09dc68d9 | 917 | .legacy_cache_size = amd_size_cache, |
6c62aa4a | 918 | #endif |
03ae5768 | 919 | .c_early_init = early_init_amd, |
b46882e4 | 920 | .c_detect_tlb = cpu_detect_tlb_amd, |
8fa8b035 | 921 | .c_bsp_init = bsp_init_amd, |
1da177e4 | 922 | .c_init = init_amd, |
10a434fc | 923 | .c_x86_vendor = X86_VENDOR_AMD, |
1da177e4 LT |
924 | }; |
925 | ||
10a434fc | 926 | cpu_dev_register(amd_cpu_dev); |
d78d671d HR |
927 | |
928 | /* | |
929 | * AMD errata checking | |
930 | * | |
931 | * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or | |
932 | * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that | |
933 | * have an OSVW id assigned, which it takes as first argument. Both take a | |
934 | * variable number of family-specific model-stepping ranges created by | |
7d7dc116 | 935 | * AMD_MODEL_RANGE(). |
d78d671d HR |
936 | * |
937 | * Example: | |
938 | * | |
939 | * const int amd_erratum_319[] = | |
940 | * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), | |
941 | * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), | |
942 | * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); | |
943 | */ | |
944 | ||
7d7dc116 BP |
945 | #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } |
946 | #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } | |
947 | #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ | |
948 | ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) | |
949 | #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) | |
950 | #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) | |
951 | #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) | |
952 | ||
953 | static const int amd_erratum_400[] = | |
328935e6 | 954 | AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), |
9d8888c2 HR |
955 | AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); |
956 | ||
e6ee94d5 | 957 | static const int amd_erratum_383[] = |
1be85a6d | 958 | AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); |
9d8888c2 | 959 | |
8c6b79bb TK |
960 | |
961 | static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) | |
d78d671d | 962 | { |
d78d671d HR |
963 | int osvw_id = *erratum++; |
964 | u32 range; | |
965 | u32 ms; | |
966 | ||
d78d671d HR |
967 | if (osvw_id >= 0 && osvw_id < 65536 && |
968 | cpu_has(cpu, X86_FEATURE_OSVW)) { | |
969 | u64 osvw_len; | |
970 | ||
971 | rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); | |
972 | if (osvw_id < osvw_len) { | |
973 | u64 osvw_bits; | |
974 | ||
975 | rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), | |
976 | osvw_bits); | |
977 | return osvw_bits & (1ULL << (osvw_id & 0x3f)); | |
978 | } | |
979 | } | |
980 | ||
981 | /* OSVW unavailable or ID unknown, match family-model-stepping range */ | |
07a7795c | 982 | ms = (cpu->x86_model << 4) | cpu->x86_mask; |
d78d671d HR |
983 | while ((range = *erratum++)) |
984 | if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && | |
985 | (ms >= AMD_MODEL_RANGE_START(range)) && | |
986 | (ms <= AMD_MODEL_RANGE_END(range))) | |
987 | return true; | |
988 | ||
989 | return false; | |
990 | } | |
d6d55f0b JS |
991 | |
992 | void set_dr_addr_mask(unsigned long mask, int dr) | |
993 | { | |
362f924b | 994 | if (!boot_cpu_has(X86_FEATURE_BPEXT)) |
d6d55f0b JS |
995 | return; |
996 | ||
997 | switch (dr) { | |
998 | case 0: | |
999 | wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); | |
1000 | break; | |
1001 | case 1: | |
1002 | case 2: | |
1003 | case 3: | |
1004 | wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); | |
1005 | break; | |
1006 | default: | |
1007 | break; | |
1008 | } | |
1009 | } |