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1353ebb4 | 1 | /* |
1353ebb4 JF |
2 | * Copyright (C) 1994 Linus Torvalds |
3 | * | |
4 | * Cyrix stuff, June 1998 by: | |
5 | * - Rafael R. Reilova (moved everything from head.S), | |
6 | * <rreilova@ececs.uc.edu> | |
7 | * - Channing Corn (tests & fixes), | |
8 | * - Andrew D. Balsa (code cleanup). | |
9 | */ | |
10 | #include <linux/init.h> | |
11 | #include <linux/utsname.h> | |
6d283d72 | 12 | #include <linux/cpu.h> |
86cdbc59 | 13 | #include <linux/smp.h> |
687cc97a | 14 | |
20b509bf | 15 | #include <asm/spec-ctrl.h> |
687cc97a | 16 | #include <asm/cmdline.h> |
91eb1b79 | 17 | #include <asm/bugs.h> |
1353ebb4 | 18 | #include <asm/processor.h> |
7ebad705 | 19 | #include <asm/processor-flags.h> |
952f07ec | 20 | #include <asm/fpu/internal.h> |
1353ebb4 JF |
21 | #include <asm/msr.h> |
22 | #include <asm/paravirt.h> | |
23 | #include <asm/alternative.h> | |
62a67e12 | 24 | #include <asm/pgtable.h> |
d1163651 | 25 | #include <asm/set_memory.h> |
12aa317c | 26 | #include <asm/intel-family.h> |
1353ebb4 | 27 | |
687cc97a | 28 | static void __init spectre_v2_select_mitigation(void); |
ef68a13e | 29 | static void __init ssb_select_mitigation(void); |
687cc97a | 30 | |
3ef956dd KRW |
31 | /* |
32 | * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any | |
33 | * writes to SPEC_CTRL contain whatever reserved bits have been set. | |
34 | */ | |
35 | static u64 __ro_after_init x86_spec_ctrl_base; | |
36 | ||
ca6704cf KRW |
37 | /* |
38 | * The vendor and possibly platform specific bits which can be modified in | |
39 | * x86_spec_ctrl_base. | |
40 | */ | |
41 | static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS; | |
42 | ||
7c60cee4 KRW |
43 | /* |
44 | * AMD specific MSR info for Speculative Store Bypass control. | |
45 | * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu(). | |
46 | */ | |
47 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
48 | u64 __ro_after_init x86_amd_ls_cfg_rds_mask; | |
49 | ||
1353ebb4 JF |
50 | void __init check_bugs(void) |
51 | { | |
52 | identify_boot_cpu(); | |
55a36b65 | 53 | |
62a67e12 BP |
54 | if (!IS_ENABLED(CONFIG_SMP)) { |
55 | pr_info("CPU: "); | |
56 | print_cpu_info(&boot_cpu_data); | |
57 | } | |
58 | ||
3ef956dd KRW |
59 | /* |
60 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
7c60cee4 KRW |
61 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
62 | * init code as it is not enumerated and depends on the family. | |
3ef956dd KRW |
63 | */ |
64 | if (ibrs_inuse) | |
65 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
66 | ||
687cc97a DW |
67 | /* Select the proper spectre mitigation before patching alternatives */ |
68 | spectre_v2_select_mitigation(); | |
69 | ||
ef68a13e KRW |
70 | /* |
71 | * Select proper mitigation for any exposure to the Speculative Store | |
72 | * Bypass vulnerability. | |
73 | */ | |
74 | ssb_select_mitigation(); | |
75 | ||
62a67e12 | 76 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
77 | /* |
78 | * Check whether we are able to run this kernel safely on SMP. | |
79 | * | |
80 | * - i386 is no longer supported. | |
81 | * - In order to run on anything without a TSC, we need to be | |
82 | * compiled for a i486. | |
83 | */ | |
84 | if (boot_cpu_data.x86 < 4) | |
85 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
86 | ||
bfe4bb15 MV |
87 | init_utsname()->machine[1] = |
88 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 89 | alternative_instructions(); |
304bceda | 90 | |
4d164092 | 91 | fpu__init_check_bugs(); |
62a67e12 BP |
92 | #else /* CONFIG_X86_64 */ |
93 | alternative_instructions(); | |
94 | ||
95 | /* | |
96 | * Make sure the first 2MB area is not mapped by huge pages | |
97 | * There are typically fixed size MTRRs in there and overlapping | |
98 | * MTRRs into large pages causes slow downs. | |
99 | * | |
100 | * Right now we don't do that with gbpages because there seems | |
101 | * very little benefit for that case. | |
102 | */ | |
103 | if (!direct_gbpages) | |
104 | set_memory_4k((unsigned long)__va(0), 1); | |
105 | #endif | |
1353ebb4 | 106 | } |
6d283d72 | 107 | |
687cc97a DW |
108 | /* The kernel command line selection */ |
109 | enum spectre_v2_mitigation_cmd { | |
110 | SPECTRE_V2_CMD_NONE, | |
111 | SPECTRE_V2_CMD_AUTO, | |
112 | SPECTRE_V2_CMD_FORCE, | |
113 | SPECTRE_V2_CMD_RETPOLINE, | |
114 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
115 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
116 | }; | |
117 | ||
118 | static const char *spectre_v2_strings[] = { | |
119 | [SPECTRE_V2_NONE] = "Vulnerable", | |
120 | [SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline", | |
121 | [SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline", | |
122 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
123 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
124 | }; | |
125 | ||
126 | #undef pr_fmt | |
127 | #define pr_fmt(fmt) "Spectre V2 mitigation: " fmt | |
128 | ||
129 | static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE; | |
130 | ||
3ef956dd KRW |
131 | void x86_spec_ctrl_set(u64 val) |
132 | { | |
ca6704cf | 133 | if (val & x86_spec_ctrl_mask) |
3ef956dd KRW |
134 | WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val); |
135 | else | |
136 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val); | |
137 | } | |
138 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set); | |
139 | ||
140 | u64 x86_spec_ctrl_get_default(void) | |
141 | { | |
142 | return x86_spec_ctrl_base; | |
143 | } | |
144 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default); | |
145 | ||
fe170612 KRW |
146 | void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl) |
147 | { | |
148 | if (!ibrs_inuse) | |
149 | return; | |
150 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
151 | wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl); | |
152 | } | |
153 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest); | |
154 | ||
155 | void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl) | |
156 | { | |
157 | if (!ibrs_inuse) | |
158 | return; | |
159 | if (x86_spec_ctrl_base != guest_spec_ctrl) | |
160 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
161 | } | |
162 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host); | |
163 | ||
7c60cee4 KRW |
164 | static void x86_amd_rds_enable(void) |
165 | { | |
166 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask; | |
167 | ||
168 | if (boot_cpu_has(X86_FEATURE_AMD_RDS)) | |
169 | wrmsrl(MSR_AMD64_LS_CFG, msrval); | |
170 | } | |
171 | ||
687cc97a DW |
172 | static void __init spec2_print_if_insecure(const char *reason) |
173 | { | |
174 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
175 | pr_info("%s\n", reason); | |
176 | } | |
177 | ||
178 | static void __init spec2_print_if_secure(const char *reason) | |
179 | { | |
180 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
181 | pr_info("%s\n", reason); | |
182 | } | |
183 | ||
184 | static inline bool retp_compiler(void) | |
185 | { | |
186 | return __is_defined(RETPOLINE); | |
187 | } | |
188 | ||
189 | static inline bool match_option(const char *arg, int arglen, const char *opt) | |
190 | { | |
191 | int len = strlen(opt); | |
192 | ||
193 | return len == arglen && !strncmp(arg, opt, len); | |
194 | } | |
195 | ||
196 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) | |
197 | { | |
198 | char arg[20]; | |
199 | int ret; | |
200 | ||
201 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, | |
202 | sizeof(arg)); | |
203 | if (ret > 0) { | |
204 | if (match_option(arg, ret, "off")) { | |
205 | goto disable; | |
206 | } else if (match_option(arg, ret, "on")) { | |
207 | spec2_print_if_secure("force enabled on command line."); | |
208 | return SPECTRE_V2_CMD_FORCE; | |
209 | } else if (match_option(arg, ret, "retpoline")) { | |
210 | spec2_print_if_insecure("retpoline selected on command line."); | |
211 | return SPECTRE_V2_CMD_RETPOLINE; | |
212 | } else if (match_option(arg, ret, "retpoline,amd")) { | |
213 | if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
214 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
215 | return SPECTRE_V2_CMD_AUTO; | |
216 | } | |
217 | spec2_print_if_insecure("AMD retpoline selected on command line."); | |
218 | return SPECTRE_V2_CMD_RETPOLINE_AMD; | |
219 | } else if (match_option(arg, ret, "retpoline,generic")) { | |
220 | spec2_print_if_insecure("generic retpoline selected on command line."); | |
221 | return SPECTRE_V2_CMD_RETPOLINE_GENERIC; | |
222 | } else if (match_option(arg, ret, "auto")) { | |
223 | return SPECTRE_V2_CMD_AUTO; | |
224 | } | |
225 | } | |
226 | ||
227 | if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2")) | |
228 | return SPECTRE_V2_CMD_AUTO; | |
229 | disable: | |
230 | spec2_print_if_insecure("disabled on command line."); | |
231 | return SPECTRE_V2_CMD_NONE; | |
232 | } | |
233 | ||
12aa317c DW |
234 | /* Check for Skylake-like CPUs (for RSB handling) */ |
235 | static bool __init is_skylake_era(void) | |
236 | { | |
237 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && | |
238 | boot_cpu_data.x86 == 6) { | |
239 | switch (boot_cpu_data.x86_model) { | |
240 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
241 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
242 | case INTEL_FAM6_SKYLAKE_X: | |
243 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
244 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
245 | return true; | |
246 | } | |
247 | } | |
248 | return false; | |
249 | } | |
250 | ||
687cc97a DW |
251 | static void __init spectre_v2_select_mitigation(void) |
252 | { | |
253 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
254 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
255 | ||
256 | /* | |
257 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
258 | * then nothing to do. | |
259 | */ | |
260 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
261 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
262 | return; | |
263 | ||
264 | switch (cmd) { | |
265 | case SPECTRE_V2_CMD_NONE: | |
266 | return; | |
267 | ||
268 | case SPECTRE_V2_CMD_FORCE: | |
269 | /* FALLTRHU */ | |
270 | case SPECTRE_V2_CMD_AUTO: | |
271 | goto retpoline_auto; | |
272 | ||
273 | case SPECTRE_V2_CMD_RETPOLINE_AMD: | |
274 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
275 | goto retpoline_amd; | |
276 | break; | |
277 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
278 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
279 | goto retpoline_generic; | |
280 | break; | |
281 | case SPECTRE_V2_CMD_RETPOLINE: | |
282 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
283 | goto retpoline_auto; | |
284 | break; | |
285 | } | |
286 | pr_err("kernel not compiled with retpoline; no mitigation available!"); | |
287 | return; | |
288 | ||
289 | retpoline_auto: | |
290 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
291 | retpoline_amd: | |
292 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
293 | pr_err("LFENCE not serializing. Switching to generic retpoline\n"); | |
294 | goto retpoline_generic; | |
295 | } | |
296 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD : | |
297 | SPECTRE_V2_RETPOLINE_MINIMAL_AMD; | |
298 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); | |
299 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
300 | } else { | |
301 | retpoline_generic: | |
302 | mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC : | |
303 | SPECTRE_V2_RETPOLINE_MINIMAL; | |
304 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
305 | } | |
306 | ||
307 | spectre_v2_enabled = mode; | |
308 | pr_info("%s\n", spectre_v2_strings[mode]); | |
12aa317c | 309 | |
86cdbc59 AW |
310 | pr_info("Speculation control IBPB %s IBRS %s", |
311 | ibpb_supported ? "supported" : "not-supported", | |
312 | ibrs_supported ? "supported" : "not-supported"); | |
313 | ||
314 | /* | |
315 | * If we have a full retpoline mode and then disable IBPB in kernel mode | |
316 | * we do not require both. | |
317 | */ | |
318 | if (mode == SPECTRE_V2_RETPOLINE_AMD || | |
319 | mode == SPECTRE_V2_RETPOLINE_GENERIC) | |
320 | { | |
321 | if (ibrs_supported) { | |
322 | pr_info("Retpoline compiled kernel. Defaulting IBRS to disabled"); | |
323 | set_ibrs_disabled(); | |
324 | if (!ibrs_inuse) | |
325 | sysctl_ibrs_enabled = 0; | |
326 | } | |
327 | } | |
328 | ||
12aa317c DW |
329 | /* |
330 | * If neither SMEP or KPTI are available, there is a risk of | |
331 | * hitting userspace addresses in the RSB after a context switch | |
332 | * from a shallow call stack to a deeper one. To prevent this fill | |
333 | * the entire RSB, even when using IBRS. | |
334 | * | |
335 | * Skylake era CPUs have a separate issue with *underflow* of the | |
336 | * RSB, when they will predict 'ret' targets from the generic BTB. | |
337 | * The proper mitigation for this is IBRS. If IBRS is not supported | |
338 | * or deactivated in favour of retpolines the RSB fill on context | |
339 | * switch is required. | |
340 | */ | |
341 | if ((!boot_cpu_has(X86_FEATURE_PTI) && | |
342 | !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) { | |
343 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); | |
344 | pr_info("Filling RSB on context switch\n"); | |
345 | } | |
687cc97a DW |
346 | } |
347 | ||
ef68a13e KRW |
348 | #undef pr_fmt |
349 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
350 | ||
351 | static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE; | |
352 | ||
353 | /* The kernel command line selection */ | |
354 | enum ssb_mitigation_cmd { | |
355 | SPEC_STORE_BYPASS_CMD_NONE, | |
356 | SPEC_STORE_BYPASS_CMD_AUTO, | |
357 | SPEC_STORE_BYPASS_CMD_ON, | |
358 | }; | |
359 | ||
360 | static const char *ssb_strings[] = { | |
361 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", | |
362 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled" | |
363 | }; | |
364 | ||
365 | static const struct { | |
366 | const char *option; | |
367 | enum ssb_mitigation_cmd cmd; | |
368 | } ssb_mitigation_options[] = { | |
369 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ | |
370 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
371 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
372 | }; | |
373 | ||
374 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
375 | { | |
376 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
377 | char arg[20]; | |
378 | int ret, i; | |
379 | ||
380 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) { | |
381 | return SPEC_STORE_BYPASS_CMD_NONE; | |
382 | } else { | |
383 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
384 | arg, sizeof(arg)); | |
385 | if (ret < 0) | |
386 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
387 | ||
388 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
389 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
390 | continue; | |
391 | ||
392 | cmd = ssb_mitigation_options[i].cmd; | |
393 | break; | |
394 | } | |
395 | ||
396 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
397 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
398 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
399 | } | |
400 | } | |
401 | ||
402 | return cmd; | |
403 | } | |
404 | ||
405 | static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void) | |
406 | { | |
407 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
408 | enum ssb_mitigation_cmd cmd; | |
409 | ||
410 | if (!boot_cpu_has(X86_FEATURE_RDS)) | |
411 | return mode; | |
412 | ||
413 | cmd = ssb_parse_cmdline(); | |
414 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
415 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
416 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
417 | return mode; | |
418 | ||
419 | switch (cmd) { | |
420 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
7c60cee4 KRW |
421 | /* |
422 | * AMD platforms by default don't need SSB mitigation. | |
423 | */ | |
424 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) | |
425 | break; | |
ef68a13e KRW |
426 | case SPEC_STORE_BYPASS_CMD_ON: |
427 | mode = SPEC_STORE_BYPASS_DISABLE; | |
428 | break; | |
429 | case SPEC_STORE_BYPASS_CMD_NONE: | |
430 | break; | |
431 | } | |
432 | ||
2b83aba8 KRW |
433 | /* |
434 | * We have three CPU feature flags that are in play here: | |
435 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
436 | * - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass | |
437 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation | |
438 | */ | |
439 | if (mode != SPEC_STORE_BYPASS_NONE) { | |
ef68a13e | 440 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
2b83aba8 KRW |
441 | /* |
442 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses | |
443 | * a completely different MSR and bit dependent on family. | |
444 | */ | |
445 | switch (boot_cpu_data.x86_vendor) { | |
446 | case X86_VENDOR_INTEL: | |
447 | x86_spec_ctrl_base |= SPEC_CTRL_RDS; | |
ca6704cf | 448 | x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS; |
2b83aba8 KRW |
449 | x86_spec_ctrl_set(SPEC_CTRL_RDS); |
450 | break; | |
451 | case X86_VENDOR_AMD: | |
7c60cee4 | 452 | x86_amd_rds_enable(); |
2b83aba8 KRW |
453 | break; |
454 | } | |
455 | } | |
456 | ||
ef68a13e KRW |
457 | return mode; |
458 | } | |
459 | ||
460 | static void ssb_select_mitigation() | |
461 | { | |
462 | ssb_mode = __ssb_select_mitigation(); | |
463 | ||
464 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
465 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
466 | } | |
467 | ||
687cc97a DW |
468 | #undef pr_fmt |
469 | ||
2b83aba8 KRW |
470 | void x86_spec_ctrl_setup_ap(void) |
471 | { | |
472 | if (ibrs_inuse) | |
ca6704cf | 473 | x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask); |
7c60cee4 KRW |
474 | |
475 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
476 | x86_amd_rds_enable(); | |
2b83aba8 KRW |
477 | } |
478 | ||
6d283d72 | 479 | #ifdef CONFIG_SYSFS |
8f04f8ba KRW |
480 | ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
481 | char *buf, unsigned int bug) | |
6d283d72 | 482 | { |
8f04f8ba | 483 | if (!boot_cpu_has_bug(bug)) |
6d283d72 | 484 | return sprintf(buf, "Not affected\n"); |
8f04f8ba KRW |
485 | |
486 | switch (bug) { | |
487 | case X86_BUG_CPU_MELTDOWN: | |
488 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
489 | return sprintf(buf, "Mitigation: PTI\n"); | |
490 | break; | |
491 | ||
492 | case X86_BUG_SPECTRE_V1: | |
493 | if (osb_is_enabled) | |
494 | return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n"); | |
495 | ||
496 | case X86_BUG_SPECTRE_V2: | |
497 | return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : ""); | |
498 | ||
ef68a13e KRW |
499 | case X86_BUG_SPEC_STORE_BYPASS: |
500 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
501 | ||
8f04f8ba KRW |
502 | default: |
503 | break; | |
504 | } | |
505 | ||
6d283d72 TG |
506 | return sprintf(buf, "Vulnerable\n"); |
507 | } | |
508 | ||
8f04f8ba KRW |
509 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, |
510 | char *buf) | |
6d283d72 | 511 | { |
8f04f8ba | 512 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); |
6d283d72 TG |
513 | } |
514 | ||
8f04f8ba KRW |
515 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, |
516 | char *buf) | |
6d283d72 | 517 | { |
8f04f8ba KRW |
518 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
519 | } | |
687cc97a | 520 | |
8f04f8ba KRW |
521 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, |
522 | char *buf) | |
523 | { | |
524 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); | |
6d283d72 | 525 | } |
abe4b60b KRW |
526 | |
527 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
528 | { | |
529 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
530 | } | |
6d283d72 | 531 | #endif |