[mirror_ubuntu-artful-kernel.git] / arch / x86 / kernel / cpu / bugs.c

/*
 *  Copyright (C) 1994  Linus Torvalds
 *
 *  Cyrix stuff, June 1998 by:
 *	- Rafael R. Reilova (moved everything from head.S),
 *        <rreilova@ececs.uc.edu>
 *	- Channing Corn (tests & fixes),
 *	- Andrew D. Balsa (code cleanup).
 */
#include <linux/init.h>
#include <linux/utsname.h>
#include <linux/cpu.h>
#include <linux/smp.h>
#include <linux/nospec.h>
#include <linux/prctl.h>

#include <asm/spec-ctrl.h>
#include <asm/cmdline.h>
#include <asm/bugs.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/fpu/internal.h>
#include <asm/msr.h>
#include <asm/paravirt.h>
#include <asm/alternative.h>
#include <asm/pgtable.h>
#include <asm/set_memory.h>
#include <asm/intel-family.h>

static void __init spectre_v2_select_mitigation(void);
static void __init ssb_select_mitigation(void);

/*
 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
 * writes to SPEC_CTRL contain whatever reserved bits have been set.
 */
u64 __ro_after_init x86_spec_ctrl_base;

/*
 * The vendor and possibly platform specific bits which can be modified in
 * x86_spec_ctrl_base.
 */
static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;

/*
 * AMD specific MSR info for Speculative Store Bypass control.
 * x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
 */
u64 __ro_after_init x86_amd_ls_cfg_base;
u64 __ro_after_init x86_amd_ls_cfg_rds_mask;

void __init check_bugs(void)
{
	identify_boot_cpu();

	if (!IS_ENABLED(CONFIG_SMP)) {
		pr_info("CPU: ");
		print_cpu_info(&boot_cpu_data);
	}

	/*
	 * Read the SPEC_CTRL MSR to account for reserved bits which may
	 * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
	 * init code as it is not enumerated and depends on the family.
	 */
	if (ibrs_inuse)
		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

	/* Select the proper spectre mitigation before patching alternatives */
	spectre_v2_select_mitigation();

	/*
	 * Select proper mitigation for any exposure to the Speculative Store
	 * Bypass vulnerability.
	 */
	ssb_select_mitigation();

#ifdef CONFIG_X86_32
	/*
	 * Check whether we are able to run this kernel safely on SMP.
	 *
	 * - i386 is no longer supported.
	 * - In order to run on anything without a TSC, we need to be
	 *   compiled for a i486.
	 */
	if (boot_cpu_data.x86 < 4)
		panic("Kernel requires i486+ for 'invlpg' and other features");

	init_utsname()->machine[1] =
		'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
	alternative_instructions();

	fpu__init_check_bugs();
#else /* CONFIG_X86_64 */
	alternative_instructions();

	/*
	 * Make sure the first 2MB area is not mapped by huge pages
	 * There are typically fixed size MTRRs in there and overlapping
	 * MTRRs into large pages causes slow downs.
	 *
	 * Right now we don't do that with gbpages because there seems
	 * very little benefit for that case.
	 */
	if (!direct_gbpages)
		set_memory_4k((unsigned long)__va(0), 1);
#endif
}

/* The kernel command line selection */
enum spectre_v2_mitigation_cmd {
	SPECTRE_V2_CMD_NONE,
	SPECTRE_V2_CMD_AUTO,
	SPECTRE_V2_CMD_FORCE,
	SPECTRE_V2_CMD_RETPOLINE,
	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
	SPECTRE_V2_CMD_RETPOLINE_AMD,
};

static const char *spectre_v2_strings[] = {
	[SPECTRE_V2_NONE]			= "Vulnerable",
	[SPECTRE_V2_RETPOLINE_MINIMAL]		= "Vulnerable: Minimal generic ASM retpoline",
	[SPECTRE_V2_RETPOLINE_MINIMAL_AMD]	= "Vulnerable: Minimal AMD ASM retpoline",
	[SPECTRE_V2_RETPOLINE_GENERIC]		= "Mitigation: Full generic retpoline",
	[SPECTRE_V2_RETPOLINE_AMD]		= "Mitigation: Full AMD retpoline",
};

#undef pr_fmt
#define pr_fmt(fmt)     "Spectre V2 mitigation: " fmt

static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;

void x86_spec_ctrl_set(u64 val)
{
	if (val & x86_spec_ctrl_mask)
		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
	else
		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);

u64 x86_spec_ctrl_get_default(void)
{
	u64 msrval = x86_spec_ctrl_base;

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		msrval |= rds_tif_to_spec_ctrl(current_thread_info()->flags);
	return msrval;
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);

void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
{
	u64 host = x86_spec_ctrl_base;

	if (!ibrs_inuse)
		return;

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);

	if (host != guest_spec_ctrl)
		wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);

void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
{
	u64 host = x86_spec_ctrl_base;

	if (!ibrs_inuse)
		return;

	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
		host |= rds_tif_to_spec_ctrl(current_thread_info()->flags);

	if (host != guest_spec_ctrl)
		wrmsrl(MSR_IA32_SPEC_CTRL, host);
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);

static void x86_amd_rds_enable(void)
{
	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_mask;

	if (boot_cpu_has(X86_FEATURE_AMD_RDS))
		wrmsrl(MSR_AMD64_LS_CFG, msrval);
}

static void __init spec2_print_if_insecure(const char *reason)
{
	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
		pr_info("%s\n", reason);
}

static void __init spec2_print_if_secure(const char *reason)
{
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
		pr_info("%s\n", reason);
}

static inline bool retp_compiler(void)
{
	return __is_defined(RETPOLINE);
}

static inline bool match_option(const char *arg, int arglen, const char *opt)
{
	int len = strlen(opt);

	return len == arglen && !strncmp(arg, opt, len);
}

static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
{
	char arg[20];
	int ret;

	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
				  sizeof(arg));
	if (ret > 0)  {
		if (match_option(arg, ret, "off")) {
			goto disable;
		} else if (match_option(arg, ret, "on")) {
			spec2_print_if_secure("force enabled on command line.");
			return SPECTRE_V2_CMD_FORCE;
		} else if (match_option(arg, ret, "retpoline")) {
			spec2_print_if_insecure("retpoline selected on command line.");
			return SPECTRE_V2_CMD_RETPOLINE;
		} else if (match_option(arg, ret, "retpoline,amd")) {
			if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
				pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
				return SPECTRE_V2_CMD_AUTO;
			}
			spec2_print_if_insecure("AMD retpoline selected on command line.");
			return SPECTRE_V2_CMD_RETPOLINE_AMD;
		} else if (match_option(arg, ret, "retpoline,generic")) {
			spec2_print_if_insecure("generic retpoline selected on command line.");
			return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
		} else if (match_option(arg, ret, "auto")) {
			return SPECTRE_V2_CMD_AUTO;
		}
	}

	if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
		return SPECTRE_V2_CMD_AUTO;
disable:
	spec2_print_if_insecure("disabled on command line.");
	return SPECTRE_V2_CMD_NONE;
}

/* Check for Skylake-like CPUs (for RSB handling) */
static bool __init is_skylake_era(void)
{
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6) {
		switch (boot_cpu_data.x86_model) {
		case INTEL_FAM6_SKYLAKE_MOBILE:
		case INTEL_FAM6_SKYLAKE_DESKTOP:
		case INTEL_FAM6_SKYLAKE_X:
		case INTEL_FAM6_KABYLAKE_MOBILE:
		case INTEL_FAM6_KABYLAKE_DESKTOP:
			return true;
		}
	}
	return false;
}

static void __init spectre_v2_select_mitigation(void)
{
	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;

	/*
	 * If the CPU is not affected and the command line mode is NONE or AUTO
	 * then nothing to do.
	 */
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
	    (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
		return;

	switch (cmd) {
	case SPECTRE_V2_CMD_NONE:
		return;

	case SPECTRE_V2_CMD_FORCE:
		/* FALLTRHU */
	case SPECTRE_V2_CMD_AUTO:
		goto retpoline_auto;

	case SPECTRE_V2_CMD_RETPOLINE_AMD:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_amd;
		break;
	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_generic;
		break;
	case SPECTRE_V2_CMD_RETPOLINE:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_auto;
		break;
	}
	pr_err("kernel not compiled with retpoline; no mitigation available!");
	return;

retpoline_auto:
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
	retpoline_amd:
		if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
			pr_err("LFENCE not serializing. Switching to generic retpoline\n");
			goto retpoline_generic;
		}
		mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
					 SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	} else {
	retpoline_generic:
		mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
					 SPECTRE_V2_RETPOLINE_MINIMAL;
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	}

	spectre_v2_enabled = mode;
	pr_info("%s\n", spectre_v2_strings[mode]);

	pr_info("Speculation control IBPB %s IBRS %s",
	        ibpb_supported ? "supported" : "not-supported",
	        ibrs_supported ? "supported" : "not-supported");

	/*
	 * If we have a full retpoline mode and then disable IBPB in kernel mode
	 * we do not require both.
	 */
	if (mode == SPECTRE_V2_RETPOLINE_AMD ||
	    mode == SPECTRE_V2_RETPOLINE_GENERIC)
	{
		if (ibrs_supported) {
			pr_info("Retpoline compiled kernel.  Defaulting IBRS to disabled");
			set_ibrs_disabled();
			if (!ibrs_inuse)
				sysctl_ibrs_enabled = 0;
		}
	}

	/*
	 * If neither SMEP or KPTI are available, there is a risk of
	 * hitting userspace addresses in the RSB after a context switch
	 * from a shallow call stack to a deeper one. To prevent this fill
	 * the entire RSB, even when using IBRS.
	 *
	 * Skylake era CPUs have a separate issue with *underflow* of the
	 * RSB, when they will predict 'ret' targets from the generic BTB.
	 * The proper mitigation for this is IBRS. If IBRS is not supported
	 * or deactivated in favour of retpolines the RSB fill on context
	 * switch is required.
	 */
	if ((!boot_cpu_has(X86_FEATURE_PTI) &&
	     !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
		pr_info("Filling RSB on context switch\n");
	}
}

#undef pr_fmt
#define pr_fmt(fmt)	"Speculative Store Bypass: " fmt

static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE;

/* The kernel command line selection */
enum ssb_mitigation_cmd {
	SPEC_STORE_BYPASS_CMD_NONE,
	SPEC_STORE_BYPASS_CMD_AUTO,
	SPEC_STORE_BYPASS_CMD_ON,
	SPEC_STORE_BYPASS_CMD_PRCTL,
};

static const char *ssb_strings[] = {
	[SPEC_STORE_BYPASS_NONE]	= "Vulnerable",
	[SPEC_STORE_BYPASS_DISABLE]	= "Mitigation: Speculative Store Bypass disabled",
	[SPEC_STORE_BYPASS_PRCTL]	= "Mitigation: Speculative Store Bypass disabled via prctl"
};

static const struct {
	const char *option;
	enum ssb_mitigation_cmd cmd;
} ssb_mitigation_options[] = {
	{ "auto",	SPEC_STORE_BYPASS_CMD_AUTO },  /* Platform decides */
	{ "on",		SPEC_STORE_BYPASS_CMD_ON },    /* Disable Speculative Store Bypass */
	{ "off",	SPEC_STORE_BYPASS_CMD_NONE },  /* Don't touch Speculative Store Bypass */
	{ "prctl",	SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
};

static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
{
	enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
	char arg[20];
	int ret, i;

	if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
		return SPEC_STORE_BYPASS_CMD_NONE;
	} else {
		ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
					  arg, sizeof(arg));
		if (ret < 0)
			return SPEC_STORE_BYPASS_CMD_AUTO;

		for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
			if (!match_option(arg, ret, ssb_mitigation_options[i].option))
				continue;

			cmd = ssb_mitigation_options[i].cmd;
			break;
		}

		if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
			pr_err("unknown option (%s). Switching to AUTO select\n", arg);
			return SPEC_STORE_BYPASS_CMD_AUTO;
		}
	}

	return cmd;
}

static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
{
	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
	enum ssb_mitigation_cmd cmd;

	if (!boot_cpu_has(X86_FEATURE_RDS))
		return mode;

	cmd = ssb_parse_cmdline();
	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
	    (cmd == SPEC_STORE_BYPASS_CMD_NONE ||
	     cmd == SPEC_STORE_BYPASS_CMD_AUTO))
		return mode;

	switch (cmd) {
	case SPEC_STORE_BYPASS_CMD_AUTO:
		/* Choose prctl as the default mode */
		mode = SPEC_STORE_BYPASS_PRCTL;
		break;
	case SPEC_STORE_BYPASS_CMD_ON:
		mode = SPEC_STORE_BYPASS_DISABLE;
		break;
	case SPEC_STORE_BYPASS_CMD_PRCTL:
		mode = SPEC_STORE_BYPASS_PRCTL;
		break;
	case SPEC_STORE_BYPASS_CMD_NONE:
		break;
	}

	/*
	 * We have three CPU feature flags that are in play here:
	 *  - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
	 *  - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
	 *  - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
	 */
	if (mode == SPEC_STORE_BYPASS_DISABLE) {
		setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
		/*
		 * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
		 * a completely different MSR and bit dependent on family.
		 */
		switch (boot_cpu_data.x86_vendor) {
		case X86_VENDOR_INTEL:
			x86_spec_ctrl_base |= SPEC_CTRL_RDS;
			x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
			x86_spec_ctrl_set(SPEC_CTRL_RDS);
			break;
		case X86_VENDOR_AMD:
			x86_amd_rds_enable();
			break;
		}
	}

	return mode;
}

static void ssb_select_mitigation()
{
	ssb_mode = __ssb_select_mitigation();

	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
		pr_info("%s\n", ssb_strings[ssb_mode]);
}

#undef pr_fmt

static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
{
	bool rds = !!test_tsk_thread_flag(task, TIF_RDS);

	if (ssb_mode != SPEC_STORE_BYPASS_PRCTL)
		return -ENXIO;

	if (ctrl == PR_SPEC_ENABLE)
		clear_tsk_thread_flag(task, TIF_RDS);
	else
		set_tsk_thread_flag(task, TIF_RDS);

	/*
	 * If being set on non-current task, delay setting the CPU
	 * mitigation until it is next scheduled.
	 */
	if (task == current && rds != !!test_tsk_thread_flag(task, TIF_RDS))
		speculative_store_bypass_update();

	return 0;
}

static int ssb_prctl_get(struct task_struct *task)
{
	switch (ssb_mode) {
	case SPEC_STORE_BYPASS_DISABLE:
		return PR_SPEC_DISABLE;
	case SPEC_STORE_BYPASS_PRCTL:
		if (test_tsk_thread_flag(task, TIF_RDS))
			return PR_SPEC_PRCTL | PR_SPEC_DISABLE;
		return PR_SPEC_PRCTL | PR_SPEC_ENABLE;
	default:
		if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
			return PR_SPEC_ENABLE;
		return PR_SPEC_NOT_AFFECTED;
	}
}

int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
			     unsigned long ctrl)
{
	if (ctrl != PR_SPEC_ENABLE && ctrl != PR_SPEC_DISABLE)
		return -ERANGE;

	switch (which) {
	case PR_SPEC_STORE_BYPASS:
		return ssb_prctl_set(task, ctrl);
	default:
		return -ENODEV;
	}
}

int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
{
	switch (which) {
	case PR_SPEC_STORE_BYPASS:
		return ssb_prctl_get(task);
	default:
		return -ENODEV;
	}
}

void x86_spec_ctrl_setup_ap(void)
{
	if (ibrs_inuse)
		x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);

	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
		x86_amd_rds_enable();
}

#ifdef CONFIG_SYSFS
ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
			char *buf, unsigned int bug)
{
	if (!boot_cpu_has_bug(bug))
		return sprintf(buf, "Not affected\n");

	switch (bug) {
	case X86_BUG_CPU_MELTDOWN:
		if (boot_cpu_has(X86_FEATURE_PTI))
			return sprintf(buf, "Mitigation: PTI\n");
		break;

	case X86_BUG_SPECTRE_V1:
		if (osb_is_enabled)
			return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");

	case X86_BUG_SPECTRE_V2:
		return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");

	case X86_BUG_SPEC_STORE_BYPASS:
		return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);

	default:
		break;
	}

	return sprintf(buf, "Vulnerable\n");
}

ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
			  char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
}

ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr,
			    char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
}

ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr,
			    char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
}

ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
}
#endif
Commit	Line	Data
1353ebb4	1	/*
1353ebb4 JF	2	* Copyright (C) 1994 Linus Torvalds
	3	*
	4	* Cyrix stuff, June 1998 by:
	5	* - Rafael R. Reilova (moved everything from head.S),
	6	* <rreilova@ececs.uc.edu>
	7	* - Channing Corn (tests & fixes),
	8	* - Andrew D. Balsa (code cleanup).
	9	*/
	10	#include <linux/init.h>
	11	#include <linux/utsname.h>
6d283d72	12	#include <linux/cpu.h>
86cdbc59	13	#include <linux/smp.h>
1de873cb TG	14	#include <linux/nospec.h>
1de873cb TG	15	#include <linux/prctl.h>
687cc97a	16
20b509bf	17	#include <asm/spec-ctrl.h>
687cc97a	18	#include <asm/cmdline.h>
91eb1b79	19	#include <asm/bugs.h>
1353ebb4	20	#include <asm/processor.h>
7ebad705	21	#include <asm/processor-flags.h>
952f07ec	22	#include <asm/fpu/internal.h>
1353ebb4 JF	23	#include <asm/msr.h>
	24	#include <asm/paravirt.h>
	25	#include <asm/alternative.h>
62a67e12	26	#include <asm/pgtable.h>
d1163651	27	#include <asm/set_memory.h>
12aa317c	28	#include <asm/intel-family.h>
1353ebb4	29
687cc97a	30	static void __init spectre_v2_select_mitigation(void);
ef68a13e	31	static void __init ssb_select_mitigation(void);
687cc97a	32
3ef956dd KRW	33	/*
	34	* Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
	35	* writes to SPEC_CTRL contain whatever reserved bits have been set.
	36	*/
0b35aca2	37	u64 __ro_after_init x86_spec_ctrl_base;
3ef956dd	38
ca6704cf KRW	39	/*
	40	* The vendor and possibly platform specific bits which can be modified in
	41	* x86_spec_ctrl_base.
	42	*/
	43	static u64 __ro_after_init x86_spec_ctrl_mask = ~SPEC_CTRL_IBRS;
	44
7c60cee4 KRW	45	/*
	46	* AMD specific MSR info for Speculative Store Bypass control.
	47	* x86_amd_ls_cfg_rds_mask is initialized in identify_boot_cpu().
	48	*/
	49	u64 __ro_after_init x86_amd_ls_cfg_base;
	50	u64 __ro_after_init x86_amd_ls_cfg_rds_mask;
	51
1353ebb4 JF	52	void __init check_bugs(void)
	53	{
	54	identify_boot_cpu();
55a36b65	55
62a67e12 BP	56	if (!IS_ENABLED(CONFIG_SMP)) {
	57	pr_info("CPU: ");
	58	print_cpu_info(&boot_cpu_data);
	59	}
	60
3ef956dd KRW	61	/*
3ef956dd KRW	62	* Read the SPEC_CTRL MSR to account for reserved bits which may
7c60cee4 KRW	63	* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
7c60cee4 KRW	64	* init code as it is not enumerated and depends on the family.
3ef956dd KRW	65	*/
	66	if (ibrs_inuse)
	67	rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
	68
687cc97a DW	69	/* Select the proper spectre mitigation before patching alternatives */
	70	spectre_v2_select_mitigation();
	71
ef68a13e KRW	72	/*
	73	* Select proper mitigation for any exposure to the Speculative Store
	74	* Bypass vulnerability.
	75	*/
	76	ssb_select_mitigation();
	77
62a67e12	78	#ifdef CONFIG_X86_32
55a36b65 BP	79	/*
	80	* Check whether we are able to run this kernel safely on SMP.
	81	*
	82	* - i386 is no longer supported.
	83	* - In order to run on anything without a TSC, we need to be
	84	* compiled for a i486.
	85	*/
	86	if (boot_cpu_data.x86 < 4)
	87	panic("Kernel requires i486+ for 'invlpg' and other features");
	88
bfe4bb15 MV	89	init_utsname()->machine[1] =
bfe4bb15 MV	90	'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
1353ebb4	91	alternative_instructions();
304bceda	92
4d164092	93	fpu__init_check_bugs();
62a67e12 BP	94	#else /* CONFIG_X86_64 */
	95	alternative_instructions();
	96
	97	/*
	98	* Make sure the first 2MB area is not mapped by huge pages
	99	* There are typically fixed size MTRRs in there and overlapping
	100	* MTRRs into large pages causes slow downs.
	101	*
	102	* Right now we don't do that with gbpages because there seems
	103	* very little benefit for that case.
	104	*/
	105	if (!direct_gbpages)
	106	set_memory_4k((unsigned long)__va(0), 1);
	107	#endif
1353ebb4	108	}
6d283d72	109
687cc97a DW	110	/* The kernel command line selection */
	111	enum spectre_v2_mitigation_cmd {
	112	SPECTRE_V2_CMD_NONE,
	113	SPECTRE_V2_CMD_AUTO,
	114	SPECTRE_V2_CMD_FORCE,
	115	SPECTRE_V2_CMD_RETPOLINE,
	116	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
	117	SPECTRE_V2_CMD_RETPOLINE_AMD,
	118	};
	119
	120	static const char *spectre_v2_strings[] = {
	121	[SPECTRE_V2_NONE] = "Vulnerable",
	122	[SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline",
	123	[SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline",
	124	[SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
	125	[SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
	126	};
	127
	128	#undef pr_fmt
	129	#define pr_fmt(fmt) "Spectre V2 mitigation: " fmt
	130
	131	static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
	132
3ef956dd KRW	133	void x86_spec_ctrl_set(u64 val)
3ef956dd KRW	134	{
ca6704cf	135	if (val & x86_spec_ctrl_mask)
3ef956dd KRW	136	WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
	137	else
	138	wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base \| val);
	139	}
	140	EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
	141
	142	u64 x86_spec_ctrl_get_default(void)
	143	{
0b35aca2 TG	144	u64 msrval = x86_spec_ctrl_base;
	145
	146	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
	147	msrval \|= rds_tif_to_spec_ctrl(current_thread_info()->flags);
	148	return msrval;
3ef956dd KRW	149	}
	150	EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
	151
fe170612 KRW	152	void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
fe170612 KRW	153	{
0b35aca2 TG	154	u64 host = x86_spec_ctrl_base;
0b35aca2 TG	155
fe170612 KRW	156	if (!ibrs_inuse)
fe170612 KRW	157	return;
0b35aca2 TG	158
	159	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
	160	host \|= rds_tif_to_spec_ctrl(current_thread_info()->flags);
	161
	162	if (host != guest_spec_ctrl)
fe170612 KRW	163	wrmsrl(MSR_IA32_SPEC_CTRL, guest_spec_ctrl);
	164	}
	165	EXPORT_SYMBOL_GPL(x86_spec_ctrl_set_guest);
	166
	167	void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
	168	{
0b35aca2 TG	169	u64 host = x86_spec_ctrl_base;
0b35aca2 TG	170
fe170612 KRW	171	if (!ibrs_inuse)
fe170612 KRW	172	return;
0b35aca2 TG	173
	174	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
	175	host \|= rds_tif_to_spec_ctrl(current_thread_info()->flags);
	176
	177	if (host != guest_spec_ctrl)
	178	wrmsrl(MSR_IA32_SPEC_CTRL, host);
fe170612 KRW	179	}
	180	EXPORT_SYMBOL_GPL(x86_spec_ctrl_restore_host);
	181
7c60cee4 KRW	182	static void x86_amd_rds_enable(void)
	183	{
	184	u64 msrval = x86_amd_ls_cfg_base \| x86_amd_ls_cfg_rds_mask;
	185
	186	if (boot_cpu_has(X86_FEATURE_AMD_RDS))
	187	wrmsrl(MSR_AMD64_LS_CFG, msrval);
	188	}
	189
687cc97a DW	190	static void __init spec2_print_if_insecure(const char *reason)
	191	{
	192	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
	193	pr_info("%s\n", reason);
	194	}
	195
	196	static void __init spec2_print_if_secure(const char *reason)
	197	{
	198	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
	199	pr_info("%s\n", reason);
	200	}
	201
	202	static inline bool retp_compiler(void)
	203	{
	204	return __is_defined(RETPOLINE);
	205	}
	206
	207	static inline bool match_option(const char arg, int arglen, const char opt)
	208	{
	209	int len = strlen(opt);
	210
	211	return len == arglen && !strncmp(arg, opt, len);
	212	}
	213
	214	static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
	215	{
	216	char arg[20];
	217	int ret;
	218
	219	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg,
	220	sizeof(arg));
	221	if (ret > 0) {
	222	if (match_option(arg, ret, "off")) {
	223	goto disable;
	224	} else if (match_option(arg, ret, "on")) {
	225	spec2_print_if_secure("force enabled on command line.");
	226	return SPECTRE_V2_CMD_FORCE;
	227	} else if (match_option(arg, ret, "retpoline")) {
	228	spec2_print_if_insecure("retpoline selected on command line.");
	229	return SPECTRE_V2_CMD_RETPOLINE;
	230	} else if (match_option(arg, ret, "retpoline,amd")) {
	231	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
	232	pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
	233	return SPECTRE_V2_CMD_AUTO;
	234	}
	235	spec2_print_if_insecure("AMD retpoline selected on command line.");
	236	return SPECTRE_V2_CMD_RETPOLINE_AMD;
	237	} else if (match_option(arg, ret, "retpoline,generic")) {
	238	spec2_print_if_insecure("generic retpoline selected on command line.");
	239	return SPECTRE_V2_CMD_RETPOLINE_GENERIC;
	240	} else if (match_option(arg, ret, "auto")) {
	241	return SPECTRE_V2_CMD_AUTO;
	242	}
	243	}
	244
	245	if (!cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
	246	return SPECTRE_V2_CMD_AUTO;
	247	disable:
	248	spec2_print_if_insecure("disabled on command line.");
	249	return SPECTRE_V2_CMD_NONE;
	250	}
	251
12aa317c DW	252	/* Check for Skylake-like CPUs (for RSB handling) */
	253	static bool __init is_skylake_era(void)
	254	{
	255	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	256	boot_cpu_data.x86 == 6) {
	257	switch (boot_cpu_data.x86_model) {
	258	case INTEL_FAM6_SKYLAKE_MOBILE:
	259	case INTEL_FAM6_SKYLAKE_DESKTOP:
	260	case INTEL_FAM6_SKYLAKE_X:
	261	case INTEL_FAM6_KABYLAKE_MOBILE:
	262	case INTEL_FAM6_KABYLAKE_DESKTOP:
	263	return true;
	264	}
	265	}
	266	return false;
	267	}
	268
687cc97a DW	269	static void __init spectre_v2_select_mitigation(void)
	270	{
	271	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
	272	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
	273
	274	/*
	275	* If the CPU is not affected and the command line mode is NONE or AUTO
	276	* then nothing to do.
	277	*/
	278	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
	279	(cmd == SPECTRE_V2_CMD_NONE \|\| cmd == SPECTRE_V2_CMD_AUTO))
	280	return;
	281
	282	switch (cmd) {
	283	case SPECTRE_V2_CMD_NONE:
	284	return;
	285
	286	case SPECTRE_V2_CMD_FORCE:
	287	/* FALLTRHU */
	288	case SPECTRE_V2_CMD_AUTO:
	289	goto retpoline_auto;
	290
	291	case SPECTRE_V2_CMD_RETPOLINE_AMD:
	292	if (IS_ENABLED(CONFIG_RETPOLINE))
	293	goto retpoline_amd;
	294	break;
	295	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
	296	if (IS_ENABLED(CONFIG_RETPOLINE))
	297	goto retpoline_generic;
	298	break;
	299	case SPECTRE_V2_CMD_RETPOLINE:
	300	if (IS_ENABLED(CONFIG_RETPOLINE))
	301	goto retpoline_auto;
	302	break;
	303	}
	304	pr_err("kernel not compiled with retpoline; no mitigation available!");
	305	return;
	306
	307	retpoline_auto:
	308	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
	309	retpoline_amd:
	310	if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
	311	pr_err("LFENCE not serializing. Switching to generic retpoline\n");
	312	goto retpoline_generic;
	313	}
	314	mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
	315	SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
	316	setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
	317	setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	318	} else {
	319	retpoline_generic:
	320	mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
	321	SPECTRE_V2_RETPOLINE_MINIMAL;
	322	setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	323	}
	324
	325	spectre_v2_enabled = mode;
	326	pr_info("%s\n", spectre_v2_strings[mode]);
12aa317c	327
86cdbc59 AW	328	pr_info("Speculation control IBPB %s IBRS %s",
	329	ibpb_supported ? "supported" : "not-supported",
	330	ibrs_supported ? "supported" : "not-supported");
	331
	332	/*
	333	* If we have a full retpoline mode and then disable IBPB in kernel mode
	334	* we do not require both.
	335	*/
	336	if (mode == SPECTRE_V2_RETPOLINE_AMD \|\|
	337	mode == SPECTRE_V2_RETPOLINE_GENERIC)
	338	{
	339	if (ibrs_supported) {
	340	pr_info("Retpoline compiled kernel. Defaulting IBRS to disabled");
	341	set_ibrs_disabled();
	342	if (!ibrs_inuse)
	343	sysctl_ibrs_enabled = 0;
	344	}
	345	}
	346
12aa317c DW	347	/*
	348	* If neither SMEP or KPTI are available, there is a risk of
	349	* hitting userspace addresses in the RSB after a context switch
	350	* from a shallow call stack to a deeper one. To prevent this fill
	351	* the entire RSB, even when using IBRS.
	352	*
	353	* Skylake era CPUs have a separate issue with underflow of the
	354	* RSB, when they will predict 'ret' targets from the generic BTB.
	355	* The proper mitigation for this is IBRS. If IBRS is not supported
	356	* or deactivated in favour of retpolines the RSB fill on context
	357	* switch is required.
	358	*/
	359	if ((!boot_cpu_has(X86_FEATURE_PTI) &&
	360	!boot_cpu_has(X86_FEATURE_SMEP)) \|\| is_skylake_era()) {
	361	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
	362	pr_info("Filling RSB on context switch\n");
	363	}
687cc97a DW	364	}
687cc97a DW	365
ef68a13e KRW	366	#undef pr_fmt
	367	#define pr_fmt(fmt) "Speculative Store Bypass: " fmt
	368
	369	static enum ssb_mitigation ssb_mode = SPEC_STORE_BYPASS_NONE;
	370
	371	/* The kernel command line selection */
	372	enum ssb_mitigation_cmd {
	373	SPEC_STORE_BYPASS_CMD_NONE,
	374	SPEC_STORE_BYPASS_CMD_AUTO,
	375	SPEC_STORE_BYPASS_CMD_ON,
1de873cb	376	SPEC_STORE_BYPASS_CMD_PRCTL,
ef68a13e KRW	377	};
	378
	379	static const char *ssb_strings[] = {
	380	[SPEC_STORE_BYPASS_NONE] = "Vulnerable",
1de873cb TG	381	[SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled",
1de873cb TG	382	[SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl"
ef68a13e KRW	383	};
	384
	385	static const struct {
	386	const char *option;
	387	enum ssb_mitigation_cmd cmd;
	388	} ssb_mitigation_options[] = {
1de873cb TG	389	{ "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */
	390	{ "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */
	391	{ "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */
	392	{ "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */
ef68a13e KRW	393	};
	394
	395	static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void)
	396	{
	397	enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO;
	398	char arg[20];
	399	int ret, i;
	400
	401	if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable")) {
	402	return SPEC_STORE_BYPASS_CMD_NONE;
	403	} else {
	404	ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable",
	405	arg, sizeof(arg));
	406	if (ret < 0)
	407	return SPEC_STORE_BYPASS_CMD_AUTO;
	408
	409	for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) {
	410	if (!match_option(arg, ret, ssb_mitigation_options[i].option))
	411	continue;
	412
	413	cmd = ssb_mitigation_options[i].cmd;
	414	break;
	415	}
	416
	417	if (i >= ARRAY_SIZE(ssb_mitigation_options)) {
	418	pr_err("unknown option (%s). Switching to AUTO select\n", arg);
	419	return SPEC_STORE_BYPASS_CMD_AUTO;
	420	}
	421	}
	422
	423	return cmd;
	424	}
	425
	426	static enum ssb_mitigation_cmd __init __ssb_select_mitigation(void)
	427	{
	428	enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE;
	429	enum ssb_mitigation_cmd cmd;
	430
	431	if (!boot_cpu_has(X86_FEATURE_RDS))
	432	return mode;
	433
	434	cmd = ssb_parse_cmdline();
	435	if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) &&
	436	(cmd == SPEC_STORE_BYPASS_CMD_NONE \|\|
	437	cmd == SPEC_STORE_BYPASS_CMD_AUTO))
	438	return mode;
	439
	440	switch (cmd) {
	441	case SPEC_STORE_BYPASS_CMD_AUTO:
1de873cb TG	442	/* Choose prctl as the default mode */
	443	mode = SPEC_STORE_BYPASS_PRCTL;
	444	break;
ef68a13e KRW	445	case SPEC_STORE_BYPASS_CMD_ON:
	446	mode = SPEC_STORE_BYPASS_DISABLE;
	447	break;
1de873cb TG	448	case SPEC_STORE_BYPASS_CMD_PRCTL:
	449	mode = SPEC_STORE_BYPASS_PRCTL;
	450	break;
ef68a13e KRW	451	case SPEC_STORE_BYPASS_CMD_NONE:
	452	break;
	453	}
	454
2b83aba8 KRW	455	/*
	456	* We have three CPU feature flags that are in play here:
	457	* - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
	458	* - X86_FEATURE_RDS - CPU is able to turn off speculative store bypass
	459	* - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation
	460	*/
1de873cb	461	if (mode == SPEC_STORE_BYPASS_DISABLE) {
ef68a13e	462	setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE);
2b83aba8 KRW	463	/*
	464	* Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD uses
	465	* a completely different MSR and bit dependent on family.
	466	*/
	467	switch (boot_cpu_data.x86_vendor) {
	468	case X86_VENDOR_INTEL:
	469	x86_spec_ctrl_base \|= SPEC_CTRL_RDS;
ca6704cf	470	x86_spec_ctrl_mask &= ~SPEC_CTRL_RDS;
2b83aba8 KRW	471	x86_spec_ctrl_set(SPEC_CTRL_RDS);
	472	break;
	473	case X86_VENDOR_AMD:
7c60cee4	474	x86_amd_rds_enable();
2b83aba8 KRW	475	break;
	476	}
	477	}
	478
ef68a13e KRW	479	return mode;
	480	}
	481
	482	static void ssb_select_mitigation()
	483	{
	484	ssb_mode = __ssb_select_mitigation();
	485
	486	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
	487	pr_info("%s\n", ssb_strings[ssb_mode]);
	488	}
	489
687cc97a DW	490	#undef pr_fmt
687cc97a DW	491
bd90e222	492	static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl)
1de873cb	493	{
bd90e222	494	bool rds = !!test_tsk_thread_flag(task, TIF_RDS);
1de873cb TG	495
	496	if (ssb_mode != SPEC_STORE_BYPASS_PRCTL)
	497	return -ENXIO;
	498
	499	if (ctrl == PR_SPEC_ENABLE)
bd90e222	500	clear_tsk_thread_flag(task, TIF_RDS);
1de873cb	501	else
bd90e222	502	set_tsk_thread_flag(task, TIF_RDS);
1de873cb	503
bd90e222 KC	504	/*
	505	* If being set on non-current task, delay setting the CPU
	506	* mitigation until it is next scheduled.
	507	*/
	508	if (task == current && rds != !!test_tsk_thread_flag(task, TIF_RDS))
1de873cb TG	509	speculative_store_bypass_update();
	510
	511	return 0;
	512	}
	513
bd90e222	514	static int ssb_prctl_get(struct task_struct *task)
1de873cb TG	515	{
	516	switch (ssb_mode) {
	517	case SPEC_STORE_BYPASS_DISABLE:
	518	return PR_SPEC_DISABLE;
	519	case SPEC_STORE_BYPASS_PRCTL:
bd90e222	520	if (test_tsk_thread_flag(task, TIF_RDS))
1de873cb TG	521	return PR_SPEC_PRCTL \| PR_SPEC_DISABLE;
	522	return PR_SPEC_PRCTL \| PR_SPEC_ENABLE;
	523	default:
	524	if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS))
	525	return PR_SPEC_ENABLE;
	526	return PR_SPEC_NOT_AFFECTED;
	527	}
	528	}
	529
bd90e222 KC	530	int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which,
bd90e222 KC	531	unsigned long ctrl)
1de873cb TG	532	{
	533	if (ctrl != PR_SPEC_ENABLE && ctrl != PR_SPEC_DISABLE)
	534	return -ERANGE;
	535
	536	switch (which) {
	537	case PR_SPEC_STORE_BYPASS:
bd90e222	538	return ssb_prctl_set(task, ctrl);
1de873cb TG	539	default:
	540	return -ENODEV;
	541	}
	542	}
	543
bd90e222	544	int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
1de873cb TG	545	{
	546	switch (which) {
	547	case PR_SPEC_STORE_BYPASS:
bd90e222	548	return ssb_prctl_get(task);
1de873cb TG	549	default:
	550	return -ENODEV;
	551	}
	552	}
	553
2b83aba8 KRW	554	void x86_spec_ctrl_setup_ap(void)
	555	{
	556	if (ibrs_inuse)
ca6704cf	557	x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
7c60cee4 KRW	558
	559	if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
	560	x86_amd_rds_enable();
2b83aba8 KRW	561	}
2b83aba8 KRW	562
6d283d72	563	#ifdef CONFIG_SYSFS
8f04f8ba KRW	564	ssize_t cpu_show_common(struct device dev, struct device_attribute attr,
8f04f8ba KRW	565	char *buf, unsigned int bug)
6d283d72	566	{
8f04f8ba	567	if (!boot_cpu_has_bug(bug))
6d283d72	568	return sprintf(buf, "Not affected\n");
8f04f8ba KRW	569
	570	switch (bug) {
	571	case X86_BUG_CPU_MELTDOWN:
	572	if (boot_cpu_has(X86_FEATURE_PTI))
	573	return sprintf(buf, "Mitigation: PTI\n");
	574	break;
	575
	576	case X86_BUG_SPECTRE_V1:
	577	if (osb_is_enabled)
	578	return sprintf(buf, "Mitigation: OSB (observable speculation barrier, Intel v6)\n");
	579
	580	case X86_BUG_SPECTRE_V2:
	581	return sprintf(buf, "%s%s\n", spectre_v2_strings[spectre_v2_enabled], ibpb_inuse ? ", IBPB (Intel v4)" : "");
	582
ef68a13e KRW	583	case X86_BUG_SPEC_STORE_BYPASS:
	584	return sprintf(buf, "%s\n", ssb_strings[ssb_mode]);
	585
8f04f8ba KRW	586	default:
	587	break;
	588	}
	589
6d283d72 TG	590	return sprintf(buf, "Vulnerable\n");
	591	}
	592
8f04f8ba KRW	593	ssize_t cpu_show_meltdown(struct device dev, struct device_attribute attr,
8f04f8ba KRW	594	char *buf)
6d283d72	595	{
8f04f8ba	596	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
6d283d72 TG	597	}
6d283d72 TG	598
8f04f8ba KRW	599	ssize_t cpu_show_spectre_v1(struct device dev, struct device_attribute attr,
8f04f8ba KRW	600	char *buf)
6d283d72	601	{
8f04f8ba KRW	602	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
8f04f8ba KRW	603	}
687cc97a	604
8f04f8ba KRW	605	ssize_t cpu_show_spectre_v2(struct device dev, struct device_attribute attr,
	606	char *buf)
	607	{
	608	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
6d283d72	609	}
abe4b60b KRW	610
	611	ssize_t cpu_show_spec_store_bypass(struct device dev, struct device_attribute attr, char *buf)
	612	{
	613	return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS);
	614	}
6d283d72	615	#endif