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Commit | Line | Data |
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c767a54b | 1 | /* |
4cedb334 GOC |
2 | * x86 SMP booting functions |
3 | * | |
87c6fe26 | 4 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 5 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
6 | * Copyright 2001 Andi Kleen, SuSE Labs. |
7 | * | |
8 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
9 | * whom a great many thanks are extended. | |
10 | * | |
11 | * Thanks to Intel for making available several different Pentium, | |
12 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
13 | * Original development of Linux SMP code supported by Caldera. | |
14 | * | |
15 | * This code is released under the GNU General Public License version 2 or | |
16 | * later. | |
17 | * | |
18 | * Fixes | |
19 | * Felix Koop : NR_CPUS used properly | |
20 | * Jose Renau : Handle single CPU case. | |
21 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
22 | * Greg Wright : Fix for kernel stacks panic. | |
23 | * Erich Boleyn : MP v1.4 and additional changes. | |
24 | * Matthias Sattler : Changes for 2.1 kernel map. | |
25 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
26 | * Michael Chastain : Change trampoline.S to gnu as. | |
27 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
28 | * Ingo Molnar : Added APIC timers, based on code | |
29 | * from Jose Renau | |
30 | * Ingo Molnar : various cleanups and rewrites | |
31 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
32 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
33 | * Andi Kleen : Changed for SMP boot into long mode. | |
34 | * Martin J. Bligh : Added support for multi-quad systems | |
35 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
36 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
37 | * Andi Kleen : Converted to new state machine. | |
38 | * Ashok Raj : CPU hotplug support | |
39 | * Glauber Costa : i386 and x86_64 integration | |
40 | */ | |
41 | ||
c767a54b JP |
42 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
43 | ||
68a1c3f8 GC |
44 | #include <linux/init.h> |
45 | #include <linux/smp.h> | |
186f4360 | 46 | #include <linux/export.h> |
70708a18 | 47 | #include <linux/sched.h> |
105ab3d8 | 48 | #include <linux/sched/topology.h> |
ef8bd77f | 49 | #include <linux/sched/hotplug.h> |
68db0cf1 | 50 | #include <linux/sched/task_stack.h> |
69c18c15 | 51 | #include <linux/percpu.h> |
91718e8d | 52 | #include <linux/bootmem.h> |
cb3c8b90 GOC |
53 | #include <linux/err.h> |
54 | #include <linux/nmi.h> | |
69575d38 | 55 | #include <linux/tboot.h> |
35f720c5 | 56 | #include <linux/stackprotector.h> |
5a0e3ad6 | 57 | #include <linux/gfp.h> |
1a022e3f | 58 | #include <linux/cpuidle.h> |
69c18c15 | 59 | |
8aef135c | 60 | #include <asm/acpi.h> |
cb3c8b90 | 61 | #include <asm/desc.h> |
69c18c15 GC |
62 | #include <asm/nmi.h> |
63 | #include <asm/irq.h> | |
48927bbb | 64 | #include <asm/realmode.h> |
69c18c15 GC |
65 | #include <asm/cpu.h> |
66 | #include <asm/numa.h> | |
cb3c8b90 GOC |
67 | #include <asm/pgtable.h> |
68 | #include <asm/tlbflush.h> | |
69 | #include <asm/mtrr.h> | |
ea530692 | 70 | #include <asm/mwait.h> |
7b6aa335 | 71 | #include <asm/apic.h> |
7167d08e | 72 | #include <asm/io_apic.h> |
78f7f1e5 | 73 | #include <asm/fpu/internal.h> |
569712b2 | 74 | #include <asm/setup.h> |
bdbcdd48 | 75 | #include <asm/uv/uv.h> |
cb3c8b90 | 76 | #include <linux/mc146818rtc.h> |
b81bb373 | 77 | #include <asm/i8259.h> |
48927bbb | 78 | #include <asm/realmode.h> |
646e29a1 | 79 | #include <asm/misc.h> |
159e800c | 80 | #include <asm/spec-ctrl.h> |
704cf01d | 81 | #include <asm/microcode.h> |
48927bbb | 82 | |
a355352b GC |
83 | /* Number of siblings per CPU package */ |
84 | int smp_num_siblings = 1; | |
85 | EXPORT_SYMBOL(smp_num_siblings); | |
86 | ||
87 | /* Last level cache ID of each logical CPU */ | |
0816b0f0 | 88 | DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; |
a355352b | 89 | |
a355352b | 90 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 91 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
92 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
93 | ||
94 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 95 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
96 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
97 | ||
0816b0f0 | 98 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 99 | |
a355352b | 100 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 101 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 102 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 103 | |
1f12e32f TG |
104 | /* Logical package management. We might want to allocate that dynamically */ |
105 | static int *physical_to_logical_pkg __read_mostly; | |
106 | static unsigned long *physical_package_map __read_mostly;; | |
1f12e32f TG |
107 | static unsigned int max_physical_pkg_id __read_mostly; |
108 | unsigned int __max_logical_packages __read_mostly; | |
109 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 110 | static unsigned int logical_packages __read_mostly; |
1f12e32f | 111 | |
70b8301f AK |
112 | /* Maximum number of SMT threads on any online core */ |
113 | int __max_smt_threads __read_mostly; | |
114 | ||
7d25127c TC |
115 | /* Flag to indicate if a complete sched domain rebuild is required */ |
116 | bool x86_topology_update; | |
117 | ||
118 | int arch_update_cpu_topology(void) | |
119 | { | |
120 | int retval = x86_topology_update; | |
121 | ||
122 | x86_topology_update = false; | |
123 | return retval; | |
124 | } | |
125 | ||
f77aa308 TG |
126 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
127 | { | |
128 | unsigned long flags; | |
129 | ||
130 | spin_lock_irqsave(&rtc_lock, flags); | |
131 | CMOS_WRITE(0xa, 0xf); | |
132 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
133 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
134 | start_eip >> 4; | |
f77aa308 TG |
135 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
136 | start_eip & 0xf; | |
f77aa308 TG |
137 | } |
138 | ||
139 | static inline void smpboot_restore_warm_reset_vector(void) | |
140 | { | |
141 | unsigned long flags; | |
142 | ||
f77aa308 TG |
143 | /* |
144 | * Paranoid: Set warm reset code and vector here back | |
145 | * to default values. | |
146 | */ | |
147 | spin_lock_irqsave(&rtc_lock, flags); | |
148 | CMOS_WRITE(0, 0xf); | |
149 | spin_unlock_irqrestore(&rtc_lock, flags); | |
150 | ||
151 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
152 | } | |
153 | ||
cb3c8b90 | 154 | /* |
30106c17 FY |
155 | * Report back to the Boot Processor during boot time or to the caller processor |
156 | * during CPU online. | |
cb3c8b90 | 157 | */ |
148f9bb8 | 158 | static void smp_callin(void) |
cb3c8b90 GOC |
159 | { |
160 | int cpuid, phys_id; | |
cb3c8b90 GOC |
161 | |
162 | /* | |
163 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
164 | * cpu_callout_mask guarantees we don't get here before |
165 | * an INIT_deassert IPI reaches our local APIC, so it is | |
166 | * now safe to touch our local APIC. | |
cb3c8b90 | 167 | */ |
e1c467e6 | 168 | cpuid = smp_processor_id(); |
cb3c8b90 GOC |
169 | |
170 | /* | |
171 | * (This works even if the APIC is not enabled.) | |
172 | */ | |
4c9961d5 | 173 | phys_id = read_apic_id(); |
cb3c8b90 GOC |
174 | |
175 | /* | |
176 | * the boot CPU has finished the init stage and is spinning | |
177 | * on callin_map until we finish. We are free to set up this | |
178 | * CPU, first the APIC. (this is probably redundant on most | |
179 | * boards) | |
180 | */ | |
05f7e46d | 181 | apic_ap_setup(); |
cb3c8b90 | 182 | |
b565201c JS |
183 | /* |
184 | * Save our processor parameters. Note: this information | |
185 | * is needed for clock calibration. | |
186 | */ | |
187 | smp_store_cpu_info(cpuid); | |
188 | ||
a55b5204 PT |
189 | /* |
190 | * The topology information must be up to date before | |
191 | * calibrate_delay() and notify_cpu_starting(). | |
192 | */ | |
193 | set_cpu_sibling_map(raw_smp_processor_id()); | |
194 | ||
cb3c8b90 GOC |
195 | /* |
196 | * Get our bogomips. | |
b565201c JS |
197 | * Update loops_per_jiffy in cpu_data. Previous call to |
198 | * smp_store_cpu_info() stored a value that is close but not as | |
199 | * accurate as the value just calculated. | |
cb3c8b90 | 200 | */ |
cb3c8b90 | 201 | calibrate_delay(); |
b565201c | 202 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 203 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 204 | |
5ef428c4 AK |
205 | wmb(); |
206 | ||
85257024 PZ |
207 | notify_cpu_starting(cpuid); |
208 | ||
cb3c8b90 GOC |
209 | /* |
210 | * Allow the master to continue. | |
211 | */ | |
c2d1cec1 | 212 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
213 | } |
214 | ||
e1c467e6 FY |
215 | static int cpu0_logical_apicid; |
216 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
217 | /* |
218 | * Activate a secondary processor. | |
219 | */ | |
148f9bb8 | 220 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
221 | { |
222 | /* | |
0e6a37a4 AL |
223 | * Don't put *anything* except direct CPU state initialization |
224 | * before cpu_init(), SMP booting is too fragile that we want to | |
225 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 226 | */ |
babace1d | 227 | if (IS_ENABLED(CONFIG_X86_64) && boot_cpu_has(X86_FEATURE_PCID)) |
0e6a37a4 | 228 | __write_cr4(__read_cr4() | X86_CR4_PCIDE); |
b40827fa | 229 | cpu_init(); |
df156f90 | 230 | x86_cpuinit.early_percpu_clock_init(); |
b40827fa BP |
231 | preempt_disable(); |
232 | smp_callin(); | |
fd89a137 | 233 | |
e1c467e6 FY |
234 | enable_start_cpu0 = 0; |
235 | ||
fd89a137 | 236 | #ifdef CONFIG_X86_32 |
b40827fa | 237 | /* switch away from the initial page table */ |
fd89a137 JR |
238 | load_cr3(swapper_pg_dir); |
239 | __flush_tlb_all(); | |
240 | #endif | |
241 | ||
bbc2ff6a GOC |
242 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
243 | barrier(); | |
244 | /* | |
245 | * Check TSC synchronization with the BP: | |
246 | */ | |
247 | check_tsc_sync_target(); | |
248 | ||
bbc2ff6a | 249 | /* |
5a3f75e3 TG |
250 | * Lock vector_lock and initialize the vectors on this cpu |
251 | * before setting the cpu online. We must set it online with | |
252 | * vector_lock held to prevent a concurrent setup/teardown | |
253 | * from seeing a half valid vector space. | |
bbc2ff6a | 254 | */ |
d388e5fd | 255 | lock_vector_lock(); |
5a3f75e3 | 256 | setup_vector_irq(smp_processor_id()); |
c2d1cec1 | 257 | set_cpu_online(smp_processor_id(), true); |
d388e5fd | 258 | unlock_vector_lock(); |
2a442c9c | 259 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 260 | x86_platform.nmi_init(); |
bbc2ff6a | 261 | |
0cefa5b9 MS |
262 | /* enable local interrupts */ |
263 | local_irq_enable(); | |
264 | ||
35f720c5 JP |
265 | /* to prevent fake stack check failure in clock setup */ |
266 | boot_init_stack_canary(); | |
0cefa5b9 | 267 | |
736decac | 268 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
269 | |
270 | wmb(); | |
fc6d73d6 | 271 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
bbc2ff6a GOC |
272 | } |
273 | ||
9d85eb91 TG |
274 | /** |
275 | * topology_update_package_map - Update the physical to logical package map | |
276 | * @pkg: The physical package id as retrieved via CPUID | |
277 | * @cpu: The cpu for which this is updated | |
278 | */ | |
279 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 280 | { |
9d85eb91 | 281 | unsigned int new; |
1f12e32f TG |
282 | |
283 | /* Called from early boot ? */ | |
284 | if (!physical_package_map) | |
285 | return 0; | |
286 | ||
287 | if (pkg >= max_physical_pkg_id) | |
288 | return -EINVAL; | |
289 | ||
290 | /* Set the logical package id */ | |
291 | if (test_and_set_bit(pkg, physical_package_map)) | |
292 | goto found; | |
293 | ||
9d85eb91 TG |
294 | if (logical_packages >= __max_logical_packages) { |
295 | pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", | |
296 | logical_packages, cpu, __max_logical_packages); | |
1f12e32f TG |
297 | return -ENOSPC; |
298 | } | |
7b0501b1 JO |
299 | |
300 | new = logical_packages++; | |
9d85eb91 TG |
301 | if (new != pkg) { |
302 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
303 | cpu, pkg, new); | |
304 | } | |
1f12e32f TG |
305 | physical_to_logical_pkg[pkg] = new; |
306 | ||
307 | found: | |
308 | cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; | |
309 | return 0; | |
310 | } | |
311 | ||
312 | /** | |
313 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
314 | * | |
315 | * Returns logical package id or -1 if not found | |
316 | */ | |
317 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
318 | { | |
319 | if (phys_pkg >= max_physical_pkg_id) | |
320 | return -1; | |
321 | return physical_to_logical_pkg[phys_pkg]; | |
322 | } | |
323 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
324 | ||
9d85eb91 | 325 | static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) |
1f12e32f | 326 | { |
9d85eb91 | 327 | unsigned int ncpus; |
1f12e32f TG |
328 | size_t size; |
329 | ||
330 | /* | |
331 | * Today neither Intel nor AMD support heterogenous systems. That | |
332 | * might change in the future.... | |
63d1e995 PZ |
333 | * |
334 | * While ideally we'd want '* smp_num_siblings' in the below @ncpus | |
335 | * computation, this won't actually work since some Intel BIOSes | |
336 | * report inconsistent HT data when they disable HT. | |
337 | * | |
338 | * In particular, they reduce the APIC-IDs to only include the cores, | |
339 | * but leave the CPUID topology to say there are (2) siblings. | |
340 | * This means we don't know how many threads there will be until | |
341 | * after the APIC enumeration. | |
342 | * | |
343 | * By not including this we'll sometimes over-estimate the number of | |
344 | * logical packages by the amount of !present siblings, but this is | |
345 | * still better than MAX_LOCAL_APIC. | |
3e8db224 TG |
346 | * |
347 | * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited | |
348 | * on the command line leading to a similar issue as the HT disable | |
349 | * problem because the hyperthreads are usually enumerated after the | |
350 | * primary cores. | |
1f12e32f | 351 | */ |
63d1e995 | 352 | ncpus = boot_cpu_data.x86_max_cores; |
56402d63 TG |
353 | if (!ncpus) { |
354 | pr_warn("x86_max_cores == zero !?!?"); | |
355 | ncpus = 1; | |
356 | } | |
357 | ||
3e8db224 | 358 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
7b0501b1 | 359 | logical_packages = 0; |
1f12e32f TG |
360 | |
361 | /* | |
362 | * Possibly larger than what we need as the number of apic ids per | |
363 | * package can be smaller than the actual used apic ids. | |
364 | */ | |
365 | max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); | |
366 | size = max_physical_pkg_id * sizeof(unsigned int); | |
367 | physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); | |
368 | memset(physical_to_logical_pkg, 0xff, size); | |
369 | size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); | |
370 | physical_package_map = kzalloc(size, GFP_KERNEL); | |
1f12e32f | 371 | |
7b0501b1 | 372 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
9d85eb91 TG |
373 | |
374 | topology_update_package_map(c->phys_proc_id, cpu); | |
1f12e32f TG |
375 | } |
376 | ||
30106c17 FY |
377 | void __init smp_store_boot_cpu_info(void) |
378 | { | |
379 | int id = 0; /* CPU 0 */ | |
380 | struct cpuinfo_x86 *c = &cpu_data(id); | |
381 | ||
382 | *c = boot_cpu_data; | |
383 | c->cpu_index = id; | |
9d85eb91 | 384 | smp_init_package_map(c, id); |
30106c17 FY |
385 | } |
386 | ||
1d89a7f0 GOC |
387 | /* |
388 | * The bootstrap kernel entry code has set these up. Save them for | |
389 | * a given CPU | |
390 | */ | |
148f9bb8 | 391 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
392 | { |
393 | struct cpuinfo_x86 *c = &cpu_data(id); | |
394 | ||
b3d7336d | 395 | *c = boot_cpu_data; |
1d89a7f0 | 396 | c->cpu_index = id; |
30106c17 FY |
397 | /* |
398 | * During boot time, CPU0 has this setup already. Save the info when | |
399 | * bringing up AP or offlined CPU0. | |
400 | */ | |
401 | identify_secondary_cpu(c); | |
1d89a7f0 GOC |
402 | } |
403 | ||
cebf15eb DH |
404 | static bool |
405 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
406 | { | |
407 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
408 | ||
409 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
410 | } | |
411 | ||
148f9bb8 | 412 | static bool |
316ad248 | 413 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 414 | { |
316ad248 PZ |
415 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
416 | ||
cebf15eb | 417 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
418 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
419 | "[node: %d != %d]. Ignoring dependency.\n", | |
420 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
421 | } | |
422 | ||
7d79a7bd | 423 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 424 | do { \ |
7d79a7bd BG |
425 | cpumask_set_cpu((c1), mfunc(c2)); \ |
426 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
427 | } while (0) |
428 | ||
148f9bb8 | 429 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 430 | { |
362f924b | 431 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
432 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
433 | ||
434 | if (c->phys_proc_id == o->phys_proc_id && | |
79a8b9aa BP |
435 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
436 | if (c->cpu_core_id == o->cpu_core_id) | |
437 | return topology_sane(c, o, "smt"); | |
438 | ||
439 | if ((c->cu_id != 0xff) && | |
440 | (o->cu_id != 0xff) && | |
441 | (c->cu_id == o->cu_id)) | |
442 | return topology_sane(c, o, "smt"); | |
443 | } | |
316ad248 PZ |
444 | |
445 | } else if (c->phys_proc_id == o->phys_proc_id && | |
446 | c->cpu_core_id == o->cpu_core_id) { | |
447 | return topology_sane(c, o, "smt"); | |
448 | } | |
449 | ||
450 | return false; | |
451 | } | |
452 | ||
148f9bb8 | 453 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
454 | { |
455 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
456 | ||
457 | if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && | |
458 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) | |
459 | return topology_sane(c, o, "llc"); | |
460 | ||
461 | return false; | |
d4fbe4f0 AH |
462 | } |
463 | ||
cebf15eb DH |
464 | /* |
465 | * Unlike the other levels, we do not enforce keeping a | |
466 | * multicore group inside a NUMA node. If this happens, we will | |
467 | * discard the MC level of the topology later. | |
468 | */ | |
469 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
316ad248 | 470 | { |
cebf15eb DH |
471 | if (c->phys_proc_id == o->phys_proc_id) |
472 | return true; | |
316ad248 PZ |
473 | return false; |
474 | } | |
1d89a7f0 | 475 | |
d3d37d85 TC |
476 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
477 | static inline int x86_sched_itmt_flags(void) | |
478 | { | |
479 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
480 | } | |
481 | ||
482 | #ifdef CONFIG_SCHED_MC | |
483 | static int x86_core_flags(void) | |
484 | { | |
485 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
486 | } | |
487 | #endif | |
488 | #ifdef CONFIG_SCHED_SMT | |
489 | static int x86_smt_flags(void) | |
490 | { | |
491 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
492 | } | |
493 | #endif | |
494 | #endif | |
495 | ||
8f37961c | 496 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 497 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 498 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
499 | #endif |
500 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 501 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
502 | #endif |
503 | { NULL, }, | |
504 | }; | |
8f37961c TC |
505 | |
506 | static struct sched_domain_topology_level x86_topology[] = { | |
507 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 508 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
509 | #endif |
510 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 511 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
512 | #endif |
513 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
514 | { NULL, }, | |
515 | }; | |
516 | ||
cebf15eb | 517 | /* |
8f37961c TC |
518 | * Set if a package/die has multiple NUMA nodes inside. |
519 | * AMD Magny-Cours and Intel Cluster-on-Die have this. | |
cebf15eb | 520 | */ |
8f37961c | 521 | static bool x86_has_numa_in_package; |
cebf15eb | 522 | |
148f9bb8 | 523 | void set_cpu_sibling_map(int cpu) |
768d9505 | 524 | { |
316ad248 | 525 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 526 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 527 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 528 | struct cpuinfo_x86 *o; |
70b8301f | 529 | int i, threads; |
768d9505 | 530 | |
c2d1cec1 | 531 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 532 | |
b0bc225d | 533 | if (!has_mp) { |
7d79a7bd | 534 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 535 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 536 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
768d9505 GC |
537 | c->booted_cores = 1; |
538 | return; | |
539 | } | |
540 | ||
c2d1cec1 | 541 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
542 | o = &cpu_data(i); |
543 | ||
544 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 545 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 546 | |
b0bc225d | 547 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 548 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 549 | |
ceb1cbac KB |
550 | } |
551 | ||
552 | /* | |
553 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 554 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
555 | */ |
556 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
557 | o = &cpu_data(i); | |
558 | ||
cebf15eb | 559 | if ((i == cpu) || (has_mp && match_die(c, o))) { |
7d79a7bd | 560 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 561 | |
768d9505 GC |
562 | /* |
563 | * Does this new cpu bringup a new core? | |
564 | */ | |
7d79a7bd BG |
565 | if (cpumask_weight( |
566 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
567 | /* |
568 | * for each core in package, increment | |
569 | * the booted_cores for this new cpu | |
570 | */ | |
7d79a7bd BG |
571 | if (cpumask_first( |
572 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
573 | c->booted_cores++; |
574 | /* | |
575 | * increment the core count for all | |
576 | * the other cpus in this package | |
577 | */ | |
578 | if (i != cpu) | |
579 | cpu_data(i).booted_cores++; | |
580 | } else if (i != cpu && !c->booted_cores) | |
581 | c->booted_cores = cpu_data(i).booted_cores; | |
582 | } | |
728e5653 | 583 | if (match_die(c, o) && !topology_same_node(c, o)) |
8f37961c | 584 | x86_has_numa_in_package = true; |
768d9505 | 585 | } |
70b8301f AK |
586 | |
587 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
588 | if (threads > __max_smt_threads) | |
589 | __max_smt_threads = threads; | |
768d9505 GC |
590 | } |
591 | ||
70708a18 | 592 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 593 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 594 | { |
9f646389 | 595 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
596 | } |
597 | ||
a4928cff | 598 | static void impress_friends(void) |
904541e2 GOC |
599 | { |
600 | int cpu; | |
601 | unsigned long bogosum = 0; | |
602 | /* | |
603 | * Allow the user to impress friends. | |
604 | */ | |
c767a54b | 605 | pr_debug("Before bogomips\n"); |
904541e2 | 606 | for_each_possible_cpu(cpu) |
c2d1cec1 | 607 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 608 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 609 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 610 | num_online_cpus(), |
904541e2 GOC |
611 | bogosum/(500000/HZ), |
612 | (bogosum/(5000/HZ))%100); | |
613 | ||
c767a54b | 614 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
615 | } |
616 | ||
569712b2 | 617 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
618 | { |
619 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 620 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
621 | int timeout; |
622 | u32 status; | |
623 | ||
c767a54b | 624 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
625 | |
626 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 627 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
628 | |
629 | /* | |
630 | * Wait for idle. | |
631 | */ | |
632 | status = safe_apic_wait_icr_idle(); | |
633 | if (status) | |
c767a54b | 634 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 635 | |
1b374e4d | 636 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
637 | |
638 | timeout = 0; | |
639 | do { | |
640 | udelay(100); | |
641 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
642 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
643 | ||
644 | switch (status) { | |
645 | case APIC_ICR_RR_VALID: | |
646 | status = apic_read(APIC_RRR); | |
c767a54b | 647 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
648 | break; |
649 | default: | |
c767a54b | 650 | pr_cont("failed\n"); |
cb3c8b90 GOC |
651 | } |
652 | } | |
653 | } | |
654 | ||
d68921f9 LB |
655 | /* |
656 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
657 | * that there should be a 10ms delay between the BSP asserting INIT | |
658 | * and de-asserting INIT, when starting a remote processor. | |
659 | * But that slows boot and resume on modern processors, which include | |
660 | * many cores and don't require that delay. | |
661 | * | |
662 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 663 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
664 | */ |
665 | #define UDELAY_10MS_DEFAULT 10000 | |
666 | ||
656279a1 | 667 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
668 | |
669 | static int __init cpu_init_udelay(char *str) | |
670 | { | |
671 | get_option(&str, &init_udelay); | |
672 | ||
673 | return 0; | |
674 | } | |
675 | early_param("cpu_init_udelay", cpu_init_udelay); | |
676 | ||
1a744cb3 LB |
677 | static void __init smp_quirk_init_udelay(void) |
678 | { | |
679 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 680 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
681 | return; |
682 | ||
683 | /* if modern processor, use no delay */ | |
684 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
656279a1 | 685 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 686 | init_udelay = 0; |
656279a1 LB |
687 | return; |
688 | } | |
f1ccd249 LB |
689 | /* else, use legacy delay */ |
690 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
691 | } |
692 | ||
cb3c8b90 GOC |
693 | /* |
694 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
695 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
696 | * won't ... remember to clear down the APIC, etc later. | |
697 | */ | |
148f9bb8 | 698 | int |
e1c467e6 | 699 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
700 | { |
701 | unsigned long send_status, accept_status = 0; | |
702 | int maxlvt; | |
703 | ||
704 | /* Target chip */ | |
cb3c8b90 GOC |
705 | /* Boot on the stack */ |
706 | /* Kick the second */ | |
e1c467e6 | 707 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 708 | |
cfc1b9a6 | 709 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
710 | send_status = safe_apic_wait_icr_idle(); |
711 | ||
712 | /* | |
713 | * Give the other CPU some time to accept the IPI. | |
714 | */ | |
715 | udelay(200); | |
cff9ab2b | 716 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
717 | maxlvt = lapic_get_maxlvt(); |
718 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
719 | apic_write(APIC_ESR, 0); | |
720 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
721 | } | |
c767a54b | 722 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
723 | |
724 | if (send_status) | |
c767a54b | 725 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 726 | if (accept_status) |
c767a54b | 727 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
728 | |
729 | return (send_status | accept_status); | |
730 | } | |
cb3c8b90 | 731 | |
148f9bb8 | 732 | static int |
569712b2 | 733 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 734 | { |
f5d6a52f | 735 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
736 | int maxlvt, num_starts, j; |
737 | ||
593f4a78 MR |
738 | maxlvt = lapic_get_maxlvt(); |
739 | ||
cb3c8b90 GOC |
740 | /* |
741 | * Be paranoid about clearing APIC errors. | |
742 | */ | |
cff9ab2b | 743 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
744 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
745 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
746 | apic_read(APIC_ESR); |
747 | } | |
748 | ||
c767a54b | 749 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
750 | |
751 | /* | |
752 | * Turn INIT on target chip | |
753 | */ | |
cb3c8b90 GOC |
754 | /* |
755 | * Send IPI | |
756 | */ | |
1b374e4d SS |
757 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
758 | phys_apicid); | |
cb3c8b90 | 759 | |
cfc1b9a6 | 760 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
761 | send_status = safe_apic_wait_icr_idle(); |
762 | ||
7cb68598 | 763 | udelay(init_udelay); |
cb3c8b90 | 764 | |
c767a54b | 765 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
766 | |
767 | /* Target chip */ | |
cb3c8b90 | 768 | /* Send IPI */ |
1b374e4d | 769 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 770 | |
cfc1b9a6 | 771 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
772 | send_status = safe_apic_wait_icr_idle(); |
773 | ||
774 | mb(); | |
cb3c8b90 GOC |
775 | |
776 | /* | |
777 | * Should we send STARTUP IPIs ? | |
778 | * | |
779 | * Determine this based on the APIC version. | |
780 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
781 | */ | |
cff9ab2b | 782 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
783 | num_starts = 2; |
784 | else | |
785 | num_starts = 0; | |
786 | ||
cb3c8b90 GOC |
787 | /* |
788 | * Run STARTUP IPI loop. | |
789 | */ | |
c767a54b | 790 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 791 | |
cb3c8b90 | 792 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 793 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
794 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
795 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 796 | apic_read(APIC_ESR); |
c767a54b | 797 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
798 | |
799 | /* | |
800 | * STARTUP IPI | |
801 | */ | |
802 | ||
803 | /* Target chip */ | |
cb3c8b90 GOC |
804 | /* Boot on the stack */ |
805 | /* Kick the second */ | |
1b374e4d SS |
806 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
807 | phys_apicid); | |
cb3c8b90 GOC |
808 | |
809 | /* | |
810 | * Give the other CPU some time to accept the IPI. | |
811 | */ | |
fcafddec LB |
812 | if (init_udelay == 0) |
813 | udelay(10); | |
814 | else | |
a9bcaa02 | 815 | udelay(300); |
cb3c8b90 | 816 | |
c767a54b | 817 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 818 | |
cfc1b9a6 | 819 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
820 | send_status = safe_apic_wait_icr_idle(); |
821 | ||
822 | /* | |
823 | * Give the other CPU some time to accept the IPI. | |
824 | */ | |
fcafddec LB |
825 | if (init_udelay == 0) |
826 | udelay(10); | |
827 | else | |
a9bcaa02 | 828 | udelay(200); |
cb3c8b90 | 829 | |
593f4a78 | 830 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 831 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
832 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
833 | if (send_status || accept_status) | |
834 | break; | |
835 | } | |
c767a54b | 836 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
837 | |
838 | if (send_status) | |
c767a54b | 839 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 840 | if (accept_status) |
c767a54b | 841 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
842 | |
843 | return (send_status | accept_status); | |
844 | } | |
cb3c8b90 | 845 | |
2eaad1fd | 846 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 847 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd MT |
848 | { |
849 | static int current_node = -1; | |
4adc8b71 | 850 | int node = early_cpu_to_node(cpu); |
a17bce4d | 851 | static int width, node_width; |
646e29a1 BP |
852 | |
853 | if (!width) | |
854 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 855 | |
a17bce4d BP |
856 | if (!node_width) |
857 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
858 | ||
859 | if (cpu == 1) | |
860 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
861 | ||
719b3680 | 862 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
863 | if (node != current_node) { |
864 | if (current_node > (-1)) | |
a17bce4d | 865 | pr_cont("\n"); |
2eaad1fd | 866 | current_node = node; |
a17bce4d BP |
867 | |
868 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
869 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 870 | } |
646e29a1 BP |
871 | |
872 | /* Add padding for the BSP */ | |
873 | if (cpu == 1) | |
874 | pr_cont("%*s", width + 1, " "); | |
875 | ||
876 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
877 | ||
2eaad1fd MT |
878 | } else |
879 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
880 | node, cpu, apicid); | |
881 | } | |
882 | ||
e1c467e6 FY |
883 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
884 | { | |
885 | int cpu; | |
886 | ||
887 | cpu = smp_processor_id(); | |
888 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
889 | return NMI_HANDLED; | |
890 | ||
891 | return NMI_DONE; | |
892 | } | |
893 | ||
894 | /* | |
895 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
896 | * | |
897 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
898 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
899 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
900 | * | |
901 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
902 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
903 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
904 | * real platform and request are available. | |
905 | */ | |
148f9bb8 | 906 | static int |
e1c467e6 FY |
907 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
908 | int *cpu0_nmi_registered) | |
909 | { | |
910 | int id; | |
911 | int boot_error; | |
912 | ||
ea7bdc65 JK |
913 | preempt_disable(); |
914 | ||
e1c467e6 FY |
915 | /* |
916 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
917 | */ | |
ea7bdc65 JK |
918 | if (cpu) { |
919 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
920 | goto out; | |
921 | } | |
e1c467e6 FY |
922 | |
923 | /* | |
924 | * Wake up BSP by nmi. | |
925 | * | |
926 | * Register a NMI handler to help wake up CPU0. | |
927 | */ | |
928 | boot_error = register_nmi_handler(NMI_LOCAL, | |
929 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
930 | ||
931 | if (!boot_error) { | |
932 | enable_start_cpu0 = 1; | |
933 | *cpu0_nmi_registered = 1; | |
934 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
935 | id = cpu0_logical_apicid; | |
936 | else | |
937 | id = apicid; | |
938 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
939 | } | |
ea7bdc65 JK |
940 | |
941 | out: | |
942 | preempt_enable(); | |
e1c467e6 FY |
943 | |
944 | return boot_error; | |
945 | } | |
946 | ||
3f85483b BO |
947 | void common_cpu_up(unsigned int cpu, struct task_struct *idle) |
948 | { | |
949 | /* Just in case we booted with a single CPU. */ | |
950 | alternatives_enable_smp(); | |
951 | ||
952 | per_cpu(current_task, cpu) = idle; | |
953 | ||
954 | #ifdef CONFIG_X86_32 | |
955 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
956 | irq_ctx_init(cpu); | |
258c98e7 | 957 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 958 | #else |
3f85483b BO |
959 | initial_gs = per_cpu_offset(cpu); |
960 | #endif | |
3f85483b BO |
961 | } |
962 | ||
cb3c8b90 GOC |
963 | /* |
964 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
965 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
966 | * Returns zero if CPU booted OK, else error code from |
967 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 968 | */ |
10e66760 VK |
969 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
970 | int *cpu0_nmi_registered) | |
cb3c8b90 | 971 | { |
48927bbb | 972 | volatile u32 *trampoline_status = |
b429dbf6 | 973 | (volatile u32 *) __va(real_mode_header->trampoline_status); |
48927bbb | 974 | /* start_ip had better be page-aligned! */ |
f37240f1 | 975 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 976 | |
cb3c8b90 | 977 | unsigned long boot_error = 0; |
ce4b1b16 | 978 | unsigned long timeout; |
cb3c8b90 | 979 | |
b9b1a9c3 | 980 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 981 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 982 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 983 | initial_stack = idle->thread.sp; |
cb3c8b90 | 984 | |
a187e1a3 | 985 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 986 | init_espfix_ap(cpu); |
20d5e4a9 | 987 | |
2eaad1fd MT |
988 | /* So we see what's up */ |
989 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
990 | |
991 | /* | |
992 | * This grunge runs the startup process for | |
993 | * the targeted processor. | |
994 | */ | |
995 | ||
34d05591 | 996 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
cb3c8b90 | 997 | |
cfc1b9a6 | 998 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 999 | |
34d05591 JS |
1000 | smpboot_setup_warm_reset_vector(start_ip); |
1001 | /* | |
1002 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1003 | */ |
cff9ab2b | 1004 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1005 | apic_write(APIC_ESR, 0); |
1006 | apic_read(APIC_ESR); | |
1007 | } | |
34d05591 | 1008 | } |
cb3c8b90 | 1009 | |
ce4b1b16 IM |
1010 | /* |
1011 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1012 | * cpu_initialized_mask set if previous attempt to online | |
1013 | * it timed-out. Clear cpu_initialized_mask so that after | |
1014 | * INIT/SIPI it could start with a clean state. | |
1015 | */ | |
1016 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1017 | smp_mb(); | |
1018 | ||
cb3c8b90 | 1019 | /* |
e1c467e6 FY |
1020 | * Wake up a CPU in difference cases: |
1021 | * - Use the method in the APIC driver if it's defined | |
1022 | * Otherwise, | |
1023 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1024 | */ |
1f5bcabf IM |
1025 | if (apic->wakeup_secondary_cpu) |
1026 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1027 | else | |
e1c467e6 | 1028 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 1029 | cpu0_nmi_registered); |
cb3c8b90 GOC |
1030 | |
1031 | if (!boot_error) { | |
1032 | /* | |
6e38f1e7 | 1033 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1034 | */ |
ce4b1b16 IM |
1035 | boot_error = -1; |
1036 | timeout = jiffies + 10*HZ; | |
1037 | while (time_before(jiffies, timeout)) { | |
1038 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1039 | /* | |
1040 | * Tell AP to proceed with initialization | |
1041 | */ | |
1042 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1043 | boot_error = 0; | |
1044 | break; | |
1045 | } | |
ce4b1b16 IM |
1046 | schedule(); |
1047 | } | |
1048 | } | |
cb3c8b90 | 1049 | |
ce4b1b16 | 1050 | if (!boot_error) { |
cb3c8b90 | 1051 | /* |
ce4b1b16 | 1052 | * Wait till AP completes initial initialization |
cb3c8b90 | 1053 | */ |
ce4b1b16 | 1054 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1055 | /* |
1056 | * Allow other tasks to run while we wait for the | |
1057 | * AP to come online. This also gives a chance | |
1058 | * for the MTRR work(triggered by the AP coming online) | |
1059 | * to be completed in the stop machine context. | |
1060 | */ | |
1061 | schedule(); | |
cb3c8b90 | 1062 | } |
cb3c8b90 GOC |
1063 | } |
1064 | ||
1065 | /* mark "stuck" area as not stuck */ | |
48927bbb | 1066 | *trampoline_status = 0; |
cb3c8b90 | 1067 | |
02421f98 YL |
1068 | if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { |
1069 | /* | |
1070 | * Cleanup possible dangling ends... | |
1071 | */ | |
1072 | smpboot_restore_warm_reset_vector(); | |
1073 | } | |
e1c467e6 | 1074 | |
cb3c8b90 GOC |
1075 | return boot_error; |
1076 | } | |
1077 | ||
148f9bb8 | 1078 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1079 | { |
a21769a4 | 1080 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1081 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1082 | unsigned long flags; |
10e66760 | 1083 | int err, ret = 0; |
cb3c8b90 GOC |
1084 | |
1085 | WARN_ON(irqs_disabled()); | |
1086 | ||
cfc1b9a6 | 1087 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1088 | |
30106c17 | 1089 | if (apicid == BAD_APICID || |
c284b42a | 1090 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1091 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1092 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1093 | return -EINVAL; |
1094 | } | |
1095 | ||
1096 | /* | |
1097 | * Already booted CPU? | |
1098 | */ | |
c2d1cec1 | 1099 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1100 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1101 | return -ENOSYS; |
1102 | } | |
1103 | ||
1104 | /* | |
1105 | * Save current MTRR state in case it was changed since early boot | |
1106 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1107 | */ | |
1108 | mtrr_save_state(); | |
1109 | ||
2a442c9c PM |
1110 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1111 | err = cpu_check_up_prepare(cpu); | |
1112 | if (err && err != -EBUSY) | |
1113 | return err; | |
cb3c8b90 | 1114 | |
644c1541 | 1115 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1116 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1117 | |
3f85483b BO |
1118 | common_cpu_up(cpu, tidle); |
1119 | ||
10e66760 | 1120 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1121 | if (err) { |
feef1e8e | 1122 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1123 | ret = -EIO; |
1124 | goto unreg_nmi; | |
cb3c8b90 GOC |
1125 | } |
1126 | ||
1127 | /* | |
1128 | * Check TSC synchronization with the AP (keep irqs disabled | |
1129 | * while doing so): | |
1130 | */ | |
1131 | local_irq_save(flags); | |
1132 | check_tsc_sync_source(cpu); | |
1133 | local_irq_restore(flags); | |
1134 | ||
7c04e64a | 1135 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1136 | cpu_relax(); |
1137 | touch_nmi_watchdog(); | |
1138 | } | |
1139 | ||
10e66760 VK |
1140 | unreg_nmi: |
1141 | /* | |
1142 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1143 | * to avoid impact of possible long unregister time. | |
1144 | */ | |
1145 | if (cpu0_nmi_registered) | |
1146 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1147 | ||
1148 | return ret; | |
cb3c8b90 GOC |
1149 | } |
1150 | ||
7167d08e HK |
1151 | /** |
1152 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1153 | */ | |
1154 | void arch_disable_smp_support(void) | |
1155 | { | |
1156 | disable_ioapic_support(); | |
1157 | } | |
1158 | ||
8aef135c GOC |
1159 | /* |
1160 | * Fall back to non SMP mode after errors. | |
1161 | * | |
1162 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1163 | */ | |
1164 | static __init void disable_smp(void) | |
1165 | { | |
613c25ef TG |
1166 | pr_info("SMP disabled\n"); |
1167 | ||
ef4c59a4 TG |
1168 | disable_ioapic_support(); |
1169 | ||
4f062896 RR |
1170 | init_cpu_present(cpumask_of(0)); |
1171 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1172 | |
8aef135c | 1173 | if (smp_found_config) |
b6df1b8b | 1174 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1175 | else |
b6df1b8b | 1176 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1177 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1178 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
8aef135c GOC |
1179 | } |
1180 | ||
613c25ef TG |
1181 | enum { |
1182 | SMP_OK, | |
1183 | SMP_NO_CONFIG, | |
1184 | SMP_NO_APIC, | |
1185 | SMP_FORCE_UP, | |
1186 | }; | |
1187 | ||
8aef135c GOC |
1188 | /* |
1189 | * Various sanity checks. | |
1190 | */ | |
1191 | static int __init smp_sanity_check(unsigned max_cpus) | |
1192 | { | |
ac23d4ee | 1193 | preempt_disable(); |
a58f03b0 | 1194 | |
1ff2f20d | 1195 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1196 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1197 | unsigned int cpu; | |
1198 | unsigned nr; | |
1199 | ||
c767a54b JP |
1200 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1201 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1202 | |
1203 | nr = 0; | |
1204 | for_each_present_cpu(cpu) { | |
1205 | if (nr >= 8) | |
c2d1cec1 | 1206 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1207 | nr++; |
1208 | } | |
1209 | ||
1210 | nr = 0; | |
1211 | for_each_possible_cpu(cpu) { | |
1212 | if (nr >= 8) | |
c2d1cec1 | 1213 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1214 | nr++; |
1215 | } | |
1216 | ||
1217 | nr_cpu_ids = 8; | |
1218 | } | |
1219 | #endif | |
1220 | ||
8aef135c | 1221 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1222 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1223 | hard_smp_processor_id()); |
1224 | ||
8aef135c GOC |
1225 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * If we couldn't find an SMP configuration at boot time, | |
1230 | * get out of here now! | |
1231 | */ | |
1232 | if (!smp_found_config && !acpi_lapic) { | |
ac23d4ee | 1233 | preempt_enable(); |
c767a54b | 1234 | pr_notice("SMP motherboard not detected\n"); |
613c25ef | 1235 | return SMP_NO_CONFIG; |
8aef135c GOC |
1236 | } |
1237 | ||
1238 | /* | |
1239 | * Should not be necessary because the MP table should list the boot | |
1240 | * CPU too, but we do it for the sake of robustness anyway. | |
1241 | */ | |
a27a6210 | 1242 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1243 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1244 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1245 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1246 | } | |
ac23d4ee | 1247 | preempt_enable(); |
8aef135c GOC |
1248 | |
1249 | /* | |
1250 | * If we couldn't find a local APIC, then get out of here now! | |
1251 | */ | |
cff9ab2b | 1252 | if (APIC_INTEGRATED(boot_cpu_apic_version) && |
93984fbd | 1253 | !boot_cpu_has(X86_FEATURE_APIC)) { |
103428e5 CG |
1254 | if (!disable_apic) { |
1255 | pr_err("BIOS bug, local APIC #%d not detected!...\n", | |
1256 | boot_cpu_physical_apicid); | |
c767a54b | 1257 | pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); |
103428e5 | 1258 | } |
613c25ef | 1259 | return SMP_NO_APIC; |
8aef135c GOC |
1260 | } |
1261 | ||
8aef135c GOC |
1262 | /* |
1263 | * If SMP should be disabled, then really disable it! | |
1264 | */ | |
1265 | if (!max_cpus) { | |
c767a54b | 1266 | pr_info("SMP mode deactivated\n"); |
613c25ef | 1267 | return SMP_FORCE_UP; |
8aef135c GOC |
1268 | } |
1269 | ||
613c25ef | 1270 | return SMP_OK; |
8aef135c GOC |
1271 | } |
1272 | ||
1273 | static void __init smp_cpu_index_default(void) | |
1274 | { | |
1275 | int i; | |
1276 | struct cpuinfo_x86 *c; | |
1277 | ||
7c04e64a | 1278 | for_each_possible_cpu(i) { |
8aef135c GOC |
1279 | c = &cpu_data(i); |
1280 | /* mark all to hotplug */ | |
9628937d | 1281 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1282 | } |
1283 | } | |
1284 | ||
1285 | /* | |
1286 | * Prepare for SMP bootup. The MP table or ACPI has been read | |
1287 | * earlier. Just do some sanity checking here and enable APIC mode. | |
1288 | */ | |
1289 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1290 | { | |
7ad728f9 RR |
1291 | unsigned int i; |
1292 | ||
8aef135c | 1293 | smp_cpu_index_default(); |
792363d2 | 1294 | |
8aef135c GOC |
1295 | /* |
1296 | * Setup boot CPU information | |
1297 | */ | |
30106c17 | 1298 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1299 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1300 | mb(); | |
bd22a2f1 | 1301 | |
7ad728f9 | 1302 | for_each_possible_cpu(i) { |
79f55997 LZ |
1303 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1304 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
b3d7336d | 1305 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1306 | } |
8f37961c TC |
1307 | |
1308 | /* | |
1309 | * Set 'default' x86 topology, this matches default_topology() in that | |
1310 | * it has NUMA nodes as a topology level. See also | |
1311 | * native_smp_cpus_done(). | |
1312 | * | |
1313 | * Must be done before set_cpus_sibling_map() is ran. | |
1314 | */ | |
1315 | set_sched_topology(x86_topology); | |
1316 | ||
8aef135c GOC |
1317 | set_cpu_sibling_map(0); |
1318 | ||
613c25ef TG |
1319 | switch (smp_sanity_check(max_cpus)) { |
1320 | case SMP_NO_CONFIG: | |
8aef135c | 1321 | disable_smp(); |
613c25ef TG |
1322 | if (APIC_init_uniprocessor()) |
1323 | pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); | |
1324 | return; | |
1325 | case SMP_NO_APIC: | |
1326 | disable_smp(); | |
1327 | return; | |
1328 | case SMP_FORCE_UP: | |
1329 | disable_smp(); | |
374aab33 | 1330 | apic_bsp_setup(false); |
250a1ac6 | 1331 | return; |
613c25ef TG |
1332 | case SMP_OK: |
1333 | break; | |
8aef135c GOC |
1334 | } |
1335 | ||
4c9961d5 | 1336 | if (read_apic_id() != boot_cpu_physical_apicid) { |
8aef135c | 1337 | panic("Boot APIC ID in local APIC unexpected (%d vs %d)", |
4c9961d5 | 1338 | read_apic_id(), boot_cpu_physical_apicid); |
8aef135c GOC |
1339 | /* Or can we switch back to PIC here? */ |
1340 | } | |
1341 | ||
384d9fe3 | 1342 | default_setup_apic_routing(); |
374aab33 | 1343 | cpu0_logical_apicid = apic_bsp_setup(false); |
ef4c59a4 | 1344 | |
d54ff31d | 1345 | pr_info("CPU0: "); |
8aef135c | 1346 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1347 | |
9ec808a0 | 1348 | uv_system_init(); |
d0af9eed SS |
1349 | |
1350 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1351 | |
1352 | smp_quirk_init_udelay(); | |
8aef135c | 1353 | } |
d0af9eed SS |
1354 | |
1355 | void arch_enable_nonboot_cpus_begin(void) | |
1356 | { | |
1357 | set_mtrr_aps_delayed_init(); | |
1358 | } | |
1359 | ||
1360 | void arch_enable_nonboot_cpus_end(void) | |
1361 | { | |
1362 | mtrr_aps_init(); | |
1363 | } | |
1364 | ||
a8db8453 GOC |
1365 | /* |
1366 | * Early setup to make printk work. | |
1367 | */ | |
1368 | void __init native_smp_prepare_boot_cpu(void) | |
1369 | { | |
1370 | int me = smp_processor_id(); | |
552be871 | 1371 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1372 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1373 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1374 | cpu_set_state_online(me); |
a8db8453 GOC |
1375 | } |
1376 | ||
83f7eb9c GOC |
1377 | void __init native_smp_cpus_done(unsigned int max_cpus) |
1378 | { | |
c767a54b | 1379 | pr_debug("Boot done\n"); |
83f7eb9c | 1380 | |
8f37961c TC |
1381 | if (x86_has_numa_in_package) |
1382 | set_sched_topology(x86_numa_in_package_topology); | |
1383 | ||
99e8b9ca | 1384 | nmi_selftest(); |
83f7eb9c | 1385 | impress_friends(); |
83f7eb9c | 1386 | setup_ioapic_dest(); |
d0af9eed | 1387 | mtrr_aps_init(); |
83f7eb9c GOC |
1388 | } |
1389 | ||
3b11ce7f MT |
1390 | static int __initdata setup_possible_cpus = -1; |
1391 | static int __init _setup_possible_cpus(char *str) | |
1392 | { | |
1393 | get_option(&str, &setup_possible_cpus); | |
1394 | return 0; | |
1395 | } | |
1396 | early_param("possible_cpus", _setup_possible_cpus); | |
1397 | ||
1398 | ||
68a1c3f8 | 1399 | /* |
4f062896 | 1400 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 GC |
1401 | * are onlined, or offlined. The reason is per-cpu data-structures |
1402 | * are allocated by some modules at init time, and dont expect to | |
1403 | * do this dynamically on cpu arrival/departure. | |
4f062896 | 1404 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1405 | * In case when cpu_hotplug is not compiled, then we resort to current |
1406 | * behaviour, which is cpu_possible == cpu_present. | |
1407 | * - Ashok Raj | |
1408 | * | |
1409 | * Three ways to find out the number of additional hotplug CPUs: | |
1410 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1411 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1412 | * - Otherwise don't reserve additional CPUs. |
1413 | * We do this because additional CPUs waste a lot of memory. | |
1414 | * -AK | |
1415 | */ | |
1416 | __init void prefill_possible_map(void) | |
1417 | { | |
cb48bb59 | 1418 | int i, possible; |
68a1c3f8 | 1419 | |
2a51fe08 PB |
1420 | /* No boot processor was found in mptable or ACPI MADT */ |
1421 | if (!num_processors) { | |
ff856051 VS |
1422 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1423 | int apicid = boot_cpu_physical_apicid; | |
1424 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1425 | |
ff856051 | 1426 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1427 | |
ff856051 VS |
1428 | /* Make sure boot cpu is enumerated */ |
1429 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1430 | apic->apic_id_valid(apicid)) | |
1431 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1432 | } | |
2a51fe08 PB |
1433 | |
1434 | if (!num_processors) | |
1435 | num_processors = 1; | |
1436 | } | |
329513a3 | 1437 | |
5f2eb550 JB |
1438 | i = setup_max_cpus ?: 1; |
1439 | if (setup_possible_cpus == -1) { | |
1440 | possible = num_processors; | |
1441 | #ifdef CONFIG_HOTPLUG_CPU | |
1442 | if (setup_max_cpus) | |
1443 | possible += disabled_cpus; | |
1444 | #else | |
1445 | if (possible > i) | |
1446 | possible = i; | |
1447 | #endif | |
1448 | } else | |
3b11ce7f MT |
1449 | possible = setup_possible_cpus; |
1450 | ||
730cf272 MT |
1451 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1452 | ||
2b633e3f YL |
1453 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1454 | if (possible > nr_cpu_ids) { | |
c767a54b | 1455 | pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", |
2b633e3f YL |
1456 | possible, nr_cpu_ids); |
1457 | possible = nr_cpu_ids; | |
3b11ce7f | 1458 | } |
68a1c3f8 | 1459 | |
5f2eb550 JB |
1460 | #ifdef CONFIG_HOTPLUG_CPU |
1461 | if (!setup_max_cpus) | |
1462 | #endif | |
1463 | if (possible > i) { | |
c767a54b | 1464 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1465 | possible, setup_max_cpus); |
1466 | possible = i; | |
1467 | } | |
1468 | ||
427d77a3 TG |
1469 | nr_cpu_ids = possible; |
1470 | ||
c767a54b | 1471 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1472 | possible, max_t(int, possible - num_processors, 0)); |
1473 | ||
427d77a3 TG |
1474 | reset_cpu_possible_mask(); |
1475 | ||
68a1c3f8 | 1476 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1477 | set_cpu_possible(i, true); |
68a1c3f8 | 1478 | } |
69c18c15 | 1479 | |
14adf855 CE |
1480 | #ifdef CONFIG_HOTPLUG_CPU |
1481 | ||
70b8301f AK |
1482 | /* Recompute SMT state for all CPUs on offline */ |
1483 | static void recompute_smt_state(void) | |
1484 | { | |
1485 | int max_threads, cpu; | |
1486 | ||
1487 | max_threads = 0; | |
1488 | for_each_online_cpu (cpu) { | |
1489 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1490 | ||
1491 | if (threads > max_threads) | |
1492 | max_threads = threads; | |
1493 | } | |
1494 | __max_smt_threads = max_threads; | |
1495 | } | |
1496 | ||
14adf855 CE |
1497 | static void remove_siblinginfo(int cpu) |
1498 | { | |
1499 | int sibling; | |
1500 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1501 | ||
7d79a7bd BG |
1502 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1503 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1504 | /*/ |
1505 | * last thread sibling in this cpu core going down | |
1506 | */ | |
7d79a7bd | 1507 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1508 | cpu_data(sibling).booted_cores--; |
1509 | } | |
1510 | ||
7d79a7bd BG |
1511 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1512 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1513 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1514 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1515 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1516 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1517 | cpumask_clear(topology_core_cpumask(cpu)); | |
14adf855 CE |
1518 | c->phys_proc_id = 0; |
1519 | c->cpu_core_id = 0; | |
c2d1cec1 | 1520 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1521 | recompute_smt_state(); |
14adf855 CE |
1522 | } |
1523 | ||
4daa832d | 1524 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1525 | { |
c2d1cec1 MT |
1526 | set_cpu_online(cpu, false); |
1527 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1528 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1529 | /* was set by cpu_init() */ |
c2d1cec1 | 1530 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1531 | numa_remove_cpu(cpu); |
69c18c15 GC |
1532 | } |
1533 | ||
8227dce7 | 1534 | void cpu_disable_common(void) |
69c18c15 GC |
1535 | { |
1536 | int cpu = smp_processor_id(); | |
69c18c15 | 1537 | |
69c18c15 GC |
1538 | remove_siblinginfo(cpu); |
1539 | ||
1540 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1541 | lock_vector_lock(); |
69c18c15 | 1542 | remove_cpu_from_maps(cpu); |
d388e5fd | 1543 | unlock_vector_lock(); |
d7b381bb | 1544 | fixup_irqs(); |
8227dce7 AN |
1545 | } |
1546 | ||
1547 | int native_cpu_disable(void) | |
1548 | { | |
da6139e4 PB |
1549 | int ret; |
1550 | ||
1551 | ret = check_irq_vectors_for_cpu_disable(); | |
1552 | if (ret) | |
1553 | return ret; | |
1554 | ||
8227dce7 | 1555 | clear_local_APIC(); |
8227dce7 | 1556 | cpu_disable_common(); |
2ed53c0d | 1557 | |
69c18c15 GC |
1558 | return 0; |
1559 | } | |
1560 | ||
2a442c9c | 1561 | int common_cpu_die(unsigned int cpu) |
54279552 | 1562 | { |
2a442c9c | 1563 | int ret = 0; |
54279552 | 1564 | |
69c18c15 | 1565 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1566 | |
2ed53c0d | 1567 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1568 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1569 | if (system_state == SYSTEM_RUNNING) |
1570 | pr_info("CPU %u is now offline\n", cpu); | |
1571 | } else { | |
1572 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1573 | ret = -1; |
69c18c15 | 1574 | } |
2a442c9c PM |
1575 | |
1576 | return ret; | |
1577 | } | |
1578 | ||
1579 | void native_cpu_die(unsigned int cpu) | |
1580 | { | |
1581 | common_cpu_die(cpu); | |
69c18c15 | 1582 | } |
a21f5d88 AN |
1583 | |
1584 | void play_dead_common(void) | |
1585 | { | |
1586 | idle_task_exit(); | |
a21f5d88 | 1587 | |
a21f5d88 | 1588 | /* Ack it */ |
2a442c9c | 1589 | (void)cpu_report_death(); |
a21f5d88 AN |
1590 | |
1591 | /* | |
1592 | * With physical CPU hotplug, we should halt the cpu | |
1593 | */ | |
1594 | local_irq_disable(); | |
1595 | } | |
1596 | ||
e1c467e6 FY |
1597 | static bool wakeup_cpu0(void) |
1598 | { | |
1599 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1600 | return true; | |
1601 | ||
1602 | return false; | |
1603 | } | |
1604 | ||
ea530692 PA |
1605 | /* |
1606 | * We need to flush the caches before going to sleep, lest we have | |
1607 | * dirty data in our caches when we come back up. | |
1608 | */ | |
1609 | static inline void mwait_play_dead(void) | |
1610 | { | |
1611 | unsigned int eax, ebx, ecx, edx; | |
1612 | unsigned int highest_cstate = 0; | |
1613 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1614 | void *mwait_ptr; |
576cfb40 | 1615 | int i; |
ea530692 | 1616 | |
69fb3676 | 1617 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1618 | return; |
840d2830 | 1619 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1620 | return; |
7b543a53 | 1621 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1622 | return; |
1623 | ||
1624 | eax = CPUID_MWAIT_LEAF; | |
1625 | ecx = 0; | |
1626 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1627 | ||
1628 | /* | |
1629 | * eax will be 0 if EDX enumeration is not valid. | |
1630 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1631 | */ | |
1632 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1633 | eax = 0; | |
1634 | } else { | |
1635 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1636 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1637 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1638 | highest_cstate = i; | |
1639 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1640 | } | |
1641 | } | |
1642 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1643 | (highest_subcstate - 1); | |
1644 | } | |
1645 | ||
ce5f6824 PA |
1646 | /* |
1647 | * This should be a memory location in a cache line which is | |
1648 | * unlikely to be touched by other processors. The actual | |
1649 | * content is immaterial as it is not actually modified in any way. | |
1650 | */ | |
1651 | mwait_ptr = ¤t_thread_info()->flags; | |
1652 | ||
a68e5c94 PA |
1653 | wbinvd(); |
1654 | ||
ea530692 | 1655 | while (1) { |
ce5f6824 PA |
1656 | /* |
1657 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1658 | * the Xeon 7400 series. It's not clear it is actually | |
1659 | * needed, but it should be harmless in either case. | |
1660 | * The WBINVD is insufficient due to the spurious-wakeup | |
1661 | * case where we return around the loop. | |
1662 | */ | |
7d590cca | 1663 | mb(); |
ce5f6824 | 1664 | clflush(mwait_ptr); |
7d590cca | 1665 | mb(); |
ce5f6824 | 1666 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1667 | mb(); |
1668 | __mwait(eax, 0); | |
e1c467e6 FY |
1669 | /* |
1670 | * If NMI wants to wake up CPU0, start CPU0. | |
1671 | */ | |
1672 | if (wakeup_cpu0()) | |
1673 | start_cpu0(); | |
ea530692 PA |
1674 | } |
1675 | } | |
1676 | ||
406f992e | 1677 | void hlt_play_dead(void) |
ea530692 | 1678 | { |
7b543a53 | 1679 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1680 | wbinvd(); |
1681 | ||
ea530692 | 1682 | while (1) { |
ea530692 | 1683 | native_halt(); |
e1c467e6 FY |
1684 | /* |
1685 | * If NMI wants to wake up CPU0, start CPU0. | |
1686 | */ | |
1687 | if (wakeup_cpu0()) | |
1688 | start_cpu0(); | |
ea530692 PA |
1689 | } |
1690 | } | |
1691 | ||
a21f5d88 AN |
1692 | void native_play_dead(void) |
1693 | { | |
1694 | play_dead_common(); | |
86886e55 | 1695 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 | 1696 | |
357b57d7 | 1697 | if (ibrs_inuse) |
159e800c | 1698 | native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default()); |
704cf01d | 1699 | |
ea530692 | 1700 | mwait_play_dead(); /* Only returns on failure */ |
1a022e3f BO |
1701 | if (cpuidle_play_dead()) |
1702 | hlt_play_dead(); | |
704cf01d | 1703 | |
357b57d7 | 1704 | if (ibrs_inuse) |
159e800c | 1705 | native_wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_get_default() | SPEC_CTRL_IBRS); |
a21f5d88 AN |
1706 | } |
1707 | ||
69c18c15 | 1708 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1709 | int native_cpu_disable(void) |
69c18c15 GC |
1710 | { |
1711 | return -ENOSYS; | |
1712 | } | |
1713 | ||
93be71b6 | 1714 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1715 | { |
1716 | /* We said "no" in __cpu_disable */ | |
1717 | BUG(); | |
1718 | } | |
a21f5d88 AN |
1719 | |
1720 | void native_play_dead(void) | |
1721 | { | |
1722 | BUG(); | |
1723 | } | |
1724 | ||
68a1c3f8 | 1725 | #endif |