]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
c767a54b JP |
12 | |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt | |
14 | ||
56dd9470 | 15 | #include <linux/context_tracking.h> |
b5964405 IM |
16 | #include <linux/interrupt.h> |
17 | #include <linux/kallsyms.h> | |
18 | #include <linux/spinlock.h> | |
b5964405 IM |
19 | #include <linux/kprobes.h> |
20 | #include <linux/uaccess.h> | |
b5964405 | 21 | #include <linux/kdebug.h> |
f503b5ae | 22 | #include <linux/kgdb.h> |
1da177e4 | 23 | #include <linux/kernel.h> |
186f4360 | 24 | #include <linux/export.h> |
b5964405 | 25 | #include <linux/ptrace.h> |
b02ef20a | 26 | #include <linux/uprobes.h> |
1da177e4 | 27 | #include <linux/string.h> |
b5964405 | 28 | #include <linux/delay.h> |
1da177e4 | 29 | #include <linux/errno.h> |
b5964405 IM |
30 | #include <linux/kexec.h> |
31 | #include <linux/sched.h> | |
68db0cf1 | 32 | #include <linux/sched/task_stack.h> |
1da177e4 | 33 | #include <linux/timer.h> |
1da177e4 | 34 | #include <linux/init.h> |
91768d6c | 35 | #include <linux/bug.h> |
b5964405 IM |
36 | #include <linux/nmi.h> |
37 | #include <linux/mm.h> | |
c1d518c8 AH |
38 | #include <linux/smp.h> |
39 | #include <linux/io.h> | |
1da177e4 LT |
40 | |
41 | #ifdef CONFIG_EISA | |
42 | #include <linux/ioport.h> | |
43 | #include <linux/eisa.h> | |
44 | #endif | |
45 | ||
c0d12172 DJ |
46 | #if defined(CONFIG_EDAC) |
47 | #include <linux/edac.h> | |
48 | #endif | |
49 | ||
f8561296 | 50 | #include <asm/kmemcheck.h> |
b5964405 | 51 | #include <asm/stacktrace.h> |
1da177e4 | 52 | #include <asm/processor.h> |
1da177e4 | 53 | #include <asm/debugreg.h> |
60063497 | 54 | #include <linux/atomic.h> |
35de5b06 | 55 | #include <asm/text-patching.h> |
08d636b6 | 56 | #include <asm/ftrace.h> |
c1d518c8 | 57 | #include <asm/traps.h> |
1da177e4 | 58 | #include <asm/desc.h> |
78f7f1e5 | 59 | #include <asm/fpu/internal.h> |
0fa11d2c | 60 | #include <asm/cpu_entry_area.h> |
9e55e44e | 61 | #include <asm/mce.h> |
4eefbe79 | 62 | #include <asm/fixmap.h> |
1164dd00 | 63 | #include <asm/mach_traps.h> |
17f41571 | 64 | #include <asm/alternative.h> |
a84eeaa9 | 65 | #include <asm/fpu/xstate.h> |
e7126cf5 | 66 | #include <asm/trace/mpx.h> |
fe3d197f | 67 | #include <asm/mpx.h> |
ba3e127e | 68 | #include <asm/vm86.h> |
c1d518c8 | 69 | |
081f75bb | 70 | #ifdef CONFIG_X86_64 |
428cf902 | 71 | #include <asm/x86_init.h> |
081f75bb AH |
72 | #include <asm/pgalloc.h> |
73 | #include <asm/proto.h> | |
4df05f36 KC |
74 | |
75 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
76 | gate_desc debug_idt_table[NR_VECTORS] __page_aligned_bss; | |
081f75bb | 77 | #else |
c1d518c8 | 78 | #include <asm/processor-flags.h> |
8e6dafd6 | 79 | #include <asm/setup.h> |
b2502b41 | 80 | #include <asm/proto.h> |
081f75bb | 81 | #endif |
1da177e4 | 82 | |
4df05f36 KC |
83 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
84 | gate_desc idt_table[NR_VECTORS] __page_aligned_bss; | |
85 | ||
b77b881f YL |
86 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
87 | EXPORT_SYMBOL_GPL(used_vectors); | |
88 | ||
d99e1bd1 | 89 | static inline void cond_local_irq_enable(struct pt_regs *regs) |
762db434 AH |
90 | { |
91 | if (regs->flags & X86_EFLAGS_IF) | |
92 | local_irq_enable(); | |
93 | } | |
94 | ||
d99e1bd1 | 95 | static inline void cond_local_irq_disable(struct pt_regs *regs) |
3d2a71a5 AH |
96 | { |
97 | if (regs->flags & X86_EFLAGS_IF) | |
98 | local_irq_disable(); | |
3d2a71a5 AH |
99 | } |
100 | ||
aaee8c3c AL |
101 | /* |
102 | * In IST context, we explicitly disable preemption. This serves two | |
103 | * purposes: it makes it much less likely that we would accidentally | |
104 | * schedule in IST context and it will force a warning if we somehow | |
105 | * manage to schedule by accident. | |
106 | */ | |
8c84014f | 107 | void ist_enter(struct pt_regs *regs) |
95927475 | 108 | { |
f39b6f0e | 109 | if (user_mode(regs)) { |
5778077d | 110 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
95927475 AL |
111 | } else { |
112 | /* | |
113 | * We might have interrupted pretty much anything. In | |
114 | * fact, if we're a machine check, we can even interrupt | |
115 | * NMI processing. We don't want in_nmi() to return true, | |
116 | * but we need to notify RCU. | |
117 | */ | |
118 | rcu_nmi_enter(); | |
95927475 | 119 | } |
b926e6f6 | 120 | |
aaee8c3c | 121 | preempt_disable(); |
b926e6f6 AL |
122 | |
123 | /* This code is a bit fragile. Test it. */ | |
f78f5b90 | 124 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "ist_enter didn't work"); |
95927475 AL |
125 | } |
126 | ||
8c84014f | 127 | void ist_exit(struct pt_regs *regs) |
95927475 | 128 | { |
aaee8c3c | 129 | preempt_enable_no_resched(); |
95927475 | 130 | |
8c84014f | 131 | if (!user_mode(regs)) |
95927475 AL |
132 | rcu_nmi_exit(); |
133 | } | |
134 | ||
bced35b6 AL |
135 | /** |
136 | * ist_begin_non_atomic() - begin a non-atomic section in an IST exception | |
137 | * @regs: regs passed to the IST exception handler | |
138 | * | |
139 | * IST exception handlers normally cannot schedule. As a special | |
140 | * exception, if the exception interrupted userspace code (i.e. | |
f39b6f0e | 141 | * user_mode(regs) would return true) and the exception was not |
bced35b6 AL |
142 | * a double fault, it can be safe to schedule. ist_begin_non_atomic() |
143 | * begins a non-atomic section within an ist_enter()/ist_exit() region. | |
144 | * Callers are responsible for enabling interrupts themselves inside | |
8c84014f | 145 | * the non-atomic section, and callers must call ist_end_non_atomic() |
bced35b6 AL |
146 | * before ist_exit(). |
147 | */ | |
148 | void ist_begin_non_atomic(struct pt_regs *regs) | |
149 | { | |
f39b6f0e | 150 | BUG_ON(!user_mode(regs)); |
bced35b6 AL |
151 | |
152 | /* | |
153 | * Sanity check: we need to be on the normal thread stack. This | |
154 | * will catch asm bugs and any attempt to use ist_preempt_enable | |
155 | * from double_fault. | |
156 | */ | |
243de7bd | 157 | BUG_ON(!on_thread_stack()); |
bced35b6 | 158 | |
aaee8c3c | 159 | preempt_enable_no_resched(); |
bced35b6 AL |
160 | } |
161 | ||
162 | /** | |
163 | * ist_end_non_atomic() - begin a non-atomic section in an IST exception | |
164 | * | |
165 | * Ends a non-atomic section started with ist_begin_non_atomic(). | |
166 | */ | |
167 | void ist_end_non_atomic(void) | |
168 | { | |
aaee8c3c | 169 | preempt_disable(); |
bced35b6 AL |
170 | } |
171 | ||
9a93848f PZ |
172 | int is_valid_bugaddr(unsigned long addr) |
173 | { | |
174 | unsigned short ud; | |
175 | ||
176 | if (addr < TASK_SIZE_MAX) | |
177 | return 0; | |
178 | ||
179 | if (probe_kernel_address((unsigned short *)addr, ud)) | |
180 | return 0; | |
181 | ||
182 | return ud == INSN_UD0 || ud == INSN_UD2; | |
183 | } | |
184 | ||
8a524f80 | 185 | int fixup_bug(struct pt_regs *regs, int trapnr) |
9a93848f PZ |
186 | { |
187 | if (trapnr != X86_TRAP_UD) | |
188 | return 0; | |
189 | ||
190 | switch (report_bug(regs->ip, regs)) { | |
191 | case BUG_TRAP_TYPE_NONE: | |
192 | case BUG_TRAP_TYPE_BUG: | |
193 | break; | |
194 | ||
195 | case BUG_TRAP_TYPE_WARN: | |
196 | regs->ip += LEN_UD0; | |
197 | return 1; | |
198 | } | |
199 | ||
200 | return 0; | |
201 | } | |
202 | ||
9326638c | 203 | static nokprobe_inline int |
c416ddf5 FW |
204 | do_trap_no_signal(struct task_struct *tsk, int trapnr, char *str, |
205 | struct pt_regs *regs, long error_code) | |
1da177e4 | 206 | { |
d74ef111 | 207 | if (v8086_mode(regs)) { |
3c1326f8 | 208 | /* |
c416ddf5 | 209 | * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. |
3c1326f8 AH |
210 | * On nmi (interrupt 2), do_trap should not be called. |
211 | */ | |
c416ddf5 FW |
212 | if (trapnr < X86_TRAP_UD) { |
213 | if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
214 | error_code, trapnr)) | |
215 | return 0; | |
216 | } | |
217 | return -1; | |
1da177e4 | 218 | } |
d74ef111 | 219 | |
55474c48 | 220 | if (!user_mode(regs)) { |
9a93848f PZ |
221 | if (fixup_exception(regs, trapnr)) |
222 | return 0; | |
223 | ||
9a93848f PZ |
224 | tsk->thread.error_code = error_code; |
225 | tsk->thread.trap_nr = trapnr; | |
226 | die(str, regs, error_code); | |
c416ddf5 | 227 | } |
1da177e4 | 228 | |
c416ddf5 FW |
229 | return -1; |
230 | } | |
1da177e4 | 231 | |
1c326c4d ON |
232 | static siginfo_t *fill_trap_info(struct pt_regs *regs, int signr, int trapnr, |
233 | siginfo_t *info) | |
958d3d72 ON |
234 | { |
235 | unsigned long siaddr; | |
236 | int sicode; | |
237 | ||
238 | switch (trapnr) { | |
1c326c4d ON |
239 | default: |
240 | return SEND_SIG_PRIV; | |
241 | ||
958d3d72 ON |
242 | case X86_TRAP_DE: |
243 | sicode = FPE_INTDIV; | |
b02ef20a | 244 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
245 | break; |
246 | case X86_TRAP_UD: | |
247 | sicode = ILL_ILLOPN; | |
b02ef20a | 248 | siaddr = uprobe_get_trap_addr(regs); |
958d3d72 ON |
249 | break; |
250 | case X86_TRAP_AC: | |
251 | sicode = BUS_ADRALN; | |
252 | siaddr = 0; | |
253 | break; | |
254 | } | |
255 | ||
256 | info->si_signo = signr; | |
257 | info->si_errno = 0; | |
258 | info->si_code = sicode; | |
259 | info->si_addr = (void __user *)siaddr; | |
1c326c4d | 260 | return info; |
958d3d72 ON |
261 | } |
262 | ||
9326638c | 263 | static void |
c416ddf5 FW |
264 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
265 | long error_code, siginfo_t *info) | |
266 | { | |
267 | struct task_struct *tsk = current; | |
268 | ||
269 | ||
270 | if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) | |
271 | return; | |
b5964405 | 272 | /* |
51e7dc70 | 273 | * We want error_code and trap_nr set for userspace faults and |
b5964405 IM |
274 | * kernelspace faults which result in die(), but not |
275 | * kernelspace faults which are fixed up. die() gives the | |
276 | * process no chance to handle the signal and notice the | |
277 | * kernel fault information, so that won't result in polluting | |
278 | * the information about previously queued, but not yet | |
279 | * delivered, faults. See also do_general_protection below. | |
280 | */ | |
281 | tsk->thread.error_code = error_code; | |
51e7dc70 | 282 | tsk->thread.trap_nr = trapnr; |
d1895183 | 283 | |
081f75bb AH |
284 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && |
285 | printk_ratelimit()) { | |
c767a54b JP |
286 | pr_info("%s[%d] trap %s ip:%lx sp:%lx error:%lx", |
287 | tsk->comm, tsk->pid, str, | |
288 | regs->ip, regs->sp, error_code); | |
1c99a687 | 289 | print_vma_addr(KERN_CONT " in ", regs->ip); |
c767a54b | 290 | pr_cont("\n"); |
081f75bb | 291 | } |
081f75bb | 292 | |
38cad57b | 293 | force_sig_info(signr, info ?: SEND_SIG_PRIV, tsk); |
1da177e4 | 294 | } |
9326638c | 295 | NOKPROBE_SYMBOL(do_trap); |
1da177e4 | 296 | |
dff0796e | 297 | static void do_error_trap(struct pt_regs *regs, long error_code, char *str, |
1c326c4d | 298 | unsigned long trapnr, int signr) |
dff0796e | 299 | { |
1c326c4d | 300 | siginfo_t info; |
dff0796e | 301 | |
5778077d | 302 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
02fdcd5e | 303 | |
3aed4a86 AS |
304 | /* |
305 | * WARN*()s end up here; fix them up before we call the | |
306 | * notifier chain. | |
307 | */ | |
308 | if (!user_mode(regs) && fixup_bug(regs, trapnr)) | |
309 | return; | |
310 | ||
dff0796e ON |
311 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != |
312 | NOTIFY_STOP) { | |
d99e1bd1 | 313 | cond_local_irq_enable(regs); |
1c326c4d ON |
314 | do_trap(trapnr, signr, str, regs, error_code, |
315 | fill_trap_info(regs, signr, trapnr, &info)); | |
dff0796e | 316 | } |
dff0796e ON |
317 | } |
318 | ||
b5964405 | 319 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 320 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 | 321 | { \ |
1c326c4d | 322 | do_error_trap(regs, error_code, str, trapnr, signr); \ |
1da177e4 LT |
323 | } |
324 | ||
0eb14833 ON |
325 | DO_ERROR(X86_TRAP_DE, SIGFPE, "divide error", divide_error) |
326 | DO_ERROR(X86_TRAP_OF, SIGSEGV, "overflow", overflow) | |
0eb14833 ON |
327 | DO_ERROR(X86_TRAP_UD, SIGILL, "invalid opcode", invalid_op) |
328 | DO_ERROR(X86_TRAP_OLD_MF, SIGFPE, "coprocessor segment overrun",coprocessor_segment_overrun) | |
329 | DO_ERROR(X86_TRAP_TS, SIGSEGV, "invalid TSS", invalid_TSS) | |
330 | DO_ERROR(X86_TRAP_NP, SIGBUS, "segment not present", segment_not_present) | |
0eb14833 | 331 | DO_ERROR(X86_TRAP_SS, SIGBUS, "stack segment", stack_segment) |
0eb14833 | 332 | DO_ERROR(X86_TRAP_AC, SIGBUS, "alignment check", alignment_check) |
1da177e4 | 333 | |
e37e43a4 | 334 | #ifdef CONFIG_VMAP_STACK |
6271cfdf AL |
335 | __visible void __noreturn handle_stack_overflow(const char *message, |
336 | struct pt_regs *regs, | |
337 | unsigned long fault_address) | |
e37e43a4 AL |
338 | { |
339 | printk(KERN_EMERG "BUG: stack guard page was hit at %p (stack is %p..%p)\n", | |
340 | (void *)fault_address, current->stack, | |
341 | (char *)current->stack + THREAD_SIZE - 1); | |
342 | die(message, regs, 0); | |
343 | ||
344 | /* Be absolutely certain we don't return. */ | |
345 | panic(message); | |
346 | } | |
347 | #endif | |
348 | ||
081f75bb AH |
349 | #ifdef CONFIG_X86_64 |
350 | /* Runs on IST stack */ | |
081f75bb AH |
351 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) |
352 | { | |
353 | static const char str[] = "double fault"; | |
354 | struct task_struct *tsk = current; | |
e37e43a4 AL |
355 | #ifdef CONFIG_VMAP_STACK |
356 | unsigned long cr2; | |
357 | #endif | |
081f75bb | 358 | |
af726f21 AL |
359 | #ifdef CONFIG_X86_ESPFIX64 |
360 | extern unsigned char native_irq_return_iret[]; | |
361 | ||
362 | /* | |
363 | * If IRET takes a non-IST fault on the espfix64 stack, then we | |
f5d8df27 AL |
364 | * end up promoting it to a doublefault. In that case, take |
365 | * advantage of the fact that we're not using the normal (TSS.sp0) | |
366 | * stack right now. We can write a fake #GP(0) frame at TSS.sp0 | |
367 | * and then modify our own IRET frame so that, when we return, | |
368 | * we land directly at the #GP(0) vector with the stack already | |
369 | * set up according to its expectations. | |
370 | * | |
371 | * The net result is that our #GP handler will think that we | |
372 | * entered from usermode with the bad user context. | |
95927475 AL |
373 | * |
374 | * No need for ist_enter here because we don't use RCU. | |
af726f21 AL |
375 | */ |
376 | if (((long)regs->sp >> PGDIR_SHIFT) == ESPFIX_PGD_ENTRY && | |
377 | regs->cs == __KERNEL_CS && | |
378 | regs->ip == (unsigned long)native_irq_return_iret) | |
379 | { | |
785be108 | 380 | struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; |
f5d8df27 AL |
381 | |
382 | /* | |
383 | * regs->sp points to the failing IRET frame on the | |
384 | * ESPFIX64 stack. Copy it to the entry stack. This fills | |
385 | * in gpregs->ss through gpregs->ip. | |
386 | * | |
387 | */ | |
388 | memmove(&gpregs->ip, (void *)regs->sp, 5*8); | |
389 | gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ | |
af726f21 | 390 | |
f5d8df27 AL |
391 | /* |
392 | * Adjust our frame so that we return straight to the #GP | |
393 | * vector with the expected RSP value. This is safe because | |
394 | * we won't enable interupts or schedule before we invoke | |
395 | * general_protection, so nothing will clobber the stack | |
396 | * frame we just set up. | |
397 | */ | |
af726f21 | 398 | regs->ip = (unsigned long)general_protection; |
f5d8df27 | 399 | regs->sp = (unsigned long)&gpregs->orig_ax; |
95927475 | 400 | |
af726f21 AL |
401 | return; |
402 | } | |
403 | #endif | |
404 | ||
8c84014f | 405 | ist_enter(regs); |
c9408265 | 406 | notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); |
081f75bb AH |
407 | |
408 | tsk->thread.error_code = error_code; | |
51e7dc70 | 409 | tsk->thread.trap_nr = X86_TRAP_DF; |
081f75bb | 410 | |
e37e43a4 AL |
411 | #ifdef CONFIG_VMAP_STACK |
412 | /* | |
413 | * If we overflow the stack into a guard page, the CPU will fail | |
414 | * to deliver #PF and will send #DF instead. Similarly, if we | |
415 | * take any non-IST exception while too close to the bottom of | |
416 | * the stack, the processor will get a page fault while | |
417 | * delivering the exception and will generate a double fault. | |
418 | * | |
419 | * According to the SDM (footnote in 6.15 under "Interrupt 14 - | |
420 | * Page-Fault Exception (#PF): | |
421 | * | |
422 | * Processors update CR2 whenever a page fault is detected. If a | |
423 | * second page fault occurs while an earlier page fault is being | |
f5d8df27 | 424 | * delivered, the faulting linear address of the second fault will |
e37e43a4 AL |
425 | * overwrite the contents of CR2 (replacing the previous |
426 | * address). These updates to CR2 occur even if the page fault | |
427 | * results in a double fault or occurs during the delivery of a | |
428 | * double fault. | |
429 | * | |
430 | * The logic below has a small possibility of incorrectly diagnosing | |
431 | * some errors as stack overflows. For example, if the IDT or GDT | |
432 | * gets corrupted such that #GP delivery fails due to a bad descriptor | |
433 | * causing #GP and we hit this condition while CR2 coincidentally | |
434 | * points to the stack guard page, we'll think we overflowed the | |
435 | * stack. Given that we're going to panic one way or another | |
436 | * if this happens, this isn't necessarily worth fixing. | |
437 | * | |
438 | * If necessary, we could improve the test by only diagnosing | |
439 | * a stack overflow if the saved RSP points within 47 bytes of | |
440 | * the bottom of the stack: if RSP == tsk_stack + 48 and we | |
441 | * take an exception, the stack is already aligned and there | |
442 | * will be enough room SS, RSP, RFLAGS, CS, RIP, and a | |
443 | * possible error code, so a stack overflow would *not* double | |
444 | * fault. With any less space left, exception delivery could | |
445 | * fail, and, as a practical matter, we've overflowed the | |
446 | * stack even if the actual trigger for the double fault was | |
447 | * something else. | |
448 | */ | |
449 | cr2 = read_cr2(); | |
450 | if ((unsigned long)task_stack_page(tsk) - 1 - cr2 < PAGE_SIZE) | |
451 | handle_stack_overflow("kernel stack overflow (double-fault)", regs, cr2); | |
452 | #endif | |
453 | ||
4d067d8e BP |
454 | #ifdef CONFIG_DOUBLEFAULT |
455 | df_debug(regs, error_code); | |
456 | #endif | |
bd8b96df IM |
457 | /* |
458 | * This is always a kernel trap and never fixable (and thus must | |
459 | * never return). | |
460 | */ | |
081f75bb AH |
461 | for (;;) |
462 | die(str, regs, error_code); | |
463 | } | |
464 | #endif | |
465 | ||
fe3d197f DH |
466 | dotraplinkage void do_bounds(struct pt_regs *regs, long error_code) |
467 | { | |
1126cb45 | 468 | const struct mpx_bndcsr *bndcsr; |
fe3d197f DH |
469 | siginfo_t *info; |
470 | ||
5778077d | 471 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
fe3d197f DH |
472 | if (notify_die(DIE_TRAP, "bounds", regs, error_code, |
473 | X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) | |
8c84014f | 474 | return; |
d99e1bd1 | 475 | cond_local_irq_enable(regs); |
fe3d197f | 476 | |
f39b6f0e | 477 | if (!user_mode(regs)) |
fe3d197f DH |
478 | die("bounds", regs, error_code); |
479 | ||
480 | if (!cpu_feature_enabled(X86_FEATURE_MPX)) { | |
481 | /* The exception is not from Intel MPX */ | |
482 | goto exit_trap; | |
483 | } | |
484 | ||
485 | /* | |
486 | * We need to look at BNDSTATUS to resolve this exception. | |
a84eeaa9 DH |
487 | * A NULL here might mean that it is in its 'init state', |
488 | * which is all zeros which indicates MPX was not | |
489 | * responsible for the exception. | |
fe3d197f | 490 | */ |
d91cab78 | 491 | bndcsr = get_xsave_field_ptr(XFEATURE_MASK_BNDCSR); |
fe3d197f DH |
492 | if (!bndcsr) |
493 | goto exit_trap; | |
494 | ||
e7126cf5 | 495 | trace_bounds_exception_mpx(bndcsr); |
fe3d197f DH |
496 | /* |
497 | * The error code field of the BNDSTATUS register communicates status | |
498 | * information of a bound range exception #BR or operation involving | |
499 | * bound directory. | |
500 | */ | |
501 | switch (bndcsr->bndstatus & MPX_BNDSTA_ERROR_CODE) { | |
502 | case 2: /* Bound directory has invalid entry. */ | |
46a6e0cf | 503 | if (mpx_handle_bd_fault()) |
fe3d197f DH |
504 | goto exit_trap; |
505 | break; /* Success, it was handled */ | |
506 | case 1: /* Bound violation. */ | |
46a6e0cf | 507 | info = mpx_generate_siginfo(regs); |
e10abb2f | 508 | if (IS_ERR(info)) { |
fe3d197f DH |
509 | /* |
510 | * We failed to decode the MPX instruction. Act as if | |
511 | * the exception was not caused by MPX. | |
512 | */ | |
513 | goto exit_trap; | |
514 | } | |
515 | /* | |
516 | * Success, we decoded the instruction and retrieved | |
517 | * an 'info' containing the address being accessed | |
518 | * which caused the exception. This information | |
519 | * allows and application to possibly handle the | |
520 | * #BR exception itself. | |
521 | */ | |
522 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, info); | |
523 | kfree(info); | |
524 | break; | |
525 | case 0: /* No exception caused by Intel MPX operations. */ | |
526 | goto exit_trap; | |
527 | default: | |
528 | die("bounds", regs, error_code); | |
529 | } | |
530 | ||
fe3d197f | 531 | return; |
8c84014f | 532 | |
fe3d197f DH |
533 | exit_trap: |
534 | /* | |
535 | * This path out is for all the cases where we could not | |
536 | * handle the exception in some way (like allocating a | |
537 | * table or telling userspace about it. We will also end | |
538 | * up here if the kernel has MPX turned off at compile | |
539 | * time.. | |
540 | */ | |
541 | do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, error_code, NULL); | |
fe3d197f DH |
542 | } |
543 | ||
9326638c | 544 | dotraplinkage void |
13485ab5 | 545 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 546 | { |
13485ab5 | 547 | struct task_struct *tsk; |
b5964405 | 548 | |
5778077d | 549 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
d99e1bd1 | 550 | cond_local_irq_enable(regs); |
c6df0d71 | 551 | |
d74ef111 | 552 | if (v8086_mode(regs)) { |
ef3f6288 FW |
553 | local_irq_enable(); |
554 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
8c84014f | 555 | return; |
ef3f6288 | 556 | } |
1da177e4 | 557 | |
13485ab5 | 558 | tsk = current; |
55474c48 | 559 | if (!user_mode(regs)) { |
548acf19 | 560 | if (fixup_exception(regs, X86_TRAP_GP)) |
8c84014f | 561 | return; |
ef3f6288 FW |
562 | |
563 | tsk->thread.error_code = error_code; | |
564 | tsk->thread.trap_nr = X86_TRAP_GP; | |
6ba3c97a FW |
565 | if (notify_die(DIE_GPF, "general protection fault", regs, error_code, |
566 | X86_TRAP_GP, SIGSEGV) != NOTIFY_STOP) | |
ef3f6288 | 567 | die("general protection fault", regs, error_code); |
8c84014f | 568 | return; |
ef3f6288 | 569 | } |
1da177e4 | 570 | |
13485ab5 | 571 | tsk->thread.error_code = error_code; |
51e7dc70 | 572 | tsk->thread.trap_nr = X86_TRAP_GP; |
b5964405 | 573 | |
13485ab5 AH |
574 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
575 | printk_ratelimit()) { | |
c767a54b | 576 | pr_info("%s[%d] general protection ip:%lx sp:%lx error:%lx", |
13485ab5 AH |
577 | tsk->comm, task_pid_nr(tsk), |
578 | regs->ip, regs->sp, error_code); | |
1c99a687 | 579 | print_vma_addr(KERN_CONT " in ", regs->ip); |
c767a54b | 580 | pr_cont("\n"); |
03252919 | 581 | } |
abd4f750 | 582 | |
38cad57b | 583 | force_sig_info(SIGSEGV, SEND_SIG_PRIV, tsk); |
1da177e4 | 584 | } |
9326638c | 585 | NOKPROBE_SYMBOL(do_general_protection); |
1da177e4 | 586 | |
9326638c | 587 | dotraplinkage void notrace do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 588 | { |
08d636b6 | 589 | #ifdef CONFIG_DYNAMIC_FTRACE |
a192cd04 SR |
590 | /* |
591 | * ftrace must be first, everything else may cause a recursive crash. | |
592 | * See note by declaration of modifying_ftrace_code in ftrace.c | |
593 | */ | |
594 | if (unlikely(atomic_read(&modifying_ftrace_code)) && | |
595 | ftrace_int3_handler(regs)) | |
08d636b6 SR |
596 | return; |
597 | #endif | |
17f41571 JK |
598 | if (poke_int3_handler(regs)) |
599 | return; | |
600 | ||
cba47a38 AL |
601 | /* |
602 | * Use ist_enter despite the fact that we don't use an IST stack. | |
603 | * We can be called from a kprobe in non-CONTEXT_KERNEL kernel | |
604 | * mode or even during context tracking state changes. | |
605 | * | |
606 | * This means that we can't schedule. That's okay. | |
607 | */ | |
8c84014f | 608 | ist_enter(regs); |
5778077d | 609 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f503b5ae | 610 | #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP |
c9408265 KC |
611 | if (kgdb_ll_trap(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
612 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 613 | goto exit; |
f503b5ae | 614 | #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ |
cc3a1bf5 | 615 | |
6f6343f5 MH |
616 | #ifdef CONFIG_KPROBES |
617 | if (kprobe_int3_handler(regs)) | |
4cdf77a8 | 618 | goto exit; |
6f6343f5 MH |
619 | #endif |
620 | ||
c9408265 KC |
621 | if (notify_die(DIE_INT3, "int3", regs, error_code, X86_TRAP_BP, |
622 | SIGTRAP) == NOTIFY_STOP) | |
6ba3c97a | 623 | goto exit; |
b5964405 | 624 | |
d99e1bd1 | 625 | cond_local_irq_enable(regs); |
c9408265 | 626 | do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, error_code, NULL); |
d99e1bd1 | 627 | cond_local_irq_disable(regs); |
cba47a38 | 628 | |
6ba3c97a | 629 | exit: |
8c84014f | 630 | ist_exit(regs); |
1da177e4 | 631 | } |
9326638c | 632 | NOKPROBE_SYMBOL(do_int3); |
1da177e4 | 633 | |
081f75bb | 634 | #ifdef CONFIG_X86_64 |
bd8b96df | 635 | /* |
bfb2d0ed AL |
636 | * Help handler running on a per-cpu (IST or entry trampoline) stack |
637 | * to switch to the normal thread stack if the interrupted code was in | |
638 | * user mode. The actual stack switch is done in entry_64.S | |
bd8b96df | 639 | */ |
7ddc6a21 | 640 | asmlinkage __visible notrace struct pt_regs *sync_regs(struct pt_regs *eregs) |
081f75bb | 641 | { |
bfb2d0ed AL |
642 | struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1; |
643 | if (regs != eregs) | |
644 | *regs = *eregs; | |
081f75bb AH |
645 | return regs; |
646 | } | |
9326638c | 647 | NOKPROBE_SYMBOL(sync_regs); |
b645af2d AL |
648 | |
649 | struct bad_iret_stack { | |
650 | void *error_entry_ret; | |
651 | struct pt_regs regs; | |
652 | }; | |
653 | ||
7ddc6a21 | 654 | asmlinkage __visible notrace |
b645af2d AL |
655 | struct bad_iret_stack *fixup_bad_iret(struct bad_iret_stack *s) |
656 | { | |
657 | /* | |
658 | * This is called from entry_64.S early in handling a fault | |
659 | * caused by a bad iret to user mode. To handle the fault | |
bfb2d0ed AL |
660 | * correctly, we want to move our stack frame to where it would |
661 | * be had we entered directly on the entry stack (rather than | |
662 | * just below the IRET frame) and we want to pretend that the | |
663 | * exception came from the IRET target. | |
b645af2d AL |
664 | */ |
665 | struct bad_iret_stack *new_stack = | |
785be108 | 666 | (struct bad_iret_stack *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; |
b645af2d AL |
667 | |
668 | /* Copy the IRET target to the new stack. */ | |
669 | memmove(&new_stack->regs.ip, (void *)s->regs.sp, 5*8); | |
670 | ||
671 | /* Copy the remainder of the stack from the current stack. */ | |
672 | memmove(new_stack, s, offsetof(struct bad_iret_stack, regs.ip)); | |
673 | ||
f39b6f0e | 674 | BUG_ON(!user_mode(&new_stack->regs)); |
b645af2d AL |
675 | return new_stack; |
676 | } | |
7ddc6a21 | 677 | NOKPROBE_SYMBOL(fixup_bad_iret); |
081f75bb AH |
678 | #endif |
679 | ||
f2b37575 AL |
680 | static bool is_sysenter_singlestep(struct pt_regs *regs) |
681 | { | |
682 | /* | |
683 | * We don't try for precision here. If we're anywhere in the region of | |
684 | * code that can be single-stepped in the SYSENTER entry path, then | |
685 | * assume that this is a useless single-step trap due to SYSENTER | |
686 | * being invoked with TF set. (We don't know in advance exactly | |
687 | * which instructions will be hit because BTF could plausibly | |
688 | * be set.) | |
689 | */ | |
690 | #ifdef CONFIG_X86_32 | |
691 | return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < | |
692 | (unsigned long)__end_SYSENTER_singlestep_region - | |
693 | (unsigned long)__begin_SYSENTER_singlestep_region; | |
694 | #elif defined(CONFIG_IA32_EMULATION) | |
695 | return (regs->ip - (unsigned long)entry_SYSENTER_compat) < | |
696 | (unsigned long)__end_entry_SYSENTER_compat - | |
697 | (unsigned long)entry_SYSENTER_compat; | |
698 | #else | |
699 | return false; | |
700 | #endif | |
701 | } | |
702 | ||
1da177e4 LT |
703 | /* |
704 | * Our handling of the processor debug registers is non-trivial. | |
705 | * We do not clear them on entry and exit from the kernel. Therefore | |
706 | * it is possible to get a watchpoint trap here from inside the kernel. | |
707 | * However, the code in ./ptrace.c has ensured that the user can | |
708 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
709 | * watchpoint trap can only occur in code which is reading/writing | |
710 | * from user space. Such code must not hold kernel locks (since it | |
711 | * can equally take a page fault), therefore it is safe to call | |
712 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 713 | * |
1da177e4 LT |
714 | * Code in ./signal.c ensures that the debug control register |
715 | * is restored before we deliver any signal, and therefore that | |
716 | * user code runs with the correct debug control register even though | |
717 | * we clear it here. | |
718 | * | |
719 | * Being careful here means that we don't have to be as careful in a | |
720 | * lot of more complicated places (task switching can be a bit lazy | |
721 | * about restoring all the debug state, and ptrace doesn't have to | |
722 | * find every occurrence of the TF bit that could be saved away even | |
723 | * by user code) | |
c1d518c8 AH |
724 | * |
725 | * May run on IST stack. | |
1da177e4 | 726 | */ |
9326638c | 727 | dotraplinkage void do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 728 | { |
1da177e4 | 729 | struct task_struct *tsk = current; |
a1e80faf | 730 | int user_icebp = 0; |
08d68323 | 731 | unsigned long dr6; |
da654b74 | 732 | int si_code; |
1da177e4 | 733 | |
8c84014f | 734 | ist_enter(regs); |
4cdf77a8 | 735 | |
08d68323 | 736 | get_debugreg(dr6, 6); |
8bb56436 AL |
737 | /* |
738 | * The Intel SDM says: | |
739 | * | |
740 | * Certain debug exceptions may clear bits 0-3. The remaining | |
741 | * contents of the DR6 register are never cleared by the | |
742 | * processor. To avoid confusion in identifying debug | |
743 | * exceptions, debug handlers should clear the register before | |
744 | * returning to the interrupted task. | |
745 | * | |
746 | * Keep it simple: clear DR6 immediately. | |
747 | */ | |
748 | set_debugreg(0, 6); | |
1da177e4 | 749 | |
40f9249a P |
750 | /* Filter out all the reserved bits which are preset to 1 */ |
751 | dr6 &= ~DR6_RESERVED; | |
752 | ||
81edd9f6 AL |
753 | /* |
754 | * The SDM says "The processor clears the BTF flag when it | |
755 | * generates a debug exception." Clear TIF_BLOCKSTEP to keep | |
756 | * TIF_BLOCKSTEP in sync with the hardware BTF flag. | |
757 | */ | |
758 | clear_tsk_thread_flag(tsk, TIF_BLOCKSTEP); | |
759 | ||
f2b37575 AL |
760 | if (unlikely(!user_mode(regs) && (dr6 & DR_STEP) && |
761 | is_sysenter_singlestep(regs))) { | |
762 | dr6 &= ~DR_STEP; | |
763 | if (!dr6) | |
764 | goto exit; | |
765 | /* | |
766 | * else we might have gotten a single-step trap and hit a | |
767 | * watchpoint at the same time, in which case we should fall | |
768 | * through and handle the watchpoint. | |
769 | */ | |
770 | } | |
771 | ||
a1e80faf FW |
772 | /* |
773 | * If dr6 has no reason to give us about the origin of this trap, | |
774 | * then it's very likely the result of an icebp/int01 trap. | |
775 | * User wants a sigtrap for that. | |
776 | */ | |
f39b6f0e | 777 | if (!dr6 && user_mode(regs)) |
a1e80faf FW |
778 | user_icebp = 1; |
779 | ||
f2b37575 | 780 | /* Catch kmemcheck conditions! */ |
eadb8a09 | 781 | if ((dr6 & DR_STEP) && kmemcheck_trap(regs)) |
6ba3c97a | 782 | goto exit; |
f8561296 | 783 | |
08d68323 P |
784 | /* Store the virtualized DR6 value */ |
785 | tsk->thread.debugreg6 = dr6; | |
786 | ||
6f6343f5 MH |
787 | #ifdef CONFIG_KPROBES |
788 | if (kprobe_debug_handler(regs)) | |
789 | goto exit; | |
790 | #endif | |
791 | ||
5a802e15 | 792 | if (notify_die(DIE_DEBUG, "debug", regs, (long)&dr6, error_code, |
62edab90 | 793 | SIGTRAP) == NOTIFY_STOP) |
6ba3c97a | 794 | goto exit; |
3d2a71a5 | 795 | |
42181186 SR |
796 | /* |
797 | * Let others (NMI) know that the debug stack is in use | |
798 | * as we may switch to the interrupt stack. | |
799 | */ | |
800 | debug_stack_usage_inc(); | |
801 | ||
1da177e4 | 802 | /* It's safe to allow irq's after DR6 has been saved */ |
d99e1bd1 | 803 | cond_local_irq_enable(regs); |
1da177e4 | 804 | |
d74ef111 | 805 | if (v8086_mode(regs)) { |
c9408265 KC |
806 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, |
807 | X86_TRAP_DB); | |
d99e1bd1 | 808 | cond_local_irq_disable(regs); |
42181186 | 809 | debug_stack_usage_dec(); |
6ba3c97a | 810 | goto exit; |
1da177e4 LT |
811 | } |
812 | ||
f2b37575 AL |
813 | if (WARN_ON_ONCE((dr6 & DR_STEP) && !user_mode(regs))) { |
814 | /* | |
815 | * Historical junk that used to handle SYSENTER single-stepping. | |
816 | * This should be unreachable now. If we survive for a while | |
817 | * without anyone hitting this warning, we'll turn this into | |
818 | * an oops. | |
819 | */ | |
08d68323 P |
820 | tsk->thread.debugreg6 &= ~DR_STEP; |
821 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
822 | regs->flags &= ~X86_EFLAGS_TF; | |
1da177e4 | 823 | } |
08d68323 | 824 | si_code = get_si_code(tsk->thread.debugreg6); |
a1e80faf | 825 | if (tsk->thread.debugreg6 & (DR_STEP | DR_TRAP_BITS) || user_icebp) |
08d68323 | 826 | send_sigtrap(tsk, regs, error_code, si_code); |
d99e1bd1 | 827 | cond_local_irq_disable(regs); |
42181186 | 828 | debug_stack_usage_dec(); |
1da177e4 | 829 | |
6ba3c97a | 830 | exit: |
8c84014f | 831 | ist_exit(regs); |
1da177e4 | 832 | } |
9326638c | 833 | NOKPROBE_SYMBOL(do_debug); |
1da177e4 LT |
834 | |
835 | /* | |
836 | * Note that we play around with the 'TS' bit in an attempt to get | |
837 | * the correct behaviour even in the presence of the asynchronous | |
838 | * IRQ13 behaviour | |
839 | */ | |
5e1b05be | 840 | static void math_error(struct pt_regs *regs, int error_code, int trapnr) |
1da177e4 | 841 | { |
e2e75c91 | 842 | struct task_struct *task = current; |
e1cebad4 | 843 | struct fpu *fpu = &task->thread.fpu; |
1da177e4 | 844 | siginfo_t info; |
c9408265 KC |
845 | char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : |
846 | "simd exception"; | |
e2e75c91 BG |
847 | |
848 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, SIGFPE) == NOTIFY_STOP) | |
849 | return; | |
d99e1bd1 | 850 | cond_local_irq_enable(regs); |
e2e75c91 | 851 | |
e1cebad4 | 852 | if (!user_mode(regs)) { |
548acf19 | 853 | if (!fixup_exception(regs, trapnr)) { |
e2e75c91 | 854 | task->thread.error_code = error_code; |
51e7dc70 | 855 | task->thread.trap_nr = trapnr; |
e2e75c91 BG |
856 | die(str, regs, error_code); |
857 | } | |
858 | return; | |
859 | } | |
1da177e4 LT |
860 | |
861 | /* | |
862 | * Save the info for the exception handler and clear the error. | |
863 | */ | |
e1cebad4 IM |
864 | fpu__save(fpu); |
865 | ||
866 | task->thread.trap_nr = trapnr; | |
9b6dba9e | 867 | task->thread.error_code = error_code; |
e1cebad4 IM |
868 | info.si_signo = SIGFPE; |
869 | info.si_errno = 0; | |
870 | info.si_addr = (void __user *)uprobe_get_trap_addr(regs); | |
adf77bac | 871 | |
e1cebad4 | 872 | info.si_code = fpu__exception_code(fpu, trapnr); |
adf77bac | 873 | |
e1cebad4 IM |
874 | /* Retry when we get spurious exceptions: */ |
875 | if (!info.si_code) | |
c9408265 | 876 | return; |
e1cebad4 | 877 | |
1da177e4 LT |
878 | force_sig_info(SIGFPE, &info, task); |
879 | } | |
880 | ||
e407d620 | 881 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 882 | { |
5778077d | 883 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 884 | math_error(regs, error_code, X86_TRAP_MF); |
1da177e4 LT |
885 | } |
886 | ||
e407d620 AH |
887 | dotraplinkage void |
888 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 889 | { |
5778077d | 890 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
c9408265 | 891 | math_error(regs, error_code, X86_TRAP_XF); |
1da177e4 LT |
892 | } |
893 | ||
e407d620 AH |
894 | dotraplinkage void |
895 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 896 | { |
d99e1bd1 | 897 | cond_local_irq_enable(regs); |
081f75bb AH |
898 | } |
899 | ||
9326638c | 900 | dotraplinkage void |
aa78bcfa | 901 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 902 | { |
bef8b6da AL |
903 | unsigned long cr0; |
904 | ||
5778077d | 905 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
304bceda | 906 | |
a334fe43 | 907 | #ifdef CONFIG_MATH_EMULATION |
c6ab109f | 908 | if (!boot_cpu_has(X86_FEATURE_FPU) && (read_cr0() & X86_CR0_EM)) { |
d315760f TH |
909 | struct math_emu_info info = { }; |
910 | ||
d99e1bd1 | 911 | cond_local_irq_enable(regs); |
d315760f | 912 | |
aa78bcfa | 913 | info.regs = regs; |
d315760f | 914 | math_emulate(&info); |
a334fe43 | 915 | return; |
7643e9b9 | 916 | } |
a334fe43 | 917 | #endif |
bef8b6da AL |
918 | |
919 | /* This should not happen. */ | |
920 | cr0 = read_cr0(); | |
921 | if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { | |
922 | /* Try to fix it up and carry on. */ | |
923 | write_cr0(cr0 & ~X86_CR0_TS); | |
924 | } else { | |
925 | /* | |
926 | * Something terrible happened, and we're better off trying | |
927 | * to kill the task than getting stuck in a never-ending | |
928 | * loop of #NM faults. | |
929 | */ | |
930 | die("unexpected #NM exception", regs, error_code); | |
931 | } | |
7643e9b9 | 932 | } |
9326638c | 933 | NOKPROBE_SYMBOL(do_device_not_available); |
7643e9b9 | 934 | |
081f75bb | 935 | #ifdef CONFIG_X86_32 |
e407d620 | 936 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
937 | { |
938 | siginfo_t info; | |
6ba3c97a | 939 | |
5778077d | 940 | RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); |
f8e0870f AH |
941 | local_irq_enable(); |
942 | ||
943 | info.si_signo = SIGILL; | |
944 | info.si_errno = 0; | |
945 | info.si_code = ILL_BADSTK; | |
fc6fcdfb | 946 | info.si_addr = NULL; |
c9408265 | 947 | if (notify_die(DIE_TRAP, "iret exception", regs, error_code, |
6ba3c97a FW |
948 | X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { |
949 | do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, error_code, | |
950 | &info); | |
951 | } | |
f8e0870f | 952 | } |
081f75bb | 953 | #endif |
f8e0870f | 954 | |
29c84391 JK |
955 | /* Set of traps needed for early debugging. */ |
956 | void __init early_trap_init(void) | |
957 | { | |
b4d83270 | 958 | /* |
5eca7453 WN |
959 | * Don't use IST to set DEBUG_STACK as it doesn't work until TSS |
960 | * is ready in cpu_init() <-- trap_init(). Before trap_init(), | |
961 | * CPU runs at ring 0 so it is impossible to hit an invalid | |
962 | * stack. Using the original stack works well enough at this | |
963 | * early stage. DEBUG_STACK will be equipped after cpu_init() in | |
b4d83270 | 964 | * trap_init(). |
5eca7453 WN |
965 | * |
966 | * We don't need to set trace_idt_table like set_intr_gate(), | |
967 | * since we don't have trace_debug and it will be reset to | |
968 | * 'debug' in trap_init() by set_intr_gate_ist(). | |
b4d83270 | 969 | */ |
5eca7453 | 970 | set_intr_gate_notrace(X86_TRAP_DB, debug); |
29c84391 | 971 | /* int3 can be called from all */ |
5eca7453 | 972 | set_system_intr_gate(X86_TRAP_BP, &int3); |
8170e6be | 973 | #ifdef CONFIG_X86_32 |
25c74b10 | 974 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be | 975 | #endif |
29c84391 JK |
976 | load_idt(&idt_descr); |
977 | } | |
978 | ||
8170e6be PA |
979 | void __init early_trap_pf_init(void) |
980 | { | |
981 | #ifdef CONFIG_X86_64 | |
25c74b10 | 982 | set_intr_gate(X86_TRAP_PF, page_fault); |
8170e6be PA |
983 | #endif |
984 | } | |
985 | ||
1da177e4 LT |
986 | void __init trap_init(void) |
987 | { | |
dbeb2be2 RR |
988 | int i; |
989 | ||
88e72777 AL |
990 | /* Init cpu_entry_area before IST entries are set up */ |
991 | setup_cpu_entry_areas(); | |
992 | ||
1da177e4 | 993 | #ifdef CONFIG_EISA |
927222b1 | 994 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
995 | |
996 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 997 | EISA_bus = 1; |
927222b1 | 998 | early_iounmap(p, 4); |
1da177e4 LT |
999 | #endif |
1000 | ||
25c74b10 | 1001 | set_intr_gate(X86_TRAP_DE, divide_error); |
c9408265 | 1002 | set_intr_gate_ist(X86_TRAP_NMI, &nmi, NMI_STACK); |
699d2937 | 1003 | /* int4 can be called from all */ |
c9408265 | 1004 | set_system_intr_gate(X86_TRAP_OF, &overflow); |
25c74b10 SA |
1005 | set_intr_gate(X86_TRAP_BR, bounds); |
1006 | set_intr_gate(X86_TRAP_UD, invalid_op); | |
1007 | set_intr_gate(X86_TRAP_NM, device_not_available); | |
081f75bb | 1008 | #ifdef CONFIG_X86_32 |
c9408265 | 1009 | set_task_gate(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb | 1010 | #else |
c9408265 | 1011 | set_intr_gate_ist(X86_TRAP_DF, &double_fault, DOUBLEFAULT_STACK); |
081f75bb | 1012 | #endif |
25c74b10 SA |
1013 | set_intr_gate(X86_TRAP_OLD_MF, coprocessor_segment_overrun); |
1014 | set_intr_gate(X86_TRAP_TS, invalid_TSS); | |
1015 | set_intr_gate(X86_TRAP_NP, segment_not_present); | |
6f442be2 | 1016 | set_intr_gate(X86_TRAP_SS, stack_segment); |
25c74b10 SA |
1017 | set_intr_gate(X86_TRAP_GP, general_protection); |
1018 | set_intr_gate(X86_TRAP_SPURIOUS, spurious_interrupt_bug); | |
1019 | set_intr_gate(X86_TRAP_MF, coprocessor_error); | |
1020 | set_intr_gate(X86_TRAP_AC, alignment_check); | |
1da177e4 | 1021 | #ifdef CONFIG_X86_MCE |
c9408265 | 1022 | set_intr_gate_ist(X86_TRAP_MC, &machine_check, MCE_STACK); |
1da177e4 | 1023 | #endif |
25c74b10 | 1024 | set_intr_gate(X86_TRAP_XF, simd_coprocessor_error); |
1da177e4 | 1025 | |
bb3f0b59 YL |
1026 | /* Reserve all the builtin and the syscall vector: */ |
1027 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) | |
1028 | set_bit(i, used_vectors); | |
1029 | ||
081f75bb | 1030 | #ifdef CONFIG_IA32_EMULATION |
2cd23553 | 1031 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_compat); |
bb3f0b59 | 1032 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb AH |
1033 | #endif |
1034 | ||
1035 | #ifdef CONFIG_X86_32 | |
a798f091 | 1036 | set_system_intr_gate(IA32_SYSCALL_VECTOR, entry_INT80_32); |
51bb9284 | 1037 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); |
081f75bb | 1038 | #endif |
bb3f0b59 | 1039 | |
4eefbe79 KC |
1040 | /* |
1041 | * Set the IDT descriptor to a fixed read-only location, so that the | |
1042 | * "sidt" instruction will not leak the location of the kernel, and | |
1043 | * to defend the IDT against arbitrary memory write vulnerabilities. | |
1044 | * It will be reloaded in cpu_init() */ | |
bda9eb32 TG |
1045 | cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table), |
1046 | PAGE_KERNEL_RO); | |
1047 | idt_descr.address = CPU_ENTRY_AREA_RO_IDT; | |
4eefbe79 | 1048 | |
1da177e4 | 1049 | /* |
b5964405 | 1050 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
1051 | */ |
1052 | cpu_init(); | |
1053 | ||
b4d83270 WN |
1054 | /* |
1055 | * X86_TRAP_DB and X86_TRAP_BP have been set | |
5eca7453 | 1056 | * in early_trap_init(). However, ITS works only after |
b4d83270 WN |
1057 | * cpu_init() loads TSS. See comments in early_trap_init(). |
1058 | */ | |
1059 | set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK); | |
b4d83270 | 1060 | |
428cf902 | 1061 | x86_init.irqs.trap_init(); |
228bdaa9 SR |
1062 | |
1063 | #ifdef CONFIG_X86_64 | |
629f4f9d | 1064 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); |
c9408265 | 1065 | set_nmi_gate(X86_TRAP_DB, &debug); |
228bdaa9 | 1066 | #endif |
1da177e4 | 1067 | } |