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block: Consolidate phys_segment and hw_segment limits
[mirror_ubuntu-artful-kernel.git] / drivers / block / sx8.c
CommitLineData
1da177e4
LT		 1/*
2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
3 *
2d5a2ae5 4 * Copyright 2004-2005 Red Hat, Inc.
1da177e4
LT		 5 *
6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/spinlock.h>
19#include <linux/blkdev.h>
20#include <linux/sched.h>
1da177e4
LT		 21#include <linux/interrupt.h>
22#include <linux/compiler.h>
23#include <linux/workqueue.h>
24#include <linux/bitops.h>
25#include <linux/delay.h>
26#include <linux/time.h>
27#include <linux/hdreg.h>
a3948663 28#include <linux/dma-mapping.h>
906c3b75 29#include <linux/completion.h>
11763609 30#include <linux/scatterlist.h>
1da177e4 31#include <asm/io.h>
1da177e4
LT		 32#include <asm/uaccess.h>
33
1da177e4
LT		 34#if 0
35#define CARM_DEBUG
36#define CARM_VERBOSE_DEBUG
37#else
38#undef CARM_DEBUG
39#undef CARM_VERBOSE_DEBUG
40#endif
41#undef CARM_NDEBUG
42
43#define DRV_NAME "sx8"
2d5a2ae5 44#define DRV_VERSION "1.0"
1da177e4
LT		 45#define PFX DRV_NAME ": "
46
2d5a2ae5
JG		 47MODULE_AUTHOR("Jeff Garzik");
48MODULE_LICENSE("GPL");
49MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50MODULE_VERSION(DRV_VERSION);
51
52/*
53 * SX8 hardware has a single message queue for all ATA ports.
54 * When this driver was written, the hardware (firmware?) would
55 * corrupt data eventually, if more than one request was outstanding.
56 * As one can imagine, having 8 ports bottlenecking on a single
57 * command hurts performance.
58 *
59 * Based on user reports, later versions of the hardware (firmware?)
60 * seem to be able to survive with more than one command queued.
61 *
62 * Therefore, we default to the safe option -- 1 command -- but
63 * allow the user to increase this.
64 *
65 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ),
66 * but problems seem to occur when you exceed ~30, even on newer hardware.
67 */
68static int max_queue = 1;
69module_param(max_queue, int, 0444);
70MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71
72
1da177e4
LT		 73#define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
74
75/* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
76#define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
77#define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
78#define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79
80/* note: prints function name for you */
81#ifdef CARM_DEBUG
cece9339 82#define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
1da177e4 83#ifdef CARM_VERBOSE_DEBUG
cece9339 84#define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
1da177e4
LT		 85#else
86#define VPRINTK(fmt, args...)
87#endif /* CARM_VERBOSE_DEBUG */
88#else
89#define DPRINTK(fmt, args...)
90#define VPRINTK(fmt, args...)
91#endif /* CARM_DEBUG */
92
93#ifdef CARM_NDEBUG
94#define assert(expr)
95#else
96#define assert(expr) \
97 if(unlikely(!(expr))) { \
98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
cece9339 99 #expr, __FILE__, __func__, __LINE__); \
1da177e4
LT		 100 }
101#endif
102
103/* defines only for the constants which don't work well as enums */
104struct carm_host;
105
106enum {
107 /* adapter-wide limits */
108 CARM_MAX_PORTS = 8,
109 CARM_SHM_SIZE = (4096 << 7),
110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
112
113 /* command message queue limits */
114 CARM_MAX_REQ = 64, /* max command msgs per host */
1da177e4
LT		 115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */
116
117 /* S/G limits, host-wide and per-request */
118 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */
1da177e4
LT		 119 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */
120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */
121
122 /* hardware registers */
123 CARM_IHQP = 0x1c,
124 CARM_INT_STAT = 0x10, /* interrupt status */
125 CARM_INT_MASK = 0x14, /* interrupt mask */
126 CARM_HMUC = 0x18, /* host message unit control */
127 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */
128 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */
129 RBUF_BYTE_SZ = 0x28,
130 CARM_RESP_IDX = 0x2c,
131 CARM_CMS0 = 0x30, /* command message size reg 0 */
132 CARM_LMUC = 0x48,
133 CARM_HMPHA = 0x6c,
134 CARM_INITC = 0xb5,
135
136 /* bits in CARM_INT_{STAT,MASK} */
137 INT_RESERVED = 0xfffffff0,
138 INT_WATCHDOG = (1 << 3), /* watchdog timer */
139 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */
140 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */
141 INT_RESPONSE = (1 << 0), /* response msg available */
142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
144 INT_RESPONSE,
145
146 /* command messages, and related register bits */
147 CARM_HAVE_RESP = 0x01,
148 CARM_MSG_READ = 1,
149 CARM_MSG_WRITE = 2,
150 CARM_MSG_VERIFY = 3,
151 CARM_MSG_GET_CAPACITY = 4,
152 CARM_MSG_FLUSH = 5,
153 CARM_MSG_IOCTL = 6,
154 CARM_MSG_ARRAY = 8,
155 CARM_MSG_MISC = 9,
156 CARM_CME = (1 << 2),
157 CARM_RME = (1 << 1),
158 CARM_WZBC = (1 << 0),
159 CARM_RMI = (1 << 0),
160 CARM_Q_FULL = (1 << 3),
161 CARM_MSG_SIZE = 288,
162 CARM_Q_LEN = 48,
163
164 /* CARM_MSG_IOCTL messages */
165 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */
166 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */
167 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */
168
169 IOC_SCAN_CHAN_NODEV = 0x1f,
170 IOC_SCAN_CHAN_OFFSET = 0x40,
171
172 /* CARM_MSG_ARRAY messages */
173 CARM_ARRAY_INFO = 0,
174
175 ARRAY_NO_EXIST = (1 << 31),
176
177 /* response messages */
178 RMSG_SZ = 8, /* sizeof(struct carm_response) */
179 RMSG_Q_LEN = 48, /* resp. msg list length */
180 RMSG_OK = 1, /* bit indicating msg was successful */
181 /* length of entire resp. msg buffer */
182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
183
184 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */
185
186 /* CARM_MSG_MISC messages */
187 MISC_GET_FW_VER = 2,
188 MISC_ALLOC_MEM = 3,
189 MISC_SET_TIME = 5,
190
191 /* MISC_GET_FW_VER feature bits */
192 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */
193 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */
194 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */
195
196 /* carm_host flags */
197 FL_NON_RAID = FW_VER_NON_RAID,
198 FL_4PORT = FW_VER_4PORT,
199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
200 FL_DAC = (1 << 16),
201 FL_DYN_MAJOR = (1 << 17),
202};
203
2d5a2ae5
JG		 204enum {
205 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */
206};
207
1da177e4
LT		 208enum scatter_gather_types {
209 SGT_32BIT = 0,
210 SGT_64BIT = 1,
211};
212
213enum host_states {
214 HST_INVALID, /* invalid state; never used */
215 HST_ALLOC_BUF, /* setting up master SHM area */
216 HST_ERROR, /* we never leave here */
217 HST_PORT_SCAN, /* start dev scan */
218 HST_DEV_SCAN_START, /* start per-device probe */
219 HST_DEV_SCAN, /* continue per-device probe */
220 HST_DEV_ACTIVATE, /* activate devices we found */
221 HST_PROBE_FINISHED, /* probe is complete */
222 HST_PROBE_START, /* initiate probe */
223 HST_SYNC_TIME, /* tell firmware what time it is */
224 HST_GET_FW_VER, /* get firmware version, adapter port cnt */
225};
226
227#ifdef CARM_DEBUG
228static const char *state_name[] = {
229 "HST_INVALID",
230 "HST_ALLOC_BUF",
231 "HST_ERROR",
232 "HST_PORT_SCAN",
233 "HST_DEV_SCAN_START",
234 "HST_DEV_SCAN",
235 "HST_DEV_ACTIVATE",
236 "HST_PROBE_FINISHED",
237 "HST_PROBE_START",
238 "HST_SYNC_TIME",
239 "HST_GET_FW_VER",
240};
241#endif
242
243struct carm_port {
244 unsigned int port_no;
1da177e4
LT		 245 struct gendisk *disk;
246 struct carm_host *host;
247
248 /* attached device characteristics */
249 u64 capacity;
250 char name[41];
251 u16 dev_geom_head;
252 u16 dev_geom_sect;
253 u16 dev_geom_cyl;
254};
255
256struct carm_request {
257 unsigned int tag;
258 int n_elem;
259 unsigned int msg_type;
260 unsigned int msg_subtype;
261 unsigned int msg_bucket;
262 struct request *rq;
263 struct carm_port *port;
264 struct scatterlist sg[CARM_MAX_REQ_SG];
265};
266
267struct carm_host {
268 unsigned long flags;
269 void __iomem *mmio;
270 void *shm;
271 dma_addr_t shm_dma;
272
273 int major;
274 int id;
275 char name[32];
276
277 spinlock_t lock;
278 struct pci_dev *pdev;
279 unsigned int state;
280 u32 fw_ver;
281
165125e1 282 struct request_queue *oob_q;
1da177e4
LT		 283 unsigned int n_oob;
284
285 unsigned int hw_sg_used;
286
287 unsigned int resp_idx;
288
289 unsigned int wait_q_prod;
290 unsigned int wait_q_cons;
165125e1 291 struct request_queue *wait_q[CARM_MAX_WAIT_Q];
1da177e4
LT		 292
293 unsigned int n_msgs;
294 u64 msg_alloc;
295 struct carm_request req[CARM_MAX_REQ];
296 void *msg_base;
297 dma_addr_t msg_dma;
298
299 int cur_scan_dev;
300 unsigned long dev_active;
301 unsigned long dev_present;
302 struct carm_port port[CARM_MAX_PORTS];
303
304 struct work_struct fsm_task;
305
906c3b75 306 struct completion probe_comp;
1da177e4
LT		 307};
308
309struct carm_response {
310 __le32 ret_handle;
311 __le32 status;
312} __attribute__((packed));
313
314struct carm_msg_sg {
315 __le32 start;
316 __le32 len;
317} __attribute__((packed));
318
319struct carm_msg_rw {
320 u8 type;
321 u8 id;
322 u8 sg_count;
323 u8 sg_type;
324 __le32 handle;
325 __le32 lba;
326 __le16 lba_count;
327 __le16 lba_high;
328 struct carm_msg_sg sg[32];
329} __attribute__((packed));
330
331struct carm_msg_allocbuf {
332 u8 type;
333 u8 subtype;
334 u8 n_sg;
335 u8 sg_type;
336 __le32 handle;
337 __le32 addr;
338 __le32 len;
339 __le32 evt_pool;
340 __le32 n_evt;
341 __le32 rbuf_pool;
342 __le32 n_rbuf;
343 __le32 msg_pool;
344 __le32 n_msg;
345 struct carm_msg_sg sg[8];
346} __attribute__((packed));
347
348struct carm_msg_ioctl {
349 u8 type;
350 u8 subtype;
351 u8 array_id;
352 u8 reserved1;
353 __le32 handle;
354 __le32 data_addr;
355 u32 reserved2;
356} __attribute__((packed));
357
358struct carm_msg_sync_time {
359 u8 type;
360 u8 subtype;
361 u16 reserved1;
362 __le32 handle;
363 u32 reserved2;
364 __le32 timestamp;
365} __attribute__((packed));
366
367struct carm_msg_get_fw_ver {
368 u8 type;
369 u8 subtype;
370 u16 reserved1;
371 __le32 handle;
372 __le32 data_addr;
373 u32 reserved2;
374} __attribute__((packed));
375
376struct carm_fw_ver {
377 __le32 version;
378 u8 features;
379 u8 reserved1;
380 u16 reserved2;
381} __attribute__((packed));
382
383struct carm_array_info {
384 __le32 size;
385
386 __le16 size_hi;
387 __le16 stripe_size;
388
389 __le32 mode;
390
391 __le16 stripe_blk_sz;
392 __le16 reserved1;
393
394 __le16 cyl;
395 __le16 head;
396
397 __le16 sect;
398 u8 array_id;
399 u8 reserved2;
400
401 char name[40];
402
403 __le32 array_status;
404
405 /* device list continues beyond this point? */
406} __attribute__((packed));
407
408static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
409static void carm_remove_one (struct pci_dev *pdev);
a885c8c4 410static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo);
1da177e4 411
3d447ec0 412static const struct pci_device_id carm_pci_tbl[] = {
1da177e4
LT		 413 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
414 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
415 { } /* terminate list */
416};
417MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
418
419static struct pci_driver carm_driver = {
420 .name = DRV_NAME,
421 .id_table = carm_pci_tbl,
422 .probe = carm_init_one,
423 .remove = carm_remove_one,
424};
425
83d5cde4 426static const struct block_device_operations carm_bd_ops = {
1da177e4 427 .owner = THIS_MODULE,
a885c8c4 428 .getgeo = carm_bdev_getgeo,
1da177e4
LT		 429};
430
431static unsigned int carm_host_id;
432static unsigned long carm_major_alloc;
433
434
435
a885c8c4 436static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1da177e4 437{
a885c8c4 438 struct carm_port *port = bdev->bd_disk->private_data;
1da177e4 439
a885c8c4
CH		 440 geo->heads = (u8) port->dev_geom_head;
441 geo->sectors = (u8) port->dev_geom_sect;
442 geo->cylinders = port->dev_geom_cyl;
443 return 0;
1da177e4
LT		 444}
445
446static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
447
448static inline int carm_lookup_bucket(u32 msg_size)
449{
450 int i;
451
452 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
453 if (msg_size <= msg_sizes[i])
454 return i;
2d5a2ae5 455
1da177e4
LT		 456 return -ENOENT;
457}
458
459static void carm_init_buckets(void __iomem *mmio)
460{
461 unsigned int i;
462
463 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
464 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
465}
466
467static inline void *carm_ref_msg(struct carm_host *host,
468 unsigned int msg_idx)
469{
470 return host->msg_base + (msg_idx * CARM_MSG_SIZE);
471}
472
473static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
474 unsigned int msg_idx)
475{
476 return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
477}
478
479static int carm_send_msg(struct carm_host *host,
480 struct carm_request *crq)
481{
482 void __iomem *mmio = host->mmio;
483 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
484 u32 cm_bucket = crq->msg_bucket;
485 u32 tmp;
486 int rc = 0;
487
488 VPRINTK("ENTER\n");
489
490 tmp = readl(mmio + CARM_HMUC);
491 if (tmp & CARM_Q_FULL) {
492#if 0
493 tmp = readl(mmio + CARM_INT_MASK);
494 tmp |= INT_Q_AVAILABLE;
495 writel(tmp, mmio + CARM_INT_MASK);
496 readl(mmio + CARM_INT_MASK); /* flush */
497#endif
498 DPRINTK("host msg queue full\n");
499 rc = -EBUSY;
500 } else {
501 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
502 readl(mmio + CARM_IHQP); /* flush */
503 }
504
505 return rc;
506}
507
508static struct carm_request *carm_get_request(struct carm_host *host)
509{
510 unsigned int i;
511
512 /* obey global hardware limit on S/G entries */
513 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
514 return NULL;
515
2d5a2ae5 516 for (i = 0; i < max_queue; i++)
1da177e4
LT		 517 if ((host->msg_alloc & (1ULL << i)) == 0) {
518 struct carm_request *crq = &host->req[i];
519 crq->port = NULL;
520 crq->n_elem = 0;
521
522 host->msg_alloc |= (1ULL << i);
523 host->n_msgs++;
524
525 assert(host->n_msgs <= CARM_MAX_REQ);
45711f1a 526 sg_init_table(crq->sg, CARM_MAX_REQ_SG);
1da177e4
LT		 527 return crq;
528 }
2d5a2ae5 529
1da177e4
LT		 530 DPRINTK("no request available, returning NULL\n");
531 return NULL;
532}
533
534static int carm_put_request(struct carm_host *host, struct carm_request *crq)
535{
2d5a2ae5 536 assert(crq->tag < max_queue);
1da177e4
LT		 537
538 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
539 return -EINVAL; /* tried to clear a tag that was not active */
540
541 assert(host->hw_sg_used >= crq->n_elem);
542
543 host->msg_alloc &= ~(1ULL << crq->tag);
544 host->hw_sg_used -= crq->n_elem;
545 host->n_msgs--;
546
547 return 0;
548}
549
550static struct carm_request *carm_get_special(struct carm_host *host)
551{
552 unsigned long flags;
553 struct carm_request *crq = NULL;
554 struct request *rq;
555 int tries = 5000;
556
557 while (tries-- > 0) {
558 spin_lock_irqsave(&host->lock, flags);
559 crq = carm_get_request(host);
560 spin_unlock_irqrestore(&host->lock, flags);
561
562 if (crq)
563 break;
564 msleep(10);
565 }
566
567 if (!crq)
568 return NULL;
569
570 rq = blk_get_request(host->oob_q, WRITE /* bogus */, GFP_KERNEL);
571 if (!rq) {
572 spin_lock_irqsave(&host->lock, flags);
573 carm_put_request(host, crq);
574 spin_unlock_irqrestore(&host->lock, flags);
575 return NULL;
576 }
577
578 crq->rq = rq;
579 return crq;
580}
581
582static int carm_array_info (struct carm_host *host, unsigned int array_idx)
583{
584 struct carm_msg_ioctl *ioc;
585 unsigned int idx;
586 u32 msg_data;
587 dma_addr_t msg_dma;
588 struct carm_request *crq;
589 int rc;
590
591 crq = carm_get_special(host);
592 if (!crq) {
593 rc = -ENOMEM;
594 goto err_out;
595 }
596
597 idx = crq->tag;
598
599 ioc = carm_ref_msg(host, idx);
600 msg_dma = carm_ref_msg_dma(host, idx);
601 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
602
603 crq->msg_type = CARM_MSG_ARRAY;
604 crq->msg_subtype = CARM_ARRAY_INFO;
605 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
606 sizeof(struct carm_array_info));
607 BUG_ON(rc < 0);
608 crq->msg_bucket = (u32) rc;
609
610 memset(ioc, 0, sizeof(*ioc));
611 ioc->type = CARM_MSG_ARRAY;
612 ioc->subtype = CARM_ARRAY_INFO;
613 ioc->array_id = (u8) array_idx;
614 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
615 ioc->data_addr = cpu_to_le32(msg_data);
616
617 spin_lock_irq(&host->lock);
618 assert(host->state == HST_DEV_SCAN_START ||
619 host->state == HST_DEV_SCAN);
620 spin_unlock_irq(&host->lock);
621
622 DPRINTK("blk_insert_request, tag == %u\n", idx);
867d1191 623 blk_insert_request(host->oob_q, crq->rq, 1, crq);
1da177e4
LT		 624
625 return 0;
626
627err_out:
628 spin_lock_irq(&host->lock);
629 host->state = HST_ERROR;
630 spin_unlock_irq(&host->lock);
631 return rc;
632}
633
634typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
635
636static int carm_send_special (struct carm_host *host, carm_sspc_t func)
637{
638 struct carm_request *crq;
639 struct carm_msg_ioctl *ioc;
640 void *mem;
641 unsigned int idx, msg_size;
642 int rc;
643
644 crq = carm_get_special(host);
645 if (!crq)
646 return -ENOMEM;
647
648 idx = crq->tag;
649
650 mem = carm_ref_msg(host, idx);
651
652 msg_size = func(host, idx, mem);
653
654 ioc = mem;
655 crq->msg_type = ioc->type;
656 crq->msg_subtype = ioc->subtype;
657 rc = carm_lookup_bucket(msg_size);
658 BUG_ON(rc < 0);
659 crq->msg_bucket = (u32) rc;
660
661 DPRINTK("blk_insert_request, tag == %u\n", idx);
867d1191 662 blk_insert_request(host->oob_q, crq->rq, 1, crq);
1da177e4
LT		 663
664 return 0;
665}
666
667static unsigned int carm_fill_sync_time(struct carm_host *host,
668 unsigned int idx, void *mem)
669{
670 struct timeval tv;
671 struct carm_msg_sync_time *st = mem;
672
673 do_gettimeofday(&tv);
674
675 memset(st, 0, sizeof(*st));
676 st->type = CARM_MSG_MISC;
677 st->subtype = MISC_SET_TIME;
678 st->handle = cpu_to_le32(TAG_ENCODE(idx));
679 st->timestamp = cpu_to_le32(tv.tv_sec);
680
681 return sizeof(struct carm_msg_sync_time);
682}
683
684static unsigned int carm_fill_alloc_buf(struct carm_host *host,
685 unsigned int idx, void *mem)
686{
687 struct carm_msg_allocbuf *ab = mem;
688
689 memset(ab, 0, sizeof(*ab));
690 ab->type = CARM_MSG_MISC;
691 ab->subtype = MISC_ALLOC_MEM;
692 ab->handle = cpu_to_le32(TAG_ENCODE(idx));
693 ab->n_sg = 1;
694 ab->sg_type = SGT_32BIT;
695 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
696 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
697 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
698 ab->n_evt = cpu_to_le32(1024);
699 ab->rbuf_pool = cpu_to_le32(host->shm_dma);
700 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
701 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
702 ab->n_msg = cpu_to_le32(CARM_Q_LEN);
703 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
704 ab->sg[0].len = cpu_to_le32(65536);
705
706 return sizeof(struct carm_msg_allocbuf);
707}
708
709static unsigned int carm_fill_scan_channels(struct carm_host *host,
710 unsigned int idx, void *mem)
711{
712 struct carm_msg_ioctl *ioc = mem;
713 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
714 IOC_SCAN_CHAN_OFFSET);
715
716 memset(ioc, 0, sizeof(*ioc));
717 ioc->type = CARM_MSG_IOCTL;
718 ioc->subtype = CARM_IOC_SCAN_CHAN;
719 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
720 ioc->data_addr = cpu_to_le32(msg_data);
721
722 /* fill output data area with "no device" default values */
723 mem += IOC_SCAN_CHAN_OFFSET;
724 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
725
726 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
727}
728
729static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
730 unsigned int idx, void *mem)
731{
732 struct carm_msg_get_fw_ver *ioc = mem;
733 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
734
735 memset(ioc, 0, sizeof(*ioc));
736 ioc->type = CARM_MSG_MISC;
737 ioc->subtype = MISC_GET_FW_VER;
738 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
739 ioc->data_addr = cpu_to_le32(msg_data);
740
741 return sizeof(struct carm_msg_get_fw_ver) +
742 sizeof(struct carm_fw_ver);
743}
744
745static inline void carm_end_request_queued(struct carm_host *host,
746 struct carm_request *crq,
a9c73d05 747 int error)
1da177e4
LT		 748{
749 struct request *req = crq->rq;
750 int rc;
751
40cbbb78 752 __blk_end_request_all(req, error);
1da177e4 753
1da177e4
LT		 754 rc = carm_put_request(host, crq);
755 assert(rc == 0);
756}
757
165125e1 758static inline void carm_push_q (struct carm_host *host, struct request_queue *q)
1da177e4
LT		 759{
760 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
761
762 blk_stop_queue(q);
763 VPRINTK("STOPPED QUEUE %p\n", q);
764
765 host->wait_q[idx] = q;
766 host->wait_q_prod++;
767 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
768}
769
165125e1 770static inline struct request_queue *carm_pop_q(struct carm_host *host)
1da177e4
LT		 771{
772 unsigned int idx;
773
774 if (host->wait_q_prod == host->wait_q_cons)
775 return NULL;
776
777 idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
778 host->wait_q_cons++;
779
780 return host->wait_q[idx];
781}
782
783static inline void carm_round_robin(struct carm_host *host)
784{
165125e1 785 struct request_queue *q = carm_pop_q(host);
1da177e4
LT		 786 if (q) {
787 blk_start_queue(q);
788 VPRINTK("STARTED QUEUE %p\n", q);
789 }
790}
791
792static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
a9c73d05 793 int error)
1da177e4 794{
a9c73d05 795 carm_end_request_queued(host, crq, error);
2d5a2ae5 796 if (max_queue == 1)
1da177e4
LT		 797 carm_round_robin(host);
798 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
799 (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
800 carm_round_robin(host);
801 }
802}
803
165125e1 804static void carm_oob_rq_fn(struct request_queue *q)
1da177e4
LT		 805{
806 struct carm_host *host = q->queuedata;
807 struct carm_request *crq;
808 struct request *rq;
809 int rc;
810
811 while (1) {
812 DPRINTK("get req\n");
9934c8c0 813 rq = blk_fetch_request(q);
1da177e4
LT		 814 if (!rq)
815 break;
816
1da177e4
LT		 817 crq = rq->special;
818 assert(crq != NULL);
819 assert(crq->rq == rq);
820
821 crq->n_elem = 0;
822
823 DPRINTK("send req\n");
824 rc = carm_send_msg(host, crq);
825 if (rc) {
826 blk_requeue_request(q, rq);
827 carm_push_q(host, q);
828 return; /* call us again later, eventually */
829 }
830 }
831}
832
165125e1 833static void carm_rq_fn(struct request_queue *q)
1da177e4
LT		 834{
835 struct carm_port *port = q->queuedata;
836 struct carm_host *host = port->host;
837 struct carm_msg_rw *msg;
838 struct carm_request *crq;
839 struct request *rq;
840 struct scatterlist *sg;
841 int writing = 0, pci_dir, i, n_elem, rc;
842 u32 tmp;
843 unsigned int msg_size;
844
845queue_one_request:
846 VPRINTK("get req\n");
9934c8c0 847 rq = blk_peek_request(q);
1da177e4
LT		 848 if (!rq)
849 return;
850
851 crq = carm_get_request(host);
852 if (!crq) {
853 carm_push_q(host, q);
854 return; /* call us again later, eventually */
855 }
856 crq->rq = rq;
857
9934c8c0 858 blk_start_request(rq);
1da177e4
LT		 859
860 if (rq_data_dir(rq) == WRITE) {
861 writing = 1;
862 pci_dir = PCI_DMA_TODEVICE;
863 } else {
864 pci_dir = PCI_DMA_FROMDEVICE;
865 }
866
867 /* get scatterlist from block layer */
868 sg = &crq->sg[0];
869 n_elem = blk_rq_map_sg(q, rq, sg);
870 if (n_elem <= 0) {
a9c73d05 871 carm_end_rq(host, crq, -EIO);
1da177e4
LT		 872 return; /* request with no s/g entries? */
873 }
874
875 /* map scatterlist to PCI bus addresses */
876 n_elem = pci_map_sg(host->pdev, sg, n_elem, pci_dir);
877 if (n_elem <= 0) {
a9c73d05 878 carm_end_rq(host, crq, -EIO);
1da177e4
LT		 879 return; /* request with no s/g entries? */
880 }
881 crq->n_elem = n_elem;
882 crq->port = port;
883 host->hw_sg_used += n_elem;
884
885 /*
886 * build read/write message
887 */
888
889 VPRINTK("build msg\n");
890 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
891
892 if (writing) {
893 msg->type = CARM_MSG_WRITE;
894 crq->msg_type = CARM_MSG_WRITE;
895 } else {
896 msg->type = CARM_MSG_READ;
897 crq->msg_type = CARM_MSG_READ;
898 }
899
900 msg->id = port->port_no;
901 msg->sg_count = n_elem;
902 msg->sg_type = SGT_32BIT;
903 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
83096ebf
TH		 904 msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff);
905 tmp = (blk_rq_pos(rq) >> 16) >> 16;
1da177e4 906 msg->lba_high = cpu_to_le16( (u16) tmp );
83096ebf 907 msg->lba_count = cpu_to_le16(blk_rq_sectors(rq));
1da177e4
LT		 908
909 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
910 for (i = 0; i < n_elem; i++) {
911 struct carm_msg_sg *carm_sg = &msg->sg[i];
912 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
913 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
914 msg_size += sizeof(struct carm_msg_sg);
915 }
916
917 rc = carm_lookup_bucket(msg_size);
918 BUG_ON(rc < 0);
919 crq->msg_bucket = (u32) rc;
920
921 /*
922 * queue read/write message to hardware
923 */
924
925 VPRINTK("send msg, tag == %u\n", crq->tag);
926 rc = carm_send_msg(host, crq);
927 if (rc) {
928 carm_put_request(host, crq);
929 blk_requeue_request(q, rq);
930 carm_push_q(host, q);
931 return; /* call us again later, eventually */
932 }
933
934 goto queue_one_request;
935}
936
937static void carm_handle_array_info(struct carm_host *host,
938 struct carm_request *crq, u8 *mem,
a9c73d05 939 int error)
1da177e4
LT		 940{
941 struct carm_port *port;
942 u8 *msg_data = mem + sizeof(struct carm_array_info);
943 struct carm_array_info *desc = (struct carm_array_info *) msg_data;
944 u64 lo, hi;
945 int cur_port;
946 size_t slen;
947
948 DPRINTK("ENTER\n");
949
a9c73d05 950 carm_end_rq(host, crq, error);
1da177e4 951
a9c73d05 952 if (error)
1da177e4
LT		 953 goto out;
954 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
955 goto out;
956
957 cur_port = host->cur_scan_dev;
958
959 /* should never occur */
960 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
961 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
962 cur_port, (int) desc->array_id);
963 goto out;
964 }
965
966 port = &host->port[cur_port];
967
968 lo = (u64) le32_to_cpu(desc->size);
969 hi = (u64) le16_to_cpu(desc->size_hi);
970
971 port->capacity = lo | (hi << 32);
972 port->dev_geom_head = le16_to_cpu(desc->head);
973 port->dev_geom_sect = le16_to_cpu(desc->sect);
974 port->dev_geom_cyl = le16_to_cpu(desc->cyl);
975
976 host->dev_active |= (1 << cur_port);
977
978 strncpy(port->name, desc->name, sizeof(port->name));
979 port->name[sizeof(port->name) - 1] = 0;
980 slen = strlen(port->name);
981 while (slen && (port->name[slen - 1] == ' ')) {
982 port->name[slen - 1] = 0;
983 slen--;
984 }
985
986 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
987 pci_name(host->pdev), port->port_no,
988 (unsigned long long) port->capacity);
989 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
990 pci_name(host->pdev), port->port_no, port->name);
991
992out:
993 assert(host->state == HST_DEV_SCAN);
994 schedule_work(&host->fsm_task);
995}
996
997static void carm_handle_scan_chan(struct carm_host *host,
998 struct carm_request *crq, u8 *mem,
a9c73d05 999 int error)
1da177e4
LT		 1000{
1001 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
1002 unsigned int i, dev_count = 0;
1003 int new_state = HST_DEV_SCAN_START;
1004
1005 DPRINTK("ENTER\n");
1006
a9c73d05 1007 carm_end_rq(host, crq, error);
1da177e4 1008
a9c73d05 1009 if (error) {
1da177e4
LT		 1010 new_state = HST_ERROR;
1011 goto out;
1012 }
1013
1014 /* TODO: scan and support non-disk devices */
1015 for (i = 0; i < 8; i++)
1016 if (msg_data[i] == 0) { /* direct-access device (disk) */
1017 host->dev_present |= (1 << i);
1018 dev_count++;
1019 }
1020
1021 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
1022 pci_name(host->pdev), dev_count);
1023
1024out:
1025 assert(host->state == HST_PORT_SCAN);
1026 host->state = new_state;
1027 schedule_work(&host->fsm_task);
1028}
1029
1030static void carm_handle_generic(struct carm_host *host,
a9c73d05 1031 struct carm_request *crq, int error,
1da177e4
LT		 1032 int cur_state, int next_state)
1033{
1034 DPRINTK("ENTER\n");
1035
a9c73d05 1036 carm_end_rq(host, crq, error);
1da177e4
LT		 1037
1038 assert(host->state == cur_state);
a9c73d05 1039 if (error)
1da177e4 1040 host->state = HST_ERROR;
a9c73d05
KU		 1041 else
1042 host->state = next_state;
1da177e4
LT		 1043 schedule_work(&host->fsm_task);
1044}
1045
1046static inline void carm_handle_rw(struct carm_host *host,
a9c73d05 1047 struct carm_request *crq, int error)
1da177e4
LT		 1048{
1049 int pci_dir;
1050
1051 VPRINTK("ENTER\n");
1052
1053 if (rq_data_dir(crq->rq) == WRITE)
1054 pci_dir = PCI_DMA_TODEVICE;
1055 else
1056 pci_dir = PCI_DMA_FROMDEVICE;
1057
1058 pci_unmap_sg(host->pdev, &crq->sg[0], crq->n_elem, pci_dir);
1059
a9c73d05 1060 carm_end_rq(host, crq, error);
1da177e4
LT		 1061}
1062
1063static inline void carm_handle_resp(struct carm_host *host,
1064 __le32 ret_handle_le, u32 status)
1065{
1066 u32 handle = le32_to_cpu(ret_handle_le);
1067 unsigned int msg_idx;
1068 struct carm_request *crq;
a9c73d05 1069 int error = (status == RMSG_OK) ? 0 : -EIO;
1da177e4
LT		 1070 u8 *mem;
1071
1072 VPRINTK("ENTER, handle == 0x%x\n", handle);
1073
1074 if (unlikely(!TAG_VALID(handle))) {
1075 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
1076 pci_name(host->pdev), handle);
1077 return;
1078 }
1079
1080 msg_idx = TAG_DECODE(handle);
1081 VPRINTK("tag == %u\n", msg_idx);
1082
1083 crq = &host->req[msg_idx];
1084
1085 /* fast path */
1086 if (likely(crq->msg_type == CARM_MSG_READ ||
1087 crq->msg_type == CARM_MSG_WRITE)) {
a9c73d05 1088 carm_handle_rw(host, crq, error);
1da177e4
LT		 1089 return;
1090 }
1091
1092 mem = carm_ref_msg(host, msg_idx);
1093
1094 switch (crq->msg_type) {
1095 case CARM_MSG_IOCTL: {
1096 switch (crq->msg_subtype) {
1097 case CARM_IOC_SCAN_CHAN:
a9c73d05 1098 carm_handle_scan_chan(host, crq, mem, error);
1da177e4
LT		 1099 break;
1100 default:
1101 /* unknown / invalid response */
1102 goto err_out;
1103 }
1104 break;
1105 }
1106
1107 case CARM_MSG_MISC: {
1108 switch (crq->msg_subtype) {
1109 case MISC_ALLOC_MEM:
a9c73d05 1110 carm_handle_generic(host, crq, error,
1da177e4
LT		 1111 HST_ALLOC_BUF, HST_SYNC_TIME);
1112 break;
1113 case MISC_SET_TIME:
a9c73d05 1114 carm_handle_generic(host, crq, error,
1da177e4
LT		 1115 HST_SYNC_TIME, HST_GET_FW_VER);
1116 break;
1117 case MISC_GET_FW_VER: {
1118 struct carm_fw_ver *ver = (struct carm_fw_ver *)
1119 mem + sizeof(struct carm_msg_get_fw_ver);
a9c73d05 1120 if (!error) {
1da177e4
LT		 1121 host->fw_ver = le32_to_cpu(ver->version);
1122 host->flags |= (ver->features & FL_FW_VER_MASK);
1123 }
a9c73d05 1124 carm_handle_generic(host, crq, error,
1da177e4
LT		 1125 HST_GET_FW_VER, HST_PORT_SCAN);
1126 break;
1127 }
1128 default:
1129 /* unknown / invalid response */
1130 goto err_out;
1131 }
1132 break;
1133 }
1134
1135 case CARM_MSG_ARRAY: {
1136 switch (crq->msg_subtype) {
1137 case CARM_ARRAY_INFO:
a9c73d05 1138 carm_handle_array_info(host, crq, mem, error);
1da177e4
LT		 1139 break;
1140 default:
1141 /* unknown / invalid response */
1142 goto err_out;
1143 }
1144 break;
1145 }
1146
1147 default:
1148 /* unknown / invalid response */
1149 goto err_out;
1150 }
1151
1152 return;
1153
1154err_out:
1155 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1156 pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
a9c73d05 1157 carm_end_rq(host, crq, -EIO);
1da177e4
LT		 1158}
1159
1160static inline void carm_handle_responses(struct carm_host *host)
1161{
1162 void __iomem *mmio = host->mmio;
1163 struct carm_response *resp = (struct carm_response *) host->shm;
1164 unsigned int work = 0;
1165 unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1166
1167 while (1) {
1168 u32 status = le32_to_cpu(resp[idx].status);
1169
1170 if (status == 0xffffffff) {
1171 VPRINTK("ending response on index %u\n", idx);
1172 writel(idx << 3, mmio + CARM_RESP_IDX);
1173 break;
1174 }
1175
1176 /* response to a message we sent */
1177 else if ((status & (1 << 31)) == 0) {
1178 VPRINTK("handling msg response on index %u\n", idx);
1179 carm_handle_resp(host, resp[idx].ret_handle, status);
1180 resp[idx].status = cpu_to_le32(0xffffffff);
1181 }
1182
1183 /* asynchronous events the hardware throws our way */
1184 else if ((status & 0xff000000) == (1 << 31)) {
1185 u8 *evt_type_ptr = (u8 *) &resp[idx];
1186 u8 evt_type = *evt_type_ptr;
1187 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1188 pci_name(host->pdev), (int) evt_type);
1189 resp[idx].status = cpu_to_le32(0xffffffff);
1190 }
1191
1192 idx = NEXT_RESP(idx);
1193 work++;
1194 }
1195
1196 VPRINTK("EXIT, work==%u\n", work);
1197 host->resp_idx += work;
1198}
1199
7d12e780 1200static irqreturn_t carm_interrupt(int irq, void *__host)
1da177e4
LT		 1201{
1202 struct carm_host *host = __host;
1203 void __iomem *mmio;
1204 u32 mask;
1205 int handled = 0;
1206 unsigned long flags;
1207
1208 if (!host) {
1209 VPRINTK("no host\n");
1210 return IRQ_NONE;
1211 }
1212
1213 spin_lock_irqsave(&host->lock, flags);
1214
1215 mmio = host->mmio;
1216
1217 /* reading should also clear interrupts */
1218 mask = readl(mmio + CARM_INT_STAT);
1219
1220 if (mask == 0 || mask == 0xffffffff) {
1221 VPRINTK("no work, mask == 0x%x\n", mask);
1222 goto out;
1223 }
1224
1225 if (mask & INT_ACK_MASK)
1226 writel(mask, mmio + CARM_INT_STAT);
1227
1228 if (unlikely(host->state == HST_INVALID)) {
1229 VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1230 goto out;
1231 }
1232
1233 if (mask & CARM_HAVE_RESP) {
1234 handled = 1;
1235 carm_handle_responses(host);
1236 }
1237
1238out:
1239 spin_unlock_irqrestore(&host->lock, flags);
1240 VPRINTK("EXIT\n");
1241 return IRQ_RETVAL(handled);
1242}
1243
c4028958 1244static void carm_fsm_task (struct work_struct *work)
1da177e4 1245{
c4028958
DH		 1246 struct carm_host *host =
1247 container_of(work, struct carm_host, fsm_task);
1da177e4
LT		 1248 unsigned long flags;
1249 unsigned int state;
1250 int rc, i, next_dev;
1251 int reschedule = 0;
1252 int new_state = HST_INVALID;
1253
1254 spin_lock_irqsave(&host->lock, flags);
1255 state = host->state;
1256 spin_unlock_irqrestore(&host->lock, flags);
1257
1258 DPRINTK("ENTER, state == %s\n", state_name[state]);
1259
1260 switch (state) {
1261 case HST_PROBE_START:
1262 new_state = HST_ALLOC_BUF;
1263 reschedule = 1;
1264 break;
1265
1266 case HST_ALLOC_BUF:
1267 rc = carm_send_special(host, carm_fill_alloc_buf);
1268 if (rc) {
1269 new_state = HST_ERROR;
1270 reschedule = 1;
1271 }
1272 break;
1273
1274 case HST_SYNC_TIME:
1275 rc = carm_send_special(host, carm_fill_sync_time);
1276 if (rc) {
1277 new_state = HST_ERROR;
1278 reschedule = 1;
1279 }
1280 break;
1281
1282 case HST_GET_FW_VER:
1283 rc = carm_send_special(host, carm_fill_get_fw_ver);
1284 if (rc) {
1285 new_state = HST_ERROR;
1286 reschedule = 1;
1287 }
1288 break;
1289
1290 case HST_PORT_SCAN:
1291 rc = carm_send_special(host, carm_fill_scan_channels);
1292 if (rc) {
1293 new_state = HST_ERROR;
1294 reschedule = 1;
1295 }
1296 break;
1297
1298 case HST_DEV_SCAN_START:
1299 host->cur_scan_dev = -1;
1300 new_state = HST_DEV_SCAN;
1301 reschedule = 1;
1302 break;
1303
1304 case HST_DEV_SCAN:
1305 next_dev = -1;
1306 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1307 if (host->dev_present & (1 << i)) {
1308 next_dev = i;
1309 break;
1310 }
1311
1312 if (next_dev >= 0) {
1313 host->cur_scan_dev = next_dev;
1314 rc = carm_array_info(host, next_dev);
1315 if (rc) {
1316 new_state = HST_ERROR;
1317 reschedule = 1;
1318 }
1319 } else {
1320 new_state = HST_DEV_ACTIVATE;
1321 reschedule = 1;
1322 }
1323 break;
1324
1325 case HST_DEV_ACTIVATE: {
1326 int activated = 0;
1327 for (i = 0; i < CARM_MAX_PORTS; i++)
1328 if (host->dev_active & (1 << i)) {
1329 struct carm_port *port = &host->port[i];
1330 struct gendisk *disk = port->disk;
1331
1332 set_capacity(disk, port->capacity);
1333 add_disk(disk);
1334 activated++;
1335 }
1336
1337 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1338 pci_name(host->pdev), activated);
1339
1340 new_state = HST_PROBE_FINISHED;
1341 reschedule = 1;
1342 break;
1343 }
1344
1345 case HST_PROBE_FINISHED:
906c3b75 1346 complete(&host->probe_comp);
1da177e4
LT		 1347 break;
1348
1349 case HST_ERROR:
1350 /* FIXME: TODO */
1351 break;
1352
1353 default:
1354 /* should never occur */
1355 printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1356 assert(0);
1357 break;
1358 }
1359
1360 if (new_state != HST_INVALID) {
1361 spin_lock_irqsave(&host->lock, flags);
1362 host->state = new_state;
1363 spin_unlock_irqrestore(&host->lock, flags);
1364 }
1365 if (reschedule)
1366 schedule_work(&host->fsm_task);
1367}
1368
1369static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1370{
1371 unsigned int i;
1372
1373 for (i = 0; i < 50000; i++) {
1374 u32 tmp = readl(mmio + CARM_LMUC);
1375 udelay(100);
1376
1377 if (test_bit) {
1378 if ((tmp & bits) == bits)
1379 return 0;
1380 } else {
1381 if ((tmp & bits) == 0)
1382 return 0;
1383 }
1384
1385 cond_resched();
1386 }
1387
1388 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1389 bits, test_bit ? "yes" : "no");
1390 return -EBUSY;
1391}
1392
1393static void carm_init_responses(struct carm_host *host)
1394{
1395 void __iomem *mmio = host->mmio;
1396 unsigned int i;
1397 struct carm_response *resp = (struct carm_response *) host->shm;
1398
1399 for (i = 0; i < RMSG_Q_LEN; i++)
1400 resp[i].status = cpu_to_le32(0xffffffff);
1401
1402 writel(0, mmio + CARM_RESP_IDX);
1403}
1404
1405static int carm_init_host(struct carm_host *host)
1406{
1407 void __iomem *mmio = host->mmio;
1408 u32 tmp;
1409 u8 tmp8;
1410 int rc;
1411
1412 DPRINTK("ENTER\n");
1413
1414 writel(0, mmio + CARM_INT_MASK);
1415
1416 tmp8 = readb(mmio + CARM_INITC);
1417 if (tmp8 & 0x01) {
1418 tmp8 &= ~0x01;
1419 writeb(tmp8, mmio + CARM_INITC);
1420 readb(mmio + CARM_INITC); /* flush */
1421
1422 DPRINTK("snooze...\n");
1423 msleep(5000);
1424 }
1425
1426 tmp = readl(mmio + CARM_HMUC);
1427 if (tmp & CARM_CME) {
1428 DPRINTK("CME bit present, waiting\n");
1429 rc = carm_init_wait(mmio, CARM_CME, 1);
1430 if (rc) {
1431 DPRINTK("EXIT, carm_init_wait 1 failed\n");
1432 return rc;
1433 }
1434 }
1435 if (tmp & CARM_RME) {
1436 DPRINTK("RME bit present, waiting\n");
1437 rc = carm_init_wait(mmio, CARM_RME, 1);
1438 if (rc) {
1439 DPRINTK("EXIT, carm_init_wait 2 failed\n");
1440 return rc;
1441 }
1442 }
1443
1444 tmp &= ~(CARM_RME | CARM_CME);
1445 writel(tmp, mmio + CARM_HMUC);
1446 readl(mmio + CARM_HMUC); /* flush */
1447
1448 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1449 if (rc) {
1450 DPRINTK("EXIT, carm_init_wait 3 failed\n");
1451 return rc;
1452 }
1453
1454 carm_init_buckets(mmio);
1455
1456 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1457 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1458 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1459
1460 tmp = readl(mmio + CARM_HMUC);
1461 tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1462 writel(tmp, mmio + CARM_HMUC);
1463 readl(mmio + CARM_HMUC); /* flush */
1464
1465 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1466 if (rc) {
1467 DPRINTK("EXIT, carm_init_wait 4 failed\n");
1468 return rc;
1469 }
1470
1471 writel(0, mmio + CARM_HMPHA);
1472 writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1473
1474 carm_init_responses(host);
1475
1476 /* start initialization, probing state machine */
1477 spin_lock_irq(&host->lock);
1478 assert(host->state == HST_INVALID);
1479 host->state = HST_PROBE_START;
1480 spin_unlock_irq(&host->lock);
1481 schedule_work(&host->fsm_task);
1482
1483 DPRINTK("EXIT\n");
1484 return 0;
1485}
1486
1487static int carm_init_disks(struct carm_host *host)
1488{
1489 unsigned int i;
1490 int rc = 0;
1491
1492 for (i = 0; i < CARM_MAX_PORTS; i++) {
1493 struct gendisk *disk;
165125e1 1494 struct request_queue *q;
1da177e4
LT		 1495 struct carm_port *port;
1496
1497 port = &host->port[i];
1498 port->host = host;
1499 port->port_no = i;
1500
1501 disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1502 if (!disk) {
1503 rc = -ENOMEM;
1504 break;
1505 }
1506
1507 port->disk = disk;
1508 sprintf(disk->disk_name, DRV_NAME "/%u",
1509 (unsigned int) (host->id * CARM_MAX_PORTS) + i);
1da177e4
LT		 1510 disk->major = host->major;
1511 disk->first_minor = i * CARM_MINORS_PER_MAJOR;
1512 disk->fops = &carm_bd_ops;
1513 disk->private_data = port;
1514
1515 q = blk_init_queue(carm_rq_fn, &host->lock);
1516 if (!q) {
1517 rc = -ENOMEM;
1518 break;
1519 }
1520 disk->queue = q;
8a78362c 1521 blk_queue_max_segments(q, CARM_MAX_REQ_SG);
1da177e4
LT		 1522 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1523
1524 q->queuedata = port;
1525 }
1526
1527 return rc;
1528}
1529
1530static void carm_free_disks(struct carm_host *host)
1531{
1532 unsigned int i;
1533
1534 for (i = 0; i < CARM_MAX_PORTS; i++) {
1535 struct gendisk *disk = host->port[i].disk;
1536 if (disk) {
165125e1 1537 struct request_queue *q = disk->queue;
1da177e4
LT		 1538
1539 if (disk->flags & GENHD_FL_UP)
1540 del_gendisk(disk);
1541 if (q)
1542 blk_cleanup_queue(q);
1543 put_disk(disk);
1544 }
1545 }
1546}
1547
1548static int carm_init_shm(struct carm_host *host)
1549{
1550 host->shm = pci_alloc_consistent(host->pdev, CARM_SHM_SIZE,
1551 &host->shm_dma);
1552 if (!host->shm)
1553 return -ENOMEM;
1554
1555 host->msg_base = host->shm + RBUF_LEN;
1556 host->msg_dma = host->shm_dma + RBUF_LEN;
1557
1558 memset(host->shm, 0xff, RBUF_LEN);
1559 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1560
1561 return 0;
1562}
1563
1564static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1565{
1da177e4
LT		 1566 struct carm_host *host;
1567 unsigned int pci_dac;
1568 int rc;
165125e1 1569 struct request_queue *q;
1da177e4
LT		 1570 unsigned int i;
1571
49b3a3cb 1572 printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1da177e4
LT		 1573
1574 rc = pci_enable_device(pdev);
1575 if (rc)
1576 return rc;
1577
1578 rc = pci_request_regions(pdev, DRV_NAME);
1579 if (rc)
1580 goto err_out;
1581
44456d37 1582#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
6a35528a 1583 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4 1584 if (!rc) {
6a35528a 1585 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1da177e4
LT		 1586 if (rc) {
1587 printk(KERN_ERR DRV_NAME "(%s): consistent DMA mask failure\n",
1588 pci_name(pdev));
1589 goto err_out_regions;
1590 }
1591 pci_dac = 1;
1592 } else {
1593#endif
284901a9 1594 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1595 if (rc) {
1596 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1597 pci_name(pdev));
1598 goto err_out_regions;
1599 }
1600 pci_dac = 0;
44456d37 1601#ifdef IF_64BIT_DMA_IS_POSSIBLE /* grrrr... */
1da177e4
LT		 1602 }
1603#endif
1604
dd00cc48 1605 host = kzalloc(sizeof(*host), GFP_KERNEL);
1da177e4
LT		 1606 if (!host) {
1607 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1608 pci_name(pdev));
1609 rc = -ENOMEM;
1610 goto err_out_regions;
1611 }
1612
1da177e4
LT		 1613 host->pdev = pdev;
1614 host->flags = pci_dac ? FL_DAC : 0;
1615 spin_lock_init(&host->lock);
c4028958 1616 INIT_WORK(&host->fsm_task, carm_fsm_task);
906c3b75 1617 init_completion(&host->probe_comp);
1da177e4
LT		 1618
1619 for (i = 0; i < ARRAY_SIZE(host->req); i++)
1620 host->req[i].tag = i;
1621
1622 host->mmio = ioremap(pci_resource_start(pdev, 0),
1623 pci_resource_len(pdev, 0));
1624 if (!host->mmio) {
1625 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1626 pci_name(pdev));
1627 rc = -ENOMEM;
1628 goto err_out_kfree;
1629 }
1630
1631 rc = carm_init_shm(host);
1632 if (rc) {
1633 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1634 pci_name(pdev));
1635 goto err_out_iounmap;
1636 }
1637
1638 q = blk_init_queue(carm_oob_rq_fn, &host->lock);
1639 if (!q) {
1640 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
1641 pci_name(pdev));
1642 rc = -ENOMEM;
1643 goto err_out_pci_free;
1644 }
1645 host->oob_q = q;
1646 q->queuedata = host;
1647
1648 /*
1649 * Figure out which major to use: 160, 161, or dynamic
1650 */
1651 if (!test_and_set_bit(0, &carm_major_alloc))
1652 host->major = 160;
1653 else if (!test_and_set_bit(1, &carm_major_alloc))
1654 host->major = 161;
1655 else
1656 host->flags |= FL_DYN_MAJOR;
1657
1658 host->id = carm_host_id;
1659 sprintf(host->name, DRV_NAME "%d", carm_host_id);
1660
1661 rc = register_blkdev(host->major, host->name);
1662 if (rc < 0)
1663 goto err_out_free_majors;
1664 if (host->flags & FL_DYN_MAJOR)
1665 host->major = rc;
1666
1da177e4
LT		 1667 rc = carm_init_disks(host);
1668 if (rc)
1669 goto err_out_blkdev_disks;
1670
1671 pci_set_master(pdev);
1672
69ab3912 1673 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host);
1da177e4
LT		 1674 if (rc) {
1675 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1676 pci_name(pdev));
1677 goto err_out_blkdev_disks;
1678 }
1679
1680 rc = carm_init_host(host);
1681 if (rc)
1682 goto err_out_free_irq;
1683
906c3b75
SR		 1684 DPRINTK("waiting for probe_comp\n");
1685 wait_for_completion(&host->probe_comp);
1da177e4 1686
e29419ff 1687 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n",
1da177e4 1688 host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
e29419ff
GKH		 1689 (unsigned long long)pci_resource_start(pdev, 0),
1690 pdev->irq, host->major);
1da177e4
LT		 1691
1692 carm_host_id++;
1693 pci_set_drvdata(pdev, host);
1694 return 0;
1695
1696err_out_free_irq:
1697 free_irq(pdev->irq, host);
1698err_out_blkdev_disks:
1699 carm_free_disks(host);
1700 unregister_blkdev(host->major, host->name);
1701err_out_free_majors:
1702 if (host->major == 160)
1703 clear_bit(0, &carm_major_alloc);
1704 else if (host->major == 161)
1705 clear_bit(1, &carm_major_alloc);
1706 blk_cleanup_queue(host->oob_q);
1707err_out_pci_free:
1708 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1709err_out_iounmap:
1710 iounmap(host->mmio);
1711err_out_kfree:
1712 kfree(host);
1713err_out_regions:
1714 pci_release_regions(pdev);
1715err_out:
1716 pci_disable_device(pdev);
1717 return rc;
1718}
1719
1720static void carm_remove_one (struct pci_dev *pdev)
1721{
1722 struct carm_host *host = pci_get_drvdata(pdev);
1723
1724 if (!host) {
1725 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1726 pci_name(pdev));
1727 return;
1728 }
1729
1730 free_irq(pdev->irq, host);
1731 carm_free_disks(host);
1da177e4
LT		 1732 unregister_blkdev(host->major, host->name);
1733 if (host->major == 160)
1734 clear_bit(0, &carm_major_alloc);
1735 else if (host->major == 161)
1736 clear_bit(1, &carm_major_alloc);
1737 blk_cleanup_queue(host->oob_q);
1738 pci_free_consistent(pdev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1739 iounmap(host->mmio);
1740 kfree(host);
1741 pci_release_regions(pdev);
1742 pci_disable_device(pdev);
1743 pci_set_drvdata(pdev, NULL);
1744}
1745
1746static int __init carm_init(void)
1747{
9bfab8ce 1748 return pci_register_driver(&carm_driver);
1da177e4
LT		 1749}
1750
1751static void __exit carm_exit(void)
1752{
1753 pci_unregister_driver(&carm_driver);
1754}
1755
1756module_init(carm_init);
1757module_exit(carm_exit);
1758
1759
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