]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/char/hpet.c
sched/headers: Prepare to move signal wakeup & sigpending methods from <linux/sched...
[mirror_ubuntu-artful-kernel.git] / drivers / char / hpet.c
CommitLineData
1da177e4
LT
1/*
2 * Intel & MS High Precision Event Timer Implementation.
3 *
4 * Copyright (C) 2003 Intel Corporation
5 * Venki Pallipadi
6 * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
7 * Bob Picco <robert.picco@hp.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
1da177e4 14#include <linux/interrupt.h>
1da177e4
LT
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/miscdevice.h>
18#include <linux/major.h>
19#include <linux/ioport.h>
20#include <linux/fcntl.h>
21#include <linux/init.h>
22#include <linux/poll.h>
f23f6e08 23#include <linux/mm.h>
1da177e4
LT
24#include <linux/proc_fs.h>
25#include <linux/spinlock.h>
26#include <linux/sysctl.h>
27#include <linux/wait.h>
174cd4b1 28#include <linux/sched/signal.h>
1da177e4
LT
29#include <linux/bcd.h>
30#include <linux/seq_file.h>
31#include <linux/bitops.h>
54066a57 32#include <linux/compat.h>
0aa366f3 33#include <linux/clocksource.h>
0ca01763 34#include <linux/uaccess.h>
5a0e3ad6 35#include <linux/slab.h>
0ca01763 36#include <linux/io.h>
8b48463f
LZ
37#include <linux/acpi.h>
38#include <linux/hpet.h>
1da177e4 39#include <asm/current.h>
1da177e4
LT
40#include <asm/irq.h>
41#include <asm/div64.h>
42
1da177e4
LT
43/*
44 * The High Precision Event Timer driver.
45 * This driver is closely modelled after the rtc.c driver.
4e7f9df2 46 * See HPET spec revision 1.
1da177e4
LT
47 */
48#define HPET_USER_FREQ (64)
49#define HPET_DRIFT (500)
50
757c4724
RD
51#define HPET_RANGE_SIZE 1024 /* from HPET spec */
52
64a76f66
DB
53
54/* WARNING -- don't get confused. These macros are never used
55 * to write the (single) counter, and rarely to read it.
56 * They're badly named; to fix, someday.
57 */
0aa366f3
TL
58#if BITS_PER_LONG == 64
59#define write_counter(V, MC) writeq(V, MC)
60#define read_counter(MC) readq(MC)
61#else
62#define write_counter(V, MC) writel(V, MC)
63#define read_counter(MC) readl(MC)
64#endif
65
54066a57 66static DEFINE_MUTEX(hpet_mutex); /* replaces BKL */
642d30bb 67static u32 hpet_nhpet, hpet_max_freq = HPET_USER_FREQ;
1da177e4 68
3dffec45
ÇO
69/* This clocksource driver currently only works on ia64 */
70#ifdef CONFIG_IA64
0aa366f3
TL
71static void __iomem *hpet_mctr;
72
a5a1d1c2 73static u64 read_hpet(struct clocksource *cs)
0aa366f3 74{
a5a1d1c2 75 return (u64)read_counter((void __iomem *)hpet_mctr);
0aa366f3
TL
76}
77
78static struct clocksource clocksource_hpet = {
0ca01763
JSR
79 .name = "hpet",
80 .rating = 250,
81 .read = read_hpet,
82 .mask = CLOCKSOURCE_MASK(64),
0ca01763 83 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
0aa366f3
TL
84};
85static struct clocksource *hpet_clocksource;
3dffec45 86#endif
0aa366f3 87
1da177e4
LT
88/* A lock for concurrent access by app and isr hpet activity. */
89static DEFINE_SPINLOCK(hpet_lock);
1da177e4
LT
90
91#define HPET_DEV_NAME (7)
92
93struct hpet_dev {
94 struct hpets *hd_hpets;
95 struct hpet __iomem *hd_hpet;
96 struct hpet_timer __iomem *hd_timer;
97 unsigned long hd_ireqfreq;
98 unsigned long hd_irqdata;
99 wait_queue_head_t hd_waitqueue;
100 struct fasync_struct *hd_async_queue;
1da177e4
LT
101 unsigned int hd_flags;
102 unsigned int hd_irq;
103 unsigned int hd_hdwirq;
104 char hd_name[HPET_DEV_NAME];
105};
106
107struct hpets {
108 struct hpets *hp_next;
109 struct hpet __iomem *hp_hpet;
110 unsigned long hp_hpet_phys;
0aa366f3 111 struct clocksource *hp_clocksource;
ba3f213f 112 unsigned long long hp_tick_freq;
1da177e4
LT
113 unsigned long hp_delta;
114 unsigned int hp_ntimer;
115 unsigned int hp_which;
116 struct hpet_dev hp_dev[1];
117};
118
119static struct hpets *hpets;
120
121#define HPET_OPEN 0x0001
122#define HPET_IE 0x0002 /* interrupt enabled */
123#define HPET_PERIODIC 0x0004
0d290861 124#define HPET_SHARED_IRQ 0x0008
1da177e4 125
1da177e4
LT
126
127#ifndef readq
887c27f3 128static inline unsigned long long readq(void __iomem *addr)
1da177e4
LT
129{
130 return readl(addr) | (((unsigned long long)readl(addr + 4)) << 32LL);
131}
132#endif
133
134#ifndef writeq
887c27f3 135static inline void writeq(unsigned long long v, void __iomem *addr)
1da177e4
LT
136{
137 writel(v & 0xffffffff, addr);
138 writel(v >> 32, addr + 4);
139}
140#endif
141
7d12e780 142static irqreturn_t hpet_interrupt(int irq, void *data)
1da177e4
LT
143{
144 struct hpet_dev *devp;
145 unsigned long isr;
146
147 devp = data;
0d290861
CL
148 isr = 1 << (devp - devp->hd_hpets->hp_dev);
149
150 if ((devp->hd_flags & HPET_SHARED_IRQ) &&
151 !(isr & readl(&devp->hd_hpet->hpet_isr)))
152 return IRQ_NONE;
1da177e4
LT
153
154 spin_lock(&hpet_lock);
155 devp->hd_irqdata++;
156
157 /*
158 * For non-periodic timers, increment the accumulator.
159 * This has the effect of treating non-periodic like periodic.
160 */
161 if ((devp->hd_flags & (HPET_IE | HPET_PERIODIC)) == HPET_IE) {
273ef950
NC
162 unsigned long m, t, mc, base, k;
163 struct hpet __iomem *hpet = devp->hd_hpet;
164 struct hpets *hpetp = devp->hd_hpets;
1da177e4
LT
165
166 t = devp->hd_ireqfreq;
ae21cf92 167 m = read_counter(&devp->hd_timer->hpet_compare);
273ef950
NC
168 mc = read_counter(&hpet->hpet_mc);
169 /* The time for the next interrupt would logically be t + m,
170 * however, if we are very unlucky and the interrupt is delayed
171 * for longer than t then we will completely miss the next
172 * interrupt if we set t + m and an application will hang.
173 * Therefore we need to make a more complex computation assuming
174 * that there exists a k for which the following is true:
175 * k * t + base < mc + delta
176 * (k + 1) * t + base > mc + delta
177 * where t is the interval in hpet ticks for the given freq,
178 * base is the theoretical start value 0 < base < t,
179 * mc is the main counter value at the time of the interrupt,
180 * delta is the time it takes to write the a value to the
181 * comparator.
182 * k may then be computed as (mc - base + delta) / t .
183 */
184 base = mc % t;
185 k = (mc - base + hpetp->hp_delta) / t;
186 write_counter(t * (k + 1) + base,
187 &devp->hd_timer->hpet_compare);
1da177e4
LT
188 }
189
0d290861
CL
190 if (devp->hd_flags & HPET_SHARED_IRQ)
191 writel(isr, &devp->hd_hpet->hpet_isr);
1da177e4
LT
192 spin_unlock(&hpet_lock);
193
1da177e4
LT
194 wake_up_interruptible(&devp->hd_waitqueue);
195
196 kill_fasync(&devp->hd_async_queue, SIGIO, POLL_IN);
197
198 return IRQ_HANDLED;
199}
200
70ef6d59
KH
201static void hpet_timer_set_irq(struct hpet_dev *devp)
202{
203 unsigned long v;
204 int irq, gsi;
205 struct hpet_timer __iomem *timer;
206
207 spin_lock_irq(&hpet_lock);
208 if (devp->hd_hdwirq) {
209 spin_unlock_irq(&hpet_lock);
210 return;
211 }
212
213 timer = devp->hd_timer;
214
215 /* we prefer level triggered mode */
216 v = readl(&timer->hpet_config);
217 if (!(v & Tn_INT_TYPE_CNF_MASK)) {
218 v |= Tn_INT_TYPE_CNF_MASK;
219 writel(v, &timer->hpet_config);
220 }
221 spin_unlock_irq(&hpet_lock);
222
223 v = (readq(&timer->hpet_config) & Tn_INT_ROUTE_CAP_MASK) >>
224 Tn_INT_ROUTE_CAP_SHIFT;
225
226 /*
227 * In PIC mode, skip IRQ0-4, IRQ6-9, IRQ12-15 which is always used by
228 * legacy device. In IO APIC mode, we skip all the legacy IRQS.
229 */
230 if (acpi_irq_model == ACPI_IRQ_MODEL_PIC)
231 v &= ~0xf3df;
232 else
233 v &= ~0xffff;
234
e5d61511 235 for_each_set_bit(irq, &v, HPET_MAX_IRQ) {
1f45f562 236 if (irq >= nr_irqs) {
70ef6d59
KH
237 irq = HPET_MAX_IRQ;
238 break;
239 }
240
a2f809b0 241 gsi = acpi_register_gsi(NULL, irq, ACPI_LEVEL_SENSITIVE,
70ef6d59
KH
242 ACPI_ACTIVE_LOW);
243 if (gsi > 0)
244 break;
245
246 /* FIXME: Setup interrupt source table */
247 }
248
249 if (irq < HPET_MAX_IRQ) {
250 spin_lock_irq(&hpet_lock);
251 v = readl(&timer->hpet_config);
252 v |= irq << Tn_INT_ROUTE_CNF_SHIFT;
253 writel(v, &timer->hpet_config);
254 devp->hd_hdwirq = gsi;
255 spin_unlock_irq(&hpet_lock);
256 }
257 return;
258}
259
1da177e4
LT
260static int hpet_open(struct inode *inode, struct file *file)
261{
262 struct hpet_dev *devp;
263 struct hpets *hpetp;
264 int i;
265
266 if (file->f_mode & FMODE_WRITE)
267 return -EINVAL;
268
54066a57 269 mutex_lock(&hpet_mutex);
1da177e4
LT
270 spin_lock_irq(&hpet_lock);
271
272 for (devp = NULL, hpetp = hpets; hpetp && !devp; hpetp = hpetp->hp_next)
273 for (i = 0; i < hpetp->hp_ntimer; i++)
64a76f66 274 if (hpetp->hp_dev[i].hd_flags & HPET_OPEN)
1da177e4
LT
275 continue;
276 else {
277 devp = &hpetp->hp_dev[i];
278 break;
279 }
280
281 if (!devp) {
282 spin_unlock_irq(&hpet_lock);
54066a57 283 mutex_unlock(&hpet_mutex);
1da177e4
LT
284 return -EBUSY;
285 }
286
287 file->private_data = devp;
288 devp->hd_irqdata = 0;
289 devp->hd_flags |= HPET_OPEN;
290 spin_unlock_irq(&hpet_lock);
54066a57 291 mutex_unlock(&hpet_mutex);
1da177e4 292
70ef6d59
KH
293 hpet_timer_set_irq(devp);
294
1da177e4
LT
295 return 0;
296}
297
298static ssize_t
299hpet_read(struct file *file, char __user *buf, size_t count, loff_t * ppos)
300{
301 DECLARE_WAITQUEUE(wait, current);
302 unsigned long data;
303 ssize_t retval;
304 struct hpet_dev *devp;
305
306 devp = file->private_data;
307 if (!devp->hd_ireqfreq)
308 return -EIO;
309
310 if (count < sizeof(unsigned long))
311 return -EINVAL;
312
313 add_wait_queue(&devp->hd_waitqueue, &wait);
314
315 for ( ; ; ) {
316 set_current_state(TASK_INTERRUPTIBLE);
317
318 spin_lock_irq(&hpet_lock);
319 data = devp->hd_irqdata;
320 devp->hd_irqdata = 0;
321 spin_unlock_irq(&hpet_lock);
322
323 if (data)
324 break;
325 else if (file->f_flags & O_NONBLOCK) {
326 retval = -EAGAIN;
327 goto out;
328 } else if (signal_pending(current)) {
329 retval = -ERESTARTSYS;
330 goto out;
331 }
332 schedule();
333 }
334
335 retval = put_user(data, (unsigned long __user *)buf);
336 if (!retval)
337 retval = sizeof(unsigned long);
338out:
339 __set_current_state(TASK_RUNNING);
340 remove_wait_queue(&devp->hd_waitqueue, &wait);
341
342 return retval;
343}
344
345static unsigned int hpet_poll(struct file *file, poll_table * wait)
346{
347 unsigned long v;
348 struct hpet_dev *devp;
349
350 devp = file->private_data;
351
352 if (!devp->hd_ireqfreq)
353 return 0;
354
355 poll_wait(file, &devp->hd_waitqueue, wait);
356
357 spin_lock_irq(&hpet_lock);
358 v = devp->hd_irqdata;
359 spin_unlock_irq(&hpet_lock);
360
361 if (v != 0)
362 return POLLIN | POLLRDNORM;
363
364 return 0;
365}
366
3d035f58
PB
367#ifdef CONFIG_HPET_MMAP
368#ifdef CONFIG_HPET_MMAP_DEFAULT
369static int hpet_mmap_enabled = 1;
370#else
371static int hpet_mmap_enabled = 0;
372#endif
373
374static __init int hpet_mmap_enable(char *str)
375{
376 get_option(&str, &hpet_mmap_enabled);
377 pr_info("HPET mmap %s\n", hpet_mmap_enabled ? "enabled" : "disabled");
378 return 1;
379}
380__setup("hpet_mmap", hpet_mmap_enable);
381
1da177e4
LT
382static int hpet_mmap(struct file *file, struct vm_area_struct *vma)
383{
1da177e4
LT
384 struct hpet_dev *devp;
385 unsigned long addr;
386
3d035f58
PB
387 if (!hpet_mmap_enabled)
388 return -EACCES;
389
1da177e4
LT
390 devp = file->private_data;
391 addr = devp->hd_hpets->hp_hpet_phys;
392
393 if (addr & (PAGE_SIZE - 1))
394 return -ENOSYS;
395
1da177e4 396 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2323036d 397 return vm_iomap_memory(vma, addr, PAGE_SIZE);
3d035f58 398}
1da177e4 399#else
3d035f58
PB
400static int hpet_mmap(struct file *file, struct vm_area_struct *vma)
401{
1da177e4 402 return -ENOSYS;
1da177e4 403}
3d035f58 404#endif
1da177e4
LT
405
406static int hpet_fasync(int fd, struct file *file, int on)
407{
408 struct hpet_dev *devp;
409
410 devp = file->private_data;
411
412 if (fasync_helper(fd, file, on, &devp->hd_async_queue) >= 0)
413 return 0;
414 else
415 return -EIO;
416}
417
418static int hpet_release(struct inode *inode, struct file *file)
419{
420 struct hpet_dev *devp;
421 struct hpet_timer __iomem *timer;
422 int irq = 0;
423
424 devp = file->private_data;
425 timer = devp->hd_timer;
426
427 spin_lock_irq(&hpet_lock);
428
429 writeq((readq(&timer->hpet_config) & ~Tn_INT_ENB_CNF_MASK),
430 &timer->hpet_config);
431
432 irq = devp->hd_irq;
433 devp->hd_irq = 0;
434
435 devp->hd_ireqfreq = 0;
436
437 if (devp->hd_flags & HPET_PERIODIC
438 && readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) {
439 unsigned long v;
440
441 v = readq(&timer->hpet_config);
442 v ^= Tn_TYPE_CNF_MASK;
443 writeq(v, &timer->hpet_config);
444 }
445
446 devp->hd_flags &= ~(HPET_OPEN | HPET_IE | HPET_PERIODIC);
447 spin_unlock_irq(&hpet_lock);
448
449 if (irq)
450 free_irq(irq, devp);
451
1da177e4
LT
452 file->private_data = NULL;
453 return 0;
454}
455
1da177e4
LT
456static int hpet_ioctl_ieon(struct hpet_dev *devp)
457{
458 struct hpet_timer __iomem *timer;
459 struct hpet __iomem *hpet;
460 struct hpets *hpetp;
461 int irq;
462 unsigned long g, v, t, m;
463 unsigned long flags, isr;
464
465 timer = devp->hd_timer;
466 hpet = devp->hd_hpet;
467 hpetp = devp->hd_hpets;
468
9090e6db
CL
469 if (!devp->hd_ireqfreq)
470 return -EIO;
471
1da177e4
LT
472 spin_lock_irq(&hpet_lock);
473
474 if (devp->hd_flags & HPET_IE) {
475 spin_unlock_irq(&hpet_lock);
476 return -EBUSY;
477 }
478
479 devp->hd_flags |= HPET_IE;
0d290861
CL
480
481 if (readl(&timer->hpet_config) & Tn_INT_TYPE_CNF_MASK)
482 devp->hd_flags |= HPET_SHARED_IRQ;
1da177e4
LT
483 spin_unlock_irq(&hpet_lock);
484
1da177e4
LT
485 irq = devp->hd_hdwirq;
486
487 if (irq) {
0d290861 488 unsigned long irq_flags;
1da177e4 489
96e9694d
CL
490 if (devp->hd_flags & HPET_SHARED_IRQ) {
491 /*
492 * To prevent the interrupt handler from seeing an
493 * unwanted interrupt status bit, program the timer
494 * so that it will not fire in the near future ...
495 */
496 writel(readl(&timer->hpet_config) & ~Tn_TYPE_CNF_MASK,
497 &timer->hpet_config);
498 write_counter(read_counter(&hpet->hpet_mc),
499 &timer->hpet_compare);
500 /* ... and clear any left-over status. */
501 isr = 1 << (devp - devp->hd_hpets->hp_dev);
502 writel(isr, &hpet->hpet_isr);
503 }
504
0d290861 505 sprintf(devp->hd_name, "hpet%d", (int)(devp - hpetp->hp_dev));
158f0bb0 506 irq_flags = devp->hd_flags & HPET_SHARED_IRQ ? IRQF_SHARED : 0;
0d290861
CL
507 if (request_irq(irq, hpet_interrupt, irq_flags,
508 devp->hd_name, (void *)devp)) {
1da177e4
LT
509 printk(KERN_ERR "hpet: IRQ %d is not free\n", irq);
510 irq = 0;
511 }
512 }
513
514 if (irq == 0) {
515 spin_lock_irq(&hpet_lock);
516 devp->hd_flags ^= HPET_IE;
517 spin_unlock_irq(&hpet_lock);
518 return -EIO;
519 }
520
521 devp->hd_irq = irq;
522 t = devp->hd_ireqfreq;
523 v = readq(&timer->hpet_config);
64a76f66
DB
524
525 /* 64-bit comparators are not yet supported through the ioctls,
526 * so force this into 32-bit mode if it supports both modes
527 */
528 g = v | Tn_32MODE_CNF_MASK | Tn_INT_ENB_CNF_MASK;
1da177e4
LT
529
530 if (devp->hd_flags & HPET_PERIODIC) {
1da177e4 531 g |= Tn_TYPE_CNF_MASK;
ae21cf92 532 v |= Tn_TYPE_CNF_MASK | Tn_VAL_SET_CNF_MASK;
1da177e4
LT
533 writeq(v, &timer->hpet_config);
534 local_irq_save(flags);
64a76f66 535
ae21cf92
NC
536 /*
537 * NOTE: First we modify the hidden accumulator
64a76f66
DB
538 * register supported by periodic-capable comparators.
539 * We never want to modify the (single) counter; that
ae21cf92
NC
540 * would affect all the comparators. The value written
541 * is the counter value when the first interrupt is due.
64a76f66 542 */
1da177e4
LT
543 m = read_counter(&hpet->hpet_mc);
544 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
ae21cf92
NC
545 /*
546 * Then we modify the comparator, indicating the period
547 * for subsequent interrupt.
548 */
549 write_counter(t, &timer->hpet_compare);
1da177e4
LT
550 } else {
551 local_irq_save(flags);
552 m = read_counter(&hpet->hpet_mc);
553 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
554 }
555
0d290861 556 if (devp->hd_flags & HPET_SHARED_IRQ) {
3d5640d1 557 isr = 1 << (devp - devp->hd_hpets->hp_dev);
0d290861
CL
558 writel(isr, &hpet->hpet_isr);
559 }
1da177e4
LT
560 writeq(g, &timer->hpet_config);
561 local_irq_restore(flags);
562
563 return 0;
564}
565
ba3f213f
CL
566/* converts Hz to number of timer ticks */
567static inline unsigned long hpet_time_div(struct hpets *hpets,
568 unsigned long dis)
1da177e4 569{
ba3f213f 570 unsigned long long m;
1da177e4 571
ba3f213f 572 m = hpets->hp_tick_freq + (dis >> 1);
1da177e4 573 do_div(m, dis);
1da177e4
LT
574 return (unsigned long)m;
575}
576
577static int
54066a57
AB
578hpet_ioctl_common(struct hpet_dev *devp, int cmd, unsigned long arg,
579 struct hpet_info *info)
1da177e4
LT
580{
581 struct hpet_timer __iomem *timer;
582 struct hpet __iomem *hpet;
583 struct hpets *hpetp;
584 int err;
585 unsigned long v;
586
587 switch (cmd) {
588 case HPET_IE_OFF:
589 case HPET_INFO:
590 case HPET_EPI:
591 case HPET_DPI:
592 case HPET_IRQFREQ:
593 timer = devp->hd_timer;
594 hpet = devp->hd_hpet;
595 hpetp = devp->hd_hpets;
596 break;
597 case HPET_IE_ON:
598 return hpet_ioctl_ieon(devp);
599 default:
600 return -EINVAL;
601 }
602
603 err = 0;
604
605 switch (cmd) {
606 case HPET_IE_OFF:
607 if ((devp->hd_flags & HPET_IE) == 0)
608 break;
609 v = readq(&timer->hpet_config);
610 v &= ~Tn_INT_ENB_CNF_MASK;
611 writeq(v, &timer->hpet_config);
612 if (devp->hd_irq) {
613 free_irq(devp->hd_irq, devp);
614 devp->hd_irq = 0;
615 }
616 devp->hd_flags ^= HPET_IE;
617 break;
618 case HPET_INFO:
619 {
dae512ed 620 memset(info, 0, sizeof(*info));
af95eade 621 if (devp->hd_ireqfreq)
54066a57 622 info->hi_ireqfreq =
af95eade 623 hpet_time_div(hpetp, devp->hd_ireqfreq);
54066a57 624 info->hi_flags =
1da177e4 625 readq(&timer->hpet_config) & Tn_PER_INT_CAP_MASK;
54066a57
AB
626 info->hi_hpet = hpetp->hp_which;
627 info->hi_timer = devp - hpetp->hp_dev;
1da177e4
LT
628 break;
629 }
630 case HPET_EPI:
631 v = readq(&timer->hpet_config);
632 if ((v & Tn_PER_INT_CAP_MASK) == 0) {
633 err = -ENXIO;
634 break;
635 }
636 devp->hd_flags |= HPET_PERIODIC;
637 break;
638 case HPET_DPI:
639 v = readq(&timer->hpet_config);
640 if ((v & Tn_PER_INT_CAP_MASK) == 0) {
641 err = -ENXIO;
642 break;
643 }
644 if (devp->hd_flags & HPET_PERIODIC &&
645 readq(&timer->hpet_config) & Tn_TYPE_CNF_MASK) {
646 v = readq(&timer->hpet_config);
647 v ^= Tn_TYPE_CNF_MASK;
648 writeq(v, &timer->hpet_config);
649 }
650 devp->hd_flags &= ~HPET_PERIODIC;
651 break;
652 case HPET_IRQFREQ:
54066a57 653 if ((arg > hpet_max_freq) &&
1da177e4
LT
654 !capable(CAP_SYS_RESOURCE)) {
655 err = -EACCES;
656 break;
657 }
658
189e2dd1 659 if (!arg) {
1da177e4
LT
660 err = -EINVAL;
661 break;
662 }
663
ba3f213f 664 devp->hd_ireqfreq = hpet_time_div(hpetp, arg);
1da177e4
LT
665 }
666
667 return err;
668}
669
54066a57
AB
670static long
671hpet_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
672{
673 struct hpet_info info;
674 int err;
675
676 mutex_lock(&hpet_mutex);
677 err = hpet_ioctl_common(file->private_data, cmd, arg, &info);
678 mutex_unlock(&hpet_mutex);
679
680 if ((cmd == HPET_INFO) && !err &&
681 (copy_to_user((void __user *)arg, &info, sizeof(info))))
682 err = -EFAULT;
683
684 return err;
685}
686
687#ifdef CONFIG_COMPAT
688struct compat_hpet_info {
689 compat_ulong_t hi_ireqfreq; /* Hz */
690 compat_ulong_t hi_flags; /* information */
691 unsigned short hi_hpet;
692 unsigned short hi_timer;
693};
694
695static long
696hpet_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
697{
698 struct hpet_info info;
699 int err;
700
701 mutex_lock(&hpet_mutex);
702 err = hpet_ioctl_common(file->private_data, cmd, arg, &info);
703 mutex_unlock(&hpet_mutex);
704
705 if ((cmd == HPET_INFO) && !err) {
706 struct compat_hpet_info __user *u = compat_ptr(arg);
707 if (put_user(info.hi_ireqfreq, &u->hi_ireqfreq) ||
708 put_user(info.hi_flags, &u->hi_flags) ||
709 put_user(info.hi_hpet, &u->hi_hpet) ||
710 put_user(info.hi_timer, &u->hi_timer))
711 err = -EFAULT;
712 }
713
714 return err;
715}
716#endif
717
62322d25 718static const struct file_operations hpet_fops = {
1da177e4
LT
719 .owner = THIS_MODULE,
720 .llseek = no_llseek,
721 .read = hpet_read,
722 .poll = hpet_poll,
55929332 723 .unlocked_ioctl = hpet_ioctl,
54066a57
AB
724#ifdef CONFIG_COMPAT
725 .compat_ioctl = hpet_compat_ioctl,
726#endif
1da177e4
LT
727 .open = hpet_open,
728 .release = hpet_release,
729 .fasync = hpet_fasync,
730 .mmap = hpet_mmap,
731};
732
3e6716e7
RD
733static int hpet_is_known(struct hpet_data *hdp)
734{
735 struct hpets *hpetp;
736
737 for (hpetp = hpets; hpetp; hpetp = hpetp->hp_next)
738 if (hpetp->hp_hpet_phys == hdp->hd_phys_address)
739 return 1;
740
741 return 0;
742}
743
a151427e 744static struct ctl_table hpet_table[] = {
1da177e4 745 {
1da177e4
LT
746 .procname = "max-user-freq",
747 .data = &hpet_max_freq,
748 .maxlen = sizeof(int),
749 .mode = 0644,
6d456111 750 .proc_handler = proc_dointvec,
1da177e4 751 },
894d2491 752 {}
1da177e4
LT
753};
754
a151427e 755static struct ctl_table hpet_root[] = {
1da177e4 756 {
1da177e4
LT
757 .procname = "hpet",
758 .maxlen = 0,
759 .mode = 0555,
760 .child = hpet_table,
761 },
894d2491 762 {}
1da177e4
LT
763};
764
a151427e 765static struct ctl_table dev_root[] = {
1da177e4 766 {
1da177e4
LT
767 .procname = "dev",
768 .maxlen = 0,
769 .mode = 0555,
770 .child = hpet_root,
771 },
894d2491 772 {}
1da177e4
LT
773};
774
775static struct ctl_table_header *sysctl_header;
776
1da177e4
LT
777/*
778 * Adjustment for when arming the timer with
779 * initial conditions. That is, main counter
780 * ticks expired before interrupts are enabled.
781 */
782#define TICK_CALIBRATE (1000UL)
783
303d379c 784static unsigned long __hpet_calibrate(struct hpets *hpetp)
1da177e4
LT
785{
786 struct hpet_timer __iomem *timer = NULL;
787 unsigned long t, m, count, i, flags, start;
788 struct hpet_dev *devp;
789 int j;
790 struct hpet __iomem *hpet;
791
792 for (j = 0, devp = hpetp->hp_dev; j < hpetp->hp_ntimer; j++, devp++)
793 if ((devp->hd_flags & HPET_OPEN) == 0) {
794 timer = devp->hd_timer;
795 break;
796 }
797
798 if (!timer)
799 return 0;
800
3d5640d1 801 hpet = hpetp->hp_hpet;
1da177e4
LT
802 t = read_counter(&timer->hpet_compare);
803
804 i = 0;
ba3f213f 805 count = hpet_time_div(hpetp, TICK_CALIBRATE);
1da177e4
LT
806
807 local_irq_save(flags);
808
809 start = read_counter(&hpet->hpet_mc);
810
811 do {
812 m = read_counter(&hpet->hpet_mc);
813 write_counter(t + m + hpetp->hp_delta, &timer->hpet_compare);
814 } while (i++, (m - start) < count);
815
816 local_irq_restore(flags);
817
818 return (m - start) / i;
819}
820
303d379c
YG
821static unsigned long hpet_calibrate(struct hpets *hpetp)
822{
2cf4e52e 823 unsigned long ret = ~0UL;
303d379c
YG
824 unsigned long tmp;
825
826 /*
827 * Try to calibrate until return value becomes stable small value.
828 * If SMI interruption occurs in calibration loop, the return value
829 * will be big. This avoids its impact.
830 */
831 for ( ; ; ) {
832 tmp = __hpet_calibrate(hpetp);
833 if (ret <= tmp)
834 break;
835 ret = tmp;
836 }
837
838 return ret;
839}
840
1da177e4
LT
841int hpet_alloc(struct hpet_data *hdp)
842{
5761d64b 843 u64 cap, mcfg;
1da177e4 844 struct hpet_dev *devp;
5761d64b 845 u32 i, ntimer;
1da177e4
LT
846 struct hpets *hpetp;
847 size_t siz;
848 struct hpet __iomem *hpet;
0ca01763 849 static struct hpets *last;
5761d64b 850 unsigned long period;
ba3f213f 851 unsigned long long temp;
f92a789d 852 u32 remainder;
1da177e4
LT
853
854 /*
855 * hpet_alloc can be called by platform dependent code.
3e6716e7
RD
856 * If platform dependent code has allocated the hpet that
857 * ACPI has also reported, then we catch it here.
1da177e4 858 */
3e6716e7
RD
859 if (hpet_is_known(hdp)) {
860 printk(KERN_DEBUG "%s: duplicate HPET ignored\n",
bf9d8929 861 __func__);
3e6716e7
RD
862 return 0;
863 }
1da177e4
LT
864
865 siz = sizeof(struct hpets) + ((hdp->hd_nirqs - 1) *
866 sizeof(struct hpet_dev));
867
3e6716e7 868 hpetp = kzalloc(siz, GFP_KERNEL);
1da177e4
LT
869
870 if (!hpetp)
871 return -ENOMEM;
872
1da177e4
LT
873 hpetp->hp_which = hpet_nhpet++;
874 hpetp->hp_hpet = hdp->hd_address;
875 hpetp->hp_hpet_phys = hdp->hd_phys_address;
876
877 hpetp->hp_ntimer = hdp->hd_nirqs;
e3f37a54 878
5761d64b
TG
879 for (i = 0; i < hdp->hd_nirqs; i++)
880 hpetp->hp_dev[i].hd_hdwirq = hdp->hd_irq[i];
37a47db8 881
5761d64b 882 hpet = hpetp->hp_hpet;
e3f37a54 883
1da177e4
LT
884 cap = readq(&hpet->hpet_cap);
885
886 ntimer = ((cap & HPET_NUM_TIM_CAP_MASK) >> HPET_NUM_TIM_CAP_SHIFT) + 1;
887
888 if (hpetp->hp_ntimer != ntimer) {
889 printk(KERN_WARNING "hpet: number irqs doesn't agree"
890 " with number of timers\n");
891 kfree(hpetp);
892 return -ENODEV;
893 }
894
895 if (last)
896 last->hp_next = hpetp;
897 else
898 hpets = hpetp;
899
900 last = hpetp;
901
ba3f213f
CL
902 period = (cap & HPET_COUNTER_CLK_PERIOD_MASK) >>
903 HPET_COUNTER_CLK_PERIOD_SHIFT; /* fs, 10^-15 */
904 temp = 1000000000000000uLL; /* 10^15 femtoseconds per second */
905 temp += period >> 1; /* round */
906 do_div(temp, period);
907 hpetp->hp_tick_freq = temp; /* ticks per second */
1da177e4 908
3034d11c
AK
909 printk(KERN_INFO "hpet%d: at MMIO 0x%lx, IRQ%s",
910 hpetp->hp_which, hdp->hd_phys_address,
1da177e4
LT
911 hpetp->hp_ntimer > 1 ? "s" : "");
912 for (i = 0; i < hpetp->hp_ntimer; i++)
5da527aa
KS
913 printk(KERN_CONT "%s %d", i > 0 ? "," : "", hdp->hd_irq[i]);
914 printk(KERN_CONT "\n");
1da177e4 915
f92a789d
DB
916 temp = hpetp->hp_tick_freq;
917 remainder = do_div(temp, 1000000);
64a76f66
DB
918 printk(KERN_INFO
919 "hpet%u: %u comparators, %d-bit %u.%06u MHz counter\n",
920 hpetp->hp_which, hpetp->hp_ntimer,
921 cap & HPET_COUNTER_SIZE_MASK ? 64 : 32,
f92a789d 922 (unsigned) temp, remainder);
1da177e4
LT
923
924 mcfg = readq(&hpet->hpet_config);
925 if ((mcfg & HPET_ENABLE_CNF_MASK) == 0) {
926 write_counter(0L, &hpet->hpet_mc);
927 mcfg |= HPET_ENABLE_CNF_MASK;
928 writeq(mcfg, &hpet->hpet_config);
929 }
930
642d30bb 931 for (i = 0, devp = hpetp->hp_dev; i < hpetp->hp_ntimer; i++, devp++) {
1da177e4
LT
932 struct hpet_timer __iomem *timer;
933
934 timer = &hpet->hpet_timers[devp - hpetp->hp_dev];
1da177e4
LT
935
936 devp->hd_hpets = hpetp;
937 devp->hd_hpet = hpet;
938 devp->hd_timer = timer;
939
940 /*
941 * If the timer was reserved by platform code,
942 * then make timer unavailable for opens.
943 */
944 if (hdp->hd_state & (1 << i)) {
945 devp->hd_flags = HPET_OPEN;
946 continue;
947 }
948
949 init_waitqueue_head(&devp->hd_waitqueue);
950 }
951
952 hpetp->hp_delta = hpet_calibrate(hpetp);
0aa366f3 953
3b2b64fd
LT
954/* This clocksource driver currently only works on ia64 */
955#ifdef CONFIG_IA64
0aa366f3
TL
956 if (!hpet_clocksource) {
957 hpet_mctr = (void __iomem *)&hpetp->hp_hpet->hpet_mc;
574c44fa 958 clocksource_hpet.archdata.fsys_mmio = hpet_mctr;
d60c3041 959 clocksource_register_hz(&clocksource_hpet, hpetp->hp_tick_freq);
0aa366f3
TL
960 hpetp->hp_clocksource = &clocksource_hpet;
961 hpet_clocksource = &clocksource_hpet;
962 }
3b2b64fd 963#endif
1da177e4
LT
964
965 return 0;
966}
967
968static acpi_status hpet_resources(struct acpi_resource *res, void *data)
969{
970 struct hpet_data *hdp;
971 acpi_status status;
972 struct acpi_resource_address64 addr;
1da177e4
LT
973
974 hdp = data;
975
976 status = acpi_resource_to_address64(res, &addr);
977
978 if (ACPI_SUCCESS(status)) {
a45de93e
LZ
979 hdp->hd_phys_address = addr.address.minimum;
980 hdp->hd_address = ioremap(addr.address.minimum, addr.address.address_length);
1da177e4 981
3e6716e7 982 if (hpet_is_known(hdp)) {
3e6716e7 983 iounmap(hdp->hd_address);
78e1ca49 984 return AE_ALREADY_EXISTS;
3e6716e7 985 }
50eca3eb
BM
986 } else if (res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
987 struct acpi_resource_fixed_memory32 *fixmem32;
757c4724
RD
988
989 fixmem32 = &res->data.fixed_memory32;
757c4724 990
50eca3eb
BM
991 hdp->hd_phys_address = fixmem32->address;
992 hdp->hd_address = ioremap(fixmem32->address,
757c4724
RD
993 HPET_RANGE_SIZE);
994
3e6716e7 995 if (hpet_is_known(hdp)) {
3e6716e7 996 iounmap(hdp->hd_address);
78e1ca49 997 return AE_ALREADY_EXISTS;
3e6716e7 998 }
50eca3eb
BM
999 } else if (res->type == ACPI_RESOURCE_TYPE_EXTENDED_IRQ) {
1000 struct acpi_resource_extended_irq *irqp;
be5efffb 1001 int i, irq;
1da177e4
LT
1002
1003 irqp = &res->data.extended_irq;
1004
be5efffb 1005 for (i = 0; i < irqp->interrupt_count; i++) {
2cf4e52e
CG
1006 if (hdp->hd_nirqs >= HPET_MAX_TIMERS)
1007 break;
1008
a2f809b0 1009 irq = acpi_register_gsi(NULL, irqp->interrupts[i],
be5efffb
BH
1010 irqp->triggering, irqp->polarity);
1011 if (irq < 0)
1012 return AE_ERROR;
1013
1014 hdp->hd_irq[hdp->hd_nirqs] = irq;
1015 hdp->hd_nirqs++;
1da177e4
LT
1016 }
1017 }
1018
1019 return AE_OK;
1020}
1021
1022static int hpet_acpi_add(struct acpi_device *device)
1023{
1024 acpi_status result;
1025 struct hpet_data data;
1026
1027 memset(&data, 0, sizeof(data));
1028
1029 result =
1030 acpi_walk_resources(device->handle, METHOD_NAME__CRS,
1031 hpet_resources, &data);
1032
1033 if (ACPI_FAILURE(result))
1034 return -ENODEV;
1035
1036 if (!data.hd_address || !data.hd_nirqs) {
a56d5318
JS
1037 if (data.hd_address)
1038 iounmap(data.hd_address);
bf9d8929 1039 printk("%s: no address or irqs in _CRS\n", __func__);
1da177e4
LT
1040 return -ENODEV;
1041 }
1042
1043 return hpet_alloc(&data);
1044}
1045
1ba90e3a
TR
1046static const struct acpi_device_id hpet_device_ids[] = {
1047 {"PNP0103", 0},
1048 {"", 0},
1049};
1ba90e3a 1050
1da177e4
LT
1051static struct acpi_driver hpet_acpi_driver = {
1052 .name = "hpet",
1ba90e3a 1053 .ids = hpet_device_ids,
1da177e4
LT
1054 .ops = {
1055 .add = hpet_acpi_add,
1da177e4
LT
1056 },
1057};
1058
1059static struct miscdevice hpet_misc = { HPET_MINOR, "hpet", &hpet_fops };
1060
1061static int __init hpet_init(void)
1062{
1063 int result;
1064
1065 result = misc_register(&hpet_misc);
1066 if (result < 0)
1067 return -ENODEV;
1068
0b4d4147 1069 sysctl_header = register_sysctl_table(dev_root);
1da177e4
LT
1070
1071 result = acpi_bus_register_driver(&hpet_acpi_driver);
1072 if (result < 0) {
1073 if (sysctl_header)
1074 unregister_sysctl_table(sysctl_header);
1075 misc_deregister(&hpet_misc);
1076 return result;
1077 }
1078
1079 return 0;
1080}
a8cedfec 1081device_initcall(hpet_init);
1da177e4 1082
a8cedfec 1083/*
1da177e4
LT
1084MODULE_AUTHOR("Bob Picco <Robert.Picco@hp.com>");
1085MODULE_LICENSE("GPL");
a8cedfec 1086*/