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Commit | Line | Data |
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1da177e4 | 1 | /* |
f30c2269 | 2 | * drivers/i2c/busses/i2c-ibm_iic.c |
1da177e4 LT |
3 | * |
4 | * Support for the IIC peripheral on IBM PPC 4xx | |
5 | * | |
6 | * Copyright (c) 2003, 2004 Zultys Technologies. | |
7 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> | |
8 | * | |
838349b5 SM |
9 | * Copyright (c) 2008 PIKA Technologies |
10 | * Sean MacLennan <smaclennan@pikatech.com> | |
11 | * | |
217bcec4 | 12 | * Based on original work by |
1da177e4 LT |
13 | * Ian DaSilva <idasilva@mvista.com> |
14 | * Armin Kuster <akuster@mvista.com> | |
15 | * Matt Porter <mporter@mvista.com> | |
16 | * | |
17 | * Copyright 2000-2003 MontaVista Software Inc. | |
18 | * | |
19 | * Original driver version was highly leveraged from i2c-elektor.c | |
20 | * | |
21 | * Copyright 1995-97 Simon G. Vogl | |
22 | * 1998-99 Hans Berglund | |
23 | * | |
96de0e25 | 24 | * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> |
1da177e4 LT |
25 | * and even Frodo Looijaard <frodol@dds.nl> |
26 | * | |
27 | * This program is free software; you can redistribute it and/or modify it | |
28 | * under the terms of the GNU General Public License as published by the | |
29 | * Free Software Foundation; either version 2 of the License, or (at your | |
30 | * option) any later version. | |
31 | * | |
32 | */ | |
33 | ||
1da177e4 LT |
34 | #include <linux/module.h> |
35 | #include <linux/kernel.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/slab.h> | |
1da177e4 | 39 | #include <linux/interrupt.h> |
174cd4b1 IM |
40 | #include <linux/sched/signal.h> |
41 | ||
1da177e4 | 42 | #include <asm/irq.h> |
21782180 | 43 | #include <linux/io.h> |
1da177e4 | 44 | #include <linux/i2c.h> |
5af50730 RH |
45 | #include <linux/of_address.h> |
46 | #include <linux/of_irq.h> | |
838349b5 | 47 | #include <linux/of_platform.h> |
1da177e4 LT |
48 | |
49 | #include "i2c-ibm_iic.h" | |
50 | ||
838349b5 | 51 | #define DRIVER_VERSION "2.2" |
1da177e4 LT |
52 | |
53 | MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION); | |
54 | MODULE_LICENSE("GPL"); | |
55 | ||
90ab5ee9 | 56 | static bool iic_force_poll; |
1da177e4 LT |
57 | module_param(iic_force_poll, bool, 0); |
58 | MODULE_PARM_DESC(iic_force_poll, "Force polling mode"); | |
59 | ||
90ab5ee9 | 60 | static bool iic_force_fast; |
1da177e4 | 61 | module_param(iic_force_fast, bool, 0); |
852fb2ac | 62 | MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)"); |
1da177e4 LT |
63 | |
64 | #define DBG_LEVEL 0 | |
65 | ||
66 | #ifdef DBG | |
67 | #undef DBG | |
68 | #endif | |
69 | ||
70 | #ifdef DBG2 | |
71 | #undef DBG2 | |
72 | #endif | |
73 | ||
74 | #if DBG_LEVEL > 0 | |
75 | # define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x) | |
76 | #else | |
77 | # define DBG(f,x...) ((void)0) | |
78 | #endif | |
79 | #if DBG_LEVEL > 1 | |
80 | # define DBG2(f,x...) DBG(f, ##x) | |
81 | #else | |
82 | # define DBG2(f,x...) ((void)0) | |
83 | #endif | |
84 | #if DBG_LEVEL > 2 | |
85 | static void dump_iic_regs(const char* header, struct ibm_iic_private* dev) | |
86 | { | |
87 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
88 | printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header); | |
ad361c98 JP |
89 | printk(KERN_DEBUG |
90 | " cntl = 0x%02x, mdcntl = 0x%02x\n" | |
91 | " sts = 0x%02x, extsts = 0x%02x\n" | |
92 | " clkdiv = 0x%02x, xfrcnt = 0x%02x\n" | |
93 | " xtcntlss = 0x%02x, directcntl = 0x%02x\n", | |
217bcec4 SR |
94 | in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), |
95 | in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), | |
1da177e4 LT |
96 | in_8(&iic->xtcntlss), in_8(&iic->directcntl)); |
97 | } | |
98 | # define DUMP_REGS(h,dev) dump_iic_regs((h),(dev)) | |
99 | #else | |
100 | # define DUMP_REGS(h,dev) ((void)0) | |
101 | #endif | |
102 | ||
103 | /* Bus timings (in ns) for bit-banging */ | |
f199b260 | 104 | static struct ibm_iic_timings { |
1da177e4 LT |
105 | unsigned int hd_sta; |
106 | unsigned int su_sto; | |
107 | unsigned int low; | |
108 | unsigned int high; | |
109 | unsigned int buf; | |
110 | } timings [] = { | |
111 | /* Standard mode (100 KHz) */ | |
112 | { | |
113 | .hd_sta = 4000, | |
114 | .su_sto = 4000, | |
115 | .low = 4700, | |
116 | .high = 4000, | |
117 | .buf = 4700, | |
118 | }, | |
119 | /* Fast mode (400 KHz) */ | |
120 | { | |
121 | .hd_sta = 600, | |
122 | .su_sto = 600, | |
123 | .low = 1300, | |
124 | .high = 600, | |
125 | .buf = 1300, | |
126 | }}; | |
127 | ||
128 | /* Enable/disable interrupt generation */ | |
129 | static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable) | |
130 | { | |
131 | out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0); | |
132 | } | |
217bcec4 | 133 | |
1da177e4 LT |
134 | /* |
135 | * Initialize IIC interface. | |
136 | */ | |
137 | static void iic_dev_init(struct ibm_iic_private* dev) | |
138 | { | |
139 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
140 | ||
141 | DBG("%d: init\n", dev->idx); | |
217bcec4 | 142 | |
1da177e4 LT |
143 | /* Clear master address */ |
144 | out_8(&iic->lmadr, 0); | |
145 | out_8(&iic->hmadr, 0); | |
146 | ||
147 | /* Clear slave address */ | |
148 | out_8(&iic->lsadr, 0); | |
149 | out_8(&iic->hsadr, 0); | |
150 | ||
151 | /* Clear status & extended status */ | |
152 | out_8(&iic->sts, STS_SCMP | STS_IRQA); | |
153 | out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA | |
154 | | EXTSTS_ICT | EXTSTS_XFRA); | |
155 | ||
156 | /* Set clock divider */ | |
157 | out_8(&iic->clkdiv, dev->clckdiv); | |
158 | ||
159 | /* Clear transfer count */ | |
160 | out_8(&iic->xfrcnt, 0); | |
161 | ||
162 | /* Clear extended control and status */ | |
163 | out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC | |
164 | | XTCNTLSS_SWS); | |
165 | ||
166 | /* Clear control register */ | |
167 | out_8(&iic->cntl, 0); | |
217bcec4 | 168 | |
1da177e4 LT |
169 | /* Enable interrupts if possible */ |
170 | iic_interrupt_mode(dev, dev->irq >= 0); | |
171 | ||
172 | /* Set mode control */ | |
173 | out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS | |
174 | | (dev->fast_mode ? MDCNTL_FSM : 0)); | |
175 | ||
176 | DUMP_REGS("iic_init", dev); | |
177 | } | |
178 | ||
217bcec4 | 179 | /* |
1da177e4 LT |
180 | * Reset IIC interface |
181 | */ | |
182 | static void iic_dev_reset(struct ibm_iic_private* dev) | |
183 | { | |
184 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
185 | int i; | |
186 | u8 dc; | |
217bcec4 | 187 | |
1da177e4 LT |
188 | DBG("%d: soft reset\n", dev->idx); |
189 | DUMP_REGS("reset", dev); | |
217bcec4 | 190 | |
1da177e4 LT |
191 | /* Place chip in the reset state */ |
192 | out_8(&iic->xtcntlss, XTCNTLSS_SRST); | |
217bcec4 | 193 | |
1da177e4 | 194 | /* Check if bus is free */ |
217bcec4 | 195 | dc = in_8(&iic->directcntl); |
1da177e4 LT |
196 | if (!DIRCTNL_FREE(dc)){ |
197 | DBG("%d: trying to regain bus control\n", dev->idx); | |
217bcec4 | 198 | |
1da177e4 | 199 | /* Try to set bus free state */ |
217bcec4 SR |
200 | out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); |
201 | ||
1da177e4 LT |
202 | /* Wait until we regain bus control */ |
203 | for (i = 0; i < 100; ++i){ | |
204 | dc = in_8(&iic->directcntl); | |
205 | if (DIRCTNL_FREE(dc)) | |
206 | break; | |
217bcec4 | 207 | |
1da177e4 LT |
208 | /* Toggle SCL line */ |
209 | dc ^= DIRCNTL_SCC; | |
210 | out_8(&iic->directcntl, dc); | |
211 | udelay(10); | |
212 | dc ^= DIRCNTL_SCC; | |
213 | out_8(&iic->directcntl, dc); | |
217bcec4 | 214 | |
1da177e4 LT |
215 | /* be nice */ |
216 | cond_resched(); | |
217 | } | |
218 | } | |
217bcec4 | 219 | |
1da177e4 LT |
220 | /* Remove reset */ |
221 | out_8(&iic->xtcntlss, 0); | |
217bcec4 | 222 | |
1da177e4 LT |
223 | /* Reinitialize interface */ |
224 | iic_dev_init(dev); | |
225 | } | |
226 | ||
227 | /* | |
228 | * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register. | |
229 | */ | |
230 | ||
231 | /* Wait for SCL and/or SDA to be high */ | |
232 | static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask) | |
233 | { | |
234 | unsigned long x = jiffies + HZ / 28 + 2; | |
235 | while ((in_8(&iic->directcntl) & mask) != mask){ | |
236 | if (unlikely(time_after(jiffies, x))) | |
237 | return -1; | |
238 | cond_resched(); | |
239 | } | |
240 | return 0; | |
241 | } | |
242 | ||
243 | static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p) | |
244 | { | |
245 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
f199b260 | 246 | const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0]; |
1da177e4 LT |
247 | u8 mask, v, sda; |
248 | int i, res; | |
249 | ||
250 | /* Only 7-bit addresses are supported */ | |
251 | if (unlikely(p->flags & I2C_M_TEN)){ | |
252 | DBG("%d: smbus_quick - 10 bit addresses are not supported\n", | |
253 | dev->idx); | |
254 | return -EINVAL; | |
255 | } | |
256 | ||
257 | DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr); | |
258 | ||
259 | /* Reset IIC interface */ | |
260 | out_8(&iic->xtcntlss, XTCNTLSS_SRST); | |
261 | ||
262 | /* Wait for bus to become free */ | |
263 | out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); | |
264 | if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC))) | |
265 | goto err; | |
266 | ndelay(t->buf); | |
267 | ||
268 | /* START */ | |
269 | out_8(&iic->directcntl, DIRCNTL_SCC); | |
270 | sda = 0; | |
271 | ndelay(t->hd_sta); | |
272 | ||
273 | /* Send address */ | |
73fef219 | 274 | v = i2c_8bit_addr_from_msg(p); |
1da177e4 LT |
275 | for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){ |
276 | out_8(&iic->directcntl, sda); | |
277 | ndelay(t->low / 2); | |
278 | sda = (v & mask) ? DIRCNTL_SDAC : 0; | |
279 | out_8(&iic->directcntl, sda); | |
280 | ndelay(t->low / 2); | |
281 | ||
282 | out_8(&iic->directcntl, DIRCNTL_SCC | sda); | |
283 | if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) | |
284 | goto err; | |
285 | ndelay(t->high); | |
286 | } | |
287 | ||
288 | /* ACK */ | |
289 | out_8(&iic->directcntl, sda); | |
290 | ndelay(t->low / 2); | |
291 | out_8(&iic->directcntl, DIRCNTL_SDAC); | |
292 | ndelay(t->low / 2); | |
293 | out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); | |
294 | if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) | |
295 | goto err; | |
296 | res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1; | |
297 | ndelay(t->high); | |
298 | ||
299 | /* STOP */ | |
300 | out_8(&iic->directcntl, 0); | |
301 | ndelay(t->low); | |
302 | out_8(&iic->directcntl, DIRCNTL_SCC); | |
303 | if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC))) | |
304 | goto err; | |
305 | ndelay(t->su_sto); | |
306 | out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC); | |
307 | ||
308 | ndelay(t->buf); | |
309 | ||
310 | DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK"); | |
311 | out: | |
312 | /* Remove reset */ | |
313 | out_8(&iic->xtcntlss, 0); | |
314 | ||
315 | /* Reinitialize interface */ | |
316 | iic_dev_init(dev); | |
317 | ||
318 | return res; | |
319 | err: | |
320 | DBG("%d: smbus_quick - bus is stuck\n", dev->idx); | |
321 | res = -EREMOTEIO; | |
322 | goto out; | |
323 | } | |
324 | ||
325 | /* | |
326 | * IIC interrupt handler | |
327 | */ | |
7d12e780 | 328 | static irqreturn_t iic_handler(int irq, void *dev_id) |
1da177e4 LT |
329 | { |
330 | struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id; | |
331 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
217bcec4 SR |
332 | |
333 | DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n", | |
1da177e4 | 334 | dev->idx, in_8(&iic->sts), in_8(&iic->extsts)); |
217bcec4 | 335 | |
1da177e4 LT |
336 | /* Acknowledge IRQ and wakeup iic_wait_for_tc */ |
337 | out_8(&iic->sts, STS_IRQA | STS_SCMP); | |
338 | wake_up_interruptible(&dev->wq); | |
217bcec4 | 339 | |
1da177e4 LT |
340 | return IRQ_HANDLED; |
341 | } | |
342 | ||
343 | /* | |
344 | * Get master transfer result and clear errors if any. | |
345 | * Returns the number of actually transferred bytes or error (<0) | |
346 | */ | |
347 | static int iic_xfer_result(struct ibm_iic_private* dev) | |
348 | { | |
217bcec4 SR |
349 | volatile struct iic_regs __iomem *iic = dev->vaddr; |
350 | ||
1da177e4 | 351 | if (unlikely(in_8(&iic->sts) & STS_ERR)){ |
217bcec4 | 352 | DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx, |
1da177e4 | 353 | in_8(&iic->extsts)); |
217bcec4 | 354 | |
1da177e4 | 355 | /* Clear errors and possible pending IRQs */ |
217bcec4 | 356 | out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | |
1da177e4 | 357 | EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA); |
217bcec4 | 358 | |
1da177e4 LT |
359 | /* Flush master data buffer */ |
360 | out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB); | |
217bcec4 | 361 | |
1da177e4 LT |
362 | /* Is bus free? |
363 | * If error happened during combined xfer | |
364 | * IIC interface is usually stuck in some strange | |
365 | * state, the only way out - soft reset. | |
366 | */ | |
367 | if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ | |
368 | DBG("%d: bus is stuck, resetting\n", dev->idx); | |
369 | iic_dev_reset(dev); | |
370 | } | |
371 | return -EREMOTEIO; | |
372 | } | |
373 | else | |
374 | return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK; | |
375 | } | |
376 | ||
377 | /* | |
378 | * Try to abort active transfer. | |
379 | */ | |
380 | static void iic_abort_xfer(struct ibm_iic_private* dev) | |
381 | { | |
382 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
383 | unsigned long x; | |
217bcec4 | 384 | |
1da177e4 | 385 | DBG("%d: iic_abort_xfer\n", dev->idx); |
217bcec4 | 386 | |
1da177e4 | 387 | out_8(&iic->cntl, CNTL_HMT); |
217bcec4 | 388 | |
1da177e4 LT |
389 | /* |
390 | * Wait for the abort command to complete. | |
391 | * It's not worth to be optimized, just poll (timeout >= 1 tick) | |
392 | */ | |
393 | x = jiffies + 2; | |
394 | while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ | |
395 | if (time_after(jiffies, x)){ | |
396 | DBG("%d: abort timeout, resetting...\n", dev->idx); | |
397 | iic_dev_reset(dev); | |
398 | return; | |
399 | } | |
400 | schedule(); | |
401 | } | |
402 | ||
403 | /* Just to clear errors */ | |
404 | iic_xfer_result(dev); | |
405 | } | |
406 | ||
407 | /* | |
408 | * Wait for master transfer to complete. | |
409 | * It puts current process to sleep until we get interrupt or timeout expires. | |
410 | * Returns the number of transferred bytes or error (<0) | |
411 | */ | |
412 | static int iic_wait_for_tc(struct ibm_iic_private* dev){ | |
217bcec4 | 413 | |
1da177e4 LT |
414 | volatile struct iic_regs __iomem *iic = dev->vaddr; |
415 | int ret = 0; | |
217bcec4 | 416 | |
1da177e4 LT |
417 | if (dev->irq >= 0){ |
418 | /* Interrupt mode */ | |
217bcec4 | 419 | ret = wait_event_interruptible_timeout(dev->wq, |
8a52c6b4 | 420 | !(in_8(&iic->sts) & STS_PT), dev->adap.timeout); |
1da177e4 LT |
421 | |
422 | if (unlikely(ret < 0)) | |
423 | DBG("%d: wait interrupted\n", dev->idx); | |
424 | else if (unlikely(in_8(&iic->sts) & STS_PT)){ | |
425 | DBG("%d: wait timeout\n", dev->idx); | |
426 | ret = -ETIMEDOUT; | |
427 | } | |
428 | } | |
429 | else { | |
430 | /* Polling mode */ | |
8a52c6b4 | 431 | unsigned long x = jiffies + dev->adap.timeout; |
217bcec4 | 432 | |
1da177e4 LT |
433 | while (in_8(&iic->sts) & STS_PT){ |
434 | if (unlikely(time_after(jiffies, x))){ | |
435 | DBG("%d: poll timeout\n", dev->idx); | |
436 | ret = -ETIMEDOUT; | |
437 | break; | |
438 | } | |
217bcec4 | 439 | |
1da177e4 LT |
440 | if (unlikely(signal_pending(current))){ |
441 | DBG("%d: poll interrupted\n", dev->idx); | |
442 | ret = -ERESTARTSYS; | |
443 | break; | |
444 | } | |
445 | schedule(); | |
217bcec4 | 446 | } |
1da177e4 | 447 | } |
217bcec4 | 448 | |
1da177e4 LT |
449 | if (unlikely(ret < 0)) |
450 | iic_abort_xfer(dev); | |
451 | else | |
452 | ret = iic_xfer_result(dev); | |
217bcec4 | 453 | |
1da177e4 | 454 | DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret); |
217bcec4 | 455 | |
1da177e4 LT |
456 | return ret; |
457 | } | |
458 | ||
459 | /* | |
460 | * Low level master transfer routine | |
461 | */ | |
217bcec4 | 462 | static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm, |
1da177e4 LT |
463 | int combined_xfer) |
464 | { | |
465 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
466 | char* buf = pm->buf; | |
467 | int i, j, loops, ret = 0; | |
468 | int len = pm->len; | |
469 | ||
470 | u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT; | |
471 | if (pm->flags & I2C_M_RD) | |
472 | cntl |= CNTL_RW; | |
217bcec4 | 473 | |
1da177e4 LT |
474 | loops = (len + 3) / 4; |
475 | for (i = 0; i < loops; ++i, len -= 4){ | |
476 | int count = len > 4 ? 4 : len; | |
477 | u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT); | |
217bcec4 | 478 | |
1da177e4 LT |
479 | if (!(cntl & CNTL_RW)) |
480 | for (j = 0; j < count; ++j) | |
481 | out_8((void __iomem *)&iic->mdbuf, *buf++); | |
217bcec4 | 482 | |
1da177e4 LT |
483 | if (i < loops - 1) |
484 | cmd |= CNTL_CHT; | |
485 | else if (combined_xfer) | |
486 | cmd |= CNTL_RPST; | |
217bcec4 | 487 | |
1da177e4 | 488 | DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd); |
217bcec4 | 489 | |
1da177e4 LT |
490 | /* Start transfer */ |
491 | out_8(&iic->cntl, cmd); | |
217bcec4 | 492 | |
1da177e4 LT |
493 | /* Wait for completion */ |
494 | ret = iic_wait_for_tc(dev); | |
495 | ||
496 | if (unlikely(ret < 0)) | |
497 | break; | |
498 | else if (unlikely(ret != count)){ | |
25985edc | 499 | DBG("%d: xfer_bytes, requested %d, transferred %d\n", |
1da177e4 | 500 | dev->idx, count, ret); |
217bcec4 | 501 | |
1da177e4 LT |
502 | /* If it's not a last part of xfer, abort it */ |
503 | if (combined_xfer || (i < loops - 1)) | |
504 | iic_abort_xfer(dev); | |
217bcec4 | 505 | |
1da177e4 | 506 | ret = -EREMOTEIO; |
217bcec4 | 507 | break; |
1da177e4 | 508 | } |
217bcec4 | 509 | |
1da177e4 LT |
510 | if (cntl & CNTL_RW) |
511 | for (j = 0; j < count; ++j) | |
512 | *buf++ = in_8((void __iomem *)&iic->mdbuf); | |
513 | } | |
217bcec4 | 514 | |
1da177e4 LT |
515 | return ret > 0 ? 0 : ret; |
516 | } | |
517 | ||
518 | /* | |
519 | * Set target slave address for master transfer | |
520 | */ | |
521 | static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg) | |
522 | { | |
523 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
524 | u16 addr = msg->addr; | |
217bcec4 SR |
525 | |
526 | DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx, | |
1da177e4 | 527 | addr, msg->flags & I2C_M_TEN ? 10 : 7); |
217bcec4 | 528 | |
1da177e4 LT |
529 | if (msg->flags & I2C_M_TEN){ |
530 | out_8(&iic->cntl, CNTL_AMD); | |
531 | out_8(&iic->lmadr, addr); | |
532 | out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06)); | |
533 | } | |
534 | else { | |
535 | out_8(&iic->cntl, 0); | |
536 | out_8(&iic->lmadr, addr << 1); | |
537 | } | |
538 | } | |
539 | ||
540 | static inline int iic_invalid_address(const struct i2c_msg* p) | |
541 | { | |
542 | return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f)); | |
543 | } | |
544 | ||
217bcec4 | 545 | static inline int iic_address_neq(const struct i2c_msg* p1, |
1da177e4 LT |
546 | const struct i2c_msg* p2) |
547 | { | |
217bcec4 | 548 | return (p1->addr != p2->addr) |
1da177e4 | 549 | || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN)); |
217bcec4 | 550 | } |
1da177e4 LT |
551 | |
552 | /* | |
217bcec4 | 553 | * Generic master transfer entrypoint. |
1da177e4 LT |
554 | * Returns the number of processed messages or error (<0) |
555 | */ | |
556 | static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) | |
557 | { | |
558 | struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap)); | |
559 | volatile struct iic_regs __iomem *iic = dev->vaddr; | |
560 | int i, ret = 0; | |
217bcec4 | 561 | |
1da177e4 | 562 | DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num); |
217bcec4 | 563 | |
1da177e4 LT |
564 | if (!num) |
565 | return 0; | |
217bcec4 | 566 | |
1da177e4 LT |
567 | /* Check the sanity of the passed messages. |
568 | * Uhh, generic i2c layer is more suitable place for such code... | |
569 | */ | |
570 | if (unlikely(iic_invalid_address(&msgs[0]))){ | |
217bcec4 | 571 | DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx, |
1da177e4 LT |
572 | msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7); |
573 | return -EINVAL; | |
217bcec4 | 574 | } |
1da177e4 LT |
575 | for (i = 0; i < num; ++i){ |
576 | if (unlikely(msgs[i].len <= 0)){ | |
577 | if (num == 1 && !msgs[0].len){ | |
578 | /* Special case for I2C_SMBUS_QUICK emulation. | |
579 | * IBM IIC doesn't support 0-length transactions | |
580 | * so we have to emulate them using bit-banging. | |
581 | */ | |
582 | return iic_smbus_quick(dev, &msgs[0]); | |
583 | } | |
217bcec4 | 584 | DBG("%d: invalid len %d in msg[%d]\n", dev->idx, |
1da177e4 LT |
585 | msgs[i].len, i); |
586 | return -EINVAL; | |
587 | } | |
588 | if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){ | |
589 | DBG("%d: invalid addr in msg[%d]\n", dev->idx, i); | |
590 | return -EINVAL; | |
591 | } | |
592 | } | |
217bcec4 | 593 | |
1da177e4 LT |
594 | /* Check bus state */ |
595 | if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){ | |
596 | DBG("%d: iic_xfer, bus is not free\n", dev->idx); | |
217bcec4 | 597 | |
25985edc | 598 | /* Usually it means something serious has happened. |
1da177e4 LT |
599 | * We *cannot* have unfinished previous transfer |
600 | * so it doesn't make any sense to try to stop it. | |
217bcec4 | 601 | * Probably we were not able to recover from the |
1da177e4 LT |
602 | * previous error. |
603 | * The only *reasonable* thing I can think of here | |
604 | * is soft reset. --ebs | |
605 | */ | |
606 | iic_dev_reset(dev); | |
217bcec4 | 607 | |
1da177e4 LT |
608 | if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){ |
609 | DBG("%d: iic_xfer, bus is still not free\n", dev->idx); | |
610 | return -EREMOTEIO; | |
611 | } | |
217bcec4 | 612 | } |
1da177e4 LT |
613 | else { |
614 | /* Flush master data buffer (just in case) */ | |
615 | out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB); | |
616 | } | |
217bcec4 | 617 | |
1da177e4 LT |
618 | /* Load slave address */ |
619 | iic_address(dev, &msgs[0]); | |
217bcec4 | 620 | |
1da177e4 LT |
621 | /* Do real transfer */ |
622 | for (i = 0; i < num && !ret; ++i) | |
623 | ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1); | |
624 | ||
625 | return ret < 0 ? ret : num; | |
626 | } | |
627 | ||
628 | static u32 iic_func(struct i2c_adapter *adap) | |
629 | { | |
630 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR; | |
631 | } | |
632 | ||
8f9082c5 | 633 | static const struct i2c_algorithm iic_algo = { |
1da177e4 LT |
634 | .master_xfer = iic_xfer, |
635 | .functionality = iic_func | |
636 | }; | |
637 | ||
638 | /* | |
639 | * Calculates IICx_CLCKDIV value for a specific OPB clock frequency | |
640 | */ | |
641 | static inline u8 iic_clckdiv(unsigned int opb) | |
642 | { | |
643 | /* Compatibility kludge, should go away after all cards | |
644 | * are fixed to fill correct value for opbfreq. | |
645 | * Previous driver version used hardcoded divider value 4, | |
646 | * it corresponds to OPB frequency from the range (40, 50] MHz | |
647 | */ | |
648 | if (!opb){ | |
649 | printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq," | |
650 | " fix your board specific setup\n"); | |
651 | opb = 50000000; | |
652 | } | |
653 | ||
654 | /* Convert to MHz */ | |
655 | opb /= 1000000; | |
217bcec4 | 656 | |
1da177e4 | 657 | if (opb < 20 || opb > 150){ |
681aae82 | 658 | printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n", |
1da177e4 LT |
659 | opb); |
660 | opb = opb < 20 ? 20 : 150; | |
661 | } | |
662 | return (u8)((opb + 9) / 10 - 1); | |
663 | } | |
664 | ||
0b255e92 | 665 | static int iic_request_irq(struct platform_device *ofdev, |
838349b5 SM |
666 | struct ibm_iic_private *dev) |
667 | { | |
61c7a080 | 668 | struct device_node *np = ofdev->dev.of_node; |
838349b5 SM |
669 | int irq; |
670 | ||
671 | if (iic_force_poll) | |
f0ec9e20 | 672 | return 0; |
838349b5 SM |
673 | |
674 | irq = irq_of_parse_and_map(np, 0); | |
f0ec9e20 | 675 | if (!irq) { |
838349b5 | 676 | dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n"); |
f0ec9e20 | 677 | return 0; |
838349b5 SM |
678 | } |
679 | ||
680 | /* Disable interrupts until we finish initialization, assumes | |
681 | * level-sensitive IRQ setup... | |
682 | */ | |
683 | iic_interrupt_mode(dev, 0); | |
684 | if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) { | |
685 | dev_err(&ofdev->dev, "request_irq %d failed\n", irq); | |
686 | /* Fallback to the polling mode */ | |
f0ec9e20 | 687 | return 0; |
838349b5 SM |
688 | } |
689 | ||
690 | return irq; | |
691 | } | |
692 | ||
693 | /* | |
694 | * Register single IIC interface | |
695 | */ | |
0b255e92 | 696 | static int iic_probe(struct platform_device *ofdev) |
838349b5 | 697 | { |
61c7a080 | 698 | struct device_node *np = ofdev->dev.of_node; |
838349b5 SM |
699 | struct ibm_iic_private *dev; |
700 | struct i2c_adapter *adap; | |
b1204e6e | 701 | const u32 *freq; |
838349b5 SM |
702 | int ret; |
703 | ||
704 | dev = kzalloc(sizeof(*dev), GFP_KERNEL); | |
705 | if (!dev) { | |
706 | dev_err(&ofdev->dev, "failed to allocate device data\n"); | |
707 | return -ENOMEM; | |
708 | } | |
709 | ||
c2c64954 | 710 | platform_set_drvdata(ofdev, dev); |
838349b5 | 711 | |
838349b5 SM |
712 | dev->vaddr = of_iomap(np, 0); |
713 | if (dev->vaddr == NULL) { | |
714 | dev_err(&ofdev->dev, "failed to iomap device\n"); | |
715 | ret = -ENXIO; | |
716 | goto error_cleanup; | |
717 | } | |
718 | ||
719 | init_waitqueue_head(&dev->wq); | |
720 | ||
721 | dev->irq = iic_request_irq(ofdev, dev); | |
f0ec9e20 | 722 | if (!dev->irq) |
838349b5 SM |
723 | dev_warn(&ofdev->dev, "using polling mode\n"); |
724 | ||
725 | /* Board specific settings */ | |
726 | if (iic_force_fast || of_get_property(np, "fast-mode", NULL)) | |
727 | dev->fast_mode = 1; | |
728 | ||
729 | freq = of_get_property(np, "clock-frequency", NULL); | |
730 | if (freq == NULL) { | |
731 | freq = of_get_property(np->parent, "clock-frequency", NULL); | |
732 | if (freq == NULL) { | |
733 | dev_err(&ofdev->dev, "Unable to get bus frequency\n"); | |
734 | ret = -EINVAL; | |
735 | goto error_cleanup; | |
736 | } | |
737 | } | |
738 | ||
739 | dev->clckdiv = iic_clckdiv(*freq); | |
740 | dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv); | |
741 | ||
742 | /* Initialize IIC interface */ | |
743 | iic_dev_init(dev); | |
744 | ||
745 | /* Register it with i2c layer */ | |
746 | adap = &dev->adap; | |
747 | adap->dev.parent = &ofdev->dev; | |
9fd04992 | 748 | adap->dev.of_node = of_node_get(np); |
838349b5 SM |
749 | strlcpy(adap->name, "IBM IIC", sizeof(adap->name)); |
750 | i2c_set_adapdata(adap, dev); | |
3401b2ff | 751 | adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; |
838349b5 | 752 | adap->algo = &iic_algo; |
8a52c6b4 | 753 | adap->timeout = HZ; |
838349b5 | 754 | |
b1204e6e | 755 | ret = i2c_add_adapter(adap); |
ea734404 | 756 | if (ret < 0) |
838349b5 | 757 | goto error_cleanup; |
838349b5 SM |
758 | |
759 | dev_info(&ofdev->dev, "using %s mode\n", | |
760 | dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)"); | |
761 | ||
762 | return 0; | |
763 | ||
764 | error_cleanup: | |
f0ec9e20 | 765 | if (dev->irq) { |
838349b5 SM |
766 | iic_interrupt_mode(dev, 0); |
767 | free_irq(dev->irq, dev); | |
768 | } | |
769 | ||
770 | if (dev->vaddr) | |
771 | iounmap(dev->vaddr); | |
772 | ||
838349b5 SM |
773 | kfree(dev); |
774 | return ret; | |
775 | } | |
776 | ||
777 | /* | |
778 | * Cleanup initialized IIC interface | |
779 | */ | |
0b255e92 | 780 | static int iic_remove(struct platform_device *ofdev) |
838349b5 | 781 | { |
c2c64954 | 782 | struct ibm_iic_private *dev = platform_get_drvdata(ofdev); |
838349b5 | 783 | |
838349b5 SM |
784 | i2c_del_adapter(&dev->adap); |
785 | ||
f0ec9e20 | 786 | if (dev->irq) { |
838349b5 SM |
787 | iic_interrupt_mode(dev, 0); |
788 | free_irq(dev->irq, dev); | |
789 | } | |
790 | ||
791 | iounmap(dev->vaddr); | |
792 | kfree(dev); | |
793 | ||
794 | return 0; | |
795 | } | |
796 | ||
797 | static const struct of_device_id ibm_iic_match[] = { | |
d3dc685e | 798 | { .compatible = "ibm,iic", }, |
838349b5 SM |
799 | {} |
800 | }; | |
d695e22a | 801 | MODULE_DEVICE_TABLE(of, ibm_iic_match); |
838349b5 | 802 | |
1c48a5c9 | 803 | static struct platform_driver ibm_iic_driver = { |
4018294b GL |
804 | .driver = { |
805 | .name = "ibm-iic", | |
4018294b GL |
806 | .of_match_table = ibm_iic_match, |
807 | }, | |
838349b5 | 808 | .probe = iic_probe, |
0b255e92 | 809 | .remove = iic_remove, |
838349b5 SM |
810 | }; |
811 | ||
a3664b51 | 812 | module_platform_driver(ibm_iic_driver); |