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KVM: Trivial: Avoid hardware_disable predeclaration
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / svm.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
e495606d
AK		 17#include "kvm_svm.h"
18#include "x86_emulate.h"
19
6aa8b732 20#include <linux/module.h>
9d8f549d 21#include <linux/kernel.h>
6aa8b732
AK		 22#include <linux/vmalloc.h>
23#include <linux/highmem.h>
07031e14 24#include <linux/profile.h>
e8edc6e0 25#include <linux/sched.h>
6aa8b732 26
e495606d 27#include <asm/desc.h>
6aa8b732
AK		 28
29MODULE_AUTHOR("Qumranet");
30MODULE_LICENSE("GPL");
31
32#define IOPM_ALLOC_ORDER 2
33#define MSRPM_ALLOC_ORDER 1
34
35#define DB_VECTOR 1
36#define UD_VECTOR 6
37#define GP_VECTOR 13
38
39#define DR7_GD_MASK (1 << 13)
40#define DR6_BD_MASK (1 << 13)
41#define CR4_DE_MASK (1UL << 3)
42
43#define SEG_TYPE_LDT 2
44#define SEG_TYPE_BUSY_TSS16 3
45
46#define KVM_EFER_LMA (1 << 10)
47#define KVM_EFER_LME (1 << 8)
48
80b7706e
JR		 49#define SVM_FEATURE_NPT (1 << 0)
50#define SVM_FEATURE_LBRV (1 << 1)
51#define SVM_DEATURE_SVML (1 << 2)
52
6aa8b732
AK		 53unsigned long iopm_base;
54unsigned long msrpm_base;
55
56struct kvm_ldttss_desc {
57 u16 limit0;
58 u16 base0;
59 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
60 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
61 u32 base3;
62 u32 zero1;
63} __attribute__((packed));
64
65struct svm_cpu_data {
66 int cpu;
67
5008fdf5
AK		 68 u64 asid_generation;
69 u32 max_asid;
70 u32 next_asid;
6aa8b732
AK		 71 struct kvm_ldttss_desc *tss_desc;
72
73 struct page *save_area;
74};
75
76static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
80b7706e 77static uint32_t svm_features;
6aa8b732
AK		 78
79struct svm_init_data {
80 int cpu;
81 int r;
82};
83
84static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
85
9d8f549d 86#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
6aa8b732
AK		 87#define MSRS_RANGE_SIZE 2048
88#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
89
90#define MAX_INST_SIZE 15
91
80b7706e
JR		 92static inline u32 svm_has(u32 feat)
93{
94 return svm_features & feat;
95}
96
6aa8b732
AK		 97static unsigned get_addr_size(struct kvm_vcpu *vcpu)
98{
99 struct vmcb_save_area *sa = &vcpu->svm->vmcb->save;
100 u16 cs_attrib;
101
102 if (!(sa->cr0 & CR0_PE_MASK) || (sa->rflags & X86_EFLAGS_VM))
103 return 2;
104
105 cs_attrib = sa->cs.attrib;
106
107 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
108 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
109}
110
111static inline u8 pop_irq(struct kvm_vcpu *vcpu)
112{
113 int word_index = __ffs(vcpu->irq_summary);
114 int bit_index = __ffs(vcpu->irq_pending[word_index]);
115 int irq = word_index * BITS_PER_LONG + bit_index;
116
117 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
118 if (!vcpu->irq_pending[word_index])
119 clear_bit(word_index, &vcpu->irq_summary);
120 return irq;
121}
122
123static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
124{
125 set_bit(irq, vcpu->irq_pending);
126 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
127}
128
129static inline void clgi(void)
130{
131 asm volatile (SVM_CLGI);
132}
133
134static inline void stgi(void)
135{
136 asm volatile (SVM_STGI);
137}
138
139static inline void invlpga(unsigned long addr, u32 asid)
140{
141 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
142}
143
144static inline unsigned long kvm_read_cr2(void)
145{
146 unsigned long cr2;
147
148 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
149 return cr2;
150}
151
152static inline void kvm_write_cr2(unsigned long val)
153{
154 asm volatile ("mov %0, %%cr2" :: "r" (val));
155}
156
157static inline unsigned long read_dr6(void)
158{
159 unsigned long dr6;
160
161 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
162 return dr6;
163}
164
165static inline void write_dr6(unsigned long val)
166{
167 asm volatile ("mov %0, %%dr6" :: "r" (val));
168}
169
170static inline unsigned long read_dr7(void)
171{
172 unsigned long dr7;
173
174 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
175 return dr7;
176}
177
178static inline void write_dr7(unsigned long val)
179{
180 asm volatile ("mov %0, %%dr7" :: "r" (val));
181}
182
6aa8b732
AK		 183static inline void force_new_asid(struct kvm_vcpu *vcpu)
184{
185 vcpu->svm->asid_generation--;
186}
187
188static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
189{
190 force_new_asid(vcpu);
191}
192
193static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
194{
195 if (!(efer & KVM_EFER_LMA))
196 efer &= ~KVM_EFER_LME;
197
198 vcpu->svm->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
199 vcpu->shadow_efer = efer;
200}
201
202static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
203{
204 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
205 SVM_EVTINJ_VALID_ERR |
206 SVM_EVTINJ_TYPE_EXEPT |
207 GP_VECTOR;
208 vcpu->svm->vmcb->control.event_inj_err = error_code;
209}
210
211static void inject_ud(struct kvm_vcpu *vcpu)
212{
213 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
214 SVM_EVTINJ_TYPE_EXEPT |
215 UD_VECTOR;
216}
217
6aa8b732
AK		 218static int is_page_fault(uint32_t info)
219{
220 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
221 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
222}
223
224static int is_external_interrupt(u32 info)
225{
226 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
228}
229
230static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
231{
232 if (!vcpu->svm->next_rip) {
233 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
234 return;
235 }
236 if (vcpu->svm->next_rip - vcpu->svm->vmcb->save.rip > 15) {
237 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
238 __FUNCTION__,
239 vcpu->svm->vmcb->save.rip,
240 vcpu->svm->next_rip);
241 }
242
243 vcpu->rip = vcpu->svm->vmcb->save.rip = vcpu->svm->next_rip;
244 vcpu->svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
c1150d8c
DL		 245
246 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 247}
248
249static int has_svm(void)
250{
251 uint32_t eax, ebx, ecx, edx;
252
1e885461 253 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
6aa8b732
AK		 254 printk(KERN_INFO "has_svm: not amd\n");
255 return 0;
256 }
257
258 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
259 if (eax < SVM_CPUID_FUNC) {
260 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
261 return 0;
262 }
263
264 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
265 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
266 printk(KERN_DEBUG "has_svm: svm not available\n");
267 return 0;
268 }
269 return 1;
270}
271
272static void svm_hardware_disable(void *garbage)
273{
274 struct svm_cpu_data *svm_data
275 = per_cpu(svm_data, raw_smp_processor_id());
276
277 if (svm_data) {
278 uint64_t efer;
279
280 wrmsrl(MSR_VM_HSAVE_PA, 0);
281 rdmsrl(MSR_EFER, efer);
282 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
8b6d44c7 283 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
6aa8b732
AK		 284 __free_page(svm_data->save_area);
285 kfree(svm_data);
286 }
287}
288
289static void svm_hardware_enable(void *garbage)
290{
291
292 struct svm_cpu_data *svm_data;
293 uint64_t efer;
05b3e0c2 294#ifdef CONFIG_X86_64
6aa8b732
AK		 295 struct desc_ptr gdt_descr;
296#else
297 struct Xgt_desc_struct gdt_descr;
298#endif
299 struct desc_struct *gdt;
300 int me = raw_smp_processor_id();
301
302 if (!has_svm()) {
303 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
304 return;
305 }
306 svm_data = per_cpu(svm_data, me);
307
308 if (!svm_data) {
309 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
310 me);
311 return;
312 }
313
314 svm_data->asid_generation = 1;
315 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
316 svm_data->next_asid = svm_data->max_asid + 1;
80b7706e 317 svm_features = cpuid_edx(SVM_CPUID_FUNC);
6aa8b732
AK		 318
319 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
320 gdt = (struct desc_struct *)gdt_descr.address;
321 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
322
323 rdmsrl(MSR_EFER, efer);
324 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
325
326 wrmsrl(MSR_VM_HSAVE_PA,
327 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
328}
329
330static int svm_cpu_init(int cpu)
331{
332 struct svm_cpu_data *svm_data;
333 int r;
334
335 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
336 if (!svm_data)
337 return -ENOMEM;
338 svm_data->cpu = cpu;
339 svm_data->save_area = alloc_page(GFP_KERNEL);
340 r = -ENOMEM;
341 if (!svm_data->save_area)
342 goto err_1;
343
344 per_cpu(svm_data, cpu) = svm_data;
345
346 return 0;
347
348err_1:
349 kfree(svm_data);
350 return r;
351
352}
353
354static int set_msr_interception(u32 *msrpm, unsigned msr,
355 int read, int write)
356{
357 int i;
358
359 for (i = 0; i < NUM_MSR_MAPS; i++) {
360 if (msr >= msrpm_ranges[i] &&
361 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
362 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
363 msrpm_ranges[i]) * 2;
364
365 u32 *base = msrpm + (msr_offset / 32);
366 u32 msr_shift = msr_offset % 32;
367 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
368 *base = (*base & ~(0x3 << msr_shift)) |
369 (mask << msr_shift);
370 return 1;
371 }
372 }
373 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
374 return 0;
375}
376
377static __init int svm_hardware_setup(void)
378{
379 int cpu;
380 struct page *iopm_pages;
381 struct page *msrpm_pages;
c8681339 382 void *iopm_va, *msrpm_va;
6aa8b732
AK		 383 int r;
384
873a7c42 385 kvm_emulator_want_group7_invlpg();
6aa8b732
AK		 386
387 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
388
389 if (!iopm_pages)
390 return -ENOMEM;
c8681339
AL		 391
392 iopm_va = page_address(iopm_pages);
393 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
394 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
6aa8b732
AK		 395 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
396
397
398 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
399
400 r = -ENOMEM;
401 if (!msrpm_pages)
402 goto err_1;
403
404 msrpm_va = page_address(msrpm_pages);
405 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
406 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
407
05b3e0c2 408#ifdef CONFIG_X86_64
6aa8b732
AK		 409 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
410 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
411 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
6aa8b732
AK		 412 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
413 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
414 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
415#endif
0e859cac 416 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
6aa8b732
AK		 417 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
418 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
419 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
420
421 for_each_online_cpu(cpu) {
422 r = svm_cpu_init(cpu);
423 if (r)
424 goto err_2;
425 }
426 return 0;
427
428err_2:
429 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
430 msrpm_base = 0;
431err_1:
432 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
433 iopm_base = 0;
434 return r;
435}
436
437static __exit void svm_hardware_unsetup(void)
438{
439 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
440 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
441 iopm_base = msrpm_base = 0;
442}
443
444static void init_seg(struct vmcb_seg *seg)
445{
446 seg->selector = 0;
447 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
448 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
449 seg->limit = 0xffff;
450 seg->base = 0;
451}
452
453static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
454{
455 seg->selector = 0;
456 seg->attrib = SVM_SELECTOR_P_MASK | type;
457 seg->limit = 0xffff;
458 seg->base = 0;
459}
460
461static int svm_vcpu_setup(struct kvm_vcpu *vcpu)
462{
463 return 0;
464}
465
466static void init_vmcb(struct vmcb *vmcb)
467{
468 struct vmcb_control_area *control = &vmcb->control;
469 struct vmcb_save_area *save = &vmcb->save;
6aa8b732
AK		 470
471 control->intercept_cr_read = INTERCEPT_CR0_MASK |
472 INTERCEPT_CR3_MASK |
473 INTERCEPT_CR4_MASK;
474
475 control->intercept_cr_write = INTERCEPT_CR0_MASK |
476 INTERCEPT_CR3_MASK |
477 INTERCEPT_CR4_MASK;
478
479 control->intercept_dr_read = INTERCEPT_DR0_MASK |
480 INTERCEPT_DR1_MASK |
481 INTERCEPT_DR2_MASK |
482 INTERCEPT_DR3_MASK;
483
484 control->intercept_dr_write = INTERCEPT_DR0_MASK |
485 INTERCEPT_DR1_MASK |
486 INTERCEPT_DR2_MASK |
487 INTERCEPT_DR3_MASK |
488 INTERCEPT_DR5_MASK |
489 INTERCEPT_DR7_MASK;
490
491 control->intercept_exceptions = 1 << PF_VECTOR;
492
493
494 control->intercept = (1ULL << INTERCEPT_INTR) |
495 (1ULL << INTERCEPT_NMI) |
0152527b 496 (1ULL << INTERCEPT_SMI) |
6aa8b732
AK		 497 /*
498 * selective cr0 intercept bug?
499 * 0: 0f 22 d8 mov %eax,%cr3
500 * 3: 0f 20 c0 mov %cr0,%eax
501 * 6: 0d 00 00 00 80 or $0x80000000,%eax
502 * b: 0f 22 c0 mov %eax,%cr0
503 * set cr3 ->interception
504 * get cr0 ->interception
505 * set cr0 -> no interception
506 */
507 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
508 (1ULL << INTERCEPT_CPUID) |
509 (1ULL << INTERCEPT_HLT) |
6aa8b732
AK		 510 (1ULL << INTERCEPT_INVLPGA) |
511 (1ULL << INTERCEPT_IOIO_PROT) |
512 (1ULL << INTERCEPT_MSR_PROT) |
513 (1ULL << INTERCEPT_TASK_SWITCH) |
46fe4ddd 514 (1ULL << INTERCEPT_SHUTDOWN) |
6aa8b732
AK		 515 (1ULL << INTERCEPT_VMRUN) |
516 (1ULL << INTERCEPT_VMMCALL) |
517 (1ULL << INTERCEPT_VMLOAD) |
518 (1ULL << INTERCEPT_VMSAVE) |
519 (1ULL << INTERCEPT_STGI) |
520 (1ULL << INTERCEPT_CLGI) |
916ce236
JR		 521 (1ULL << INTERCEPT_SKINIT) |
522 (1ULL << INTERCEPT_MONITOR) |
523 (1ULL << INTERCEPT_MWAIT);
6aa8b732
AK		 524
525 control->iopm_base_pa = iopm_base;
526 control->msrpm_base_pa = msrpm_base;
0cc5064d 527 control->tsc_offset = 0;
6aa8b732
AK		 528 control->int_ctl = V_INTR_MASKING_MASK;
529
530 init_seg(&save->es);
531 init_seg(&save->ss);
532 init_seg(&save->ds);
533 init_seg(&save->fs);
534 init_seg(&save->gs);
535
536 save->cs.selector = 0xf000;
537 /* Executable/Readable Code Segment */
538 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
539 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
540 save->cs.limit = 0xffff;
d92899a0
AK		 541 /*
542 * cs.base should really be 0xffff0000, but vmx can't handle that, so
543 * be consistent with it.
544 *
545 * Replace when we have real mode working for vmx.
546 */
547 save->cs.base = 0xf0000;
6aa8b732
AK		 548
549 save->gdtr.limit = 0xffff;
550 save->idtr.limit = 0xffff;
551
552 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
553 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
554
555 save->efer = MSR_EFER_SVME_MASK;
556
557 save->dr6 = 0xffff0ff0;
558 save->dr7 = 0x400;
559 save->rflags = 2;
560 save->rip = 0x0000fff0;
561
562 /*
563 * cr0 val on cpu init should be 0x60000010, we enable cpu
564 * cache by default. the orderly way is to enable cache in bios.
565 */
cd205625 566 save->cr0 = 0x00000010 | CR0_PG_MASK | CR0_WP_MASK;
6aa8b732
AK		 567 save->cr4 = CR4_PAE_MASK;
568 /* rdx = ?? */
569}
570
571static int svm_create_vcpu(struct kvm_vcpu *vcpu)
572{
573 struct page *page;
574 int r;
575
576 r = -ENOMEM;
577 vcpu->svm = kzalloc(sizeof *vcpu->svm, GFP_KERNEL);
578 if (!vcpu->svm)
579 goto out1;
580 page = alloc_page(GFP_KERNEL);
581 if (!page)
582 goto out2;
583
584 vcpu->svm->vmcb = page_address(page);
129ee910 585 clear_page(vcpu->svm->vmcb);
6aa8b732 586 vcpu->svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
6aa8b732
AK		 587 vcpu->svm->asid_generation = 0;
588 memset(vcpu->svm->db_regs, 0, sizeof(vcpu->svm->db_regs));
589 init_vmcb(vcpu->svm->vmcb);
590
36241b8c 591 fx_init(vcpu);
7807fa6c 592 vcpu->fpu_active = 1;
94cea1bb 593 vcpu->apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
dad3795d 594 if (vcpu->vcpu_id == 0)
94cea1bb 595 vcpu->apic_base |= MSR_IA32_APICBASE_BSP;
36241b8c 596
6aa8b732
AK		 597 return 0;
598
599out2:
600 kfree(vcpu->svm);
601out1:
602 return r;
603}
604
605static void svm_free_vcpu(struct kvm_vcpu *vcpu)
606{
607 if (!vcpu->svm)
608 return;
609 if (vcpu->svm->vmcb)
610 __free_page(pfn_to_page(vcpu->svm->vmcb_pa >> PAGE_SHIFT));
611 kfree(vcpu->svm);
612}
613
bccf2150 614static void svm_vcpu_load(struct kvm_vcpu *vcpu)
6aa8b732 615{
94dfbdb3 616 int cpu, i;
0cc5064d
AK		 617
618 cpu = get_cpu();
619 if (unlikely(cpu != vcpu->cpu)) {
620 u64 tsc_this, delta;
621
622 /*
623 * Make sure that the guest sees a monotonically
624 * increasing TSC.
625 */
626 rdtscll(tsc_this);
627 delta = vcpu->host_tsc - tsc_this;
628 vcpu->svm->vmcb->control.tsc_offset += delta;
629 vcpu->cpu = cpu;
630 }
94dfbdb3
AL		 631
632 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
633 rdmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
6aa8b732
AK		 634}
635
636static void svm_vcpu_put(struct kvm_vcpu *vcpu)
637{
94dfbdb3
AL		 638 int i;
639
640 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
641 wrmsrl(host_save_user_msrs[i], vcpu->svm->host_user_msrs[i]);
642
0cc5064d 643 rdtscll(vcpu->host_tsc);
6aa8b732
AK		 644 put_cpu();
645}
646
774c47f1
AK		 647static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
648{
649}
650
6aa8b732
AK		 651static void svm_cache_regs(struct kvm_vcpu *vcpu)
652{
653 vcpu->regs[VCPU_REGS_RAX] = vcpu->svm->vmcb->save.rax;
654 vcpu->regs[VCPU_REGS_RSP] = vcpu->svm->vmcb->save.rsp;
655 vcpu->rip = vcpu->svm->vmcb->save.rip;
656}
657
658static void svm_decache_regs(struct kvm_vcpu *vcpu)
659{
660 vcpu->svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
661 vcpu->svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
662 vcpu->svm->vmcb->save.rip = vcpu->rip;
663}
664
665static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
666{
667 return vcpu->svm->vmcb->save.rflags;
668}
669
670static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
671{
672 vcpu->svm->vmcb->save.rflags = rflags;
673}
674
675static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
676{
677 struct vmcb_save_area *save = &vcpu->svm->vmcb->save;
678
679 switch (seg) {
680 case VCPU_SREG_CS: return &save->cs;
681 case VCPU_SREG_DS: return &save->ds;
682 case VCPU_SREG_ES: return &save->es;
683 case VCPU_SREG_FS: return &save->fs;
684 case VCPU_SREG_GS: return &save->gs;
685 case VCPU_SREG_SS: return &save->ss;
686 case VCPU_SREG_TR: return &save->tr;
687 case VCPU_SREG_LDTR: return &save->ldtr;
688 }
689 BUG();
8b6d44c7 690 return NULL;
6aa8b732
AK		 691}
692
693static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
694{
695 struct vmcb_seg *s = svm_seg(vcpu, seg);
696
697 return s->base;
698}
699
700static void svm_get_segment(struct kvm_vcpu *vcpu,
701 struct kvm_segment *var, int seg)
702{
703 struct vmcb_seg *s = svm_seg(vcpu, seg);
704
705 var->base = s->base;
706 var->limit = s->limit;
707 var->selector = s->selector;
708 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
709 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
710 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
711 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
712 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
713 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
714 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
715 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
716 var->unusable = !var->present;
717}
718
719static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
720{
721 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
722
723 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
724 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
725}
726
727static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
728{
bce66ca4
LN		 729 dt->limit = vcpu->svm->vmcb->save.idtr.limit;
730 dt->base = vcpu->svm->vmcb->save.idtr.base;
6aa8b732
AK		 731}
732
733static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
734{
bce66ca4
LN		 735 vcpu->svm->vmcb->save.idtr.limit = dt->limit;
736 vcpu->svm->vmcb->save.idtr.base = dt->base ;
6aa8b732
AK		 737}
738
739static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
740{
741 dt->limit = vcpu->svm->vmcb->save.gdtr.limit;
742 dt->base = vcpu->svm->vmcb->save.gdtr.base;
743}
744
745static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
746{
747 vcpu->svm->vmcb->save.gdtr.limit = dt->limit;
748 vcpu->svm->vmcb->save.gdtr.base = dt->base ;
749}
750
25c4c276 751static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3
AK		 752{
753}
754
6aa8b732
AK		 755static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
756{
05b3e0c2 757#ifdef CONFIG_X86_64
6aa8b732
AK		 758 if (vcpu->shadow_efer & KVM_EFER_LME) {
759 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK)) {
760 vcpu->shadow_efer |= KVM_EFER_LMA;
761 vcpu->svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
762 }
763
764 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK) ) {
765 vcpu->shadow_efer &= ~KVM_EFER_LMA;
766 vcpu->svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
767 }
768 }
769#endif
7807fa6c
AL		 770 if ((vcpu->cr0 & CR0_TS_MASK) && !(cr0 & CR0_TS_MASK)) {
771 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
772 vcpu->fpu_active = 1;
773 }
774
6aa8b732 775 vcpu->cr0 = cr0;
6da63cf9
AK		 776 cr0 |= CR0_PG_MASK | CR0_WP_MASK;
777 cr0 &= ~(CR0_CD_MASK | CR0_NW_MASK);
778 vcpu->svm->vmcb->save.cr0 = cr0;
6aa8b732
AK		 779}
780
781static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
782{
783 vcpu->cr4 = cr4;
784 vcpu->svm->vmcb->save.cr4 = cr4 | CR4_PAE_MASK;
785}
786
787static void svm_set_segment(struct kvm_vcpu *vcpu,
788 struct kvm_segment *var, int seg)
789{
790 struct vmcb_seg *s = svm_seg(vcpu, seg);
791
792 s->base = var->base;
793 s->limit = var->limit;
794 s->selector = var->selector;
795 if (var->unusable)
796 s->attrib = 0;
797 else {
798 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
799 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
800 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
801 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
802 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
803 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
804 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
805 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
806 }
807 if (seg == VCPU_SREG_CS)
808 vcpu->svm->vmcb->save.cpl
809 = (vcpu->svm->vmcb->save.cs.attrib
810 >> SVM_SELECTOR_DPL_SHIFT) & 3;
811
812}
813
814/* FIXME:
815
816 vcpu->svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
817 vcpu->svm->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
818
819*/
820
821static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
822{
823 return -EOPNOTSUPP;
824}
825
826static void load_host_msrs(struct kvm_vcpu *vcpu)
827{
94dfbdb3
AL		 828#ifdef CONFIG_X86_64
829 wrmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
830#endif
6aa8b732
AK		 831}
832
833static void save_host_msrs(struct kvm_vcpu *vcpu)
834{
94dfbdb3
AL		 835#ifdef CONFIG_X86_64
836 rdmsrl(MSR_GS_BASE, vcpu->svm->host_gs_base);
837#endif
6aa8b732
AK		 838}
839
840static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
841{
842 if (svm_data->next_asid > svm_data->max_asid) {
843 ++svm_data->asid_generation;
844 svm_data->next_asid = 1;
845 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
846 }
847
848 vcpu->cpu = svm_data->cpu;
849 vcpu->svm->asid_generation = svm_data->asid_generation;
850 vcpu->svm->vmcb->control.asid = svm_data->next_asid++;
851}
852
853static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
854{
855 invlpga(address, vcpu->svm->vmcb->control.asid); // is needed?
856}
857
858static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
859{
860 return vcpu->svm->db_regs[dr];
861}
862
863static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
864 int *exception)
865{
866 *exception = 0;
867
868 if (vcpu->svm->vmcb->save.dr7 & DR7_GD_MASK) {
869 vcpu->svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
870 vcpu->svm->vmcb->save.dr6 |= DR6_BD_MASK;
871 *exception = DB_VECTOR;
872 return;
873 }
874
875 switch (dr) {
876 case 0 ... 3:
877 vcpu->svm->db_regs[dr] = value;
878 return;
879 case 4 ... 5:
880 if (vcpu->cr4 & CR4_DE_MASK) {
881 *exception = UD_VECTOR;
882 return;
883 }
884 case 7: {
885 if (value & ~((1ULL << 32) - 1)) {
886 *exception = GP_VECTOR;
887 return;
888 }
889 vcpu->svm->vmcb->save.dr7 = value;
890 return;
891 }
892 default:
893 printk(KERN_DEBUG "%s: unexpected dr %u\n",
894 __FUNCTION__, dr);
895 *exception = UD_VECTOR;
896 return;
897 }
898}
899
900static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
901{
902 u32 exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
903 u64 fault_address;
904 u32 error_code;
905 enum emulation_result er;
e2dec939 906 int r;
6aa8b732
AK		 907
908 if (is_external_interrupt(exit_int_info))
909 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
910
911 spin_lock(&vcpu->kvm->lock);
912
913 fault_address = vcpu->svm->vmcb->control.exit_info_2;
914 error_code = vcpu->svm->vmcb->control.exit_info_1;
e2dec939
AK		 915 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
916 if (r < 0) {
917 spin_unlock(&vcpu->kvm->lock);
918 return r;
919 }
920 if (!r) {
6aa8b732
AK		 921 spin_unlock(&vcpu->kvm->lock);
922 return 1;
923 }
924 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
925 spin_unlock(&vcpu->kvm->lock);
926
927 switch (er) {
928 case EMULATE_DONE:
929 return 1;
930 case EMULATE_DO_MMIO:
1165f5fe 931 ++vcpu->stat.mmio_exits;
6aa8b732
AK		 932 kvm_run->exit_reason = KVM_EXIT_MMIO;
933 return 0;
934 case EMULATE_FAIL:
935 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
936 break;
937 default:
938 BUG();
939 }
940
941 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
942 return 0;
943}
944
7807fa6c
AL		 945static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
946{
947 vcpu->svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
948 if (!(vcpu->cr0 & CR0_TS_MASK))
949 vcpu->svm->vmcb->save.cr0 &= ~CR0_TS_MASK;
950 vcpu->fpu_active = 1;
951
952 return 1;
953}
954
46fe4ddd
JR		 955static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
956{
957 /*
958 * VMCB is undefined after a SHUTDOWN intercept
959 * so reinitialize it.
960 */
129ee910 961 clear_page(vcpu->svm->vmcb);
46fe4ddd
JR		 962 init_vmcb(vcpu->svm->vmcb);
963
964 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
965 return 0;
966}
967
6aa8b732
AK		 968static int io_get_override(struct kvm_vcpu *vcpu,
969 struct vmcb_seg **seg,
970 int *addr_override)
971{
972 u8 inst[MAX_INST_SIZE];
973 unsigned ins_length;
974 gva_t rip;
975 int i;
976
977 rip = vcpu->svm->vmcb->save.rip;
978 ins_length = vcpu->svm->next_rip - rip;
979 rip += vcpu->svm->vmcb->save.cs.base;
980
981 if (ins_length > MAX_INST_SIZE)
982 printk(KERN_DEBUG
983 "%s: inst length err, cs base 0x%llx rip 0x%llx "
984 "next rip 0x%llx ins_length %u\n",
985 __FUNCTION__,
986 vcpu->svm->vmcb->save.cs.base,
987 vcpu->svm->vmcb->save.rip,
988 vcpu->svm->vmcb->control.exit_info_2,
989 ins_length);
990
991 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
992 /* #PF */
993 return 0;
994
995 *addr_override = 0;
8b6d44c7 996 *seg = NULL;
6aa8b732
AK		 997 for (i = 0; i < ins_length; i++)
998 switch (inst[i]) {
999 case 0xf0:
1000 case 0xf2:
1001 case 0xf3:
1002 case 0x66:
1003 continue;
1004 case 0x67:
1005 *addr_override = 1;
1006 continue;
1007 case 0x2e:
1008 *seg = &vcpu->svm->vmcb->save.cs;
1009 continue;
1010 case 0x36:
1011 *seg = &vcpu->svm->vmcb->save.ss;
1012 continue;
1013 case 0x3e:
1014 *seg = &vcpu->svm->vmcb->save.ds;
1015 continue;
1016 case 0x26:
1017 *seg = &vcpu->svm->vmcb->save.es;
1018 continue;
1019 case 0x64:
1020 *seg = &vcpu->svm->vmcb->save.fs;
1021 continue;
1022 case 0x65:
1023 *seg = &vcpu->svm->vmcb->save.gs;
1024 continue;
1025 default:
1026 return 1;
1027 }
1028 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
1029 return 0;
1030}
1031
039576c0 1032static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address)
6aa8b732
AK		 1033{
1034 unsigned long addr_mask;
1035 unsigned long *reg;
1036 struct vmcb_seg *seg;
1037 int addr_override;
1038 struct vmcb_save_area *save_area = &vcpu->svm->vmcb->save;
1039 u16 cs_attrib = save_area->cs.attrib;
1040 unsigned addr_size = get_addr_size(vcpu);
1041
1042 if (!io_get_override(vcpu, &seg, &addr_override))
1043 return 0;
1044
1045 if (addr_override)
1046 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
1047
1048 if (ins) {
1049 reg = &vcpu->regs[VCPU_REGS_RDI];
1050 seg = &vcpu->svm->vmcb->save.es;
1051 } else {
1052 reg = &vcpu->regs[VCPU_REGS_RSI];
1053 seg = (seg) ? seg : &vcpu->svm->vmcb->save.ds;
1054 }
1055
1056 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1057
1058 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1059 !(vcpu->svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1060 *address = (*reg & addr_mask);
1061 return addr_mask;
1062 }
1063
1064 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1065 svm_inject_gp(vcpu, 0);
1066 return 0;
1067 }
1068
1069 *address = (*reg & addr_mask) + seg->base;
1070 return addr_mask;
1071}
1072
1073static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1074{
1075 u32 io_info = vcpu->svm->vmcb->control.exit_info_1; //address size bug?
039576c0
AK		 1076 int size, down, in, string, rep;
1077 unsigned port;
1078 unsigned long count;
1079 gva_t address = 0;
6aa8b732 1080
1165f5fe 1081 ++vcpu->stat.io_exits;
6aa8b732
AK		 1082
1083 vcpu->svm->next_rip = vcpu->svm->vmcb->control.exit_info_2;
1084
039576c0
AK		 1085 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1086 port = io_info >> 16;
1087 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1088 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1089 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1090 count = 1;
1091 down = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
6aa8b732 1092
039576c0 1093 if (string) {
6aa8b732
AK		 1094 unsigned addr_mask;
1095
039576c0 1096 addr_mask = io_adress(vcpu, in, &address);
6aa8b732 1097 if (!addr_mask) {
d27d4aca
AK		 1098 printk(KERN_DEBUG "%s: get io address failed\n",
1099 __FUNCTION__);
6aa8b732
AK		 1100 return 1;
1101 }
1102
039576c0
AK		 1103 if (rep)
1104 count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1105 }
1106 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1107 address, rep, port);
6aa8b732
AK		 1108}
1109
6aa8b732
AK		 1110static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1111{
1112 return 1;
1113}
1114
1115static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1116{
1117 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 1;
1118 skip_emulated_instruction(vcpu);
d3bef15f 1119 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 1120}
1121
02e235bc
AK		 1122static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1123{
510043da
DL		 1124 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 3;
1125 skip_emulated_instruction(vcpu);
270fd9b9 1126 return kvm_hypercall(vcpu, kvm_run);
02e235bc
AK		 1127}
1128
6aa8b732
AK		 1129static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1130{
1131 inject_ud(vcpu);
1132 return 1;
1133}
1134
1135static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1136{
1137 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1138 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1139 return 0;
1140}
1141
1142static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1143{
1144 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
06465c5a
AK		 1145 kvm_emulate_cpuid(vcpu);
1146 return 1;
6aa8b732
AK		 1147}
1148
1149static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1150{
8b6d44c7 1151 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
6aa8b732
AK		 1152 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1153 return 1;
1154}
1155
1156static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1157{
1158 switch (ecx) {
6aa8b732
AK		 1159 case MSR_IA32_TIME_STAMP_COUNTER: {
1160 u64 tsc;
1161
1162 rdtscll(tsc);
1163 *data = vcpu->svm->vmcb->control.tsc_offset + tsc;
1164 break;
1165 }
0e859cac 1166 case MSR_K6_STAR:
6aa8b732
AK		 1167 *data = vcpu->svm->vmcb->save.star;
1168 break;
0e859cac 1169#ifdef CONFIG_X86_64
6aa8b732
AK		 1170 case MSR_LSTAR:
1171 *data = vcpu->svm->vmcb->save.lstar;
1172 break;
1173 case MSR_CSTAR:
1174 *data = vcpu->svm->vmcb->save.cstar;
1175 break;
1176 case MSR_KERNEL_GS_BASE:
1177 *data = vcpu->svm->vmcb->save.kernel_gs_base;
1178 break;
1179 case MSR_SYSCALL_MASK:
1180 *data = vcpu->svm->vmcb->save.sfmask;
1181 break;
1182#endif
1183 case MSR_IA32_SYSENTER_CS:
1184 *data = vcpu->svm->vmcb->save.sysenter_cs;
1185 break;
1186 case MSR_IA32_SYSENTER_EIP:
1187 *data = vcpu->svm->vmcb->save.sysenter_eip;
1188 break;
1189 case MSR_IA32_SYSENTER_ESP:
1190 *data = vcpu->svm->vmcb->save.sysenter_esp;
1191 break;
1192 default:
3bab1f5d 1193 return kvm_get_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1194 }
1195 return 0;
1196}
1197
1198static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1199{
1200 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1201 u64 data;
1202
1203 if (svm_get_msr(vcpu, ecx, &data))
1204 svm_inject_gp(vcpu, 0);
1205 else {
1206 vcpu->svm->vmcb->save.rax = data & 0xffffffff;
1207 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1208 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1209 skip_emulated_instruction(vcpu);
1210 }
1211 return 1;
1212}
1213
1214static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1215{
1216 switch (ecx) {
6aa8b732
AK		 1217 case MSR_IA32_TIME_STAMP_COUNTER: {
1218 u64 tsc;
1219
1220 rdtscll(tsc);
1221 vcpu->svm->vmcb->control.tsc_offset = data - tsc;
1222 break;
1223 }
0e859cac 1224 case MSR_K6_STAR:
6aa8b732
AK		 1225 vcpu->svm->vmcb->save.star = data;
1226 break;
49b14f24 1227#ifdef CONFIG_X86_64
6aa8b732
AK		 1228 case MSR_LSTAR:
1229 vcpu->svm->vmcb->save.lstar = data;
1230 break;
1231 case MSR_CSTAR:
1232 vcpu->svm->vmcb->save.cstar = data;
1233 break;
1234 case MSR_KERNEL_GS_BASE:
1235 vcpu->svm->vmcb->save.kernel_gs_base = data;
1236 break;
1237 case MSR_SYSCALL_MASK:
1238 vcpu->svm->vmcb->save.sfmask = data;
1239 break;
1240#endif
1241 case MSR_IA32_SYSENTER_CS:
1242 vcpu->svm->vmcb->save.sysenter_cs = data;
1243 break;
1244 case MSR_IA32_SYSENTER_EIP:
1245 vcpu->svm->vmcb->save.sysenter_eip = data;
1246 break;
1247 case MSR_IA32_SYSENTER_ESP:
1248 vcpu->svm->vmcb->save.sysenter_esp = data;
1249 break;
1250 default:
3bab1f5d 1251 return kvm_set_msr_common(vcpu, ecx, data);
6aa8b732
AK		 1252 }
1253 return 0;
1254}
1255
1256static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1257{
1258 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1259 u64 data = (vcpu->svm->vmcb->save.rax & -1u)
1260 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1261 vcpu->svm->next_rip = vcpu->svm->vmcb->save.rip + 2;
1262 if (svm_set_msr(vcpu, ecx, data))
1263 svm_inject_gp(vcpu, 0);
1264 else
1265 skip_emulated_instruction(vcpu);
1266 return 1;
1267}
1268
1269static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1270{
1271 if (vcpu->svm->vmcb->control.exit_info_1)
1272 return wrmsr_interception(vcpu, kvm_run);
1273 else
1274 return rdmsr_interception(vcpu, kvm_run);
1275}
1276
c1150d8c
DL		 1277static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1278 struct kvm_run *kvm_run)
1279{
1280 /*
1281 * If the user space waits to inject interrupts, exit as soon as
1282 * possible
1283 */
1284 if (kvm_run->request_interrupt_window &&
022a9308 1285 !vcpu->irq_summary) {
1165f5fe 1286 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 1287 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1288 return 0;
1289 }
1290
1291 return 1;
1292}
1293
6aa8b732
AK		 1294static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1295 struct kvm_run *kvm_run) = {
1296 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1297 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1298 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1299 /* for now: */
1300 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1301 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1302 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1303 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1304 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1305 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1306 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1307 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1308 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1309 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1310 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1311 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1312 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1313 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
7807fa6c 1314 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
6aa8b732
AK		 1315 [SVM_EXIT_INTR] = nop_on_interception,
1316 [SVM_EXIT_NMI] = nop_on_interception,
1317 [SVM_EXIT_SMI] = nop_on_interception,
1318 [SVM_EXIT_INIT] = nop_on_interception,
c1150d8c 1319 [SVM_EXIT_VINTR] = interrupt_window_interception,
6aa8b732
AK		 1320 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1321 [SVM_EXIT_CPUID] = cpuid_interception,
1322 [SVM_EXIT_HLT] = halt_interception,
1323 [SVM_EXIT_INVLPG] = emulate_on_interception,
1324 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1325 [SVM_EXIT_IOIO] = io_interception,
1326 [SVM_EXIT_MSR] = msr_interception,
1327 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
46fe4ddd 1328 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
6aa8b732 1329 [SVM_EXIT_VMRUN] = invalid_op_interception,
02e235bc 1330 [SVM_EXIT_VMMCALL] = vmmcall_interception,
6aa8b732
AK		 1331 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1332 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1333 [SVM_EXIT_STGI] = invalid_op_interception,
1334 [SVM_EXIT_CLGI] = invalid_op_interception,
1335 [SVM_EXIT_SKINIT] = invalid_op_interception,
916ce236
JR		 1336 [SVM_EXIT_MONITOR] = invalid_op_interception,
1337 [SVM_EXIT_MWAIT] = invalid_op_interception,
6aa8b732
AK		 1338};
1339
1340
1341static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1342{
1343 u32 exit_code = vcpu->svm->vmcb->control.exit_code;
1344
6aa8b732
AK		 1345 if (is_external_interrupt(vcpu->svm->vmcb->control.exit_int_info) &&
1346 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1347 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1348 "exit_code 0x%x\n",
1349 __FUNCTION__, vcpu->svm->vmcb->control.exit_int_info,
1350 exit_code);
1351
9d8f549d 1352 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
6aa8b732
AK		 1353 || svm_exit_handlers[exit_code] == 0) {
1354 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
364b625b 1355 kvm_run->hw.hardware_exit_reason = exit_code;
6aa8b732
AK		 1356 return 0;
1357 }
1358
1359 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1360}
1361
1362static void reload_tss(struct kvm_vcpu *vcpu)
1363{
1364 int cpu = raw_smp_processor_id();
1365
1366 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1367 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1368 load_TR_desc();
1369}
1370
1371static void pre_svm_run(struct kvm_vcpu *vcpu)
1372{
1373 int cpu = raw_smp_processor_id();
1374
1375 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1376
1377 vcpu->svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1378 if (vcpu->cpu != cpu ||
1379 vcpu->svm->asid_generation != svm_data->asid_generation)
1380 new_asid(vcpu, svm_data);
1381}
1382
1383
c1150d8c 1384static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
6aa8b732
AK		 1385{
1386 struct vmcb_control_area *control;
1387
6aa8b732 1388 control = &vcpu->svm->vmcb->control;
6aa8b732
AK		 1389 control->int_vector = pop_irq(vcpu);
1390 control->int_ctl &= ~V_INTR_PRIO_MASK;
1391 control->int_ctl |= V_IRQ_MASK |
1392 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1393}
1394
1395static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1396{
1397 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1398
1399 if (control->int_ctl & V_IRQ_MASK) {
1400 control->int_ctl &= ~V_IRQ_MASK;
1401 push_irq(vcpu, control->int_vector);
1402 }
c1150d8c
DL		 1403
1404 vcpu->interrupt_window_open =
1405 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1406}
1407
1408static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1409 struct kvm_run *kvm_run)
1410{
1411 struct vmcb_control_area *control = &vcpu->svm->vmcb->control;
1412
1413 vcpu->interrupt_window_open =
1414 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1415 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
1416
1417 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1418 /*
1419 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1420 */
1421 kvm_do_inject_irq(vcpu);
1422
1423 /*
1424 * Interrupts blocked. Wait for unblock.
1425 */
1426 if (!vcpu->interrupt_window_open &&
1427 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1428 control->intercept |= 1ULL << INTERCEPT_VINTR;
1429 } else
1430 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1431}
1432
1433static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1434 struct kvm_run *kvm_run)
1435{
1436 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1437 vcpu->irq_summary == 0);
1438 kvm_run->if_flag = (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1439 kvm_run->cr8 = vcpu->cr8;
1440 kvm_run->apic_base = vcpu->apic_base;
1441}
1442
1443/*
1444 * Check if userspace requested an interrupt window, and that the
1445 * interrupt window is open.
1446 *
1447 * No need to exit to userspace if we already have an interrupt queued.
1448 */
1449static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1450 struct kvm_run *kvm_run)
1451{
1452 return (!vcpu->irq_summary &&
1453 kvm_run->request_interrupt_window &&
1454 vcpu->interrupt_window_open &&
1455 (vcpu->svm->vmcb->save.rflags & X86_EFLAGS_IF));
6aa8b732
AK		 1456}
1457
1458static void save_db_regs(unsigned long *db_regs)
1459{
5aff458e
AK		 1460 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1461 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1462 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1463 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
6aa8b732
AK		 1464}
1465
1466static void load_db_regs(unsigned long *db_regs)
1467{
5aff458e
AK		 1468 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1469 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1470 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1471 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
6aa8b732
AK		 1472}
1473
d9e368d6
AK		 1474static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1475{
1476 force_new_asid(vcpu);
1477}
1478
6aa8b732
AK		 1479static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1480{
1481 u16 fs_selector;
1482 u16 gs_selector;
1483 u16 ldt_selector;
e2dec939 1484 int r;
6aa8b732
AK		 1485
1486again:
17c3ba9d
AK		 1487 r = kvm_mmu_reload(vcpu);
1488 if (unlikely(r))
1489 return r;
1490
cccf748b
AK		 1491 if (!vcpu->mmio_read_completed)
1492 do_interrupt_requests(vcpu, kvm_run);
6aa8b732
AK		 1493
1494 clgi();
1495
d9e368d6
AK		 1496 vcpu->guest_mode = 1;
1497 if (vcpu->requests)
1498 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1499 svm_flush_tlb(vcpu);
1500
6aa8b732
AK		 1501 pre_svm_run(vcpu);
1502
1503 save_host_msrs(vcpu);
1504 fs_selector = read_fs();
1505 gs_selector = read_gs();
1506 ldt_selector = read_ldt();
1507 vcpu->svm->host_cr2 = kvm_read_cr2();
1508 vcpu->svm->host_dr6 = read_dr6();
1509 vcpu->svm->host_dr7 = read_dr7();
1510 vcpu->svm->vmcb->save.cr2 = vcpu->cr2;
1511
1512 if (vcpu->svm->vmcb->save.dr7 & 0xff) {
1513 write_dr7(0);
1514 save_db_regs(vcpu->svm->host_db_regs);
1515 load_db_regs(vcpu->svm->db_regs);
1516 }
36241b8c 1517
7807fa6c
AL		 1518 if (vcpu->fpu_active) {
1519 fx_save(vcpu->host_fx_image);
1520 fx_restore(vcpu->guest_fx_image);
1521 }
36241b8c 1522
6aa8b732 1523 asm volatile (
05b3e0c2 1524#ifdef CONFIG_X86_64
6aa8b732
AK		 1525 "push %%rbx; push %%rcx; push %%rdx;"
1526 "push %%rsi; push %%rdi; push %%rbp;"
1527 "push %%r8; push %%r9; push %%r10; push %%r11;"
1528 "push %%r12; push %%r13; push %%r14; push %%r15;"
1529#else
1530 "push %%ebx; push %%ecx; push %%edx;"
1531 "push %%esi; push %%edi; push %%ebp;"
1532#endif
1533
05b3e0c2 1534#ifdef CONFIG_X86_64
6aa8b732
AK		 1535 "mov %c[rbx](%[vcpu]), %%rbx \n\t"
1536 "mov %c[rcx](%[vcpu]), %%rcx \n\t"
1537 "mov %c[rdx](%[vcpu]), %%rdx \n\t"
1538 "mov %c[rsi](%[vcpu]), %%rsi \n\t"
1539 "mov %c[rdi](%[vcpu]), %%rdi \n\t"
1540 "mov %c[rbp](%[vcpu]), %%rbp \n\t"
1541 "mov %c[r8](%[vcpu]), %%r8 \n\t"
1542 "mov %c[r9](%[vcpu]), %%r9 \n\t"
1543 "mov %c[r10](%[vcpu]), %%r10 \n\t"
1544 "mov %c[r11](%[vcpu]), %%r11 \n\t"
1545 "mov %c[r12](%[vcpu]), %%r12 \n\t"
1546 "mov %c[r13](%[vcpu]), %%r13 \n\t"
1547 "mov %c[r14](%[vcpu]), %%r14 \n\t"
1548 "mov %c[r15](%[vcpu]), %%r15 \n\t"
1549#else
1550 "mov %c[rbx](%[vcpu]), %%ebx \n\t"
1551 "mov %c[rcx](%[vcpu]), %%ecx \n\t"
1552 "mov %c[rdx](%[vcpu]), %%edx \n\t"
1553 "mov %c[rsi](%[vcpu]), %%esi \n\t"
1554 "mov %c[rdi](%[vcpu]), %%edi \n\t"
1555 "mov %c[rbp](%[vcpu]), %%ebp \n\t"
1556#endif
1557
05b3e0c2 1558#ifdef CONFIG_X86_64
6aa8b732
AK		 1559 /* Enter guest mode */
1560 "push %%rax \n\t"
1561 "mov %c[svm](%[vcpu]), %%rax \n\t"
1562 "mov %c[vmcb](%%rax), %%rax \n\t"
1563 SVM_VMLOAD "\n\t"
1564 SVM_VMRUN "\n\t"
1565 SVM_VMSAVE "\n\t"
1566 "pop %%rax \n\t"
1567#else
1568 /* Enter guest mode */
1569 "push %%eax \n\t"
1570 "mov %c[svm](%[vcpu]), %%eax \n\t"
1571 "mov %c[vmcb](%%eax), %%eax \n\t"
1572 SVM_VMLOAD "\n\t"
1573 SVM_VMRUN "\n\t"
1574 SVM_VMSAVE "\n\t"
1575 "pop %%eax \n\t"
1576#endif
1577
1578 /* Save guest registers, load host registers */
05b3e0c2 1579#ifdef CONFIG_X86_64
6aa8b732
AK		 1580 "mov %%rbx, %c[rbx](%[vcpu]) \n\t"
1581 "mov %%rcx, %c[rcx](%[vcpu]) \n\t"
1582 "mov %%rdx, %c[rdx](%[vcpu]) \n\t"
1583 "mov %%rsi, %c[rsi](%[vcpu]) \n\t"
1584 "mov %%rdi, %c[rdi](%[vcpu]) \n\t"
1585 "mov %%rbp, %c[rbp](%[vcpu]) \n\t"
1586 "mov %%r8, %c[r8](%[vcpu]) \n\t"
1587 "mov %%r9, %c[r9](%[vcpu]) \n\t"
1588 "mov %%r10, %c[r10](%[vcpu]) \n\t"
1589 "mov %%r11, %c[r11](%[vcpu]) \n\t"
1590 "mov %%r12, %c[r12](%[vcpu]) \n\t"
1591 "mov %%r13, %c[r13](%[vcpu]) \n\t"
1592 "mov %%r14, %c[r14](%[vcpu]) \n\t"
1593 "mov %%r15, %c[r15](%[vcpu]) \n\t"
1594
1595 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1596 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1597 "pop %%rbp; pop %%rdi; pop %%rsi;"
1598 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1599#else
1600 "mov %%ebx, %c[rbx](%[vcpu]) \n\t"
1601 "mov %%ecx, %c[rcx](%[vcpu]) \n\t"
1602 "mov %%edx, %c[rdx](%[vcpu]) \n\t"
1603 "mov %%esi, %c[rsi](%[vcpu]) \n\t"
1604 "mov %%edi, %c[rdi](%[vcpu]) \n\t"
1605 "mov %%ebp, %c[rbp](%[vcpu]) \n\t"
1606
1607 "pop %%ebp; pop %%edi; pop %%esi;"
1608 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1609#endif
1610 :
1611 : [vcpu]"a"(vcpu),
1612 [svm]"i"(offsetof(struct kvm_vcpu, svm)),
1613 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1614 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1615 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1616 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1617 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1618 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1619 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP]))
05b3e0c2 1620#ifdef CONFIG_X86_64
6aa8b732
AK		 1621 ,[r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1622 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1623 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1624 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1625 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1626 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1627 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1628 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15]))
1629#endif
1630 : "cc", "memory" );
1631
d9e368d6
AK		 1632 vcpu->guest_mode = 0;
1633
7807fa6c
AL		 1634 if (vcpu->fpu_active) {
1635 fx_save(vcpu->guest_fx_image);
1636 fx_restore(vcpu->host_fx_image);
1637 }
36241b8c 1638
6aa8b732
AK		 1639 if ((vcpu->svm->vmcb->save.dr7 & 0xff))
1640 load_db_regs(vcpu->svm->host_db_regs);
1641
1642 vcpu->cr2 = vcpu->svm->vmcb->save.cr2;
1643
1644 write_dr6(vcpu->svm->host_dr6);
1645 write_dr7(vcpu->svm->host_dr7);
1646 kvm_write_cr2(vcpu->svm->host_cr2);
1647
1648 load_fs(fs_selector);
1649 load_gs(gs_selector);
1650 load_ldt(ldt_selector);
1651 load_host_msrs(vcpu);
1652
1653 reload_tss(vcpu);
1654
07031e14
IM		 1655 /*
1656 * Profile KVM exit RIPs:
1657 */
1658 if (unlikely(prof_on == KVM_PROFILING))
1659 profile_hit(KVM_PROFILING,
1660 (void *)(unsigned long)vcpu->svm->vmcb->save.rip);
1661
6aa8b732
AK		 1662 stgi();
1663
1664 kvm_reput_irq(vcpu);
1665
1666 vcpu->svm->next_rip = 0;
1667
1668 if (vcpu->svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
8eb7d334
AK		 1669 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1670 kvm_run->fail_entry.hardware_entry_failure_reason
1671 = vcpu->svm->vmcb->control.exit_code;
c1150d8c 1672 post_kvm_run_save(vcpu, kvm_run);
6aa8b732
AK		 1673 return 0;
1674 }
1675
e2dec939
AK		 1676 r = handle_exit(vcpu, kvm_run);
1677 if (r > 0) {
6aa8b732 1678 if (signal_pending(current)) {
1165f5fe 1679 ++vcpu->stat.signal_exits;
c1150d8c 1680 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1681 kvm_run->exit_reason = KVM_EXIT_INTR;
c1150d8c
DL		 1682 return -EINTR;
1683 }
1684
1685 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1165f5fe 1686 ++vcpu->stat.request_irq_exits;
c1150d8c 1687 post_kvm_run_save(vcpu, kvm_run);
1b19f3e6 1688 kvm_run->exit_reason = KVM_EXIT_INTR;
6aa8b732
AK		 1689 return -EINTR;
1690 }
1691 kvm_resched(vcpu);
1692 goto again;
1693 }
c1150d8c 1694 post_kvm_run_save(vcpu, kvm_run);
e2dec939 1695 return r;
6aa8b732
AK		 1696}
1697
6aa8b732
AK		 1698static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1699{
1700 vcpu->svm->vmcb->save.cr3 = root;
1701 force_new_asid(vcpu);
7807fa6c
AL		 1702
1703 if (vcpu->fpu_active) {
1704 vcpu->svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1705 vcpu->svm->vmcb->save.cr0 |= CR0_TS_MASK;
1706 vcpu->fpu_active = 0;
1707 }
6aa8b732
AK		 1708}
1709
1710static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1711 unsigned long addr,
1712 uint32_t err_code)
1713{
1714 uint32_t exit_int_info = vcpu->svm->vmcb->control.exit_int_info;
1715
1165f5fe 1716 ++vcpu->stat.pf_guest;
6aa8b732
AK		 1717
1718 if (is_page_fault(exit_int_info)) {
1719
1720 vcpu->svm->vmcb->control.event_inj_err = 0;
1721 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1722 SVM_EVTINJ_VALID_ERR |
1723 SVM_EVTINJ_TYPE_EXEPT |
1724 DF_VECTOR;
1725 return;
1726 }
1727 vcpu->cr2 = addr;
1728 vcpu->svm->vmcb->save.cr2 = addr;
1729 vcpu->svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1730 SVM_EVTINJ_VALID_ERR |
1731 SVM_EVTINJ_TYPE_EXEPT |
1732 PF_VECTOR;
1733 vcpu->svm->vmcb->control.event_inj_err = err_code;
1734}
1735
1736
1737static int is_disabled(void)
1738{
6031a61c
JR		 1739 u64 vm_cr;
1740
1741 rdmsrl(MSR_VM_CR, vm_cr);
1742 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1743 return 1;
1744
6aa8b732
AK		 1745 return 0;
1746}
1747
102d8325
IM		 1748static void
1749svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1750{
1751 /*
1752 * Patch in the VMMCALL instruction:
1753 */
1754 hypercall[0] = 0x0f;
1755 hypercall[1] = 0x01;
1756 hypercall[2] = 0xd9;
1757 hypercall[3] = 0xc3;
1758}
1759
6aa8b732
AK		 1760static struct kvm_arch_ops svm_arch_ops = {
1761 .cpu_has_kvm_support = has_svm,
1762 .disabled_by_bios = is_disabled,
1763 .hardware_setup = svm_hardware_setup,
1764 .hardware_unsetup = svm_hardware_unsetup,
1765 .hardware_enable = svm_hardware_enable,
1766 .hardware_disable = svm_hardware_disable,
1767
1768 .vcpu_create = svm_create_vcpu,
1769 .vcpu_free = svm_free_vcpu,
1770
1771 .vcpu_load = svm_vcpu_load,
1772 .vcpu_put = svm_vcpu_put,
774c47f1 1773 .vcpu_decache = svm_vcpu_decache,
6aa8b732
AK		 1774
1775 .set_guest_debug = svm_guest_debug,
1776 .get_msr = svm_get_msr,
1777 .set_msr = svm_set_msr,
1778 .get_segment_base = svm_get_segment_base,
1779 .get_segment = svm_get_segment,
1780 .set_segment = svm_set_segment,
6aa8b732 1781 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
25c4c276 1782 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
6aa8b732 1783 .set_cr0 = svm_set_cr0,
6aa8b732
AK		 1784 .set_cr3 = svm_set_cr3,
1785 .set_cr4 = svm_set_cr4,
1786 .set_efer = svm_set_efer,
1787 .get_idt = svm_get_idt,
1788 .set_idt = svm_set_idt,
1789 .get_gdt = svm_get_gdt,
1790 .set_gdt = svm_set_gdt,
1791 .get_dr = svm_get_dr,
1792 .set_dr = svm_set_dr,
1793 .cache_regs = svm_cache_regs,
1794 .decache_regs = svm_decache_regs,
1795 .get_rflags = svm_get_rflags,
1796 .set_rflags = svm_set_rflags,
1797
1798 .invlpg = svm_invlpg,
1799 .tlb_flush = svm_flush_tlb,
1800 .inject_page_fault = svm_inject_page_fault,
1801
1802 .inject_gp = svm_inject_gp,
1803
1804 .run = svm_vcpu_run,
1805 .skip_emulated_instruction = skip_emulated_instruction,
1806 .vcpu_setup = svm_vcpu_setup,
102d8325 1807 .patch_hypercall = svm_patch_hypercall,
6aa8b732
AK		 1808};
1809
1810static int __init svm_init(void)
1811{
873a7c42 1812 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
6aa8b732
AK		 1813}
1814
1815static void __exit svm_exit(void)
1816{
1817 kvm_exit_arch();
1818}
1819
1820module_init(svm_init)
1821module_exit(svm_exit)
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