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[PATCH] KVM: Clean up AMD SVM debug registers load and unload
[mirror_ubuntu-artful-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
19#include "vmx.h"
20#include "kvm_vmx.h"
21#include <linux/module.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <asm/io.h>
3b3be0d1 25#include <asm/desc.h>
6aa8b732
AK		 26
27#include "segment_descriptor.h"
28
29#define MSR_IA32_FEATURE_CONTROL 0x03a
30
31MODULE_AUTHOR("Qumranet");
32MODULE_LICENSE("GPL");
33
34static DEFINE_PER_CPU(struct vmcs *, vmxarea);
35static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
36
37#ifdef __x86_64__
38#define HOST_IS_64 1
39#else
40#define HOST_IS_64 0
41#endif
42
43static struct vmcs_descriptor {
44 int size;
45 int order;
46 u32 revision_id;
47} vmcs_descriptor;
48
49#define VMX_SEGMENT_FIELD(seg) \
50 [VCPU_SREG_##seg] = { \
51 .selector = GUEST_##seg##_SELECTOR, \
52 .base = GUEST_##seg##_BASE, \
53 .limit = GUEST_##seg##_LIMIT, \
54 .ar_bytes = GUEST_##seg##_AR_BYTES, \
55 }
56
57static struct kvm_vmx_segment_field {
58 unsigned selector;
59 unsigned base;
60 unsigned limit;
61 unsigned ar_bytes;
62} kvm_vmx_segment_fields[] = {
63 VMX_SEGMENT_FIELD(CS),
64 VMX_SEGMENT_FIELD(DS),
65 VMX_SEGMENT_FIELD(ES),
66 VMX_SEGMENT_FIELD(FS),
67 VMX_SEGMENT_FIELD(GS),
68 VMX_SEGMENT_FIELD(SS),
69 VMX_SEGMENT_FIELD(TR),
70 VMX_SEGMENT_FIELD(LDTR),
71};
72
73static const u32 vmx_msr_index[] = {
74#ifdef __x86_64__
75 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
76#endif
77 MSR_EFER, MSR_K6_STAR,
78};
79#define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
80
81struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr);
82
83static inline int is_page_fault(u32 intr_info)
84{
85 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
86 INTR_INFO_VALID_MASK)) ==
87 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
88}
89
90static inline int is_external_interrupt(u32 intr_info)
91{
92 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
93 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
94}
95
96static void vmcs_clear(struct vmcs *vmcs)
97{
98 u64 phys_addr = __pa(vmcs);
99 u8 error;
100
101 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
102 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
103 : "cc", "memory");
104 if (error)
105 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
106 vmcs, phys_addr);
107}
108
109static void __vcpu_clear(void *arg)
110{
111 struct kvm_vcpu *vcpu = arg;
112 int cpu = smp_processor_id();
113
114 if (vcpu->cpu == cpu)
115 vmcs_clear(vcpu->vmcs);
116 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
117 per_cpu(current_vmcs, cpu) = NULL;
118}
119
120static unsigned long vmcs_readl(unsigned long field)
121{
122 unsigned long value;
123
124 asm volatile (ASM_VMX_VMREAD_RDX_RAX
125 : "=a"(value) : "d"(field) : "cc");
126 return value;
127}
128
129static u16 vmcs_read16(unsigned long field)
130{
131 return vmcs_readl(field);
132}
133
134static u32 vmcs_read32(unsigned long field)
135{
136 return vmcs_readl(field);
137}
138
139static u64 vmcs_read64(unsigned long field)
140{
141#ifdef __x86_64__
142 return vmcs_readl(field);
143#else
144 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
145#endif
146}
147
148static void vmcs_writel(unsigned long field, unsigned long value)
149{
150 u8 error;
151
152 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
153 : "=q"(error) : "a"(value), "d"(field) : "cc" );
154 if (error)
155 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
156 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
157}
158
159static void vmcs_write16(unsigned long field, u16 value)
160{
161 vmcs_writel(field, value);
162}
163
164static void vmcs_write32(unsigned long field, u32 value)
165{
166 vmcs_writel(field, value);
167}
168
169static void vmcs_write64(unsigned long field, u64 value)
170{
171#ifdef __x86_64__
172 vmcs_writel(field, value);
173#else
174 vmcs_writel(field, value);
175 asm volatile ("");
176 vmcs_writel(field+1, value >> 32);
177#endif
178}
179
180/*
181 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
182 * vcpu mutex is already taken.
183 */
184static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
185{
186 u64 phys_addr = __pa(vcpu->vmcs);
187 int cpu;
188
189 cpu = get_cpu();
190
191 if (vcpu->cpu != cpu) {
192 smp_call_function(__vcpu_clear, vcpu, 0, 1);
193 vcpu->launched = 0;
194 }
195
196 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
197 u8 error;
198
199 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
200 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
201 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
202 : "cc");
203 if (error)
204 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
205 vcpu->vmcs, phys_addr);
206 }
207
208 if (vcpu->cpu != cpu) {
209 struct descriptor_table dt;
210 unsigned long sysenter_esp;
211
212 vcpu->cpu = cpu;
213 /*
214 * Linux uses per-cpu TSS and GDT, so set these when switching
215 * processors.
216 */
217 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
218 get_gdt(&dt);
219 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
220
221 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
222 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
223 }
224 return vcpu;
225}
226
227static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
228{
229 put_cpu();
230}
231
232static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
233{
234 return vmcs_readl(GUEST_RFLAGS);
235}
236
237static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
238{
239 vmcs_writel(GUEST_RFLAGS, rflags);
240}
241
242static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
243{
244 unsigned long rip;
245 u32 interruptibility;
246
247 rip = vmcs_readl(GUEST_RIP);
248 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
249 vmcs_writel(GUEST_RIP, rip);
250
251 /*
252 * We emulated an instruction, so temporary interrupt blocking
253 * should be removed, if set.
254 */
255 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
256 if (interruptibility & 3)
257 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
258 interruptibility & ~3);
259}
260
261static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
262{
263 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
264 vmcs_readl(GUEST_RIP));
265 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
266 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
267 GP_VECTOR |
268 INTR_TYPE_EXCEPTION |
269 INTR_INFO_DELIEVER_CODE_MASK |
270 INTR_INFO_VALID_MASK);
271}
272
273/*
274 * reads and returns guest's timestamp counter "register"
275 * guest_tsc = host_tsc + tsc_offset -- 21.3
276 */
277static u64 guest_read_tsc(void)
278{
279 u64 host_tsc, tsc_offset;
280
281 rdtscll(host_tsc);
282 tsc_offset = vmcs_read64(TSC_OFFSET);
283 return host_tsc + tsc_offset;
284}
285
286/*
287 * writes 'guest_tsc' into guest's timestamp counter "register"
288 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
289 */
290static void guest_write_tsc(u64 guest_tsc)
291{
292 u64 host_tsc;
293
294 rdtscll(host_tsc);
295 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
296}
297
298static void reload_tss(void)
299{
300#ifndef __x86_64__
301
302 /*
303 * VT restores TR but not its size. Useless.
304 */
305 struct descriptor_table gdt;
306 struct segment_descriptor *descs;
307
308 get_gdt(&gdt);
309 descs = (void *)gdt.base;
310 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
311 load_TR_desc();
312#endif
313}
314
315/*
316 * Reads an msr value (of 'msr_index') into 'pdata'.
317 * Returns 0 on success, non-0 otherwise.
318 * Assumes vcpu_load() was already called.
319 */
320static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
321{
322 u64 data;
323 struct vmx_msr_entry *msr;
324
325 if (!pdata) {
326 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
327 return -EINVAL;
328 }
329
330 switch (msr_index) {
331#ifdef __x86_64__
332 case MSR_FS_BASE:
333 data = vmcs_readl(GUEST_FS_BASE);
334 break;
335 case MSR_GS_BASE:
336 data = vmcs_readl(GUEST_GS_BASE);
337 break;
338 case MSR_EFER:
339 data = vcpu->shadow_efer;
340 break;
341#endif
342 case MSR_IA32_TIME_STAMP_COUNTER:
343 data = guest_read_tsc();
344 break;
345 case MSR_IA32_SYSENTER_CS:
346 data = vmcs_read32(GUEST_SYSENTER_CS);
347 break;
348 case MSR_IA32_SYSENTER_EIP:
349 data = vmcs_read32(GUEST_SYSENTER_EIP);
350 break;
351 case MSR_IA32_SYSENTER_ESP:
352 data = vmcs_read32(GUEST_SYSENTER_ESP);
353 break;
354 case MSR_IA32_MC0_CTL:
355 case MSR_IA32_MCG_STATUS:
356 case MSR_IA32_MCG_CAP:
357 case MSR_IA32_MC0_MISC:
358 case MSR_IA32_MC0_MISC+4:
359 case MSR_IA32_MC0_MISC+8:
360 case MSR_IA32_MC0_MISC+12:
361 case MSR_IA32_MC0_MISC+16:
362 case MSR_IA32_UCODE_REV:
363 /* MTRR registers */
364 case 0xfe:
365 case 0x200 ... 0x2ff:
366 data = 0;
367 break;
368 case MSR_IA32_APICBASE:
369 data = vcpu->apic_base;
370 break;
371 default:
372 msr = find_msr_entry(vcpu, msr_index);
373 if (!msr) {
374 printk(KERN_ERR "kvm: unhandled rdmsr: %x\n", msr_index);
375 return 1;
376 }
377 data = msr->data;
378 break;
379 }
380
381 *pdata = data;
382 return 0;
383}
384
385/*
386 * Writes msr value into into the appropriate "register".
387 * Returns 0 on success, non-0 otherwise.
388 * Assumes vcpu_load() was already called.
389 */
390static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
391{
392 struct vmx_msr_entry *msr;
393 switch (msr_index) {
394#ifdef __x86_64__
395 case MSR_FS_BASE:
396 vmcs_writel(GUEST_FS_BASE, data);
397 break;
398 case MSR_GS_BASE:
399 vmcs_writel(GUEST_GS_BASE, data);
400 break;
401#endif
402 case MSR_IA32_SYSENTER_CS:
403 vmcs_write32(GUEST_SYSENTER_CS, data);
404 break;
405 case MSR_IA32_SYSENTER_EIP:
406 vmcs_write32(GUEST_SYSENTER_EIP, data);
407 break;
408 case MSR_IA32_SYSENTER_ESP:
409 vmcs_write32(GUEST_SYSENTER_ESP, data);
410 break;
411#ifdef __x86_64
412 case MSR_EFER:
413 set_efer(vcpu, data);
414 break;
415 case MSR_IA32_MC0_STATUS:
416 printk(KERN_WARNING "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n"
417 , __FUNCTION__, data);
418 break;
419#endif
420 case MSR_IA32_TIME_STAMP_COUNTER: {
421 guest_write_tsc(data);
422 break;
423 }
424 case MSR_IA32_UCODE_REV:
425 case MSR_IA32_UCODE_WRITE:
426 case 0x200 ... 0x2ff: /* MTRRs */
427 break;
428 case MSR_IA32_APICBASE:
429 vcpu->apic_base = data;
430 break;
431 default:
432 msr = find_msr_entry(vcpu, msr_index);
433 if (!msr) {
434 printk(KERN_ERR "kvm: unhandled wrmsr: 0x%x\n", msr_index);
435 return 1;
436 }
437 msr->data = data;
438 break;
439 }
440
441 return 0;
442}
443
444/*
445 * Sync the rsp and rip registers into the vcpu structure. This allows
446 * registers to be accessed by indexing vcpu->regs.
447 */
448static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
449{
450 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
451 vcpu->rip = vmcs_readl(GUEST_RIP);
452}
453
454/*
455 * Syncs rsp and rip back into the vmcs. Should be called after possible
456 * modification.
457 */
458static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
459{
460 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
461 vmcs_writel(GUEST_RIP, vcpu->rip);
462}
463
464static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
465{
466 unsigned long dr7 = 0x400;
467 u32 exception_bitmap;
468 int old_singlestep;
469
470 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
471 old_singlestep = vcpu->guest_debug.singlestep;
472
473 vcpu->guest_debug.enabled = dbg->enabled;
474 if (vcpu->guest_debug.enabled) {
475 int i;
476
477 dr7 |= 0x200; /* exact */
478 for (i = 0; i < 4; ++i) {
479 if (!dbg->breakpoints[i].enabled)
480 continue;
481 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
482 dr7 |= 2 << (i*2); /* global enable */
483 dr7 |= 0 << (i*4+16); /* execution breakpoint */
484 }
485
486 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
487
488 vcpu->guest_debug.singlestep = dbg->singlestep;
489 } else {
490 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
491 vcpu->guest_debug.singlestep = 0;
492 }
493
494 if (old_singlestep && !vcpu->guest_debug.singlestep) {
495 unsigned long flags;
496
497 flags = vmcs_readl(GUEST_RFLAGS);
498 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
499 vmcs_writel(GUEST_RFLAGS, flags);
500 }
501
502 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
503 vmcs_writel(GUEST_DR7, dr7);
504
505 return 0;
506}
507
508static __init int cpu_has_kvm_support(void)
509{
510 unsigned long ecx = cpuid_ecx(1);
511 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
512}
513
514static __init int vmx_disabled_by_bios(void)
515{
516 u64 msr;
517
518 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
519 return (msr & 5) == 1; /* locked but not enabled */
520}
521
522static __init void hardware_enable(void *garbage)
523{
524 int cpu = raw_smp_processor_id();
525 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
526 u64 old;
527
528 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
529 if ((old & 5) == 0)
530 /* enable and lock */
531 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
532 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
533 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
534 : "memory", "cc");
535}
536
537static void hardware_disable(void *garbage)
538{
539 asm volatile (ASM_VMX_VMXOFF : : : "cc");
540}
541
542static __init void setup_vmcs_descriptor(void)
543{
544 u32 vmx_msr_low, vmx_msr_high;
545
546 rdmsr(MSR_IA32_VMX_BASIC_MSR, vmx_msr_low, vmx_msr_high);
547 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
548 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
549 vmcs_descriptor.revision_id = vmx_msr_low;
550};
551
552static struct vmcs *alloc_vmcs_cpu(int cpu)
553{
554 int node = cpu_to_node(cpu);
555 struct page *pages;
556 struct vmcs *vmcs;
557
558 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
559 if (!pages)
560 return NULL;
561 vmcs = page_address(pages);
562 memset(vmcs, 0, vmcs_descriptor.size);
563 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
564 return vmcs;
565}
566
567static struct vmcs *alloc_vmcs(void)
568{
569 return alloc_vmcs_cpu(smp_processor_id());
570}
571
572static void free_vmcs(struct vmcs *vmcs)
573{
574 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
575}
576
577static __exit void free_kvm_area(void)
578{
579 int cpu;
580
581 for_each_online_cpu(cpu)
582 free_vmcs(per_cpu(vmxarea, cpu));
583}
584
585extern struct vmcs *alloc_vmcs_cpu(int cpu);
586
587static __init int alloc_kvm_area(void)
588{
589 int cpu;
590
591 for_each_online_cpu(cpu) {
592 struct vmcs *vmcs;
593
594 vmcs = alloc_vmcs_cpu(cpu);
595 if (!vmcs) {
596 free_kvm_area();
597 return -ENOMEM;
598 }
599
600 per_cpu(vmxarea, cpu) = vmcs;
601 }
602 return 0;
603}
604
605static __init int hardware_setup(void)
606{
607 setup_vmcs_descriptor();
608 return alloc_kvm_area();
609}
610
611static __exit void hardware_unsetup(void)
612{
613 free_kvm_area();
614}
615
616static void update_exception_bitmap(struct kvm_vcpu *vcpu)
617{
618 if (vcpu->rmode.active)
619 vmcs_write32(EXCEPTION_BITMAP, ~0);
620 else
621 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
622}
623
624static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
625{
626 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
627
628 if (vmcs_readl(sf->base) == save->base) {
629 vmcs_write16(sf->selector, save->selector);
630 vmcs_writel(sf->base, save->base);
631 vmcs_write32(sf->limit, save->limit);
632 vmcs_write32(sf->ar_bytes, save->ar);
633 } else {
634 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
635 << AR_DPL_SHIFT;
636 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
637 }
638}
639
640static void enter_pmode(struct kvm_vcpu *vcpu)
641{
642 unsigned long flags;
643
644 vcpu->rmode.active = 0;
645
646 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
647 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
648 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
649
650 flags = vmcs_readl(GUEST_RFLAGS);
651 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
652 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
653 vmcs_writel(GUEST_RFLAGS, flags);
654
655 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
656 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
657
658 update_exception_bitmap(vcpu);
659
660 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
661 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
662 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
663 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
664
665 vmcs_write16(GUEST_SS_SELECTOR, 0);
666 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
667
668 vmcs_write16(GUEST_CS_SELECTOR,
669 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
670 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
671}
672
673static int rmode_tss_base(struct kvm* kvm)
674{
675 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
676 return base_gfn << PAGE_SHIFT;
677}
678
679static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
680{
681 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
682
683 save->selector = vmcs_read16(sf->selector);
684 save->base = vmcs_readl(sf->base);
685 save->limit = vmcs_read32(sf->limit);
686 save->ar = vmcs_read32(sf->ar_bytes);
687 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
688 vmcs_write32(sf->limit, 0xffff);
689 vmcs_write32(sf->ar_bytes, 0xf3);
690}
691
692static void enter_rmode(struct kvm_vcpu *vcpu)
693{
694 unsigned long flags;
695
696 vcpu->rmode.active = 1;
697
698 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
699 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
700
701 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
702 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
703
704 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
705 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
706
707 flags = vmcs_readl(GUEST_RFLAGS);
708 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
709
710 flags |= IOPL_MASK | X86_EFLAGS_VM;
711
712 vmcs_writel(GUEST_RFLAGS, flags);
713 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
714 update_exception_bitmap(vcpu);
715
716 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
717 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
718 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
719
720 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
721 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
722
723 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
724 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
725 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
726 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
727}
728
729#ifdef __x86_64__
730
731static void enter_lmode(struct kvm_vcpu *vcpu)
732{
733 u32 guest_tr_ar;
734
735 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
736 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
737 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
738 __FUNCTION__);
739 vmcs_write32(GUEST_TR_AR_BYTES,
740 (guest_tr_ar & ~AR_TYPE_MASK)
741 | AR_TYPE_BUSY_64_TSS);
742 }
743
744 vcpu->shadow_efer |= EFER_LMA;
745
746 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
747 vmcs_write32(VM_ENTRY_CONTROLS,
748 vmcs_read32(VM_ENTRY_CONTROLS)
749 | VM_ENTRY_CONTROLS_IA32E_MASK);
750}
751
752static void exit_lmode(struct kvm_vcpu *vcpu)
753{
754 vcpu->shadow_efer &= ~EFER_LMA;
755
756 vmcs_write32(VM_ENTRY_CONTROLS,
757 vmcs_read32(VM_ENTRY_CONTROLS)
758 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
759}
760
761#endif
762
763static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
764{
765 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
766 enter_pmode(vcpu);
767
768 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
769 enter_rmode(vcpu);
770
771#ifdef __x86_64__
772 if (vcpu->shadow_efer & EFER_LME) {
773 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
774 enter_lmode(vcpu);
775 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
776 exit_lmode(vcpu);
777 }
778#endif
779
780 vmcs_writel(CR0_READ_SHADOW, cr0);
781 vmcs_writel(GUEST_CR0,
782 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
783 vcpu->cr0 = cr0;
784}
785
786/*
787 * Used when restoring the VM to avoid corrupting segment registers
788 */
789static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
790{
791 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
792 update_exception_bitmap(vcpu);
793 vmcs_writel(CR0_READ_SHADOW, cr0);
794 vmcs_writel(GUEST_CR0,
795 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
796 vcpu->cr0 = cr0;
797}
798
799static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
800{
801 vmcs_writel(GUEST_CR3, cr3);
802}
803
804static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
805{
806 vmcs_writel(CR4_READ_SHADOW, cr4);
807 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
808 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
809 vcpu->cr4 = cr4;
810}
811
812#ifdef __x86_64__
813
814static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
815{
816 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
817
818 vcpu->shadow_efer = efer;
819 if (efer & EFER_LMA) {
820 vmcs_write32(VM_ENTRY_CONTROLS,
821 vmcs_read32(VM_ENTRY_CONTROLS) |
822 VM_ENTRY_CONTROLS_IA32E_MASK);
823 msr->data = efer;
824
825 } else {
826 vmcs_write32(VM_ENTRY_CONTROLS,
827 vmcs_read32(VM_ENTRY_CONTROLS) &
828 ~VM_ENTRY_CONTROLS_IA32E_MASK);
829
830 msr->data = efer & ~EFER_LME;
831 }
832}
833
834#endif
835
836static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
837{
838 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
839
840 return vmcs_readl(sf->base);
841}
842
843static void vmx_get_segment(struct kvm_vcpu *vcpu,
844 struct kvm_segment *var, int seg)
845{
846 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
847 u32 ar;
848
849 var->base = vmcs_readl(sf->base);
850 var->limit = vmcs_read32(sf->limit);
851 var->selector = vmcs_read16(sf->selector);
852 ar = vmcs_read32(sf->ar_bytes);
853 if (ar & AR_UNUSABLE_MASK)
854 ar = 0;
855 var->type = ar & 15;
856 var->s = (ar >> 4) & 1;
857 var->dpl = (ar >> 5) & 3;
858 var->present = (ar >> 7) & 1;
859 var->avl = (ar >> 12) & 1;
860 var->l = (ar >> 13) & 1;
861 var->db = (ar >> 14) & 1;
862 var->g = (ar >> 15) & 1;
863 var->unusable = (ar >> 16) & 1;
864}
865
866static void vmx_set_segment(struct kvm_vcpu *vcpu,
867 struct kvm_segment *var, int seg)
868{
869 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
870 u32 ar;
871
872 vmcs_writel(sf->base, var->base);
873 vmcs_write32(sf->limit, var->limit);
874 vmcs_write16(sf->selector, var->selector);
875 if (var->unusable)
876 ar = 1 << 16;
877 else {
878 ar = var->type & 15;
879 ar |= (var->s & 1) << 4;
880 ar |= (var->dpl & 3) << 5;
881 ar |= (var->present & 1) << 7;
882 ar |= (var->avl & 1) << 12;
883 ar |= (var->l & 1) << 13;
884 ar |= (var->db & 1) << 14;
885 ar |= (var->g & 1) << 15;
886 }
887 vmcs_write32(sf->ar_bytes, ar);
888}
889
890static int vmx_is_long_mode(struct kvm_vcpu *vcpu)
891{
892 return vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_CONTROLS_IA32E_MASK;
893}
894
895static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
896{
897 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
898
899 *db = (ar >> 14) & 1;
900 *l = (ar >> 13) & 1;
901}
902
903static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
904{
905 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
906 dt->base = vmcs_readl(GUEST_IDTR_BASE);
907}
908
909static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
910{
911 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
912 vmcs_writel(GUEST_IDTR_BASE, dt->base);
913}
914
915static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
916{
917 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
918 dt->base = vmcs_readl(GUEST_GDTR_BASE);
919}
920
921static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
922{
923 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
924 vmcs_writel(GUEST_GDTR_BASE, dt->base);
925}
926
927static int init_rmode_tss(struct kvm* kvm)
928{
929 struct page *p1, *p2, *p3;
930 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
931 char *page;
932
933 p1 = _gfn_to_page(kvm, fn++);
934 p2 = _gfn_to_page(kvm, fn++);
935 p3 = _gfn_to_page(kvm, fn);
936
937 if (!p1 || !p2 || !p3) {
938 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
939 return 0;
940 }
941
942 page = kmap_atomic(p1, KM_USER0);
943 memset(page, 0, PAGE_SIZE);
944 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
945 kunmap_atomic(page, KM_USER0);
946
947 page = kmap_atomic(p2, KM_USER0);
948 memset(page, 0, PAGE_SIZE);
949 kunmap_atomic(page, KM_USER0);
950
951 page = kmap_atomic(p3, KM_USER0);
952 memset(page, 0, PAGE_SIZE);
953 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
954 kunmap_atomic(page, KM_USER0);
955
956 return 1;
957}
958
959static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
960{
961 u32 msr_high, msr_low;
962
963 rdmsr(msr, msr_low, msr_high);
964
965 val &= msr_high;
966 val |= msr_low;
967 vmcs_write32(vmcs_field, val);
968}
969
970static void seg_setup(int seg)
971{
972 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
973
974 vmcs_write16(sf->selector, 0);
975 vmcs_writel(sf->base, 0);
976 vmcs_write32(sf->limit, 0xffff);
977 vmcs_write32(sf->ar_bytes, 0x93);
978}
979
980/*
981 * Sets up the vmcs for emulated real mode.
982 */
983static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
984{
985 u32 host_sysenter_cs;
986 u32 junk;
987 unsigned long a;
988 struct descriptor_table dt;
989 int i;
990 int ret = 0;
991 int nr_good_msrs;
992 extern asmlinkage void kvm_vmx_return(void);
993
994 if (!init_rmode_tss(vcpu->kvm)) {
995 ret = -ENOMEM;
996 goto out;
997 }
998
999 memset(vcpu->regs, 0, sizeof(vcpu->regs));
1000 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
1001 vcpu->cr8 = 0;
1002 vcpu->apic_base = 0xfee00000 |
1003 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
1004 MSR_IA32_APICBASE_ENABLE;
1005
1006 fx_init(vcpu);
1007
1008 /*
1009 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1010 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1011 */
1012 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1013 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1014 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1015 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1016
1017 seg_setup(VCPU_SREG_DS);
1018 seg_setup(VCPU_SREG_ES);
1019 seg_setup(VCPU_SREG_FS);
1020 seg_setup(VCPU_SREG_GS);
1021 seg_setup(VCPU_SREG_SS);
1022
1023 vmcs_write16(GUEST_TR_SELECTOR, 0);
1024 vmcs_writel(GUEST_TR_BASE, 0);
1025 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1026 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1027
1028 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1029 vmcs_writel(GUEST_LDTR_BASE, 0);
1030 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1031 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1032
1033 vmcs_write32(GUEST_SYSENTER_CS, 0);
1034 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1035 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1036
1037 vmcs_writel(GUEST_RFLAGS, 0x02);
1038 vmcs_writel(GUEST_RIP, 0xfff0);
1039 vmcs_writel(GUEST_RSP, 0);
1040
1041 vmcs_writel(GUEST_CR3, 0);
1042
1043 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1044 vmcs_writel(GUEST_DR7, 0x400);
1045
1046 vmcs_writel(GUEST_GDTR_BASE, 0);
1047 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1048
1049 vmcs_writel(GUEST_IDTR_BASE, 0);
1050 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1051
1052 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1053 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1054 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1055
1056 /* I/O */
1057 vmcs_write64(IO_BITMAP_A, 0);
1058 vmcs_write64(IO_BITMAP_B, 0);
1059
1060 guest_write_tsc(0);
1061
1062 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1063
1064 /* Special registers */
1065 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1066
1067 /* Control */
1068 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS_MSR,
1069 PIN_BASED_VM_EXEC_CONTROL,
1070 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1071 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1072 );
1073 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS_MSR,
1074 CPU_BASED_VM_EXEC_CONTROL,
1075 CPU_BASED_HLT_EXITING /* 20.6.2 */
1076 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1077 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1078 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1079 | CPU_BASED_INVDPG_EXITING
1080 | CPU_BASED_MOV_DR_EXITING
1081 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1082 );
1083
1084 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1085 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1086 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1087 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1088
1089 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1090 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1091 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1092
1093 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1094 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1095 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1096 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1097 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1098 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1099#ifdef __x86_64__
1100 rdmsrl(MSR_FS_BASE, a);
1101 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1102 rdmsrl(MSR_GS_BASE, a);
1103 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1104#else
1105 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1106 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1107#endif
1108
1109 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1110
1111 get_idt(&dt);
1112 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1113
1114
1115 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1116
1117 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1118 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1119 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1120 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1121 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1122 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1123
1124 ret = -ENOMEM;
1125 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1126 if (!vcpu->guest_msrs)
1127 goto out;
1128 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1129 if (!vcpu->host_msrs)
1130 goto out_free_guest_msrs;
1131
1132 for (i = 0; i < NR_VMX_MSR; ++i) {
1133 u32 index = vmx_msr_index[i];
1134 u32 data_low, data_high;
1135 u64 data;
1136 int j = vcpu->nmsrs;
1137
1138 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1139 continue;
1140 data = data_low | ((u64)data_high << 32);
1141 vcpu->host_msrs[j].index = index;
1142 vcpu->host_msrs[j].reserved = 0;
1143 vcpu->host_msrs[j].data = data;
1144 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1145 ++vcpu->nmsrs;
1146 }
1147 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1148
1149 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1150 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1151 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1152 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1153 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1154 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1155 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1156 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS_MSR, VM_EXIT_CONTROLS,
1157 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1158 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1159 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1160 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1161
1162
1163 /* 22.2.1, 20.8.1 */
1164 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS_MSR,
1165 VM_ENTRY_CONTROLS, 0);
1166 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1167
1168 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1169 vmcs_writel(TPR_THRESHOLD, 0);
1170
1171 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1172 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1173
1174 vcpu->cr0 = 0x60000010;
1175 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1176 vmx_set_cr4(vcpu, 0);
1177#ifdef __x86_64__
1178 vmx_set_efer(vcpu, 0);
1179#endif
1180
1181 return 0;
1182
1183out_free_guest_msrs:
1184 kfree(vcpu->guest_msrs);
1185out:
1186 return ret;
1187}
1188
1189static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1190{
1191 u16 ent[2];
1192 u16 cs;
1193 u16 ip;
1194 unsigned long flags;
1195 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1196 u16 sp = vmcs_readl(GUEST_RSP);
1197 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1198
1199 if (sp > ss_limit || sp - 6 > sp) {
1200 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1201 __FUNCTION__,
1202 vmcs_readl(GUEST_RSP),
1203 vmcs_readl(GUEST_SS_BASE),
1204 vmcs_read32(GUEST_SS_LIMIT));
1205 return;
1206 }
1207
1208 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1209 sizeof(ent)) {
1210 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1211 return;
1212 }
1213
1214 flags = vmcs_readl(GUEST_RFLAGS);
1215 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1216 ip = vmcs_readl(GUEST_RIP);
1217
1218
1219 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1220 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1221 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1222 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1223 return;
1224 }
1225
1226 vmcs_writel(GUEST_RFLAGS, flags &
1227 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1228 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1229 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1230 vmcs_writel(GUEST_RIP, ent[0]);
1231 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1232}
1233
1234static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1235{
1236 int word_index = __ffs(vcpu->irq_summary);
1237 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1238 int irq = word_index * BITS_PER_LONG + bit_index;
1239
1240 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1241 if (!vcpu->irq_pending[word_index])
1242 clear_bit(word_index, &vcpu->irq_summary);
1243
1244 if (vcpu->rmode.active) {
1245 inject_rmode_irq(vcpu, irq);
1246 return;
1247 }
1248 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1249 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1250}
1251
1252static void kvm_try_inject_irq(struct kvm_vcpu *vcpu)
1253{
1254 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)
1255 && (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0)
1256 /*
1257 * Interrupts enabled, and not blocked by sti or mov ss. Good.
1258 */
1259 kvm_do_inject_irq(vcpu);
1260 else
1261 /*
1262 * Interrupts blocked. Wait for unblock.
1263 */
1264 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1265 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1266 | CPU_BASED_VIRTUAL_INTR_PENDING);
1267}
1268
1269static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1270{
1271 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1272
1273 set_debugreg(dbg->bp[0], 0);
1274 set_debugreg(dbg->bp[1], 1);
1275 set_debugreg(dbg->bp[2], 2);
1276 set_debugreg(dbg->bp[3], 3);
1277
1278 if (dbg->singlestep) {
1279 unsigned long flags;
1280
1281 flags = vmcs_readl(GUEST_RFLAGS);
1282 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1283 vmcs_writel(GUEST_RFLAGS, flags);
1284 }
1285}
1286
1287static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1288 int vec, u32 err_code)
1289{
1290 if (!vcpu->rmode.active)
1291 return 0;
1292
1293 if (vec == GP_VECTOR && err_code == 0)
1294 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1295 return 1;
1296 return 0;
1297}
1298
1299static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1300{
1301 u32 intr_info, error_code;
1302 unsigned long cr2, rip;
1303 u32 vect_info;
1304 enum emulation_result er;
1305
1306 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1307 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1308
1309 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1310 !is_page_fault(intr_info)) {
1311 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1312 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1313 }
1314
1315 if (is_external_interrupt(vect_info)) {
1316 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1317 set_bit(irq, vcpu->irq_pending);
1318 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1319 }
1320
1321 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1322 asm ("int $2");
1323 return 1;
1324 }
1325 error_code = 0;
1326 rip = vmcs_readl(GUEST_RIP);
1327 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1328 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1329 if (is_page_fault(intr_info)) {
1330 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1331
1332 spin_lock(&vcpu->kvm->lock);
1333 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1334 spin_unlock(&vcpu->kvm->lock);
1335 return 1;
1336 }
1337
1338 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1339 spin_unlock(&vcpu->kvm->lock);
1340
1341 switch (er) {
1342 case EMULATE_DONE:
1343 return 1;
1344 case EMULATE_DO_MMIO:
1345 ++kvm_stat.mmio_exits;
1346 kvm_run->exit_reason = KVM_EXIT_MMIO;
1347 return 0;
1348 case EMULATE_FAIL:
1349 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1350 break;
1351 default:
1352 BUG();
1353 }
1354 }
1355
1356 if (vcpu->rmode.active &&
1357 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1358 error_code))
1359 return 1;
1360
1361 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1362 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1363 return 0;
1364 }
1365 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1366 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1367 kvm_run->ex.error_code = error_code;
1368 return 0;
1369}
1370
1371static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1372 struct kvm_run *kvm_run)
1373{
1374 ++kvm_stat.irq_exits;
1375 return 1;
1376}
1377
1378
1379static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1380{
1381 u64 inst;
1382 gva_t rip;
1383 int countr_size;
1384 int i, n;
1385
1386 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1387 countr_size = 2;
1388 } else {
1389 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1390
1391 countr_size = (cs_ar & AR_L_MASK) ? 8:
1392 (cs_ar & AR_DB_MASK) ? 4: 2;
1393 }
1394
1395 rip = vmcs_readl(GUEST_RIP);
1396 if (countr_size != 8)
1397 rip += vmcs_readl(GUEST_CS_BASE);
1398
1399 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1400
1401 for (i = 0; i < n; i++) {
1402 switch (((u8*)&inst)[i]) {
1403 case 0xf0:
1404 case 0xf2:
1405 case 0xf3:
1406 case 0x2e:
1407 case 0x36:
1408 case 0x3e:
1409 case 0x26:
1410 case 0x64:
1411 case 0x65:
1412 case 0x66:
1413 break;
1414 case 0x67:
1415 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1416 default:
1417 goto done;
1418 }
1419 }
1420 return 0;
1421done:
1422 countr_size *= 8;
1423 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1424 return 1;
1425}
1426
1427static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1428{
1429 u64 exit_qualification;
1430
1431 ++kvm_stat.io_exits;
1432 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1433 kvm_run->exit_reason = KVM_EXIT_IO;
1434 if (exit_qualification & 8)
1435 kvm_run->io.direction = KVM_EXIT_IO_IN;
1436 else
1437 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1438 kvm_run->io.size = (exit_qualification & 7) + 1;
1439 kvm_run->io.string = (exit_qualification & 16) != 0;
1440 kvm_run->io.string_down
1441 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1442 kvm_run->io.rep = (exit_qualification & 32) != 0;
1443 kvm_run->io.port = exit_qualification >> 16;
1444 if (kvm_run->io.string) {
1445 if (!get_io_count(vcpu, &kvm_run->io.count))
1446 return 1;
1447 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1448 } else
1449 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1450 return 0;
1451}
1452
1453static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1454{
1455 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1456 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1457 spin_lock(&vcpu->kvm->lock);
1458 vcpu->mmu.inval_page(vcpu, address);
1459 spin_unlock(&vcpu->kvm->lock);
1460 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1461 return 1;
1462}
1463
1464static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1465{
1466 u64 exit_qualification;
1467 int cr;
1468 int reg;
1469
1470 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1471 cr = exit_qualification & 15;
1472 reg = (exit_qualification >> 8) & 15;
1473 switch ((exit_qualification >> 4) & 3) {
1474 case 0: /* mov to cr */
1475 switch (cr) {
1476 case 0:
1477 vcpu_load_rsp_rip(vcpu);
1478 set_cr0(vcpu, vcpu->regs[reg]);
1479 skip_emulated_instruction(vcpu);
1480 return 1;
1481 case 3:
1482 vcpu_load_rsp_rip(vcpu);
1483 set_cr3(vcpu, vcpu->regs[reg]);
1484 skip_emulated_instruction(vcpu);
1485 return 1;
1486 case 4:
1487 vcpu_load_rsp_rip(vcpu);
1488 set_cr4(vcpu, vcpu->regs[reg]);
1489 skip_emulated_instruction(vcpu);
1490 return 1;
1491 case 8:
1492 vcpu_load_rsp_rip(vcpu);
1493 set_cr8(vcpu, vcpu->regs[reg]);
1494 skip_emulated_instruction(vcpu);
1495 return 1;
1496 };
1497 break;
1498 case 1: /*mov from cr*/
1499 switch (cr) {
1500 case 3:
1501 vcpu_load_rsp_rip(vcpu);
1502 vcpu->regs[reg] = vcpu->cr3;
1503 vcpu_put_rsp_rip(vcpu);
1504 skip_emulated_instruction(vcpu);
1505 return 1;
1506 case 8:
1507 printk(KERN_DEBUG "handle_cr: read CR8 "
1508 "cpu erratum AA15\n");
1509 vcpu_load_rsp_rip(vcpu);
1510 vcpu->regs[reg] = vcpu->cr8;
1511 vcpu_put_rsp_rip(vcpu);
1512 skip_emulated_instruction(vcpu);
1513 return 1;
1514 }
1515 break;
1516 case 3: /* lmsw */
1517 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1518
1519 skip_emulated_instruction(vcpu);
1520 return 1;
1521 default:
1522 break;
1523 }
1524 kvm_run->exit_reason = 0;
1525 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1526 (int)(exit_qualification >> 4) & 3, cr);
1527 return 0;
1528}
1529
1530static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1531{
1532 u64 exit_qualification;
1533 unsigned long val;
1534 int dr, reg;
1535
1536 /*
1537 * FIXME: this code assumes the host is debugging the guest.
1538 * need to deal with guest debugging itself too.
1539 */
1540 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1541 dr = exit_qualification & 7;
1542 reg = (exit_qualification >> 8) & 15;
1543 vcpu_load_rsp_rip(vcpu);
1544 if (exit_qualification & 16) {
1545 /* mov from dr */
1546 switch (dr) {
1547 case 6:
1548 val = 0xffff0ff0;
1549 break;
1550 case 7:
1551 val = 0x400;
1552 break;
1553 default:
1554 val = 0;
1555 }
1556 vcpu->regs[reg] = val;
1557 } else {
1558 /* mov to dr */
1559 }
1560 vcpu_put_rsp_rip(vcpu);
1561 skip_emulated_instruction(vcpu);
1562 return 1;
1563}
1564
1565static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1566{
1567 kvm_run->exit_reason = KVM_EXIT_CPUID;
1568 return 0;
1569}
1570
1571static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1572{
1573 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1574 u64 data;
1575
1576 if (vmx_get_msr(vcpu, ecx, &data)) {
1577 vmx_inject_gp(vcpu, 0);
1578 return 1;
1579 }
1580
1581 /* FIXME: handling of bits 32:63 of rax, rdx */
1582 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1583 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1584 skip_emulated_instruction(vcpu);
1585 return 1;
1586}
1587
1588static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1589{
1590 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1591 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1592 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1593
1594 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1595 vmx_inject_gp(vcpu, 0);
1596 return 1;
1597 }
1598
1599 skip_emulated_instruction(vcpu);
1600 return 1;
1601}
1602
1603static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1604 struct kvm_run *kvm_run)
1605{
1606 /* Turn off interrupt window reporting. */
1607 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1608 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL)
1609 & ~CPU_BASED_VIRTUAL_INTR_PENDING);
1610 return 1;
1611}
1612
1613static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1614{
1615 skip_emulated_instruction(vcpu);
1616 if (vcpu->irq_summary && (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF))
1617 return 1;
1618
1619 kvm_run->exit_reason = KVM_EXIT_HLT;
1620 return 0;
1621}
1622
1623/*
1624 * The exit handlers return 1 if the exit was handled fully and guest execution
1625 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1626 * to be done to userspace and return 0.
1627 */
1628static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1629 struct kvm_run *kvm_run) = {
1630 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1631 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1632 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1633 [EXIT_REASON_INVLPG] = handle_invlpg,
1634 [EXIT_REASON_CR_ACCESS] = handle_cr,
1635 [EXIT_REASON_DR_ACCESS] = handle_dr,
1636 [EXIT_REASON_CPUID] = handle_cpuid,
1637 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1638 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1639 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1640 [EXIT_REASON_HLT] = handle_halt,
1641};
1642
1643static const int kvm_vmx_max_exit_handlers =
1644 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1645
1646/*
1647 * The guest has exited. See if we can fix it or if we need userspace
1648 * assistance.
1649 */
1650static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1651{
1652 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1653 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1654
1655 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1656 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1657 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1658 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1659 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1660 if (exit_reason < kvm_vmx_max_exit_handlers
1661 && kvm_vmx_exit_handlers[exit_reason])
1662 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1663 else {
1664 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1665 kvm_run->hw.hardware_exit_reason = exit_reason;
1666 }
1667 return 0;
1668}
1669
1670static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1671{
1672 u8 fail;
1673 u16 fs_sel, gs_sel, ldt_sel;
1674 int fs_gs_ldt_reload_needed;
1675
1676again:
1677 /*
1678 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1679 * allow segment selectors with cpl > 0 or ti == 1.
1680 */
1681 fs_sel = read_fs();
1682 gs_sel = read_gs();
1683 ldt_sel = read_ldt();
1684 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1685 if (!fs_gs_ldt_reload_needed) {
1686 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1687 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1688 } else {
1689 vmcs_write16(HOST_FS_SELECTOR, 0);
1690 vmcs_write16(HOST_GS_SELECTOR, 0);
1691 }
1692
1693#ifdef __x86_64__
1694 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1695 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1696#else
1697 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1698 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1699#endif
1700
1701 if (vcpu->irq_summary &&
1702 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1703 kvm_try_inject_irq(vcpu);
1704
1705 if (vcpu->guest_debug.enabled)
1706 kvm_guest_debug_pre(vcpu);
1707
1708 fx_save(vcpu->host_fx_image);
1709 fx_restore(vcpu->guest_fx_image);
1710
1711 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1712 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1713
1714 asm (
1715 /* Store host registers */
1716 "pushf \n\t"
1717#ifdef __x86_64__
1718 "push %%rax; push %%rbx; push %%rdx;"
1719 "push %%rsi; push %%rdi; push %%rbp;"
1720 "push %%r8; push %%r9; push %%r10; push %%r11;"
1721 "push %%r12; push %%r13; push %%r14; push %%r15;"
1722 "push %%rcx \n\t"
1723 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1724#else
1725 "pusha; push %%ecx \n\t"
1726 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1727#endif
1728 /* Check if vmlaunch of vmresume is needed */
1729 "cmp $0, %1 \n\t"
1730 /* Load guest registers. Don't clobber flags. */
1731#ifdef __x86_64__
1732 "mov %c[cr2](%3), %%rax \n\t"
1733 "mov %%rax, %%cr2 \n\t"
1734 "mov %c[rax](%3), %%rax \n\t"
1735 "mov %c[rbx](%3), %%rbx \n\t"
1736 "mov %c[rdx](%3), %%rdx \n\t"
1737 "mov %c[rsi](%3), %%rsi \n\t"
1738 "mov %c[rdi](%3), %%rdi \n\t"
1739 "mov %c[rbp](%3), %%rbp \n\t"
1740 "mov %c[r8](%3), %%r8 \n\t"
1741 "mov %c[r9](%3), %%r9 \n\t"
1742 "mov %c[r10](%3), %%r10 \n\t"
1743 "mov %c[r11](%3), %%r11 \n\t"
1744 "mov %c[r12](%3), %%r12 \n\t"
1745 "mov %c[r13](%3), %%r13 \n\t"
1746 "mov %c[r14](%3), %%r14 \n\t"
1747 "mov %c[r15](%3), %%r15 \n\t"
1748 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1749#else
1750 "mov %c[cr2](%3), %%eax \n\t"
1751 "mov %%eax, %%cr2 \n\t"
1752 "mov %c[rax](%3), %%eax \n\t"
1753 "mov %c[rbx](%3), %%ebx \n\t"
1754 "mov %c[rdx](%3), %%edx \n\t"
1755 "mov %c[rsi](%3), %%esi \n\t"
1756 "mov %c[rdi](%3), %%edi \n\t"
1757 "mov %c[rbp](%3), %%ebp \n\t"
1758 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1759#endif
1760 /* Enter guest mode */
1761 "jne launched \n\t"
1762 ASM_VMX_VMLAUNCH "\n\t"
1763 "jmp kvm_vmx_return \n\t"
1764 "launched: " ASM_VMX_VMRESUME "\n\t"
1765 ".globl kvm_vmx_return \n\t"
1766 "kvm_vmx_return: "
1767 /* Save guest registers, load host registers, keep flags */
1768#ifdef __x86_64__
1769 "xchg %3, 0(%%rsp) \n\t"
1770 "mov %%rax, %c[rax](%3) \n\t"
1771 "mov %%rbx, %c[rbx](%3) \n\t"
1772 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1773 "mov %%rdx, %c[rdx](%3) \n\t"
1774 "mov %%rsi, %c[rsi](%3) \n\t"
1775 "mov %%rdi, %c[rdi](%3) \n\t"
1776 "mov %%rbp, %c[rbp](%3) \n\t"
1777 "mov %%r8, %c[r8](%3) \n\t"
1778 "mov %%r9, %c[r9](%3) \n\t"
1779 "mov %%r10, %c[r10](%3) \n\t"
1780 "mov %%r11, %c[r11](%3) \n\t"
1781 "mov %%r12, %c[r12](%3) \n\t"
1782 "mov %%r13, %c[r13](%3) \n\t"
1783 "mov %%r14, %c[r14](%3) \n\t"
1784 "mov %%r15, %c[r15](%3) \n\t"
1785 "mov %%cr2, %%rax \n\t"
1786 "mov %%rax, %c[cr2](%3) \n\t"
1787 "mov 0(%%rsp), %3 \n\t"
1788
1789 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1790 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1791 "pop %%rbp; pop %%rdi; pop %%rsi;"
1792 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1793#else
1794 "xchg %3, 0(%%esp) \n\t"
1795 "mov %%eax, %c[rax](%3) \n\t"
1796 "mov %%ebx, %c[rbx](%3) \n\t"
1797 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1798 "mov %%edx, %c[rdx](%3) \n\t"
1799 "mov %%esi, %c[rsi](%3) \n\t"
1800 "mov %%edi, %c[rdi](%3) \n\t"
1801 "mov %%ebp, %c[rbp](%3) \n\t"
1802 "mov %%cr2, %%eax \n\t"
1803 "mov %%eax, %c[cr2](%3) \n\t"
1804 "mov 0(%%esp), %3 \n\t"
1805
1806 "pop %%ecx; popa \n\t"
1807#endif
1808 "setbe %0 \n\t"
1809 "popf \n\t"
1810 : "=g" (fail)
1811 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1812 "c"(vcpu),
1813 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1814 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1815 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1816 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1817 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1818 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1819 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1820#ifdef __x86_64__
1821 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1822 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1823 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1824 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1825 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1826 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1827 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1828 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1829#endif
1830 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1831 : "cc", "memory" );
1832
1833 ++kvm_stat.exits;
1834
1835 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1836 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1837
1838 fx_save(vcpu->guest_fx_image);
1839 fx_restore(vcpu->host_fx_image);
1840
1841#ifndef __x86_64__
1842 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1843#endif
1844
1845 kvm_run->exit_type = 0;
1846 if (fail) {
1847 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1848 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1849 } else {
1850 if (fs_gs_ldt_reload_needed) {
1851 load_ldt(ldt_sel);
1852 load_fs(fs_sel);
1853 /*
1854 * If we have to reload gs, we must take care to
1855 * preserve our gs base.
1856 */
1857 local_irq_disable();
1858 load_gs(gs_sel);
1859#ifdef __x86_64__
1860 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1861#endif
1862 local_irq_enable();
1863
1864 reload_tss();
1865 }
1866 vcpu->launched = 1;
1867 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1868 if (kvm_handle_exit(kvm_run, vcpu)) {
1869 /* Give scheduler a change to reschedule. */
1870 if (signal_pending(current)) {
1871 ++kvm_stat.signal_exits;
1872 return -EINTR;
1873 }
1874 kvm_resched(vcpu);
1875 goto again;
1876 }
1877 }
1878 return 0;
1879}
1880
1881static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1882{
1883 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1884}
1885
1886static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1887 unsigned long addr,
1888 u32 err_code)
1889{
1890 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1891
1892 ++kvm_stat.pf_guest;
1893
1894 if (is_page_fault(vect_info)) {
1895 printk(KERN_DEBUG "inject_page_fault: "
1896 "double fault 0x%lx @ 0x%lx\n",
1897 addr, vmcs_readl(GUEST_RIP));
1898 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1899 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1900 DF_VECTOR |
1901 INTR_TYPE_EXCEPTION |
1902 INTR_INFO_DELIEVER_CODE_MASK |
1903 INTR_INFO_VALID_MASK);
1904 return;
1905 }
1906 vcpu->cr2 = addr;
1907 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1908 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1909 PF_VECTOR |
1910 INTR_TYPE_EXCEPTION |
1911 INTR_INFO_DELIEVER_CODE_MASK |
1912 INTR_INFO_VALID_MASK);
1913
1914}
1915
1916static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1917{
1918 if (vcpu->vmcs) {
1919 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1920 free_vmcs(vcpu->vmcs);
1921 vcpu->vmcs = NULL;
1922 }
1923}
1924
1925static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1926{
1927 vmx_free_vmcs(vcpu);
1928}
1929
1930static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1931{
1932 struct vmcs *vmcs;
1933
1934 vmcs = alloc_vmcs();
1935 if (!vmcs)
1936 return -ENOMEM;
1937 vmcs_clear(vmcs);
1938 vcpu->vmcs = vmcs;
1939 vcpu->launched = 0;
1940 return 0;
1941}
1942
1943static struct kvm_arch_ops vmx_arch_ops = {
1944 .cpu_has_kvm_support = cpu_has_kvm_support,
1945 .disabled_by_bios = vmx_disabled_by_bios,
1946 .hardware_setup = hardware_setup,
1947 .hardware_unsetup = hardware_unsetup,
1948 .hardware_enable = hardware_enable,
1949 .hardware_disable = hardware_disable,
1950
1951 .vcpu_create = vmx_create_vcpu,
1952 .vcpu_free = vmx_free_vcpu,
1953
1954 .vcpu_load = vmx_vcpu_load,
1955 .vcpu_put = vmx_vcpu_put,
1956
1957 .set_guest_debug = set_guest_debug,
1958 .get_msr = vmx_get_msr,
1959 .set_msr = vmx_set_msr,
1960 .get_segment_base = vmx_get_segment_base,
1961 .get_segment = vmx_get_segment,
1962 .set_segment = vmx_set_segment,
1963 .is_long_mode = vmx_is_long_mode,
1964 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
1965 .set_cr0 = vmx_set_cr0,
1966 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
1967 .set_cr3 = vmx_set_cr3,
1968 .set_cr4 = vmx_set_cr4,
1969#ifdef __x86_64__
1970 .set_efer = vmx_set_efer,
1971#endif
1972 .get_idt = vmx_get_idt,
1973 .set_idt = vmx_set_idt,
1974 .get_gdt = vmx_get_gdt,
1975 .set_gdt = vmx_set_gdt,
1976 .cache_regs = vcpu_load_rsp_rip,
1977 .decache_regs = vcpu_put_rsp_rip,
1978 .get_rflags = vmx_get_rflags,
1979 .set_rflags = vmx_set_rflags,
1980
1981 .tlb_flush = vmx_flush_tlb,
1982 .inject_page_fault = vmx_inject_page_fault,
1983
1984 .inject_gp = vmx_inject_gp,
1985
1986 .run = vmx_vcpu_run,
1987 .skip_emulated_instruction = skip_emulated_instruction,
1988 .vcpu_setup = vmx_vcpu_setup,
1989};
1990
1991static int __init vmx_init(void)
1992{
1993 kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
1994 return 0;
1995}
1996
1997static void __exit vmx_exit(void)
1998{
1999 kvm_exit_arch();
2000}
2001
2002module_init(vmx_init)
2003module_exit(vmx_exit)
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