]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/media/pci/ivtv/ivtv-driver.h
sched/headers: Prepare to move signal wakeup & sigpending methods from <linux/sched...
[mirror_ubuntu-artful-kernel.git] / drivers / media / pci / ivtv / ivtv-driver.h
CommitLineData
1a0adaf3
HV
1/*
2 ivtv driver internal defines and structures
3 Copyright (C) 2003-2004 Kevin Thayer <nufan_wfk at yahoo.com>
4 Copyright (C) 2004 Chris Kennedy <c@groovy.org>
5 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef IVTV_DRIVER_H
23#define IVTV_DRIVER_H
24
bbdba43f
MCC
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
1a0adaf3
HV
27/* Internal header for ivtv project:
28 * Driver for the cx23415/6 chip.
29 * Author: Kevin Thayer (nufan_wfk at yahoo.com)
30 * License: GPL
31 * http://www.ivtvdriver.org
32 *
33 * -----
34 * MPG600/MPG160 support by T.Adachi <tadachi@tadachi-net.com>
35 * and Takeru KOMORIYA<komoriya@paken.org>
36 *
37 * AVerMedia M179 GPIO info by Chris Pinkham <cpinkham@bc2va.org>
38 * using information provided by Jiun-Kuei Jung @ AVerMedia.
39 */
40
174cd4b1
IM
41#include <linux/module.h>
42#include <linux/init.h>
1a0adaf3 43#include <linux/delay.h>
174cd4b1 44#include <linux/sched/signal.h>
1a0adaf3 45#include <linux/fs.h>
174cd4b1
IM
46#include <linux/pci.h>
47#include <linux/interrupt.h>
48#include <linux/spinlock.h>
1a0adaf3
HV
49#include <linux/i2c.h>
50#include <linux/i2c-algo-bit.h>
51#include <linux/list.h>
174cd4b1 52#include <linux/unistd.h>
1a0adaf3 53#include <linux/pagemap.h>
11763609 54#include <linux/scatterlist.h>
174cd4b1
IM
55#include <linux/kthread.h>
56#include <linux/mutex.h>
5a0e3ad6 57#include <linux/slab.h>
7c0f6ba6 58#include <linux/uaccess.h>
174cd4b1 59#include <asm/byteorder.h>
1a0adaf3 60
174cd4b1
IM
61#include <linux/dvb/video.h>
62#include <linux/dvb/audio.h>
1a0adaf3 63#include <media/v4l2-common.h>
174cd4b1 64#include <media/v4l2-ioctl.h>
f7b80e69 65#include <media/v4l2-ctrls.h>
67ec09fd 66#include <media/v4l2-device.h>
09250193 67#include <media/v4l2-fh.h>
174cd4b1
IM
68#include <media/tuner.h>
69#include <media/drv-intf/cx2341x.h>
70#include <media/i2c/ir-kbd-i2c.h>
71
72#include <linux/ivtv.h>
1a0adaf3 73
33c0fcad 74/* Memory layout */
1a0adaf3 75#define IVTV_ENCODER_OFFSET 0x00000000
33c0fcad 76#define IVTV_ENCODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */
1a0adaf3 77#define IVTV_DECODER_OFFSET 0x01000000
33c0fcad 78#define IVTV_DECODER_SIZE 0x00800000 /* Total size is 0x01000000, but only first half is used */
1a0adaf3
HV
79#define IVTV_REG_OFFSET 0x02000000
80#define IVTV_REG_SIZE 0x00010000
81
32db7754
HV
82/* Maximum ivtv driver instances. Some people have a huge number of
83 capture cards, so set this to a high value. */
84#define IVTV_MAX_CARDS 32
1a0adaf3 85
1a0adaf3
HV
86#define IVTV_ENC_STREAM_TYPE_MPG 0
87#define IVTV_ENC_STREAM_TYPE_YUV 1
88#define IVTV_ENC_STREAM_TYPE_VBI 2
89#define IVTV_ENC_STREAM_TYPE_PCM 3
90#define IVTV_ENC_STREAM_TYPE_RAD 4
91#define IVTV_DEC_STREAM_TYPE_MPG 5
92#define IVTV_DEC_STREAM_TYPE_VBI 6
93#define IVTV_DEC_STREAM_TYPE_VOUT 7
94#define IVTV_DEC_STREAM_TYPE_YUV 8
95#define IVTV_MAX_STREAMS 9
96
1a0adaf3
HV
97#define IVTV_DMA_SG_OSD_ENT (2883584/PAGE_SIZE) /* sg entities */
98
1a0adaf3
HV
99/* DMA Registers */
100#define IVTV_REG_DMAXFER (0x0000)
101#define IVTV_REG_DMASTATUS (0x0004)
102#define IVTV_REG_DECDMAADDR (0x0008)
103#define IVTV_REG_ENCDMAADDR (0x000c)
104#define IVTV_REG_DMACONTROL (0x0010)
105#define IVTV_REG_IRQSTATUS (0x0040)
106#define IVTV_REG_IRQMASK (0x0048)
107
108/* Setup Registers */
109#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
110#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
111#define IVTV_REG_DEC_SDRAM_REFRESH (0x08F8)
112#define IVTV_REG_DEC_SDRAM_PRECHARGE (0x08FC)
113#define IVTV_REG_VDM (0x2800)
114#define IVTV_REG_AO (0x2D00)
115#define IVTV_REG_BYTEFLUSH (0x2D24)
116#define IVTV_REG_SPU (0x9050)
117#define IVTV_REG_HW_BLOCKS (0x9054)
118#define IVTV_REG_VPU (0x9058)
119#define IVTV_REG_APU (0xA064)
120
4e1af31a
AW
121/* Other registers */
122#define IVTV_REG_DEC_LINE_FIELD (0x28C0)
123
1a0adaf3 124/* debugging */
33c0fcad 125extern int ivtv_debug;
914610e8
IA
126#ifdef CONFIG_VIDEO_ADV_DEBUG
127extern int ivtv_fw_debug;
128#endif
1a0adaf3 129
1aa32c2f
HV
130#define IVTV_DBGFLG_WARN (1 << 0)
131#define IVTV_DBGFLG_INFO (1 << 1)
132#define IVTV_DBGFLG_MB (1 << 2)
133#define IVTV_DBGFLG_IOCTL (1 << 3)
134#define IVTV_DBGFLG_FILE (1 << 4)
135#define IVTV_DBGFLG_DMA (1 << 5)
136#define IVTV_DBGFLG_IRQ (1 << 6)
137#define IVTV_DBGFLG_DEC (1 << 7)
138#define IVTV_DBGFLG_YUV (1 << 8)
139#define IVTV_DBGFLG_I2C (1 << 9)
bd58df6d 140/* Flag to turn on high volume debugging */
1aa32c2f 141#define IVTV_DBGFLG_HIGHVOL (1 << 10)
1a0adaf3 142
1a0adaf3
HV
143#define IVTV_DEBUG(x, type, fmt, args...) \
144 do { \
145 if ((x) & ivtv_debug) \
8ac05ae3 146 v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args); \
1a0adaf3 147 } while (0)
1aa32c2f
HV
148#define IVTV_DEBUG_WARN(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_WARN, "warn", fmt , ## args)
149#define IVTV_DEBUG_INFO(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_INFO, "info", fmt , ## args)
150#define IVTV_DEBUG_MB(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_MB, "mb", fmt , ## args)
151#define IVTV_DEBUG_DMA(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DMA, "dma", fmt , ## args)
1a0adaf3 152#define IVTV_DEBUG_IOCTL(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
1aa32c2f
HV
153#define IVTV_DEBUG_FILE(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_FILE, "file", fmt , ## args)
154#define IVTV_DEBUG_I2C(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_I2C, "i2c", fmt , ## args)
155#define IVTV_DEBUG_IRQ(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_IRQ, "irq", fmt , ## args)
156#define IVTV_DEBUG_DEC(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_DEC, "dec", fmt , ## args)
157#define IVTV_DEBUG_YUV(fmt, args...) IVTV_DEBUG(IVTV_DBGFLG_YUV, "yuv", fmt , ## args)
1a0adaf3 158
bd58df6d
HV
159#define IVTV_DEBUG_HIGH_VOL(x, type, fmt, args...) \
160 do { \
67ec09fd 161 if (((x) & ivtv_debug) && (ivtv_debug & IVTV_DBGFLG_HIGHVOL)) \
8ac05ae3 162 v4l2_info(&itv->v4l2_dev, " " type ": " fmt , ##args); \
bd58df6d 163 } while (0)
1aa32c2f
HV
164#define IVTV_DEBUG_HI_WARN(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_WARN, "warn", fmt , ## args)
165#define IVTV_DEBUG_HI_INFO(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_INFO, "info", fmt , ## args)
166#define IVTV_DEBUG_HI_MB(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_MB, "mb", fmt , ## args)
167#define IVTV_DEBUG_HI_DMA(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DMA, "dma", fmt , ## args)
bd58df6d 168#define IVTV_DEBUG_HI_IOCTL(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IOCTL, "ioctl", fmt , ## args)
1aa32c2f
HV
169#define IVTV_DEBUG_HI_FILE(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_FILE, "file", fmt , ## args)
170#define IVTV_DEBUG_HI_I2C(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_I2C, "i2c", fmt , ## args)
171#define IVTV_DEBUG_HI_IRQ(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_IRQ, "irq", fmt , ## args)
172#define IVTV_DEBUG_HI_DEC(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_DEC, "dec", fmt , ## args)
173#define IVTV_DEBUG_HI_YUV(fmt, args...) IVTV_DEBUG_HIGH_VOL(IVTV_DBGFLG_YUV, "yuv", fmt , ## args)
bd58df6d 174
1a0adaf3 175/* Standard kernel messages */
8ac05ae3
HV
176#define IVTV_ERR(fmt, args...) v4l2_err(&itv->v4l2_dev, fmt , ## args)
177#define IVTV_WARN(fmt, args...) v4l2_warn(&itv->v4l2_dev, fmt , ## args)
178#define IVTV_INFO(fmt, args...) v4l2_info(&itv->v4l2_dev, fmt , ## args)
1a0adaf3 179
1a0adaf3
HV
180/* output modes (cx23415 only) */
181#define OUT_NONE 0
182#define OUT_MPG 1
183#define OUT_YUV 2
184#define OUT_UDMA_YUV 3
185#define OUT_PASSTHROUGH 4
186
187#define IVTV_MAX_PGM_INDEX (400)
188
f412d36a
AW
189/* Default I2C SCL period in microseconds */
190#define IVTV_DEFAULT_I2C_CLOCK_PERIOD 20
191
1a0adaf3 192struct ivtv_options {
a158f355
HV
193 int kilobytes[IVTV_MAX_STREAMS]; /* size in kilobytes of each stream */
194 int cardtype; /* force card type on load */
195 int tuner; /* set tuner on load */
196 int radio; /* enable/disable radio */
197 int newi2c; /* new I2C algorithm */
f412d36a 198 int i2c_clock_period; /* period of SCL for I2C bus */
1a0adaf3
HV
199};
200
1a0adaf3
HV
201/* ivtv-specific mailbox template */
202struct ivtv_mailbox {
203 u32 flags;
204 u32 cmd;
205 u32 retval;
206 u32 timeout;
207 u32 data[CX2341X_MBOX_MAX_DATA];
208};
209
210struct ivtv_api_cache {
211 unsigned long last_jiffies; /* when last command was issued */
212 u32 data[CX2341X_MBOX_MAX_DATA]; /* last sent api data */
213};
214
215struct ivtv_mailbox_data {
216 volatile struct ivtv_mailbox __iomem *mbox;
217 /* Bits 0-2 are for the encoder mailboxes, 0-1 are for the decoder mailboxes.
218 If the bit is set, then the corresponding mailbox is in use by the driver. */
219 unsigned long busy;
220 u8 max_mbox;
221};
222
223/* per-buffer bit flags */
f4071b85 224#define IVTV_F_B_NEED_BUF_SWAP (1 << 0) /* this buffer should be byte swapped */
1a0adaf3
HV
225
226/* per-stream, s_flags */
227#define IVTV_F_S_DMA_PENDING 0 /* this stream has pending DMA */
228#define IVTV_F_S_DMA_HAS_VBI 1 /* the current DMA request also requests VBI data */
229#define IVTV_F_S_NEEDS_DATA 2 /* this decoding stream needs more data */
230
231#define IVTV_F_S_CLAIMED 3 /* this stream is claimed */
232#define IVTV_F_S_STREAMING 4 /* the fw is decoding/encoding this stream */
233#define IVTV_F_S_INTERNAL_USE 5 /* this stream is used internally (sliced VBI processing) */
234#define IVTV_F_S_PASSTHROUGH 6 /* this stream is in passthrough mode */
235#define IVTV_F_S_STREAMOFF 7 /* signal end of stream EOS */
236#define IVTV_F_S_APPL_IO 8 /* this stream is used read/written by an application */
237
dc02d50a
HV
238#define IVTV_F_S_PIO_PENDING 9 /* this stream has pending PIO */
239#define IVTV_F_S_PIO_HAS_VBI 1 /* the current PIO request also requests VBI data */
240
1a0adaf3 241/* per-ivtv, i_flags */
1e13f9e3
HV
242#define IVTV_F_I_DMA 0 /* DMA in progress */
243#define IVTV_F_I_UDMA 1 /* UDMA in progress */
244#define IVTV_F_I_UDMA_PENDING 2 /* UDMA pending */
a158f355
HV
245#define IVTV_F_I_SPEED_CHANGE 3 /* a speed change is in progress */
246#define IVTV_F_I_EOS 4 /* end of encoder stream reached */
247#define IVTV_F_I_RADIO_USER 5 /* the radio tuner is selected */
248#define IVTV_F_I_DIG_RST 6 /* reset digitizer */
1e13f9e3 249#define IVTV_F_I_DEC_YUV 7 /* YUV instead of MPG is being decoded */
1e13f9e3
HV
250#define IVTV_F_I_UPDATE_CC 9 /* CC should be updated */
251#define IVTV_F_I_UPDATE_WSS 10 /* WSS should be updated */
252#define IVTV_F_I_UPDATE_VPS 11 /* VPS should be updated */
253#define IVTV_F_I_DECODING_YUV 12 /* this stream is YUV frame decoding */
254#define IVTV_F_I_ENC_PAUSED 13 /* the encoder is paused */
1a0adaf3 255#define IVTV_F_I_VALID_DEC_TIMINGS 14 /* last_dec_timing is valid */
a158f355 256#define IVTV_F_I_HAVE_WORK 15 /* used in the interrupt handler: there is work to be done */
dc02d50a
HV
257#define IVTV_F_I_WORK_HANDLER_VBI 16 /* there is work to be done for VBI */
258#define IVTV_F_I_WORK_HANDLER_YUV 17 /* there is work to be done for YUV */
259#define IVTV_F_I_WORK_HANDLER_PIO 18 /* there is work to be done for PIO */
260#define IVTV_F_I_PIO 19 /* PIO in progress */
ac425144 261#define IVTV_F_I_DEC_PAUSED 20 /* the decoder is paused */
c976bc82
HV
262#define IVTV_F_I_INITED 21 /* set after first open */
263#define IVTV_F_I_FAILED 22 /* set if first open failed */
4313902e 264#define IVTV_F_I_WORK_HANDLER_PCM 23 /* there is work to be done for PCM */
1a0adaf3
HV
265
266/* Event notifications */
1e13f9e3
HV
267#define IVTV_F_I_EV_DEC_STOPPED 28 /* decoder stopped event */
268#define IVTV_F_I_EV_VSYNC 29 /* VSYNC event */
269#define IVTV_F_I_EV_VSYNC_FIELD 30 /* VSYNC event field (0 = first, 1 = second field) */
270#define IVTV_F_I_EV_VSYNC_ENABLED 31 /* VSYNC event enabled */
1a0adaf3
HV
271
272/* Scatter-Gather array element, used in DMA transfers */
37093b1e 273struct ivtv_sg_element {
b0510f8d
AV
274 __le32 src;
275 __le32 dst;
276 __le32 size;
277};
278
279struct ivtv_sg_host_element {
1a0adaf3
HV
280 u32 src;
281 u32 dst;
282 u32 size;
283};
284
285struct ivtv_user_dma {
286 struct mutex lock;
287 int page_count;
288 struct page *map[IVTV_DMA_SG_OSD_ENT];
0989fd2c
HV
289 /* Needed when dealing with highmem userspace buffers */
290 struct page *bouncemap[IVTV_DMA_SG_OSD_ENT];
1a0adaf3
HV
291
292 /* Base Dev SG Array for cx23415/6 */
37093b1e 293 struct ivtv_sg_element SGarray[IVTV_DMA_SG_OSD_ENT];
1a0adaf3
HV
294 dma_addr_t SG_handle;
295 int SG_length;
296
297 /* SG List of Buffers */
298 struct scatterlist SGlist[IVTV_DMA_SG_OSD_ENT];
299};
300
301struct ivtv_dma_page_info {
302 unsigned long uaddr;
303 unsigned long first;
304 unsigned long last;
305 unsigned int offset;
306 unsigned int tail;
307 int page_count;
308};
309
310struct ivtv_buffer {
311 struct list_head list;
312 dma_addr_t dma_handle;
f4071b85
HV
313 unsigned short b_flags;
314 unsigned short dma_xfer_cnt;
1a0adaf3 315 char *buf;
1a0adaf3
HV
316 u32 bytesused;
317 u32 readpos;
318};
319
320struct ivtv_queue {
a158f355
HV
321 struct list_head list; /* the list of buffers in this queue */
322 u32 buffers; /* number of buffers in this queue */
323 u32 length; /* total number of bytes of available buffer space */
324 u32 bytesused; /* total number of bytes used in this queue */
1a0adaf3
HV
325};
326
a158f355 327struct ivtv; /* forward reference */
1a0adaf3
HV
328
329struct ivtv_stream {
330 /* These first four fields are always set, even if the stream
331 is not actually created. */
635d62f0 332 struct video_device vdev; /* vdev.v4l2_dev is NULL if there is no device */
1a0adaf3
HV
333 struct ivtv *itv; /* for ease of use */
334 const char *name; /* name of the stream */
335 int type; /* stream type */
d0c8b2d4 336 u32 caps; /* V4L2 capabilities */
1a0adaf3 337
61bb725e 338 struct v4l2_fh *fh; /* pointer to the streaming filehandle */
a158f355
HV
339 spinlock_t qlock; /* locks access to the queues */
340 unsigned long s_flags; /* status flags, see above */
341 int dma; /* can be PCI_DMA_TODEVICE, PCI_DMA_FROMDEVICE or PCI_DMA_NONE */
37093b1e
HV
342 u32 pending_offset;
343 u32 pending_backup;
344 u64 pending_pts;
345
1a0adaf3
HV
346 u32 dma_offset;
347 u32 dma_backup;
348 u64 dma_pts;
349
350 int subtype;
351 wait_queue_head_t waitq;
352 u32 dma_last_offset;
353
354 /* Buffer Stats */
355 u32 buffers;
356 u32 buf_size;
357 u32 buffers_stolen;
358
359 /* Buffer Queues */
360 struct ivtv_queue q_free; /* free buffers */
361 struct ivtv_queue q_full; /* full buffers */
362 struct ivtv_queue q_io; /* waiting for I/O */
363 struct ivtv_queue q_dma; /* waiting for DMA */
364 struct ivtv_queue q_predma; /* waiting for DMA */
365
f4071b85
HV
366 /* DMA xfer counter, buffers belonging to the same DMA
367 xfer will have the same dma_xfer_cnt. */
368 u16 dma_xfer_cnt;
369
1a0adaf3 370 /* Base Dev SG Array for cx23415/6 */
b0510f8d
AV
371 struct ivtv_sg_host_element *sg_pending;
372 struct ivtv_sg_host_element *sg_processing;
37093b1e
HV
373 struct ivtv_sg_element *sg_dma;
374 dma_addr_t sg_handle;
375 int sg_pending_size;
376 int sg_processing_size;
377 int sg_processed;
1a0adaf3
HV
378
379 /* SG List of Buffers */
380 struct scatterlist *SGlist;
381};
382
383struct ivtv_open_id {
09250193 384 struct v4l2_fh fh;
a158f355
HV
385 int type; /* stream type */
386 int yuv_frames; /* 1: started OUT_UDMA_YUV output mode */
1a0adaf3
HV
387 struct ivtv *itv;
388};
389
09250193
HV
390static inline struct ivtv_open_id *fh2id(struct v4l2_fh *fh)
391{
392 return container_of(fh, struct ivtv_open_id, fh);
393}
394
1a0adaf3
HV
395struct yuv_frame_info
396{
397 u32 update;
33c0fcad
HV
398 s32 src_x;
399 s32 src_y;
400 u32 src_w;
401 u32 src_h;
402 s32 dst_x;
403 s32 dst_y;
404 u32 dst_w;
405 u32 dst_h;
406 s32 pan_x;
407 s32 pan_y;
1a0adaf3
HV
408 u32 vis_w;
409 u32 vis_h;
410 u32 interlaced_y;
411 u32 interlaced_uv;
33c0fcad 412 s32 tru_x;
1a0adaf3
HV
413 u32 tru_w;
414 u32 tru_h;
415 u32 offset_y;
33c0fcad 416 s32 lace_mode;
3b5c1c8e
IA
417 u32 sync_field;
418 u32 delay;
419 u32 interlaced;
1a0adaf3
HV
420};
421
422#define IVTV_YUV_MODE_INTERLACED 0x00
423#define IVTV_YUV_MODE_PROGRESSIVE 0x01
424#define IVTV_YUV_MODE_AUTO 0x02
425#define IVTV_YUV_MODE_MASK 0x03
426
427#define IVTV_YUV_SYNC_EVEN 0x00
428#define IVTV_YUV_SYNC_ODD 0x04
429#define IVTV_YUV_SYNC_MASK 0x04
430
a3e5f5e2
IA
431#define IVTV_YUV_BUFFERS 8
432
1a0adaf3
HV
433struct yuv_playback_info
434{
435 u32 reg_2834;
436 u32 reg_2838;
437 u32 reg_283c;
438 u32 reg_2840;
439 u32 reg_2844;
440 u32 reg_2848;
441 u32 reg_2854;
442 u32 reg_285c;
443 u32 reg_2864;
444
445 u32 reg_2870;
446 u32 reg_2874;
447 u32 reg_2890;
448 u32 reg_2898;
449 u32 reg_289c;
450
451 u32 reg_2918;
452 u32 reg_291c;
453 u32 reg_2920;
454 u32 reg_2924;
455 u32 reg_2928;
456 u32 reg_292c;
457 u32 reg_2930;
458
459 u32 reg_2934;
460
461 u32 reg_2938;
462 u32 reg_293c;
463 u32 reg_2940;
464 u32 reg_2944;
465 u32 reg_2948;
466 u32 reg_294c;
467 u32 reg_2950;
468 u32 reg_2954;
469 u32 reg_2958;
470 u32 reg_295c;
471 u32 reg_2960;
472 u32 reg_2964;
473 u32 reg_2968;
474 u32 reg_296c;
475
476 u32 reg_2970;
477
478 int v_filter_1;
479 int v_filter_2;
480 int h_filter;
481
88ab075a
IA
482 u8 track_osd; /* Should yuv output track the OSD size & position */
483
1a0adaf3
HV
484 u32 osd_x_offset;
485 u32 osd_y_offset;
486
487 u32 osd_x_pan;
488 u32 osd_y_pan;
489
490 u32 osd_vis_w;
491 u32 osd_vis_h;
492
77aded6b
IA
493 u32 osd_full_w;
494 u32 osd_full_h;
495
1a0adaf3
HV
496 int decode_height;
497
1a0adaf3
HV
498 int lace_mode;
499 int lace_threshold;
1a0adaf3
HV
500 int lace_sync_field;
501
502 atomic_t next_dma_frame;
503 atomic_t next_fill_frame;
504
505 u32 yuv_forced_update;
506 int update_frame;
bfd7beac 507
bfd7beac
IA
508 u8 fields_lapsed; /* Counter used when delaying a frame */
509
a3e5f5e2 510 struct yuv_frame_info new_frame_info[IVTV_YUV_BUFFERS];
1a0adaf3
HV
511 struct yuv_frame_info old_frame_info;
512 struct yuv_frame_info old_frame_info_args;
513
514 void *blanking_ptr;
515 dma_addr_t blanking_dmaptr;
c240ad00
IA
516
517 int stream_size;
a3e5f5e2
IA
518
519 u8 draw_frame; /* PVR350 buffer to draw into */
520 u8 max_frames_buffered; /* Maximum number of frames to buffer */
77aded6b
IA
521
522 struct v4l2_rect main_rect;
523 u32 v4l2_src_w;
524 u32 v4l2_src_h;
2bd7ac55
IA
525
526 u8 running; /* Have any frames been displayed */
1a0adaf3
HV
527};
528
529#define IVTV_VBI_FRAMES 32
530
531/* VBI data */
2f3a9893
HV
532struct vbi_cc {
533 u8 odd[2]; /* two-byte payload of odd field */
534 u8 even[2]; /* two-byte payload of even field */;
535};
536
537struct vbi_vps {
538 u8 data[5]; /* five-byte VPS payload */
539};
540
1a0adaf3 541struct vbi_info {
effa0b08
HV
542 /* VBI general data, does not change during streaming */
543
a158f355
HV
544 u32 raw_decoder_line_size; /* raw VBI line size from digitizer */
545 u8 raw_decoder_sav_odd_field; /* raw VBI Start Active Video digitizer code of odd field */
546 u8 raw_decoder_sav_even_field; /* raw VBI Start Active Video digitizer code of even field */
547 u32 sliced_decoder_line_size; /* sliced VBI line size from digitizer */
548 u8 sliced_decoder_sav_odd_field; /* sliced VBI Start Active Video digitizer code of odd field */
549 u8 sliced_decoder_sav_even_field; /* sliced VBI Start Active Video digitizer code of even field */
550
effa0b08
HV
551 u32 start[2]; /* start of first VBI line in the odd/even fields */
552 u32 count; /* number of VBI lines per field */
553 u32 raw_size; /* size of raw VBI line from the digitizer */
554 u32 sliced_size; /* size of sliced VBI line from the digitizer */
555
556 u32 dec_start; /* start in decoder memory of VBI re-insertion buffers */
557 u32 enc_start; /* start in encoder memory of VBI capture buffers */
558 u32 enc_size; /* size of VBI capture area */
559 int fpi; /* number of VBI frames per interrupt */
560
561 struct v4l2_format in; /* current VBI capture format */
562 struct v4l2_sliced_vbi_format *sliced_in; /* convenience pointer to sliced struct in vbi.in union */
563 int insert_mpeg; /* if non-zero, then embed VBI data in MPEG stream */
564
565 /* Raw VBI compatibility hack */
566
567 u32 frame; /* frame counter hack needed for backwards compatibility
568 of old VBI software */
569
570 /* Sliced VBI output data */
571
572 struct vbi_cc cc_payload[256]; /* sliced VBI CC payload array: it is an array to
2f3a9893 573 prevent dropping CC data if they couldn't be
effa0b08
HV
574 processed fast enough */
575 int cc_payload_idx; /* index in cc_payload */
576 u8 cc_missing_cnt; /* counts number of frames without CC for passthrough mode */
577 int wss_payload; /* sliced VBI WSS payload */
578 u8 wss_missing_cnt; /* counts number of frames without WSS for passthrough mode */
579 struct vbi_vps vps_payload; /* sliced VBI VPS payload */
580
581 /* Sliced VBI capture data */
582
583 struct v4l2_sliced_vbi_data sliced_data[36]; /* sliced VBI storage for VBI encoder stream */
584 struct v4l2_sliced_vbi_data sliced_dec_data[36];/* sliced VBI storage for VBI decoder stream */
585
586 /* VBI Embedding data */
1a0adaf3
HV
587
588 /* Buffer for VBI data inserted into MPEG stream.
589 The first byte is a dummy byte that's never used.
590 The next 16 bytes contain the MPEG header for the VBI data,
591 the remainder is the actual VBI data.
592 The max size accepted by the MPEG VBI reinsertion turns out
593 to be 1552 bytes, which happens to be 4 + (1 + 42) * (2 * 18) bytes,
594 where 4 is a four byte header, 42 is the max sliced VBI payload, 1 is
595 a single line header byte and 2 * 18 is the number of VBI lines per frame.
596
597 However, it seems that the data must be 1K aligned, so we have to
598 pad the data until the 1 or 2 K boundary.
599
600 This pointer array will allocate 2049 bytes to store each VBI frame. */
601 u8 *sliced_mpeg_data[IVTV_VBI_FRAMES];
602 u32 sliced_mpeg_size[IVTV_VBI_FRAMES];
effa0b08
HV
603 struct ivtv_buffer sliced_mpeg_buf; /* temporary buffer holding data from sliced_mpeg_data */
604 u32 inserted_frame; /* index in sliced_mpeg_size of next sliced data
605 to be inserted in the MPEG stream */
1a0adaf3
HV
606};
607
608/* forward declaration of struct defined in ivtv-cards.h */
609struct ivtv_card;
610
611/* Struct to hold info about ivtv cards */
612struct ivtv {
fd8b281a 613 /* General fixed card data */
8ac05ae3 614 struct pci_dev *pdev; /* PCI device */
1a0adaf3 615 const struct ivtv_card *card; /* card information */
fd8b281a 616 const char *card_name; /* full name of the card */
d9009201 617 const struct ivtv_card_tuner_i2c *card_i2c; /* i2c addresses to probe for tuner */
fd8b281a
HV
618 u8 has_cx23415; /* 1 if it is a cx23415 based card, 0 for cx23416 */
619 u8 pvr150_workaround; /* 1 if the cx25840 needs to workaround a PVR150 bug */
620 u8 nof_inputs; /* number of video inputs */
621 u8 nof_audio_inputs; /* number of audio inputs */
622 u32 v4l2_cap; /* V4L2 capabilities of card */
623 u32 hw_flags; /* hardware description of the board */
fd8b281a 624 v4l2_std_id tuner_std; /* the norm of the card's tuner (fixed) */
67ec09fd
HV
625 struct v4l2_subdev *sd_video; /* controlling video decoder subdev */
626 struct v4l2_subdev *sd_audio; /* controlling audio subdev */
627 struct v4l2_subdev *sd_muxer; /* controlling audio muxer subdev */
1c36dfc5 628 resource_size_t base_addr; /* PCI resource base address */
fd8b281a
HV
629 volatile void __iomem *enc_mem; /* pointer to mapped encoder memory */
630 volatile void __iomem *dec_mem; /* pointer to mapped decoder memory */
631 volatile void __iomem *reg_mem; /* pointer to mapped registers */
632 struct ivtv_options options; /* user options */
633
8ac05ae3 634 struct v4l2_device v4l2_dev;
f7b80e69 635 struct cx2341x_handler cxhdl;
debf8001
HV
636 struct {
637 /* PTS/Frame count control cluster */
638 struct v4l2_ctrl *ctrl_pts;
639 struct v4l2_ctrl *ctrl_frame;
640 };
641 struct {
642 /* Audio Playback control cluster */
643 struct v4l2_ctrl *ctrl_audio_playback;
644 struct v4l2_ctrl *ctrl_audio_multilingual_playback;
645 };
2fd78144 646 struct v4l2_ctrl_handler hdl_gpio;
f7b80e69 647 struct v4l2_subdev sd_gpio; /* GPIO sub-device */
67ec09fd 648 u16 instance;
fd8b281a
HV
649
650 /* High-level state info */
651 unsigned long i_flags; /* global ivtv flags */
652 u8 is_50hz; /* 1 if the current capture standard is 50 Hz */
653 u8 is_60hz /* 1 if the current capture standard is 60 Hz */;
654 u8 is_out_50hz /* 1 if the current TV output standard is 50 Hz */;
655 u8 is_out_60hz /* 1 if the current TV output standard is 60 Hz */;
656 int output_mode; /* decoder output mode: NONE, MPG, YUV, UDMA YUV, passthrough */
657 u32 audio_input; /* current audio input */
658 u32 active_input; /* current video input */
659 u32 active_output; /* current video output */
660 v4l2_std_id std; /* current capture TV standard */
661 v4l2_std_id std_out; /* current TV output standard */
662 u8 audio_stereo_mode; /* decoder setting how to handle stereo MPEG audio */
663 u8 audio_bilingual_mode; /* decoder setting how to handle bilingual MPEG audio */
fd8b281a 664
fd8b281a
HV
665 /* Locking */
666 spinlock_t lock; /* lock access to this struct */
a158f355 667 struct mutex serialize_lock; /* mutex used to serialize open/close/start/stop/ioctl operations */
fd8b281a 668
fd8b281a
HV
669 /* Streams */
670 int stream_buf_size[IVTV_MAX_STREAMS]; /* stream buffer size */
671 struct ivtv_stream streams[IVTV_MAX_STREAMS]; /* stream data */
672 atomic_t capturing; /* count number of active capture streams */
673 atomic_t decoding; /* count number of active decoding streams */
674
269c11fb
AW
675 /* ALSA interface for PCM capture stream */
676 struct snd_ivtv_card *alsa;
677 void (*pcm_announce_callback)(struct snd_ivtv_card *card, u8 *pcm_data,
678 size_t num_bytes);
679
680 /* Used for ivtv-alsa module loading */
681 struct work_struct request_module_wk;
fd8b281a
HV
682
683 /* Interrupts & DMA */
684 u32 irqmask; /* active interrupts */
685 u32 irq_rr_idx; /* round-robin stream index */
7bc46560
TH
686 struct kthread_worker irq_worker; /* kthread worker for PIO/YUV/VBI actions */
687 struct task_struct *irq_worker_task; /* task for irq_worker */
688 struct kthread_work irq_work; /* kthread work entry */
fd8b281a
HV
689 spinlock_t dma_reg_lock; /* lock access to DMA engine registers */
690 int cur_dma_stream; /* index of current stream doing DMA (-1 if none) */
691 int cur_pio_stream; /* index of current stream doing PIO (-1 if none) */
692 u32 dma_data_req_offset; /* store offset in decoder memory of current DMA request */
693 u32 dma_data_req_size; /* store size of current DMA request */
694 int dma_retries; /* current DMA retry attempt */
695 struct ivtv_user_dma udma; /* user based DMA for OSD */
696 struct timer_list dma_timer; /* timer used to catch unfinished DMAs */
a158f355 697 u32 last_vsync_field; /* last seen vsync field */
fd8b281a
HV
698 wait_queue_head_t dma_waitq; /* wake up when the current DMA is finished */
699 wait_queue_head_t eos_waitq; /* wake up when EOS arrives */
700 wait_queue_head_t event_waitq; /* wake up when the next decoder event arrives */
701 wait_queue_head_t vsync_waitq; /* wake up when the next decoder vsync arrives */
702
703
704 /* Mailbox */
705 struct ivtv_mailbox_data enc_mbox; /* encoder mailboxes */
706 struct ivtv_mailbox_data dec_mbox; /* decoder mailboxes */
707 struct ivtv_api_cache api_cache[256]; /* cached API commands */
708
709
710 /* I2C */
711 struct i2c_adapter i2c_adap;
712 struct i2c_algo_bit_data i2c_algo;
713 struct i2c_client i2c_client;
fd8b281a
HV
714 int i2c_state; /* i2c bit state */
715 struct mutex i2c_bus_lock; /* lock i2c bus */
716
ad2fe2d4 717 struct IR_i2c_init_data ir_i2c_init_data;
fd8b281a
HV
718
719 /* Program Index information */
720 u32 pgm_info_offset; /* start of pgm info in encoder memory */
721 u32 pgm_info_num; /* number of elements in the pgm cyclic buffer in encoder memory */
722 u32 pgm_info_write_idx; /* last index written by the card that was transferred to pgm_info[] */
723 u32 pgm_info_read_idx; /* last index in pgm_info read by the application */
724 struct v4l2_enc_idx_entry pgm_info[IVTV_MAX_PGM_INDEX]; /* filled from the pgm cyclic buffer on the card */
725
726
727 /* Miscellaneous */
728 u32 open_id; /* incremented each time an open occurs, is >= 1 */
fd8b281a
HV
729 int search_pack_header; /* 1 if ivtv_copy_buf_to_user() is scanning for a pack header (0xba) */
730 int speed; /* current playback speed setting */
731 u8 speed_mute_audio; /* 1 if audio should be muted when fast forward */
732 u64 mpg_data_received; /* number of bytes received from the MPEG stream */
733 u64 vbi_data_inserted; /* number of VBI bytes inserted into the MPEG stream */
734 u32 last_dec_timing[3]; /* cache last retrieved pts/scr/frame values */
735 unsigned long dualwatch_jiffies;/* jiffies value of the previous dualwatch check */
0d82fe80 736 u32 dualwatch_stereo_mode; /* current detected dualwatch stereo mode */
fd8b281a
HV
737
738
739 /* VBI state info */
740 struct vbi_info vbi; /* VBI-specific data */
741
742
743 /* YUV playback */
744 struct yuv_playback_info yuv_info; /* YUV playback data */
1a0adaf3 745
1a0adaf3
HV
746
747 /* OSD support */
748 unsigned long osd_video_pbase;
fd8b281a
HV
749 int osd_global_alpha_state; /* 1 = global alpha is on */
750 int osd_local_alpha_state; /* 1 = local alpha is on */
751 int osd_chroma_key_state; /* 1 = chroma-keying is on */
752 u8 osd_global_alpha; /* current global alpha */
753 u32 osd_chroma_key; /* current chroma key */
fd8b281a
HV
754 struct v4l2_rect osd_rect; /* current OSD position and size */
755 struct v4l2_rect main_rect; /* current Main window position and size */
7b3a0d49 756 struct osd_info *osd_info; /* ivtvfb private OSD info */
215659d1 757 void (*ivtvfb_restore)(struct ivtv *itv); /* Used for a warm start */
1a0adaf3
HV
758};
759
8ac05ae3 760static inline struct ivtv *to_ivtv(struct v4l2_device *v4l2_dev)
67ec09fd 761{
8ac05ae3 762 return container_of(v4l2_dev, struct ivtv, v4l2_dev);
67ec09fd
HV
763}
764
269c11fb
AW
765/* ivtv extensions to be loaded */
766extern int (*ivtv_ext_init)(struct ivtv *);
767
1a0adaf3 768/* Globals */
1a0adaf3 769extern int ivtv_first_minor;
1a0adaf3
HV
770
771/*==============Prototypes==================*/
772
773/* Hardware/IRQ */
774void ivtv_set_irq_mask(struct ivtv *itv, u32 mask);
775void ivtv_clear_irq_mask(struct ivtv *itv, u32 mask);
776
777/* try to set output mode, return current mode. */
778int ivtv_set_output_mode(struct ivtv *itv, int mode);
779
780/* return current output stream based on current mode */
781struct ivtv_stream *ivtv_get_output_stream(struct ivtv *itv);
782
783/* Return non-zero if a signal is pending */
201700d3 784int ivtv_msleep_timeout(unsigned int msecs, int intr);
1a0adaf3
HV
785
786/* Wait on queue, returns -EINTR if interrupted */
787int ivtv_waitq(wait_queue_head_t *waitq);
788
789/* Read Hauppauge eeprom */
790struct tveeprom; /* forward reference */
791void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv);
792
c976bc82
HV
793/* First-open initialization: load firmware, init cx25840, etc. */
794int ivtv_init_on_first_open(struct ivtv *itv);
795
a8b86435
HV
796/* Test if the current VBI mode is raw (1) or sliced (0) */
797static inline int ivtv_raw_vbi(const struct ivtv *itv)
798{
799 return itv->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
800}
801
1a0adaf3
HV
802/* This is a PCI post thing, where if the pci register is not read, then
803 the write doesn't always take effect right away. By reading back the
804 register any pending PCI writes will be performed (in order), and so
805 you can be sure that the writes are guaranteed to be done.
806
807 Rarely needed, only in some timing sensitive cases.
808 Apparently if this is not done some motherboards seem
809 to kill the firmware and get into the broken state until computer is
810 rebooted. */
811#define write_sync(val, reg) \
812 do { writel(val, reg); readl(reg); } while (0)
813
814#define read_reg(reg) readl(itv->reg_mem + (reg))
815#define write_reg(val, reg) writel(val, itv->reg_mem + (reg))
816#define write_reg_sync(val, reg) \
817 do { write_reg(val, reg); read_reg(reg); } while (0)
818
819#define read_enc(addr) readl(itv->enc_mem + (u32)(addr))
820#define write_enc(val, addr) writel(val, itv->enc_mem + (u32)(addr))
821#define write_enc_sync(val, addr) \
822 do { write_enc(val, addr); read_enc(addr); } while (0)
823
824#define read_dec(addr) readl(itv->dec_mem + (u32)(addr))
825#define write_dec(val, addr) writel(val, itv->dec_mem + (u32)(addr))
826#define write_dec_sync(val, addr) \
827 do { write_dec(val, addr); read_dec(addr); } while (0)
828
67ec09fd
HV
829/* Call the specified callback for all subdevs matching hw (if 0, then
830 match them all). Ignore any errors. */
831#define ivtv_call_hw(itv, hw, o, f, args...) \
fe293011 832 v4l2_device_mask_call_all(&(itv)->v4l2_dev, hw, o, f, ##args)
67ec09fd
HV
833
834#define ivtv_call_all(itv, o, f, args...) ivtv_call_hw(itv, 0, o, f , ##args)
835
836/* Call the specified callback for all subdevs matching hw (if 0, then
837 match them all). If the callback returns an error other than 0 or
838 -ENOIOCTLCMD, then return with that error code. */
6c2d4dd1 839#define ivtv_call_hw_err(itv, hw, o, f, args...) \
fe293011 840 v4l2_device_mask_call_until_err(&(itv)->v4l2_dev, hw, o, f, ##args)
67ec09fd
HV
841
842#define ivtv_call_all_err(itv, o, f, args...) ivtv_call_hw_err(itv, 0, o, f , ##args)
843
612570f2 844#endif