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amd-xgbe: Support defining PHY resources in ETH device node
[mirror_ubuntu-artful-kernel.git] / drivers / net / ethernet / amd / xgbe / xgbe-mdio.c
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c5aa9e3b
LT		 1/*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117#include <linux/module.h>
118#include <linux/kmod.h>
c5aa9e3b
LT		 119#include <linux/mdio.h>
120#include <linux/phy.h>
121#include <linux/of.h>
7c12aa08
LT		 122#include <linux/bitops.h>
123#include <linux/jiffies.h>
c5aa9e3b
LT		 124
125#include "xgbe.h"
126#include "xgbe-common.h"
127
7c12aa08 128static void xgbe_an_enable_kr_training(struct xgbe_prv_data *pdata)
c5aa9e3b 129{
7c12aa08 130 unsigned int reg;
c5aa9e3b 131
7c12aa08 132 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
c5aa9e3b 133
7c12aa08
LT		 134 reg |= XGBE_KR_TRAINING_ENABLE;
135 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
136}
137
138static void xgbe_an_disable_kr_training(struct xgbe_prv_data *pdata)
139{
140 unsigned int reg;
141
142 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
143
144 reg &= ~XGBE_KR_TRAINING_ENABLE;
145 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
146}
147
148static void xgbe_pcs_power_cycle(struct xgbe_prv_data *pdata)
149{
150 unsigned int reg;
151
152 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
153
154 reg |= MDIO_CTRL1_LPOWER;
155 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
156
157 usleep_range(75, 100);
158
159 reg &= ~MDIO_CTRL1_LPOWER;
160 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
161}
162
163static void xgbe_serdes_start_ratechange(struct xgbe_prv_data *pdata)
164{
165 /* Assert Rx and Tx ratechange */
166 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1);
167}
168
169static void xgbe_serdes_complete_ratechange(struct xgbe_prv_data *pdata)
170{
171 unsigned int wait;
172 u16 status;
173
174 /* Release Rx and Tx ratechange */
175 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0);
176
177 /* Wait for Rx and Tx ready */
178 wait = XGBE_RATECHANGE_COUNT;
179 while (wait--) {
180 usleep_range(50, 75);
181
182 status = XSIR0_IOREAD(pdata, SIR0_STATUS);
183 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
184 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
185 goto rx_reset;
186 }
187
188 netdev_dbg(pdata->netdev, "SerDes rx/tx not ready (%#hx)\n",
189 status);
190
191rx_reset:
192 /* Perform Rx reset for the DFE changes */
193 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0);
194 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1);
195}
196
197static void xgbe_xgmii_mode(struct xgbe_prv_data *pdata)
198{
199 unsigned int reg;
200
201 /* Enable KR training */
202 xgbe_an_enable_kr_training(pdata);
203
204 /* Set MAC to 10G speed */
205 pdata->hw_if.set_xgmii_speed(pdata);
206
207 /* Set PCS to KR/10G speed */
208 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
209 reg &= ~MDIO_PCS_CTRL2_TYPE;
210 reg |= MDIO_PCS_CTRL2_10GBR;
211 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
212
213 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
214 reg &= ~MDIO_CTRL1_SPEEDSEL;
215 reg |= MDIO_CTRL1_SPEED10G;
216 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
217
218 xgbe_pcs_power_cycle(pdata);
219
220 /* Set SerDes to 10G speed */
221 xgbe_serdes_start_ratechange(pdata);
222
223 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE);
224 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD);
225 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL);
226
227 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
228 pdata->serdes_cdr_rate[XGBE_SPEED_10000]);
229 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
230 pdata->serdes_tx_amp[XGBE_SPEED_10000]);
231 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
232 pdata->serdes_blwc[XGBE_SPEED_10000]);
233 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
234 pdata->serdes_pq_skew[XGBE_SPEED_10000]);
235 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
236 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_10000]);
237 XRXTX_IOWRITE(pdata, RXTX_REG22,
238 pdata->serdes_dfe_tap_ena[XGBE_SPEED_10000]);
239
240 xgbe_serdes_complete_ratechange(pdata);
241}
242
243static void xgbe_gmii_2500_mode(struct xgbe_prv_data *pdata)
244{
245 unsigned int reg;
246
247 /* Disable KR training */
248 xgbe_an_disable_kr_training(pdata);
249
250 /* Set MAC to 2.5G speed */
251 pdata->hw_if.set_gmii_2500_speed(pdata);
252
253 /* Set PCS to KX/1G speed */
254 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
255 reg &= ~MDIO_PCS_CTRL2_TYPE;
256 reg |= MDIO_PCS_CTRL2_10GBX;
257 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
258
259 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
260 reg &= ~MDIO_CTRL1_SPEEDSEL;
261 reg |= MDIO_CTRL1_SPEED1G;
262 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
263
264 xgbe_pcs_power_cycle(pdata);
265
266 /* Set SerDes to 2.5G speed */
267 xgbe_serdes_start_ratechange(pdata);
268
269 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE);
270 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD);
271 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL);
272
273 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
274 pdata->serdes_cdr_rate[XGBE_SPEED_2500]);
275 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
276 pdata->serdes_tx_amp[XGBE_SPEED_2500]);
277 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
278 pdata->serdes_blwc[XGBE_SPEED_2500]);
279 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
280 pdata->serdes_pq_skew[XGBE_SPEED_2500]);
281 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
282 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_2500]);
283 XRXTX_IOWRITE(pdata, RXTX_REG22,
284 pdata->serdes_dfe_tap_ena[XGBE_SPEED_2500]);
285
286 xgbe_serdes_complete_ratechange(pdata);
287}
288
289static void xgbe_gmii_mode(struct xgbe_prv_data *pdata)
290{
291 unsigned int reg;
292
293 /* Disable KR training */
294 xgbe_an_disable_kr_training(pdata);
295
296 /* Set MAC to 1G speed */
297 pdata->hw_if.set_gmii_speed(pdata);
298
299 /* Set PCS to KX/1G speed */
300 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
301 reg &= ~MDIO_PCS_CTRL2_TYPE;
302 reg |= MDIO_PCS_CTRL2_10GBX;
303 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg);
304
305 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
306 reg &= ~MDIO_CTRL1_SPEEDSEL;
307 reg |= MDIO_CTRL1_SPEED1G;
308 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
309
310 xgbe_pcs_power_cycle(pdata);
311
312 /* Set SerDes to 1G speed */
313 xgbe_serdes_start_ratechange(pdata);
314
315 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE);
316 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD);
317 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL);
318
319 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE,
320 pdata->serdes_cdr_rate[XGBE_SPEED_1000]);
321 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP,
322 pdata->serdes_tx_amp[XGBE_SPEED_1000]);
323 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA,
324 pdata->serdes_blwc[XGBE_SPEED_1000]);
325 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG,
326 pdata->serdes_pq_skew[XGBE_SPEED_1000]);
327 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG,
328 pdata->serdes_dfe_tap_cfg[XGBE_SPEED_1000]);
329 XRXTX_IOWRITE(pdata, RXTX_REG22,
330 pdata->serdes_dfe_tap_ena[XGBE_SPEED_1000]);
331
332 xgbe_serdes_complete_ratechange(pdata);
333}
334
335static void xgbe_cur_mode(struct xgbe_prv_data *pdata,
336 enum xgbe_mode *mode)
337{
338 unsigned int reg;
339
340 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2);
341 if ((reg & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
342 *mode = XGBE_MODE_KR;
343 else
344 *mode = XGBE_MODE_KX;
345}
346
347static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
348{
349 enum xgbe_mode mode;
350
351 xgbe_cur_mode(pdata, &mode);
352
353 return (mode == XGBE_MODE_KR);
354}
355
356static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
357{
358 /* If we are in KR switch to KX, and vice-versa */
359 if (xgbe_in_kr_mode(pdata)) {
360 if (pdata->speed_set == XGBE_SPEEDSET_1000_10000)
361 xgbe_gmii_mode(pdata);
362 else
363 xgbe_gmii_2500_mode(pdata);
364 } else {
365 xgbe_xgmii_mode(pdata);
366 }
367}
368
369static void xgbe_set_mode(struct xgbe_prv_data *pdata,
370 enum xgbe_mode mode)
371{
372 enum xgbe_mode cur_mode;
373
374 xgbe_cur_mode(pdata, &cur_mode);
375 if (mode != cur_mode)
376 xgbe_switch_mode(pdata);
377}
378
379static void xgbe_set_an(struct xgbe_prv_data *pdata, bool enable, bool restart)
380{
381 unsigned int reg;
382
383 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
384 reg &= ~MDIO_AN_CTRL1_ENABLE;
385
386 if (enable)
387 reg |= MDIO_AN_CTRL1_ENABLE;
388
389 if (restart)
390 reg |= MDIO_AN_CTRL1_RESTART;
391
392 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
393}
394
395static void xgbe_restart_an(struct xgbe_prv_data *pdata)
396{
397 xgbe_set_an(pdata, true, true);
398}
399
400static void xgbe_disable_an(struct xgbe_prv_data *pdata)
401{
402 xgbe_set_an(pdata, false, false);
403}
404
405static enum xgbe_an xgbe_an_tx_training(struct xgbe_prv_data *pdata,
406 enum xgbe_rx *state)
407{
408 unsigned int ad_reg, lp_reg, reg;
409
410 *state = XGBE_RX_COMPLETE;
411
412 /* If we're not in KR mode then we're done */
413 if (!xgbe_in_kr_mode(pdata))
414 return XGBE_AN_PAGE_RECEIVED;
415
416 /* Enable/Disable FEC */
417 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
418 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
419
420 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
421 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
422 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
423 reg |= pdata->fec_ability;
424
425 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
426
427 /* Start KR training */
428 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
429 if (reg & XGBE_KR_TRAINING_ENABLE) {
430 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1);
431
432 reg |= XGBE_KR_TRAINING_START;
433 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
434 reg);
435
436 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0);
437 }
438
439 return XGBE_AN_PAGE_RECEIVED;
440}
441
442static enum xgbe_an xgbe_an_tx_xnp(struct xgbe_prv_data *pdata,
443 enum xgbe_rx *state)
444{
445 u16 msg;
446
447 *state = XGBE_RX_XNP;
448
449 msg = XGBE_XNP_MCF_NULL_MESSAGE;
450 msg |= XGBE_XNP_MP_FORMATTED;
451
452 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
453 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
454 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
455
456 return XGBE_AN_PAGE_RECEIVED;
457}
458
459static enum xgbe_an xgbe_an_rx_bpa(struct xgbe_prv_data *pdata,
460 enum xgbe_rx *state)
461{
462 unsigned int link_support;
463 unsigned int reg, ad_reg, lp_reg;
464
465 /* Read Base Ability register 2 first */
466 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
467
468 /* Check for a supported mode, otherwise restart in a different one */
469 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
470 if (!(reg & link_support))
471 return XGBE_AN_INCOMPAT_LINK;
472
473 /* Check Extended Next Page support */
474 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
475 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
476
477 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
478 (lp_reg & XGBE_XNP_NP_EXCHANGE))
479 ? xgbe_an_tx_xnp(pdata, state)
480 : xgbe_an_tx_training(pdata, state);
481}
482
483static enum xgbe_an xgbe_an_rx_xnp(struct xgbe_prv_data *pdata,
484 enum xgbe_rx *state)
485{
486 unsigned int ad_reg, lp_reg;
487
488 /* Check Extended Next Page support */
489 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
490 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
491
492 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
493 (lp_reg & XGBE_XNP_NP_EXCHANGE))
494 ? xgbe_an_tx_xnp(pdata, state)
495 : xgbe_an_tx_training(pdata, state);
496}
497
498static enum xgbe_an xgbe_an_page_received(struct xgbe_prv_data *pdata)
499{
500 enum xgbe_rx *state;
501 unsigned long an_timeout;
502 enum xgbe_an ret;
503
504 if (!pdata->an_start) {
505 pdata->an_start = jiffies;
506 } else {
507 an_timeout = pdata->an_start +
508 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
509 if (time_after(jiffies, an_timeout)) {
510 /* Auto-negotiation timed out, reset state */
511 pdata->kr_state = XGBE_RX_BPA;
512 pdata->kx_state = XGBE_RX_BPA;
513
514 pdata->an_start = jiffies;
515 }
516 }
517
518 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
519 : &pdata->kx_state;
520
521 switch (*state) {
522 case XGBE_RX_BPA:
523 ret = xgbe_an_rx_bpa(pdata, state);
524 break;
525
526 case XGBE_RX_XNP:
527 ret = xgbe_an_rx_xnp(pdata, state);
528 break;
529
530 default:
531 ret = XGBE_AN_ERROR;
532 }
533
534 return ret;
535}
536
537static enum xgbe_an xgbe_an_incompat_link(struct xgbe_prv_data *pdata)
538{
539 /* Be sure we aren't looping trying to negotiate */
540 if (xgbe_in_kr_mode(pdata)) {
541 pdata->kr_state = XGBE_RX_ERROR;
542
543 if (!(pdata->phy.advertising & ADVERTISED_1000baseKX_Full) &&
544 !(pdata->phy.advertising & ADVERTISED_2500baseX_Full))
545 return XGBE_AN_NO_LINK;
546
547 if (pdata->kx_state != XGBE_RX_BPA)
548 return XGBE_AN_NO_LINK;
549 } else {
550 pdata->kx_state = XGBE_RX_ERROR;
551
552 if (!(pdata->phy.advertising & ADVERTISED_10000baseKR_Full))
553 return XGBE_AN_NO_LINK;
554
555 if (pdata->kr_state != XGBE_RX_BPA)
556 return XGBE_AN_NO_LINK;
557 }
558
559 xgbe_disable_an(pdata);
560
561 xgbe_switch_mode(pdata);
562
563 xgbe_restart_an(pdata);
564
565 return XGBE_AN_INCOMPAT_LINK;
566}
567
568static irqreturn_t xgbe_an_isr(int irq, void *data)
569{
570 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
571
572 /* Interrupt reason must be read and cleared outside of IRQ context */
573 disable_irq_nosync(pdata->an_irq);
574
575 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
576
577 return IRQ_HANDLED;
578}
579
580static void xgbe_an_irq_work(struct work_struct *work)
581{
582 struct xgbe_prv_data *pdata = container_of(work,
583 struct xgbe_prv_data,
584 an_irq_work);
585
586 /* Avoid a race between enabling the IRQ and exiting the work by
587 * waiting for the work to finish and then queueing it
588 */
589 flush_work(&pdata->an_work);
590 queue_work(pdata->an_workqueue, &pdata->an_work);
591}
592
593static void xgbe_an_state_machine(struct work_struct *work)
594{
595 struct xgbe_prv_data *pdata = container_of(work,
596 struct xgbe_prv_data,
597 an_work);
598 enum xgbe_an cur_state = pdata->an_state;
599 unsigned int int_reg, int_mask;
600
601 mutex_lock(&pdata->an_mutex);
602
603 /* Read the interrupt */
604 int_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
605 if (!int_reg)
606 goto out;
607
608next_int:
609 if (int_reg & XGBE_AN_PG_RCV) {
610 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
611 int_mask = XGBE_AN_PG_RCV;
612 } else if (int_reg & XGBE_AN_INC_LINK) {
613 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
614 int_mask = XGBE_AN_INC_LINK;
615 } else if (int_reg & XGBE_AN_INT_CMPLT) {
616 pdata->an_state = XGBE_AN_COMPLETE;
617 int_mask = XGBE_AN_INT_CMPLT;
618 } else {
619 pdata->an_state = XGBE_AN_ERROR;
620 int_mask = 0;
621 }
622
623 /* Clear the interrupt to be processed */
624 int_reg &= ~int_mask;
625 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
626
627 pdata->an_result = pdata->an_state;
628
629again:
630 cur_state = pdata->an_state;
631
632 switch (pdata->an_state) {
633 case XGBE_AN_READY:
634 pdata->an_supported = 0;
635 break;
636
637 case XGBE_AN_PAGE_RECEIVED:
638 pdata->an_state = xgbe_an_page_received(pdata);
639 pdata->an_supported++;
640 break;
c5aa9e3b 641
7c12aa08
LT		 642 case XGBE_AN_INCOMPAT_LINK:
643 pdata->an_supported = 0;
644 pdata->parallel_detect = 0;
645 pdata->an_state = xgbe_an_incompat_link(pdata);
646 break;
c5aa9e3b 647
7c12aa08
LT		 648 case XGBE_AN_COMPLETE:
649 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
650 netdev_dbg(pdata->netdev, "%s successful\n",
651 pdata->an_supported ? "Auto negotiation"
652 : "Parallel detection");
653 break;
654
655 case XGBE_AN_NO_LINK:
656 break;
657
658 default:
659 pdata->an_state = XGBE_AN_ERROR;
660 }
661
662 if (pdata->an_state == XGBE_AN_NO_LINK) {
663 int_reg = 0;
664 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
665 } else if (pdata->an_state == XGBE_AN_ERROR) {
666 netdev_err(pdata->netdev,
667 "error during auto-negotiation, state=%u\n",
668 cur_state);
669
670 int_reg = 0;
671 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
672 }
673
674 if (pdata->an_state >= XGBE_AN_COMPLETE) {
675 pdata->an_result = pdata->an_state;
676 pdata->an_state = XGBE_AN_READY;
677 pdata->kr_state = XGBE_RX_BPA;
678 pdata->kx_state = XGBE_RX_BPA;
679 pdata->an_start = 0;
680 }
681
682 if (cur_state != pdata->an_state)
683 goto again;
684
685 if (int_reg)
686 goto next_int;
687
688out:
689 enable_irq(pdata->an_irq);
690
691 mutex_unlock(&pdata->an_mutex);
c5aa9e3b
LT		 692}
693
7c12aa08 694static void xgbe_an_init(struct xgbe_prv_data *pdata)
c5aa9e3b 695{
7c12aa08
LT		 696 unsigned int reg;
697
698 /* Set up Advertisement register 3 first */
699 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
700 if (pdata->phy.advertising & ADVERTISED_10000baseR_FEC)
701 reg |= 0xc000;
702 else
703 reg &= ~0xc000;
704
705 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
706
707 /* Set up Advertisement register 2 next */
708 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
709 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full)
710 reg |= 0x80;
711 else
712 reg &= ~0x80;
713
714 if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
715 (pdata->phy.advertising & ADVERTISED_2500baseX_Full))
716 reg |= 0x20;
717 else
718 reg &= ~0x20;
719
720 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
c5aa9e3b 721
7c12aa08
LT		 722 /* Set up Advertisement register 1 last */
723 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
724 if (pdata->phy.advertising & ADVERTISED_Pause)
725 reg |= 0x400;
726 else
727 reg &= ~0x400;
c5aa9e3b 728
7c12aa08
LT		 729 if (pdata->phy.advertising & ADVERTISED_Asym_Pause)
730 reg |= 0x800;
731 else
732 reg &= ~0x800;
733
734 /* We don't intend to perform XNP */
735 reg &= ~XGBE_XNP_NP_EXCHANGE;
736
737 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
738}
739
740static const char *xgbe_phy_speed_string(int speed)
741{
742 switch (speed) {
743 case SPEED_1000:
744 return "1Gbps";
745 case SPEED_2500:
746 return "2.5Gbps";
747 case SPEED_10000:
748 return "10Gbps";
749 case SPEED_UNKNOWN:
750 return "Unknown";
751 default:
752 return "Unsupported";
753 }
754}
755
756static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
757{
758 if (pdata->phy.link)
759 netdev_info(pdata->netdev,
760 "Link is Up - %s/%s - flow control %s\n",
761 xgbe_phy_speed_string(pdata->phy.speed),
762 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
763 pdata->phy.pause ? "rx/tx" : "off");
764 else
765 netdev_info(pdata->netdev, "Link is Down\n");
766}
767
768static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
769{
770 int new_state = 0;
771
772 if (pdata->phy.link) {
773 /* Flow control support */
774 if (pdata->pause_autoneg) {
775 if (pdata->phy.pause || pdata->phy.asym_pause) {
776 pdata->tx_pause = 1;
777 pdata->rx_pause = 1;
778 } else {
779 pdata->tx_pause = 0;
780 pdata->rx_pause = 0;
781 }
782 }
783
784 if (pdata->tx_pause != pdata->phy_tx_pause) {
785 pdata->hw_if.config_tx_flow_control(pdata);
786 pdata->phy_tx_pause = pdata->tx_pause;
787 }
788
789 if (pdata->rx_pause != pdata->phy_rx_pause) {
790 pdata->hw_if.config_rx_flow_control(pdata);
791 pdata->phy_rx_pause = pdata->rx_pause;
792 }
793
794 /* Speed support */
795 if (pdata->phy_speed != pdata->phy.speed) {
796 new_state = 1;
797 pdata->phy_speed = pdata->phy.speed;
798 }
799
800 if (pdata->phy_link != pdata->phy.link) {
801 new_state = 1;
802 pdata->phy_link = pdata->phy.link;
803 }
804 } else if (pdata->phy_link) {
805 new_state = 1;
806 pdata->phy_link = 0;
807 pdata->phy_speed = SPEED_UNKNOWN;
808 }
809
810 if (new_state && netif_msg_link(pdata))
811 xgbe_phy_print_status(pdata);
812}
813
814static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
815{
816 /* Disable auto-negotiation */
817 xgbe_disable_an(pdata);
818
819 /* Validate/Set specified speed */
820 switch (pdata->phy.speed) {
821 case SPEED_10000:
822 xgbe_set_mode(pdata, XGBE_MODE_KR);
823 break;
824
825 case SPEED_2500:
826 case SPEED_1000:
827 xgbe_set_mode(pdata, XGBE_MODE_KX);
828 break;
829
830 default:
831 return -EINVAL;
832 }
c5aa9e3b 833
7c12aa08
LT		 834 /* Validate duplex mode */
835 if (pdata->phy.duplex != DUPLEX_FULL)
836 return -EINVAL;
837
838 pdata->phy.pause = 0;
839 pdata->phy.asym_pause = 0;
c5aa9e3b
LT		 840
841 return 0;
842}
843
7c12aa08
LT		 844static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
845{
846 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
847 pdata->link_check = jiffies;
848
849 if (pdata->phy.autoneg != AUTONEG_ENABLE)
850 return xgbe_phy_config_fixed(pdata);
851
852 /* Disable auto-negotiation interrupt */
853 disable_irq(pdata->an_irq);
854
855 /* Start auto-negotiation in a supported mode */
856 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) {
857 xgbe_set_mode(pdata, XGBE_MODE_KR);
858 } else if ((pdata->phy.advertising & ADVERTISED_1000baseKX_Full) ||
859 (pdata->phy.advertising & ADVERTISED_2500baseX_Full)) {
860 xgbe_set_mode(pdata, XGBE_MODE_KX);
861 } else {
862 enable_irq(pdata->an_irq);
863 return -EINVAL;
864 }
865
866 /* Disable and stop any in progress auto-negotiation */
867 xgbe_disable_an(pdata);
868
869 /* Clear any auto-negotitation interrupts */
870 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
871
872 pdata->an_result = XGBE_AN_READY;
873 pdata->an_state = XGBE_AN_READY;
874 pdata->kr_state = XGBE_RX_BPA;
875 pdata->kx_state = XGBE_RX_BPA;
876
877 /* Re-enable auto-negotiation interrupt */
878 enable_irq(pdata->an_irq);
879
880 /* Set up advertisement registers based on current settings */
881 xgbe_an_init(pdata);
882
883 /* Enable and start auto-negotiation */
884 xgbe_restart_an(pdata);
885
886 return 0;
887}
888
889static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
890{
891 int ret;
892
893 mutex_lock(&pdata->an_mutex);
894
895 ret = __xgbe_phy_config_aneg(pdata);
896 if (ret)
897 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
898 else
899 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
900
901 mutex_unlock(&pdata->an_mutex);
902
903 return ret;
904}
905
906static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
907{
908 return (pdata->an_result == XGBE_AN_COMPLETE);
909}
910
911static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
912{
913 unsigned long link_timeout;
914
915 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
916 if (time_after(jiffies, link_timeout))
917 xgbe_phy_config_aneg(pdata);
918}
919
920static void xgbe_phy_status_force(struct xgbe_prv_data *pdata)
921{
922 if (xgbe_in_kr_mode(pdata)) {
923 pdata->phy.speed = SPEED_10000;
924 } else {
925 switch (pdata->speed_set) {
926 case XGBE_SPEEDSET_1000_10000:
927 pdata->phy.speed = SPEED_1000;
928 break;
929
930 case XGBE_SPEEDSET_2500_10000:
931 pdata->phy.speed = SPEED_2500;
932 break;
933 }
934 }
935 pdata->phy.duplex = DUPLEX_FULL;
936 pdata->phy.pause = 0;
937 pdata->phy.asym_pause = 0;
938}
939
940static void xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
941{
942 unsigned int ad_reg, lp_reg;
943
944 pdata->phy.lp_advertising = 0;
945
946 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
947 return xgbe_phy_status_force(pdata);
948
949 pdata->phy.lp_advertising |= ADVERTISED_Autoneg;
950 pdata->phy.lp_advertising |= ADVERTISED_Backplane;
951
952 /* Compare Advertisement and Link Partner register 1 */
953 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
954 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
955 if (lp_reg & 0x400)
956 pdata->phy.lp_advertising |= ADVERTISED_Pause;
957 if (lp_reg & 0x800)
958 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause;
959
960 ad_reg &= lp_reg;
961 pdata->phy.pause = (ad_reg & 0x400) ? 1 : 0;
962 pdata->phy.asym_pause = (ad_reg & 0x800) ? 1 : 0;
963
964 /* Compare Advertisement and Link Partner register 2 */
965 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
966 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
967 if (lp_reg & 0x80)
968 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full;
969 if (lp_reg & 0x20) {
970 switch (pdata->speed_set) {
971 case XGBE_SPEEDSET_1000_10000:
972 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full;
973 break;
974 case XGBE_SPEEDSET_2500_10000:
975 pdata->phy.lp_advertising |= ADVERTISED_2500baseX_Full;
976 break;
977 }
978 }
979
980 ad_reg &= lp_reg;
981 if (ad_reg & 0x80) {
982 pdata->phy.speed = SPEED_10000;
983 xgbe_set_mode(pdata, XGBE_MODE_KR);
984 } else if (ad_reg & 0x20) {
985 switch (pdata->speed_set) {
986 case XGBE_SPEEDSET_1000_10000:
987 pdata->phy.speed = SPEED_1000;
988 break;
989
990 case XGBE_SPEEDSET_2500_10000:
991 pdata->phy.speed = SPEED_2500;
992 break;
993 }
994
995 xgbe_set_mode(pdata, XGBE_MODE_KX);
996 } else {
997 pdata->phy.speed = SPEED_UNKNOWN;
998 }
999
1000 /* Compare Advertisement and Link Partner register 3 */
1001 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1002 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
1003 if (lp_reg & 0xc000)
1004 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC;
1005
1006 pdata->phy.duplex = DUPLEX_FULL;
1007}
1008
1009static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1010{
1011 unsigned int reg, link_aneg;
1012
1013 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1014 if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state))
1015 netif_carrier_off(pdata->netdev);
1016
1017 pdata->phy.link = 0;
1018 goto adjust_link;
1019 }
1020
1021 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1022
1023 /* Get the link status. Link status is latched low, so read
1024 * once to clear and then read again to get current state
1025 */
1026 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1027 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1);
1028 pdata->phy.link = (reg & MDIO_STAT1_LSTATUS) ? 1 : 0;
1029
1030 if (pdata->phy.link) {
1031 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1032 xgbe_check_link_timeout(pdata);
1033 return;
1034 }
1035
1036 xgbe_phy_status_aneg(pdata);
1037
1038 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1039 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1040
1041 if (!test_bit(XGBE_LINK, &pdata->dev_state)) {
1042 set_bit(XGBE_LINK, &pdata->dev_state);
1043 netif_carrier_on(pdata->netdev);
1044 }
1045 } else {
1046 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1047 xgbe_check_link_timeout(pdata);
1048
1049 if (link_aneg)
1050 return;
1051 }
1052
1053 xgbe_phy_status_aneg(pdata);
1054
1055 if (test_bit(XGBE_LINK, &pdata->dev_state)) {
1056 clear_bit(XGBE_LINK, &pdata->dev_state);
1057 netif_carrier_off(pdata->netdev);
1058 }
1059 }
1060
1061adjust_link:
1062 xgbe_phy_adjust_link(pdata);
1063}
1064
1065static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1066{
1067 /* Disable auto-negotiation */
1068 xgbe_disable_an(pdata);
1069
1070 /* Disable auto-negotiation interrupts */
1071 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1072
1073 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1074
1075 pdata->phy.link = 0;
1076 if (test_and_clear_bit(XGBE_LINK, &pdata->dev_state))
1077 netif_carrier_off(pdata->netdev);
1078
1079 xgbe_phy_adjust_link(pdata);
1080}
1081
1082static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1083{
1084 struct net_device *netdev = pdata->netdev;
1085 int ret;
1086
1087 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1088 xgbe_an_isr, 0, pdata->an_name,
1089 pdata);
1090 if (ret) {
1091 netdev_err(netdev, "phy irq request failed\n");
1092 return ret;
1093 }
1094
1095 /* Set initial mode - call the mode setting routines
1096 * directly to insure we are properly configured
1097 */
1098 if (pdata->phy.advertising & ADVERTISED_10000baseKR_Full) {
1099 xgbe_xgmii_mode(pdata);
1100 } else if (pdata->phy.advertising & ADVERTISED_1000baseKX_Full) {
1101 xgbe_gmii_mode(pdata);
1102 } else if (pdata->phy.advertising & ADVERTISED_2500baseX_Full) {
1103 xgbe_gmii_2500_mode(pdata);
1104 } else {
1105 ret = -EINVAL;
1106 goto err_irq;
1107 }
1108
1109 /* Set up advertisement registers based on current settings */
1110 xgbe_an_init(pdata);
1111
1112 /* Enable auto-negotiation interrupts */
1113 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
1114
1115 return xgbe_phy_config_aneg(pdata);
1116
1117err_irq:
1118 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1119
1120 return ret;
1121}
1122
1123static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1124{
1125 unsigned int count, reg;
1126
1127 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1128 reg |= MDIO_CTRL1_RESET;
1129 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg);
1130
1131 count = 50;
1132 do {
1133 msleep(20);
1134 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1);
1135 } while ((reg & MDIO_CTRL1_RESET) && --count);
1136
1137 if (reg & MDIO_CTRL1_RESET)
1138 return -ETIMEDOUT;
1139
1140 /* Disable auto-negotiation for now */
1141 xgbe_disable_an(pdata);
1142
1143 /* Clear auto-negotiation interrupts */
1144 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
1145
1146 return 0;
1147}
1148
1149static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
c5aa9e3b
LT		 1150{
1151 struct device *dev = pdata->dev;
c5aa9e3b 1152
34bf65df
LT		 1153 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1154
1155 dev_dbg(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1156 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1157 dev_dbg(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1158 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1159 dev_dbg(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1,
1160 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1161 dev_dbg(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2,
1162 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1163 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1,
1164 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1165 dev_dbg(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2,
1166 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1167
1168 dev_dbg(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
1169 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1170 dev_dbg(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
1171 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1172 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n",
1173 MDIO_AN_ADVERTISE,
1174 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1175 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n",
1176 MDIO_AN_ADVERTISE + 1,
1177 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1178 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n",
1179 MDIO_AN_ADVERTISE + 2,
1180 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1181 dev_dbg(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n",
1182 MDIO_AN_COMP_STAT,
1183 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1184
34bf65df 1185 dev_dbg(dev, "\n*************************************************\n");
c5aa9e3b
LT		 1186}
1187
7c12aa08 1188static void xgbe_phy_init(struct xgbe_prv_data *pdata)
c5aa9e3b 1189{
7c12aa08
LT		 1190 mutex_init(&pdata->an_mutex);
1191 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1192 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1193 pdata->mdio_mmd = MDIO_MMD_PCS;
c5aa9e3b 1194
7c12aa08
LT		 1195 /* Initialize supported features */
1196 pdata->phy.supported = SUPPORTED_Autoneg;
1197 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1198 pdata->phy.supported |= SUPPORTED_Backplane;
1199 pdata->phy.supported |= SUPPORTED_10000baseKR_Full;
1200 switch (pdata->speed_set) {
1201 case XGBE_SPEEDSET_1000_10000:
1202 pdata->phy.supported |= SUPPORTED_1000baseKX_Full;
1203 break;
1204 case XGBE_SPEEDSET_2500_10000:
1205 pdata->phy.supported |= SUPPORTED_2500baseX_Full;
1206 break;
94c043e5 1207 }
c5aa9e3b 1208
7c12aa08
LT		 1209 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1210 MDIO_PMA_10GBR_FECABLE);
1211 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1212 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1213 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE)
1214 pdata->phy.supported |= SUPPORTED_10000baseR_FEC;
c5aa9e3b 1215
7c12aa08 1216 pdata->phy.advertising = pdata->phy.supported;
c5aa9e3b 1217
7c12aa08 1218 pdata->phy.address = 0;
c5aa9e3b 1219
7c12aa08
LT		 1220 pdata->phy.autoneg = AUTONEG_ENABLE;
1221 pdata->phy.speed = SPEED_UNKNOWN;
1222 pdata->phy.duplex = DUPLEX_UNKNOWN;
c5aa9e3b 1223
7c12aa08 1224 pdata->phy.link = 0;
c5aa9e3b 1225
34bf65df
LT		 1226 if (netif_msg_drv(pdata))
1227 xgbe_dump_phy_registers(pdata);
c5aa9e3b
LT		 1228}
1229
7c12aa08 1230void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
c5aa9e3b 1231{
7c12aa08 1232 phy_if->phy_init = xgbe_phy_init;
c5aa9e3b 1233
7c12aa08
LT		 1234 phy_if->phy_reset = xgbe_phy_reset;
1235 phy_if->phy_start = xgbe_phy_start;
1236 phy_if->phy_stop = xgbe_phy_stop;
c5aa9e3b 1237
7c12aa08
LT		 1238 phy_if->phy_status = xgbe_phy_status;
1239 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
c5aa9e3b 1240}
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