[mirror_ubuntu-artful-kernel.git] / drivers / scsi / 53c700.h

/* -*- mode: c; c-basic-offset: 8 -*- */

/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
 *
 * Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
 */

#ifndef _53C700_H
#define _53C700_H

#include <linux/interrupt.h>
#include <asm/io.h>

#include <scsi/scsi_device.h>
#include <scsi/scsi_cmnd.h>

/* Turn on for general debugging---too verbose for normal use */
#undef	NCR_700_DEBUG
/* Debug the tag queues, checking hash queue allocation and deallocation
 * and search for duplicate tags */
#undef NCR_700_TAG_DEBUG

#ifdef NCR_700_DEBUG
#define DEBUG(x)	printk x
#define DDEBUG(prefix, sdev, fmt, a...) \
	sdev_printk(prefix, sdev, fmt, ##a)
#define CDEBUG(prefix, scmd, fmt, a...) \
	scmd_printk(prefix, scmd, fmt, ##a)
#else
#define DEBUG(x)	do {} while (0)
#define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
#define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
#endif

/* The number of available command slots */
#define NCR_700_COMMAND_SLOTS_PER_HOST	64
/* The maximum number of Scatter Gathers we allow */
#define NCR_700_SG_SEGMENTS		32
/* The maximum number of luns (make this of the form 2^n) */
#define NCR_700_MAX_LUNS		32
#define NCR_700_LUN_MASK		(NCR_700_MAX_LUNS - 1)
/* Maximum number of tags the driver ever allows per device */
#define NCR_700_MAX_TAGS		16
/* Tag depth the driver starts out with (can be altered in sysfs) */
#define NCR_700_DEFAULT_TAGS		4
/* This is the default number of commands per LUN in the untagged case.
 * two is a good value because it means we can have one command active and
 * one command fully prepared and waiting
 */
#define NCR_700_CMD_PER_LUN		2
/* magic byte identifying an internally generated REQUEST_SENSE command */
#define NCR_700_INTERNAL_SENSE_MAGIC	0x42

struct NCR_700_Host_Parameters;

/* These are the externally used routines */
struct Scsi_Host *NCR_700_detect(struct scsi_host_template *,
		struct NCR_700_Host_Parameters *, struct device *);
int NCR_700_release(struct Scsi_Host *host);
irqreturn_t NCR_700_intr(int, void *);


enum NCR_700_Host_State {
	NCR_700_HOST_BUSY,
	NCR_700_HOST_FREE,
};

struct NCR_700_SG_List {
	/* The following is a script fragment to move the buffer onto the
	 * bus and then link the next fragment or return */
	#define	SCRIPT_MOVE_DATA_IN		0x09000000
	#define	SCRIPT_MOVE_DATA_OUT		0x08000000
	__u32	ins;
	__u32	pAddr;
	#define	SCRIPT_NOP			0x80000000
	#define	SCRIPT_RETURN			0x90080000
};

struct NCR_700_Device_Parameters {
	/* space for creating a request sense command. Really, except
	 * for the annoying SCSI-2 requirement for LUN information in
	 * cmnd[1], this could be in static storage */
	unsigned char cmnd[MAX_COMMAND_SIZE];
	__u8	depth;
	struct scsi_cmnd *current_cmnd;	/* currently active command */
};


/* The SYNC negotiation sequence looks like:
 * 
 * If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
 * initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
 * If we get an SDTR reply, work out the SXFER parameters, squirrel
 * them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
 * DEV_NEGOTIATED_SYNC.  If we get a REJECT msg, squirrel
 *
 *
 * 0:7	SXFER_REG negotiated value for this device
 * 8:15 Current queue depth
 * 16	negotiated SYNC flag
 * 17 begin SYNC negotiation flag 
 * 18 device supports tag queueing */
#define NCR_700_DEV_NEGOTIATED_SYNC	(1<<16)
#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION	(1<<17)
#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)

static inline char *NCR_700_get_sense_cmnd(struct scsi_device *SDp)
{
	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;

	return hostdata->cmnd;
}

static inline void
NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
{
	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;

	hostdata->depth = depth;
}
static inline __u8
NCR_700_get_depth(struct scsi_device *SDp)
{
	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;

	return hostdata->depth;
}
static inline int
NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
{
	return (spi_flags(SDp->sdev_target) & flag) == flag;
}
static inline int
NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
{
	return (spi_flags(SDp->sdev_target) & flag) == 0;
}
static inline void
NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
{
	spi_flags(SDp->sdev_target) |= flag;
}
static inline void
NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
{
	spi_flags(SDp->sdev_target) &= ~flag;
}

enum NCR_700_tag_neg_state {
	NCR_700_START_TAG_NEGOTIATION = 0,
	NCR_700_DURING_TAG_NEGOTIATION = 1,
	NCR_700_FINISHED_TAG_NEGOTIATION = 2,
};

static inline enum NCR_700_tag_neg_state
NCR_700_get_tag_neg_state(struct scsi_device *SDp)
{
	return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
}

static inline void
NCR_700_set_tag_neg_state(struct scsi_device *SDp,
			  enum NCR_700_tag_neg_state state)
{
	/* clear the slot */
	spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
	spi_flags(SDp->sdev_target) |= ((__u32)state) << 20;
}

struct NCR_700_command_slot {
	struct NCR_700_SG_List	SG[NCR_700_SG_SEGMENTS+1];
	struct NCR_700_SG_List	*pSG;
	#define NCR_700_SLOT_MASK 0xFC
	#define NCR_700_SLOT_MAGIC 0xb8
	#define	NCR_700_SLOT_FREE (0|NCR_700_SLOT_MAGIC) /* slot may be used */
	#define NCR_700_SLOT_BUSY (1|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
	#define NCR_700_SLOT_QUEUED (2|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
	__u8	state;
	#define NCR_700_FLAG_AUTOSENSE	0x01
	__u8	flags;
	__u8	pad1[2];	/* Needed for m68k where min alignment is 2 bytes */
	int	tag;
	__u32	resume_offset;
	struct scsi_cmnd *cmnd;
	/* The pci_mapped address of the actual command in cmnd */
	dma_addr_t	pCmd;
	__u32		temp;
	/* if this command is a pci_single mapping, holds the dma address
	 * for later unmapping in the done routine */
	dma_addr_t	dma_handle;
	/* historical remnant, now used to link free commands */
	struct NCR_700_command_slot *ITL_forw;
};

struct NCR_700_Host_Parameters {
	/* These must be filled in by the calling driver */
	int	clock;			/* board clock speed in MHz */
	void __iomem	*base;		/* the base for the port (copied to host) */
	struct device	*dev;
	__u32	dmode_extra;	/* adjustable bus settings */
	__u32	dcntl_extra;	/* adjustable bus settings */
	__u32	ctest7_extra;	/* adjustable bus settings */
	__u32	differential:1;	/* if we are differential */
#ifdef CONFIG_53C700_LE_ON_BE
	/* This option is for HP only.  Set it if your chip is wired for
	 * little endian on this platform (which is big endian) */
	__u32	force_le_on_be:1;
#endif
	__u32	chip710:1;	/* set if really a 710 not 700 */
	__u32	burst_length:4;	/* set to 0 to disable 710 bursting */

	/* NOTHING BELOW HERE NEEDS ALTERING */
	__u32	fast:1;		/* if we can alter the SCSI bus clock
                                   speed (so can negiotiate sync) */
	int	sync_clock;	/* The speed of the SYNC core */

	__u32	*script;		/* pointer to script location */
	__u32	pScript;		/* physical mem addr of script */

	enum NCR_700_Host_State state; /* protected by state lock */
	struct scsi_cmnd *cmd;
	/* Note: pScript contains the single consistent block of
	 * memory.  All the msgin, msgout and status are allocated in
	 * this memory too (at separate cache lines).  TOTAL_MEM_SIZE
	 * represents the total size of this area */
#define	MSG_ARRAY_SIZE	8
#define	MSGOUT_OFFSET	(L1_CACHE_ALIGN(sizeof(SCRIPT)))
	__u8	*msgout;
#define MSGIN_OFFSET	(MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	__u8	*msgin;
#define STATUS_OFFSET	(MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	__u8	*status;
#define SLOTS_OFFSET	(STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	struct NCR_700_command_slot	*slots;
#define	TOTAL_MEM_SIZE	(SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
	int	saved_slot_position;
	int	command_slot_count; /* protected by state lock */
	__u8	tag_negotiated;
	__u8	rev;
	__u8	reselection_id;
	__u8	min_period;

	/* Free list, singly linked by ITL_forw elements */
	struct NCR_700_command_slot *free_list;
	/* Completion for waited for ops, like reset, abort or
	 * device reset.
	 *
	 * NOTE: relies on single threading in the error handler to
	 * have only one outstanding at once */
	struct completion *eh_complete;
};

/*
 *	53C700 Register Interface - the offset from the Selected base
 *	I/O address */
#ifdef CONFIG_53C700_LE_ON_BE
#define bE	(hostdata->force_le_on_be ? 0 : 3)
#define	bSWAP	(hostdata->force_le_on_be)
#define bEBus	(!hostdata->force_le_on_be)
#elif defined(__BIG_ENDIAN)
#define bE	3
#define bSWAP	0
#elif defined(__LITTLE_ENDIAN)
#define bE	0
#define bSWAP	0
#else
#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
#endif
#ifndef bEBus
#ifdef CONFIG_53C700_BE_BUS
#define bEBus	1
#else
#define bEBus	0
#endif
#endif
#define bS_to_cpu(x)	(bSWAP ? le32_to_cpu(x) : (x))
#define bS_to_host(x)	(bSWAP ? cpu_to_le32(x) : (x))

/* NOTE: These registers are in the LE register space only, the required byte
 * swapping is done by the NCR_700_{read|write}[b] functions */
#define	SCNTL0_REG			0x00
#define		FULL_ARBITRATION	0xc0
#define 	PARITY			0x08
#define		ENABLE_PARITY		0x04
#define 	AUTO_ATN		0x02
#define	SCNTL1_REG			0x01
#define 	SLOW_BUS		0x80
#define		ENABLE_SELECT		0x20
#define		ASSERT_RST		0x08
#define		ASSERT_EVEN_PARITY	0x04
#define	SDID_REG			0x02
#define	SIEN_REG			0x03
#define 	PHASE_MM_INT		0x80
#define 	FUNC_COMP_INT		0x40
#define 	SEL_TIMEOUT_INT		0x20
#define 	SELECT_INT		0x10
#define 	GROSS_ERR_INT		0x08
#define 	UX_DISC_INT		0x04
#define 	RST_INT			0x02
#define 	PAR_ERR_INT		0x01
#define	SCID_REG			0x04
#define SXFER_REG			0x05
#define		ASYNC_OPERATION		0x00
#define SODL_REG                        0x06
#define	SOCL_REG			0x07
#define	SFBR_REG			0x08
#define	SIDL_REG			0x09
#define	SBDL_REG			0x0A
#define	SBCL_REG			0x0B
/* read bits */
#define		SBCL_IO			0x01
/*write bits */
#define		SYNC_DIV_AS_ASYNC	0x00
#define		SYNC_DIV_1_0		0x01
#define		SYNC_DIV_1_5		0x02
#define		SYNC_DIV_2_0		0x03
#define	DSTAT_REG			0x0C
#define		ILGL_INST_DETECTED	0x01
#define		WATCH_DOG_INTERRUPT	0x02
#define		SCRIPT_INT_RECEIVED	0x04
#define		ABORTED			0x10
#define	SSTAT0_REG			0x0D
#define		PARITY_ERROR		0x01
#define		SCSI_RESET_DETECTED	0x02
#define		UNEXPECTED_DISCONNECT	0x04
#define		SCSI_GROSS_ERROR	0x08
#define		SELECTED		0x10
#define		SELECTION_TIMEOUT	0x20
#define		FUNCTION_COMPLETE	0x40
#define		PHASE_MISMATCH 		0x80
#define	SSTAT1_REG			0x0E
#define		SIDL_REG_FULL		0x80
#define		SODR_REG_FULL		0x40
#define		SODL_REG_FULL		0x20
#define SSTAT2_REG                      0x0F
#define CTEST0_REG                      0x14
#define		BTB_TIMER_DISABLE	0x40
#define CTEST1_REG                      0x15
#define CTEST2_REG                      0x16
#define CTEST3_REG                      0x17
#define CTEST4_REG                      0x18
#define         DISABLE_FIFO            0x00
#define         SLBE                    0x10
#define         SFWR                    0x08
#define         BYTE_LANE0              0x04
#define         BYTE_LANE1              0x05
#define         BYTE_LANE2              0x06
#define         BYTE_LANE3              0x07
#define         SCSI_ZMODE              0x20
#define         ZMODE                   0x40
#define CTEST5_REG                      0x19
#define         MASTER_CONTROL          0x10
#define         DMA_DIRECTION           0x08
#define CTEST7_REG                      0x1B
#define		BURST_DISABLE		0x80 /* 710 only */
#define		SEL_TIMEOUT_DISABLE	0x10 /* 710 only */
#define         DFP                     0x08
#define         EVP                     0x04
#define         CTEST7_TT1              0x02
#define		DIFF			0x01
#define CTEST6_REG                      0x1A
#define	TEMP_REG			0x1C
#define	DFIFO_REG			0x20
#define		FLUSH_DMA_FIFO		0x80
#define		CLR_FIFO		0x40
#define	ISTAT_REG			0x21
#define		ABORT_OPERATION		0x80
#define		SOFTWARE_RESET_710	0x40
#define		DMA_INT_PENDING		0x01
#define		SCSI_INT_PENDING	0x02
#define		CONNECTED		0x08
#define CTEST8_REG                      0x22
#define         LAST_DIS_ENBL           0x01
#define		SHORTEN_FILTERING	0x04
#define		ENABLE_ACTIVE_NEGATION	0x10
#define		GENERATE_RECEIVE_PARITY	0x20
#define		CLR_FIFO_710		0x04
#define		FLUSH_DMA_FIFO_710	0x08
#define CTEST9_REG                      0x23
#define	DBC_REG				0x24
#define	DCMD_REG			0x27
#define	DNAD_REG			0x28
#define	DIEN_REG			0x39
#define		BUS_FAULT		0x20
#define 	ABORT_INT		0x10
#define 	INT_INST_INT		0x04
#define 	WD_INT			0x02
#define 	ILGL_INST_INT		0x01
#define	DCNTL_REG			0x3B
#define		SOFTWARE_RESET		0x01
#define		COMPAT_700_MODE		0x01
#define 	SCRPTS_16BITS		0x20
#define		EA_710			0x20
#define		ASYNC_DIV_2_0		0x00
#define		ASYNC_DIV_1_5		0x40
#define		ASYNC_DIV_1_0		0x80
#define		ASYNC_DIV_3_0		0xc0
#define DMODE_710_REG			0x38
#define	DMODE_700_REG			0x34
#define		BURST_LENGTH_1		0x00
#define		BURST_LENGTH_2		0x40
#define		BURST_LENGTH_4		0x80
#define		BURST_LENGTH_8		0xC0
#define		DMODE_FC1		0x10
#define		DMODE_FC2		0x20
#define 	BW16			32 
#define 	MODE_286		16
#define 	IO_XFER			8
#define 	FIXED_ADDR		4

#define DSP_REG                         0x2C
#define DSPS_REG                        0x30

/* Parameters to begin SDTR negotiations.  Empirically, I find that
 * the 53c700-66 cannot handle an offset >8, so don't change this  */
#define NCR_700_MAX_OFFSET	8
/* Was hoping the max offset would be greater for the 710, but
 * empirically it seems to be 8 also */
#define NCR_710_MAX_OFFSET	8
#define NCR_700_MIN_XFERP	1
#define NCR_710_MIN_XFERP	0
#define NCR_700_MIN_PERIOD	25 /* for SDTR message, 100ns */

#define script_patch_32(dev, script, symbol, value) \
{ \
	int i; \
	dma_addr_t da = value; \
	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
		__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
		(script)[A_##symbol##_used[i]] = bS_to_host(val); \
		dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
		DEBUG((" script, patching %s at %d to %pad\n", \
		       #symbol, A_##symbol##_used[i], &da)); \
	} \
}

#define script_patch_32_abs(dev, script, symbol, value) \
{ \
	int i; \
	dma_addr_t da = value; \
	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
		(script)[A_##symbol##_used[i]] = bS_to_host(da); \
		dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
		DEBUG((" script, patching %s at %d to %pad\n", \
		       #symbol, A_##symbol##_used[i], &da)); \
	} \
}

/* Used for patching the SCSI ID in the SELECT instruction */
#define script_patch_ID(dev, script, symbol, value) \
{ \
	int i; \
	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
		__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
		val &= 0xff00ffff; \
		val |= ((value) & 0xff) << 16; \
		(script)[A_##symbol##_used[i]] = bS_to_host(val); \
		dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
		DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
		       #symbol, A_##symbol##_used[i], val)); \
	} \
}

#define script_patch_16(dev, script, symbol, value) \
{ \
	int i; \
	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
		__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
		val &= 0xffff0000; \
		val |= ((value) & 0xffff); \
		(script)[A_##symbol##_used[i]] = bS_to_host(val); \
		dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
		DEBUG((" script, patching short field %s at %d to 0x%x\n", \
		       #symbol, A_##symbol##_used[i], val)); \
	} \
}


static inline __u8
NCR_700_readb(struct Scsi_Host *host, __u32 reg)
{
	const struct NCR_700_Host_Parameters *hostdata
		= (struct NCR_700_Host_Parameters *)host->hostdata[0];

	return ioread8(hostdata->base + (reg^bE));
}

static inline __u32
NCR_700_readl(struct Scsi_Host *host, __u32 reg)
{
	const struct NCR_700_Host_Parameters *hostdata
		= (struct NCR_700_Host_Parameters *)host->hostdata[0];
	__u32 value = bEBus ? ioread32be(hostdata->base + reg) :
		ioread32(hostdata->base + reg);
#if 1
	/* sanity check the register */
	BUG_ON((reg & 0x3) != 0);
#endif

	return value;
}

static inline void
NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
{
	const struct NCR_700_Host_Parameters *hostdata
		= (struct NCR_700_Host_Parameters *)host->hostdata[0];

	iowrite8(value, hostdata->base + (reg^bE));
}

static inline void
NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
{
	const struct NCR_700_Host_Parameters *hostdata
		= (struct NCR_700_Host_Parameters *)host->hostdata[0];

#if 1
	/* sanity check the register */
	BUG_ON((reg & 0x3) != 0);
#endif

	bEBus ? iowrite32be(value, hostdata->base + reg): 
		iowrite32(value, hostdata->base + reg);
}

#endif
Commit	Line	Data
1da177e4 LT	1	/* -- mode: c; c-basic-offset: 8 -- */
	2
	3	/* Driver for 53c700 and 53c700-66 chips from NCR and Symbios
	4	*
	5	* Copyright (C) 2001 by James.Bottomley@HansenPartnership.com
	6	*/
	7
	8	#ifndef _53C700_H
	9	#define _53C700_H
	10
	11	#include <linux/interrupt.h>
	12	#include <asm/io.h>
	13
	14	#include <scsi/scsi_device.h>
0f13fc09	15	#include <scsi/scsi_cmnd.h>
1da177e4	16
1da177e4 LT	17	/* Turn on for general debugging---too verbose for normal use */
	18	#undef NCR_700_DEBUG
	19	/* Debug the tag queues, checking hash queue allocation and deallocation
	20	* and search for duplicate tags */
	21	#undef NCR_700_TAG_DEBUG
	22
	23	#ifdef NCR_700_DEBUG
	24	#define DEBUG(x) printk x
017560fc JG	25	#define DDEBUG(prefix, sdev, fmt, a...) \
	26	sdev_printk(prefix, sdev, fmt, ##a)
	27	#define CDEBUG(prefix, scmd, fmt, a...) \
	28	scmd_printk(prefix, scmd, fmt, ##a)
1da177e4	29	#else
017560fc JG	30	#define DEBUG(x) do {} while (0)
	31	#define DDEBUG(prefix, scmd, fmt, a...) do {} while (0)
	32	#define CDEBUG(prefix, scmd, fmt, a...) do {} while (0)
1da177e4 LT	33	#endif
	34
	35	/* The number of available command slots */
	36	#define NCR_700_COMMAND_SLOTS_PER_HOST 64
	37	/* The maximum number of Scatter Gathers we allow */
	38	#define NCR_700_SG_SEGMENTS 32
	39	/* The maximum number of luns (make this of the form 2^n) */
	40	#define NCR_700_MAX_LUNS 32
	41	#define NCR_700_LUN_MASK (NCR_700_MAX_LUNS - 1)
	42	/* Maximum number of tags the driver ever allows per device */
	43	#define NCR_700_MAX_TAGS 16
	44	/* Tag depth the driver starts out with (can be altered in sysfs) */
	45	#define NCR_700_DEFAULT_TAGS 4
	46	/* This is the default number of commands per LUN in the untagged case.
	47	* two is a good value because it means we can have one command active and
	48	* one command fully prepared and waiting
	49	*/
	50	#define NCR_700_CMD_PER_LUN 2
	51	/* magic byte identifying an internally generated REQUEST_SENSE command */
	52	#define NCR_700_INTERNAL_SENSE_MAGIC 0x42
	53
1da177e4 LT	54	struct NCR_700_Host_Parameters;
	55
	56	/* These are the externally used routines */
	57	struct Scsi_Host NCR_700_detect(struct scsi_host_template ,
	58	struct NCR_700_Host_Parameters , struct device );
	59	int NCR_700_release(struct Scsi_Host *host);
7d12e780	60	irqreturn_t NCR_700_intr(int, void *);
1da177e4 LT	61
	62
	63	enum NCR_700_Host_State {
	64	NCR_700_HOST_BUSY,
	65	NCR_700_HOST_FREE,
	66	};
	67
	68	struct NCR_700_SG_List {
	69	/* The following is a script fragment to move the buffer onto the
	70	* bus and then link the next fragment or return */
	71	#define SCRIPT_MOVE_DATA_IN 0x09000000
	72	#define SCRIPT_MOVE_DATA_OUT 0x08000000
	73	__u32 ins;
	74	__u32 pAddr;
	75	#define SCRIPT_NOP 0x80000000
	76	#define SCRIPT_RETURN 0x90080000
	77	};
	78
0f13fc09 JB	79	struct NCR_700_Device_Parameters {
	80	/* space for creating a request sense command. Really, except
	81	* for the annoying SCSI-2 requirement for LUN information in
	82	* cmnd[1], this could be in static storage */
	83	unsigned char cmnd[MAX_COMMAND_SIZE];
	84	__u8 depth;
68350a88	85	struct scsi_cmnd current_cmnd; / currently active command */
0f13fc09 JB	86	};
	87
	88
	89	/* The SYNC negotiation sequence looks like:
1da177e4 LT	90	*
	91	* If DEV_NEGOTIATED_SYNC not set, tack and SDTR message on to the
	92	* initial identify for the device and set DEV_BEGIN_SYNC_NEGOTATION
	93	* If we get an SDTR reply, work out the SXFER parameters, squirrel
	94	* them away here, clear DEV_BEGIN_SYNC_NEGOTIATION and set
	95	* DEV_NEGOTIATED_SYNC. If we get a REJECT msg, squirrel
	96	*
	97	*
	98	* 0:7 SXFER_REG negotiated value for this device
	99	* 8:15 Current queue depth
	100	* 16 negotiated SYNC flag
	101	* 17 begin SYNC negotiation flag
	102	* 18 device supports tag queueing */
	103	#define NCR_700_DEV_NEGOTIATED_SYNC (1<<16)
	104	#define NCR_700_DEV_BEGIN_SYNC_NEGOTIATION (1<<17)
	105	#define NCR_700_DEV_PRINT_SYNC_NEGOTIATION (1<<19)
	106
0f13fc09 JB	107	static inline char NCR_700_get_sense_cmnd(struct scsi_device SDp)
	108	{
	109	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
	110
	111	return hostdata->cmnd;
	112	}
	113
1da177e4 LT	114	static inline void
	115	NCR_700_set_depth(struct scsi_device *SDp, __u8 depth)
	116	{
0f13fc09	117	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
1da177e4	118
0f13fc09	119	hostdata->depth = depth;
1da177e4 LT	120	}
	121	static inline __u8
	122	NCR_700_get_depth(struct scsi_device *SDp)
	123	{
0f13fc09 JB	124	struct NCR_700_Device_Parameters *hostdata = SDp->hostdata;
	125
	126	return hostdata->depth;
1da177e4 LT	127	}
	128	static inline int
	129	NCR_700_is_flag_set(struct scsi_device *SDp, __u32 flag)
	130	{
	131	return (spi_flags(SDp->sdev_target) & flag) == flag;
	132	}
	133	static inline int
	134	NCR_700_is_flag_clear(struct scsi_device *SDp, __u32 flag)
	135	{
	136	return (spi_flags(SDp->sdev_target) & flag) == 0;
	137	}
	138	static inline void
	139	NCR_700_set_flag(struct scsi_device *SDp, __u32 flag)
	140	{
	141	spi_flags(SDp->sdev_target) \|= flag;
	142	}
	143	static inline void
	144	NCR_700_clear_flag(struct scsi_device *SDp, __u32 flag)
	145	{
	146	spi_flags(SDp->sdev_target) &= ~flag;
	147	}
	148
	149	enum NCR_700_tag_neg_state {
	150	NCR_700_START_TAG_NEGOTIATION = 0,
	151	NCR_700_DURING_TAG_NEGOTIATION = 1,
	152	NCR_700_FINISHED_TAG_NEGOTIATION = 2,
	153	};
	154
	155	static inline enum NCR_700_tag_neg_state
	156	NCR_700_get_tag_neg_state(struct scsi_device *SDp)
	157	{
	158	return (enum NCR_700_tag_neg_state)((spi_flags(SDp->sdev_target)>>20) & 0x3);
	159	}
	160
	161	static inline void
	162	NCR_700_set_tag_neg_state(struct scsi_device *SDp,
	163	enum NCR_700_tag_neg_state state)
	164	{
	165	/* clear the slot */
	166	spi_flags(SDp->sdev_target) &= ~(0x3 << 20);
	167	spi_flags(SDp->sdev_target) \|= ((__u32)state) << 20;
	168	}
	169
	170	struct NCR_700_command_slot {
	171	struct NCR_700_SG_List SG[NCR_700_SG_SEGMENTS+1];
	172	struct NCR_700_SG_List *pSG;
	173	#define NCR_700_SLOT_MASK 0xFC
	174	#define NCR_700_SLOT_MAGIC 0xb8
	175	#define NCR_700_SLOT_FREE (0\|NCR_700_SLOT_MAGIC) /* slot may be used */
	176	#define NCR_700_SLOT_BUSY (1\|NCR_700_SLOT_MAGIC) /* slot has command active on HA */
	177	#define NCR_700_SLOT_QUEUED (2\|NCR_700_SLOT_MAGIC) /* slot has command to be made active on HA */
	178	__u8 state;
67d59dfd JB	179	#define NCR_700_FLAG_AUTOSENSE 0x01
67d59dfd JB	180	__u8 flags;
63273134	181	__u8 pad1[2]; /* Needed for m68k where min alignment is 2 bytes */
1da177e4 LT	182	int tag;
	183	__u32 resume_offset;
	184	struct scsi_cmnd *cmnd;
	185	/* The pci_mapped address of the actual command in cmnd */
	186	dma_addr_t pCmd;
	187	__u32 temp;
	188	/* if this command is a pci_single mapping, holds the dma address
	189	* for later unmapping in the done routine */
	190	dma_addr_t dma_handle;
	191	/* historical remnant, now used to link free commands */
	192	struct NCR_700_command_slot *ITL_forw;
	193	};
	194
	195	struct NCR_700_Host_Parameters {
	196	/* These must be filled in by the calling driver */
	197	int clock; /* board clock speed in MHz */
56fece20	198	void __iomem base; / the base for the port (copied to host) */
1da177e4 LT	199	struct device *dev;
1da177e4 LT	200	__u32 dmode_extra; /* adjustable bus settings */
63273134 KJ	201	__u32 dcntl_extra; /* adjustable bus settings */
63273134 KJ	202	__u32 ctest7_extra; /* adjustable bus settings */
1da177e4 LT	203	__u32 differential:1; /* if we are differential */
	204	#ifdef CONFIG_53C700_LE_ON_BE
	205	/* This option is for HP only. Set it if your chip is wired for
	206	* little endian on this platform (which is big endian) */
	207	__u32 force_le_on_be:1;
	208	#endif
	209	__u32 chip710:1; /* set if really a 710 not 700 */
f67a9c15	210	__u32 burst_length:4; /* set to 0 to disable 710 bursting */
1da177e4 LT	211
	212	/* NOTHING BELOW HERE NEEDS ALTERING */
	213	__u32 fast:1; /* if we can alter the SCSI bus clock
	214	speed (so can negiotiate sync) */
1da177e4 LT	215	int sync_clock; /* The speed of the SYNC core */
	216
	217	__u32 script; / pointer to script location */
	218	__u32 pScript; /* physical mem addr of script */
	219
	220	enum NCR_700_Host_State state; /* protected by state lock */
	221	struct scsi_cmnd *cmd;
	222	/* Note: pScript contains the single consistent block of
	223	* memory. All the msgin, msgout and status are allocated in
	224	* this memory too (at separate cache lines). TOTAL_MEM_SIZE
	225	* represents the total size of this area */
	226	#define MSG_ARRAY_SIZE 8
	227	#define MSGOUT_OFFSET (L1_CACHE_ALIGN(sizeof(SCRIPT)))
	228	__u8 *msgout;
	229	#define MSGIN_OFFSET (MSGOUT_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	230	__u8 *msgin;
	231	#define STATUS_OFFSET (MSGIN_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	232	__u8 *status;
	233	#define SLOTS_OFFSET (STATUS_OFFSET + L1_CACHE_ALIGN(MSG_ARRAY_SIZE))
	234	struct NCR_700_command_slot *slots;
	235	#define TOTAL_MEM_SIZE (SLOTS_OFFSET + L1_CACHE_ALIGN(sizeof(struct NCR_700_command_slot) * NCR_700_COMMAND_SLOTS_PER_HOST))
	236	int saved_slot_position;
	237	int command_slot_count; /* protected by state lock */
	238	__u8 tag_negotiated;
	239	__u8 rev;
	240	__u8 reselection_id;
	241	__u8 min_period;
	242
	243	/* Free list, singly linked by ITL_forw elements */
	244	struct NCR_700_command_slot *free_list;
	245	/* Completion for waited for ops, like reset, abort or
	246	* device reset.
	247	*
	248	* NOTE: relies on single threading in the error handler to
	249	* have only one outstanding at once */
	250	struct completion *eh_complete;
	251	};
	252
	253	/*
	254	* 53C700 Register Interface - the offset from the Selected base
	255	* I/O address */
	256	#ifdef CONFIG_53C700_LE_ON_BE
	257	#define bE (hostdata->force_le_on_be ? 0 : 3)
	258	#define bSWAP (hostdata->force_le_on_be)
8f23d475	259	#define bEBus (!hostdata->force_le_on_be)
1da177e4 LT	260	#elif defined(__BIG_ENDIAN)
	261	#define bE 3
	262	#define bSWAP 0
	263	#elif defined(__LITTLE_ENDIAN)
	264	#define bE 0
	265	#define bSWAP 0
	266	#else
	267	#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined, did you include byteorder.h?"
	268	#endif
8f23d475 JB	269	#ifndef bEBus
	270	#ifdef CONFIG_53C700_BE_BUS
	271	#define bEBus 1
	272	#else
	273	#define bEBus 0
	274	#endif
	275	#endif
1da177e4 LT	276	#define bS_to_cpu(x) (bSWAP ? le32_to_cpu(x) : (x))
	277	#define bS_to_host(x) (bSWAP ? cpu_to_le32(x) : (x))
	278
	279	/* NOTE: These registers are in the LE register space only, the required byte
	280	* swapping is done by the NCR_700_{read\|write}[b] functions */
	281	#define SCNTL0_REG 0x00
	282	#define FULL_ARBITRATION 0xc0
	283	#define PARITY 0x08
	284	#define ENABLE_PARITY 0x04
	285	#define AUTO_ATN 0x02
	286	#define SCNTL1_REG 0x01
	287	#define SLOW_BUS 0x80
	288	#define ENABLE_SELECT 0x20
	289	#define ASSERT_RST 0x08
	290	#define ASSERT_EVEN_PARITY 0x04
	291	#define SDID_REG 0x02
	292	#define SIEN_REG 0x03
	293	#define PHASE_MM_INT 0x80
	294	#define FUNC_COMP_INT 0x40
	295	#define SEL_TIMEOUT_INT 0x20
	296	#define SELECT_INT 0x10
	297	#define GROSS_ERR_INT 0x08
	298	#define UX_DISC_INT 0x04
	299	#define RST_INT 0x02
	300	#define PAR_ERR_INT 0x01
	301	#define SCID_REG 0x04
	302	#define SXFER_REG 0x05
	303	#define ASYNC_OPERATION 0x00
	304	#define SODL_REG 0x06
	305	#define SOCL_REG 0x07
	306	#define SFBR_REG 0x08
	307	#define SIDL_REG 0x09
	308	#define SBDL_REG 0x0A
	309	#define SBCL_REG 0x0B
	310	/* read bits */
	311	#define SBCL_IO 0x01
	312	/write bits /
	313	#define SYNC_DIV_AS_ASYNC 0x00
	314	#define SYNC_DIV_1_0 0x01
	315	#define SYNC_DIV_1_5 0x02
	316	#define SYNC_DIV_2_0 0x03
	317	#define DSTAT_REG 0x0C
	318	#define ILGL_INST_DETECTED 0x01
	319	#define WATCH_DOG_INTERRUPT 0x02
	320	#define SCRIPT_INT_RECEIVED 0x04
	321	#define ABORTED 0x10
	322	#define SSTAT0_REG 0x0D
	323	#define PARITY_ERROR 0x01
	324	#define SCSI_RESET_DETECTED 0x02
	325	#define UNEXPECTED_DISCONNECT 0x04
	326	#define SCSI_GROSS_ERROR 0x08
	327	#define SELECTED 0x10
	328	#define SELECTION_TIMEOUT 0x20
	329	#define FUNCTION_COMPLETE 0x40
	330	#define PHASE_MISMATCH 0x80
	331	#define SSTAT1_REG 0x0E
	332	#define SIDL_REG_FULL 0x80
	333	#define SODR_REG_FULL 0x40
	334	#define SODL_REG_FULL 0x20
	335	#define SSTAT2_REG 0x0F
	336	#define CTEST0_REG 0x14
	337	#define BTB_TIMER_DISABLE 0x40
	338	#define CTEST1_REG 0x15
	339	#define CTEST2_REG 0x16
340	#define CTEST3_REG 0x17
341	#define CTEST4_REG 0x18
342	#define DISABLE_FIFO 0x00
343	#define SLBE 0x10
344	#define SFWR 0x08
345	#define BYTE_LANE0 0x04
346	#define BYTE_LANE1 0x05
347	#define BYTE_LANE2 0x06
348	#define BYTE_LANE3 0x07
349	#define SCSI_ZMODE 0x20
350	#define ZMODE 0x40
351	#define CTEST5_REG 0x19
352	#define MASTER_CONTROL 0x10
353	#define DMA_DIRECTION 0x08
354	#define CTEST7_REG 0x1B
355	#define BURST_DISABLE 0x80 /* 710 only */
356	#define SEL_TIMEOUT_DISABLE 0x10 /* 710 only */
357	#define DFP 0x08
358	#define EVP 0x04
63273134	359	#define CTEST7_TT1 0x02
1da177e4 LT	360	#define DIFF 0x01
	361	#define CTEST6_REG 0x1A
	362	#define TEMP_REG 0x1C
	363	#define DFIFO_REG 0x20
	364	#define FLUSH_DMA_FIFO 0x80
	365	#define CLR_FIFO 0x40
	366	#define ISTAT_REG 0x21
	367	#define ABORT_OPERATION 0x80
	368	#define SOFTWARE_RESET_710 0x40
	369	#define DMA_INT_PENDING 0x01
	370	#define SCSI_INT_PENDING 0x02
	371	#define CONNECTED 0x08
	372	#define CTEST8_REG 0x22
	373	#define LAST_DIS_ENBL 0x01
	374	#define SHORTEN_FILTERING 0x04
	375	#define ENABLE_ACTIVE_NEGATION 0x10
	376	#define GENERATE_RECEIVE_PARITY 0x20
	377	#define CLR_FIFO_710 0x04
	378	#define FLUSH_DMA_FIFO_710 0x08
	379	#define CTEST9_REG 0x23
	380	#define DBC_REG 0x24
	381	#define DCMD_REG 0x27
	382	#define DNAD_REG 0x28
	383	#define DIEN_REG 0x39
	384	#define BUS_FAULT 0x20
	385	#define ABORT_INT 0x10
	386	#define INT_INST_INT 0x04
	387	#define WD_INT 0x02
	388	#define ILGL_INST_INT 0x01
	389	#define DCNTL_REG 0x3B
	390	#define SOFTWARE_RESET 0x01
	391	#define COMPAT_700_MODE 0x01
	392	#define SCRPTS_16BITS 0x20
63273134	393	#define EA_710 0x20
1da177e4 LT	394	#define ASYNC_DIV_2_0 0x00
	395	#define ASYNC_DIV_1_5 0x40
	396	#define ASYNC_DIV_1_0 0x80
	397	#define ASYNC_DIV_3_0 0xc0
	398	#define DMODE_710_REG 0x38
	399	#define DMODE_700_REG 0x34
	400	#define BURST_LENGTH_1 0x00
	401	#define BURST_LENGTH_2 0x40
	402	#define BURST_LENGTH_4 0x80
	403	#define BURST_LENGTH_8 0xC0
	404	#define DMODE_FC1 0x10
	405	#define DMODE_FC2 0x20
	406	#define BW16 32
	407	#define MODE_286 16
	408	#define IO_XFER 8
	409	#define FIXED_ADDR 4
	410
	411	#define DSP_REG 0x2C
	412	#define DSPS_REG 0x30
	413
	414	/* Parameters to begin SDTR negotiations. Empirically, I find that
	415	* the 53c700-66 cannot handle an offset >8, so don't change this */
	416	#define NCR_700_MAX_OFFSET 8
	417	/* Was hoping the max offset would be greater for the 710, but
	418	* empirically it seems to be 8 also */
	419	#define NCR_710_MAX_OFFSET 8
	420	#define NCR_700_MIN_XFERP 1
	421	#define NCR_710_MIN_XFERP 0
	422	#define NCR_700_MIN_PERIOD 25 /* for SDTR message, 100ns */
	423
d3fa72e4	424	#define script_patch_32(dev, script, symbol, value) \
1da177e4 LT	425	{ \
1da177e4 LT	426	int i; \
0da21c44	427	dma_addr_t da = value; \
1da177e4	428	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0da21c44	429	__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]) + da; \
1da177e4	430	(script)[A_##symbol##_used[i]] = bS_to_host(val); \
d3fa72e4	431	dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
0da21c44 HD	432	DEBUG((" script, patching %s at %d to %pad\n", \
0da21c44 HD	433	#symbol, A_##symbol##_used[i], &da)); \
1da177e4 LT	434	} \
	435	}
	436
d3fa72e4	437	#define script_patch_32_abs(dev, script, symbol, value) \
1da177e4 LT	438	{ \
1da177e4 LT	439	int i; \
0da21c44	440	dma_addr_t da = value; \
1da177e4	441	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
0da21c44	442	(script)[A_##symbol##_used[i]] = bS_to_host(da); \
d3fa72e4	443	dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
0da21c44 HD	444	DEBUG((" script, patching %s at %d to %pad\n", \
0da21c44 HD	445	#symbol, A_##symbol##_used[i], &da)); \
1da177e4 LT	446	} \
	447	}
	448
	449	/* Used for patching the SCSI ID in the SELECT instruction */
d3fa72e4	450	#define script_patch_ID(dev, script, symbol, value) \
1da177e4 LT	451	{ \
	452	int i; \
	453	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
	454	__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
	455	val &= 0xff00ffff; \
	456	val \|= ((value) & 0xff) << 16; \
	457	(script)[A_##symbol##_used[i]] = bS_to_host(val); \
d3fa72e4	458	dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
1da177e4 LT	459	DEBUG((" script, patching ID field %s at %d to 0x%x\n", \
	460	#symbol, A_##symbol##_used[i], val)); \
	461	} \
	462	}
	463
d3fa72e4	464	#define script_patch_16(dev, script, symbol, value) \
1da177e4 LT	465	{ \
	466	int i; \
	467	for(i=0; i< (sizeof(A_##symbol##_used) / sizeof(__u32)); i++) { \
	468	__u32 val = bS_to_cpu((script)[A_##symbol##_used[i]]); \
	469	val &= 0xffff0000; \
	470	val \|= ((value) & 0xffff); \
	471	(script)[A_##symbol##_used[i]] = bS_to_host(val); \
d3fa72e4	472	dma_cache_sync((dev), &(script)[A_##symbol##_used[i]], 4, DMA_TO_DEVICE); \
1da177e4 LT	473	DEBUG((" script, patching short field %s at %d to 0x%x\n", \
	474	#symbol, A_##symbol##_used[i], val)); \
	475	} \
	476	}
	477
	478
	479	static inline __u8
56fece20	480	NCR_700_readb(struct Scsi_Host *host, __u32 reg)
1da177e4	481	{
56fece20	482	const struct NCR_700_Host_Parameters *hostdata
1da177e4 LT	483	= (struct NCR_700_Host_Parameters *)host->hostdata[0];
1da177e4 LT	484
56fece20	485	return ioread8(hostdata->base + (reg^bE));
1da177e4 LT	486	}
	487
	488	static inline __u32
56fece20	489	NCR_700_readl(struct Scsi_Host *host, __u32 reg)
1da177e4	490	{
56fece20	491	const struct NCR_700_Host_Parameters *hostdata
1da177e4	492	= (struct NCR_700_Host_Parameters *)host->hostdata[0];
8f23d475 JB	493	__u32 value = bEBus ? ioread32be(hostdata->base + reg) :
8f23d475 JB	494	ioread32(hostdata->base + reg);
1da177e4 LT	495	#if 1
1da177e4 LT	496	/* sanity check the register */
125e1874	497	BUG_ON((reg & 0x3) != 0);
1da177e4 LT	498	#endif
1da177e4 LT	499
8f23d475	500	return value;
1da177e4 LT	501	}
	502
	503	static inline void
56fece20	504	NCR_700_writeb(__u8 value, struct Scsi_Host *host, __u32 reg)
1da177e4	505	{
56fece20	506	const struct NCR_700_Host_Parameters *hostdata
1da177e4 LT	507	= (struct NCR_700_Host_Parameters *)host->hostdata[0];
1da177e4 LT	508
56fece20	509	iowrite8(value, hostdata->base + (reg^bE));
1da177e4 LT	510	}
	511
	512	static inline void
56fece20	513	NCR_700_writel(__u32 value, struct Scsi_Host *host, __u32 reg)
1da177e4	514	{
56fece20	515	const struct NCR_700_Host_Parameters *hostdata
1da177e4 LT	516	= (struct NCR_700_Host_Parameters *)host->hostdata[0];
	517
	518	#if 1
	519	/* sanity check the register */
125e1874	520	BUG_ON((reg & 0x3) != 0);
1da177e4 LT	521	#endif
1da177e4 LT	522
8f23d475 JB	523	bEBus ? iowrite32be(value, hostdata->base + reg):
8f23d475 JB	524	iowrite32(value, hostdata->base + reg);
1da177e4 LT	525	}
1da177e4 LT	526
1da177e4	527	#endif