[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hptiop.h

/*
 * HighPoint RR3xxx/4xxx controller driver for Linux
 * Copyright (C) 2006-2015 HighPoint Technologies, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * Please report bugs/comments/suggestions to linux@highpoint-tech.com
 *
 * For more information, visit http://www.highpoint-tech.com
 */
#ifndef _HPTIOP_H_
#define _HPTIOP_H_

struct hpt_iopmu_itl {
	__le32 resrved0[4];
	__le32 inbound_msgaddr0;
	__le32 inbound_msgaddr1;
	__le32 outbound_msgaddr0;
	__le32 outbound_msgaddr1;
	__le32 inbound_doorbell;
	__le32 inbound_intstatus;
	__le32 inbound_intmask;
	__le32 outbound_doorbell;
	__le32 outbound_intstatus;
	__le32 outbound_intmask;
	__le32 reserved1[2];
	__le32 inbound_queue;
	__le32 outbound_queue;
};

#define IOPMU_QUEUE_EMPTY            0xffffffff
#define IOPMU_QUEUE_MASK_HOST_BITS   0xf0000000
#define IOPMU_QUEUE_ADDR_HOST_BIT    0x80000000
#define IOPMU_QUEUE_REQUEST_SIZE_BIT    0x40000000
#define IOPMU_QUEUE_REQUEST_RESULT_BIT   0x40000000

#define IOPMU_OUTBOUND_INT_MSG0      1
#define IOPMU_OUTBOUND_INT_MSG1      2
#define IOPMU_OUTBOUND_INT_DOORBELL  4
#define IOPMU_OUTBOUND_INT_POSTQUEUE 8
#define IOPMU_OUTBOUND_INT_PCI       0x10

#define IOPMU_INBOUND_INT_MSG0       1
#define IOPMU_INBOUND_INT_MSG1       2
#define IOPMU_INBOUND_INT_DOORBELL   4
#define IOPMU_INBOUND_INT_ERROR      8
#define IOPMU_INBOUND_INT_POSTQUEUE  0x10

#define MVIOP_QUEUE_LEN  512

struct hpt_iopmu_mv {
	__le32 inbound_head;
	__le32 inbound_tail;
	__le32 outbound_head;
	__le32 outbound_tail;
	__le32 inbound_msg;
	__le32 outbound_msg;
	__le32 reserve[10];
	__le64 inbound_q[MVIOP_QUEUE_LEN];
	__le64 outbound_q[MVIOP_QUEUE_LEN];
};

struct hpt_iopmv_regs {
	__le32 reserved[0x20400 / 4];
	__le32 inbound_doorbell;
	__le32 inbound_intmask;
	__le32 outbound_doorbell;
	__le32 outbound_intmask;
};

#pragma pack(1)
struct hpt_iopmu_mvfrey {
	__le32 reserved0[(0x4000 - 0) / 4];
	__le32 inbound_base;
	__le32 inbound_base_high;
	__le32 reserved1[(0x4018 - 0x4008) / 4];
	__le32 inbound_write_ptr;
	__le32 reserved2[(0x402c - 0x401c) / 4];
	__le32 inbound_conf_ctl;
	__le32 reserved3[(0x4050 - 0x4030) / 4];
	__le32 outbound_base;
	__le32 outbound_base_high;
	__le32 outbound_shadow_base;
	__le32 outbound_shadow_base_high;
	__le32 reserved4[(0x4088 - 0x4060) / 4];
	__le32 isr_cause;
	__le32 isr_enable;
	__le32 reserved5[(0x1020c - 0x4090) / 4];
	__le32 pcie_f0_int_enable;
	__le32 reserved6[(0x10400 - 0x10210) / 4];
	__le32 f0_to_cpu_msg_a;
	__le32 reserved7[(0x10420 - 0x10404) / 4];
	__le32 cpu_to_f0_msg_a;
	__le32 reserved8[(0x10480 - 0x10424) / 4];
	__le32 f0_doorbell;
	__le32 f0_doorbell_enable;
};

struct mvfrey_inlist_entry {
	dma_addr_t addr;
	__le32 intrfc_len;
	__le32 reserved;
};

struct mvfrey_outlist_entry {
	__le32 val;
};
#pragma pack()

#define MVIOP_MU_QUEUE_ADDR_HOST_MASK   (~(0x1full))
#define MVIOP_MU_QUEUE_ADDR_HOST_BIT    4

#define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32  0xffffffff
#define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT   1
#define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2

#define MVIOP_MU_INBOUND_INT_MSG        1
#define MVIOP_MU_INBOUND_INT_POSTQUEUE  2
#define MVIOP_MU_OUTBOUND_INT_MSG       1
#define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2

#define CL_POINTER_TOGGLE        0x00004000
#define CPU_TO_F0_DRBL_MSG_BIT   0x02000000

enum hpt_iopmu_message {
	/* host-to-iop messages */
	IOPMU_INBOUND_MSG0_NOP = 0,
	IOPMU_INBOUND_MSG0_RESET,
	IOPMU_INBOUND_MSG0_FLUSH,
	IOPMU_INBOUND_MSG0_SHUTDOWN,
	IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
	IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
	IOPMU_INBOUND_MSG0_RESET_COMM,
	IOPMU_INBOUND_MSG0_MAX = 0xff,
	/* iop-to-host messages */
	IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
	IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
	IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
	IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
	IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
	IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
};

struct hpt_iop_request_header {
	__le32 size;
	__le32 type;
	__le32 flags;
	__le32 result;
	__le32 context; /* host context */
	__le32 context_hi32;
};

#define IOP_REQUEST_FLAG_SYNC_REQUEST 1
#define IOP_REQUEST_FLAG_BIST_REQUEST 2
#define IOP_REQUEST_FLAG_REMAPPED     4
#define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
#define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */

enum hpt_iop_request_type {
	IOP_REQUEST_TYPE_GET_CONFIG = 0,
	IOP_REQUEST_TYPE_SET_CONFIG,
	IOP_REQUEST_TYPE_BLOCK_COMMAND,
	IOP_REQUEST_TYPE_SCSI_COMMAND,
	IOP_REQUEST_TYPE_IOCTL_COMMAND,
	IOP_REQUEST_TYPE_MAX
};

enum hpt_iop_result_type {
	IOP_RESULT_PENDING = 0,
	IOP_RESULT_SUCCESS,
	IOP_RESULT_FAIL,
	IOP_RESULT_BUSY,
	IOP_RESULT_RESET,
	IOP_RESULT_INVALID_REQUEST,
	IOP_RESULT_BAD_TARGET,
	IOP_RESULT_CHECK_CONDITION,
};

struct hpt_iop_request_get_config {
	struct hpt_iop_request_header header;
	__le32 interface_version;
	__le32 firmware_version;
	__le32 max_requests;
	__le32 request_size;
	__le32 max_sg_count;
	__le32 data_transfer_length;
	__le32 alignment_mask;
	__le32 max_devices;
	__le32 sdram_size;
};

struct hpt_iop_request_set_config {
	struct hpt_iop_request_header header;
	__le32 iop_id;
	__le16 vbus_id;
	__le16 max_host_request_size;
	__le32 reserve[6];
};

struct hpt_iopsg {
	__le32 size;
	__le32 eot; /* non-zero: end of table */
	__le64 pci_address;
};

struct hpt_iop_request_block_command {
	struct hpt_iop_request_header header;
	u8     channel;
	u8     target;
	u8     lun;
	u8     pad1;
	__le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */
	__le16 sectors;
	__le64 lba;
	struct hpt_iopsg sg_list[1];
};

#define IOP_BLOCK_COMMAND_READ     1
#define IOP_BLOCK_COMMAND_WRITE    2
#define IOP_BLOCK_COMMAND_VERIFY   3
#define IOP_BLOCK_COMMAND_FLUSH    4
#define IOP_BLOCK_COMMAND_SHUTDOWN 5

struct hpt_iop_request_scsi_command {
	struct hpt_iop_request_header header;
	u8     channel;
	u8     target;
	u8     lun;
	u8     pad1;
	u8     cdb[16];
	__le32 dataxfer_length;
	struct hpt_iopsg sg_list[1];
};

struct hpt_iop_request_ioctl_command {
	struct hpt_iop_request_header header;
	__le32 ioctl_code;
	__le32 inbuf_size;
	__le32 outbuf_size;
	__le32 bytes_returned;
	u8     buf[1];
	/* out data should be put at buf[(inbuf_size+3)&~3] */
};

#define HPTIOP_MAX_REQUESTS  256u

struct hptiop_request {
	struct hptiop_request *next;
	void                  *req_virt;
	u32                   req_shifted_phy;
	struct scsi_cmnd      *scp;
	int                   index;
};

struct hpt_scsi_pointer {
	int mapped;
	int sgcnt;
	dma_addr_t dma_handle;
};

#define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp)

enum hptiop_family {
	UNKNOWN_BASED_IOP,
	INTEL_BASED_IOP,
	MV_BASED_IOP,
	MVFREY_BASED_IOP
} ;

struct hptiop_hba {
	struct hptiop_adapter_ops *ops;
	union {
		struct {
			struct hpt_iopmu_itl __iomem *iop;
			void __iomem *plx;
		} itl;
		struct {
			struct hpt_iopmv_regs *regs;
			struct hpt_iopmu_mv __iomem *mu;
			void *internal_req;
			dma_addr_t internal_req_phy;
		} mv;
		struct {
			struct hpt_iop_request_get_config __iomem *config;
			struct hpt_iopmu_mvfrey __iomem *mu;

			int internal_mem_size;
			struct hptiop_request internal_req;
			int list_count;
			struct mvfrey_inlist_entry *inlist;
			dma_addr_t inlist_phy;
			__le32 inlist_wptr;
			struct mvfrey_outlist_entry *outlist;
			dma_addr_t outlist_phy;
			__le32 *outlist_cptr; /* copy pointer shadow */
			dma_addr_t outlist_cptr_phy;
			__le32 outlist_rptr;
		} mvfrey;
	} u;

	struct Scsi_Host *host;
	struct pci_dev *pcidev;

	/* IOP config info */
	u32     interface_version;
	u32     firmware_version;
	u32     sdram_size;
	u32     max_devices;
	u32     max_requests;
	u32     max_request_size;
	u32     max_sg_descriptors;

	u32     req_size; /* host-allocated request buffer size */

	u32     iopintf_v2: 1;
	u32     initialized: 1;
	u32     msg_done: 1;

	struct hptiop_request * req_list;
	struct hptiop_request reqs[HPTIOP_MAX_REQUESTS];

	/* used to free allocated dma area */
	void        *dma_coherent[HPTIOP_MAX_REQUESTS];
	dma_addr_t  dma_coherent_handle[HPTIOP_MAX_REQUESTS];

	atomic_t    reset_count;
	atomic_t    resetting;

	wait_queue_head_t reset_wq;
	wait_queue_head_t ioctl_wq;
};

struct hpt_ioctl_k {
	struct hptiop_hba * hba;
	u32    ioctl_code;
	u32    inbuf_size;
	u32    outbuf_size;
	void   *inbuf;
	void   *outbuf;
	u32    *bytes_returned;
	void (*done)(struct hpt_ioctl_k *);
	int    result; /* HPT_IOCTL_RESULT_ */
};

struct hptiop_adapter_ops {
	enum hptiop_family family;
	int  (*iop_wait_ready)(struct hptiop_hba *hba, u32 millisec);
	int  (*internal_memalloc)(struct hptiop_hba *hba);
	int  (*internal_memfree)(struct hptiop_hba *hba);
	int  (*map_pci_bar)(struct hptiop_hba *hba);
	void (*unmap_pci_bar)(struct hptiop_hba *hba);
	void (*enable_intr)(struct hptiop_hba *hba);
	void (*disable_intr)(struct hptiop_hba *hba);
	int  (*get_config)(struct hptiop_hba *hba,
				struct hpt_iop_request_get_config *config);
	int  (*set_config)(struct hptiop_hba *hba,
				struct hpt_iop_request_set_config *config);
	int  (*iop_intr)(struct hptiop_hba *hba);
	void (*post_msg)(struct hptiop_hba *hba, u32 msg);
	void (*post_req)(struct hptiop_hba *hba, struct hptiop_request *_req);
	int  hw_dma_bit_mask;
	int  (*reset_comm)(struct hptiop_hba *hba);
	__le64  host_phy_flag;
};

#define HPT_IOCTL_RESULT_OK         0
#define HPT_IOCTL_RESULT_FAILED     (-1)

#if 0
#define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0)
#else
#define dprintk(fmt, args...)
#endif

#endif
Commit	Line	Data
ede1e6f8	1	/*
00f59701	2	* HighPoint RR3xxx/4xxx controller driver for Linux
a93429c3	3	* Copyright (C) 2006-2015 HighPoint Technologies, Inc. All Rights Reserved.
ede1e6f8 HLT	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* Please report bugs/comments/suggestions to linux@highpoint-tech.com
	15	*
	16	* For more information, visit http://www.highpoint-tech.com
	17	*/
	18	#ifndef _HPTIOP_H_
	19	#define _HPTIOP_H_
	20
00f59701	21	struct hpt_iopmu_itl {
ede1e6f8 HLT	22	__le32 resrved0[4];
	23	__le32 inbound_msgaddr0;
	24	__le32 inbound_msgaddr1;
	25	__le32 outbound_msgaddr0;
	26	__le32 outbound_msgaddr1;
	27	__le32 inbound_doorbell;
	28	__le32 inbound_intstatus;
	29	__le32 inbound_intmask;
	30	__le32 outbound_doorbell;
	31	__le32 outbound_intstatus;
	32	__le32 outbound_intmask;
	33	__le32 reserved1[2];
	34	__le32 inbound_queue;
	35	__le32 outbound_queue;
	36	};
	37
	38	#define IOPMU_QUEUE_EMPTY 0xffffffff
	39	#define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000
	40	#define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000
db9b6e89 HLT	41	#define IOPMU_QUEUE_REQUEST_SIZE_BIT 0x40000000
db9b6e89 HLT	42	#define IOPMU_QUEUE_REQUEST_RESULT_BIT 0x40000000
ede1e6f8 HLT	43
	44	#define IOPMU_OUTBOUND_INT_MSG0 1
	45	#define IOPMU_OUTBOUND_INT_MSG1 2
	46	#define IOPMU_OUTBOUND_INT_DOORBELL 4
	47	#define IOPMU_OUTBOUND_INT_POSTQUEUE 8
	48	#define IOPMU_OUTBOUND_INT_PCI 0x10
	49
	50	#define IOPMU_INBOUND_INT_MSG0 1
	51	#define IOPMU_INBOUND_INT_MSG1 2
	52	#define IOPMU_INBOUND_INT_DOORBELL 4
	53	#define IOPMU_INBOUND_INT_ERROR 8
	54	#define IOPMU_INBOUND_INT_POSTQUEUE 0x10
	55
00f59701 HLT	56	#define MVIOP_QUEUE_LEN 512
	57
	58	struct hpt_iopmu_mv {
	59	__le32 inbound_head;
	60	__le32 inbound_tail;
	61	__le32 outbound_head;
	62	__le32 outbound_tail;
	63	__le32 inbound_msg;
	64	__le32 outbound_msg;
	65	__le32 reserve[10];
	66	__le64 inbound_q[MVIOP_QUEUE_LEN];
	67	__le64 outbound_q[MVIOP_QUEUE_LEN];
	68	};
	69
	70	struct hpt_iopmv_regs {
	71	__le32 reserved[0x20400 / 4];
	72	__le32 inbound_doorbell;
	73	__le32 inbound_intmask;
	74	__le32 outbound_doorbell;
	75	__le32 outbound_intmask;
	76	};
	77
286aa031 HLT	78	#pragma pack(1)
	79	struct hpt_iopmu_mvfrey {
	80	__le32 reserved0[(0x4000 - 0) / 4];
	81	__le32 inbound_base;
	82	__le32 inbound_base_high;
	83	__le32 reserved1[(0x4018 - 0x4008) / 4];
	84	__le32 inbound_write_ptr;
	85	__le32 reserved2[(0x402c - 0x401c) / 4];
	86	__le32 inbound_conf_ctl;
	87	__le32 reserved3[(0x4050 - 0x4030) / 4];
	88	__le32 outbound_base;
	89	__le32 outbound_base_high;
	90	__le32 outbound_shadow_base;
	91	__le32 outbound_shadow_base_high;
	92	__le32 reserved4[(0x4088 - 0x4060) / 4];
	93	__le32 isr_cause;
	94	__le32 isr_enable;
	95	__le32 reserved5[(0x1020c - 0x4090) / 4];
	96	__le32 pcie_f0_int_enable;
	97	__le32 reserved6[(0x10400 - 0x10210) / 4];
	98	__le32 f0_to_cpu_msg_a;
	99	__le32 reserved7[(0x10420 - 0x10404) / 4];
	100	__le32 cpu_to_f0_msg_a;
	101	__le32 reserved8[(0x10480 - 0x10424) / 4];
	102	__le32 f0_doorbell;
	103	__le32 f0_doorbell_enable;
	104	};
	105
	106	struct mvfrey_inlist_entry {
	107	dma_addr_t addr;
	108	__le32 intrfc_len;
	109	__le32 reserved;
	110	};
	111
	112	struct mvfrey_outlist_entry {
	113	__le32 val;
	114	};
	115	#pragma pack()
	116
00f59701 HLT	117	#define MVIOP_MU_QUEUE_ADDR_HOST_MASK (~(0x1full))
	118	#define MVIOP_MU_QUEUE_ADDR_HOST_BIT 4
	119
	120	#define MVIOP_MU_QUEUE_ADDR_IOP_HIGH32 0xffffffff
	121	#define MVIOP_MU_QUEUE_REQUEST_RESULT_BIT 1
	122	#define MVIOP_MU_QUEUE_REQUEST_RETURN_CONTEXT 2
	123
	124	#define MVIOP_MU_INBOUND_INT_MSG 1
	125	#define MVIOP_MU_INBOUND_INT_POSTQUEUE 2
	126	#define MVIOP_MU_OUTBOUND_INT_MSG 1
	127	#define MVIOP_MU_OUTBOUND_INT_POSTQUEUE 2
	128
286aa031 HLT	129	#define CL_POINTER_TOGGLE 0x00004000
	130	#define CPU_TO_F0_DRBL_MSG_BIT 0x02000000
	131
ede1e6f8 HLT	132	enum hpt_iopmu_message {
	133	/* host-to-iop messages */
	134	IOPMU_INBOUND_MSG0_NOP = 0,
	135	IOPMU_INBOUND_MSG0_RESET,
	136	IOPMU_INBOUND_MSG0_FLUSH,
	137	IOPMU_INBOUND_MSG0_SHUTDOWN,
	138	IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
	139	IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
286aa031	140	IOPMU_INBOUND_MSG0_RESET_COMM,
ede1e6f8 HLT	141	IOPMU_INBOUND_MSG0_MAX = 0xff,
	142	/* iop-to-host messages */
	143	IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
	144	IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
	145	IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
	146	IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
	147	IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
	148	IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
	149	};
	150
00f59701	151	struct hpt_iop_request_header {
ede1e6f8 HLT	152	__le32 size;
	153	__le32 type;
	154	__le32 flags;
	155	__le32 result;
	156	__le32 context; /* host context */
	157	__le32 context_hi32;
	158	};
	159
	160	#define IOP_REQUEST_FLAG_SYNC_REQUEST 1
	161	#define IOP_REQUEST_FLAG_BIST_REQUEST 2
	162	#define IOP_REQUEST_FLAG_REMAPPED 4
	163	#define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
286aa031	164	#define IOP_REQUEST_FLAG_ADDR_BITS 0x40 /* flags[31:16] is phy_addr[47:32] */
ede1e6f8 HLT	165
	166	enum hpt_iop_request_type {
	167	IOP_REQUEST_TYPE_GET_CONFIG = 0,
	168	IOP_REQUEST_TYPE_SET_CONFIG,
	169	IOP_REQUEST_TYPE_BLOCK_COMMAND,
	170	IOP_REQUEST_TYPE_SCSI_COMMAND,
	171	IOP_REQUEST_TYPE_IOCTL_COMMAND,
	172	IOP_REQUEST_TYPE_MAX
	173	};
	174
	175	enum hpt_iop_result_type {
	176	IOP_RESULT_PENDING = 0,
	177	IOP_RESULT_SUCCESS,
	178	IOP_RESULT_FAIL,
	179	IOP_RESULT_BUSY,
	180	IOP_RESULT_RESET,
	181	IOP_RESULT_INVALID_REQUEST,
	182	IOP_RESULT_BAD_TARGET,
00f59701	183	IOP_RESULT_CHECK_CONDITION,
ede1e6f8 HLT	184	};
ede1e6f8 HLT	185
00f59701	186	struct hpt_iop_request_get_config {
ede1e6f8 HLT	187	struct hpt_iop_request_header header;
	188	__le32 interface_version;
	189	__le32 firmware_version;
	190	__le32 max_requests;
	191	__le32 request_size;
	192	__le32 max_sg_count;
	193	__le32 data_transfer_length;
	194	__le32 alignment_mask;
	195	__le32 max_devices;
	196	__le32 sdram_size;
	197	};
	198
00f59701	199	struct hpt_iop_request_set_config {
ede1e6f8 HLT	200	struct hpt_iop_request_header header;
ede1e6f8 HLT	201	__le32 iop_id;
db9b6e89 HLT	202	__le16 vbus_id;
db9b6e89 HLT	203	__le16 max_host_request_size;
ede1e6f8 HLT	204	__le32 reserve[6];
	205	};
	206
00f59701	207	struct hpt_iopsg {
ede1e6f8 HLT	208	__le32 size;
	209	__le32 eot; /* non-zero: end of table */
	210	__le64 pci_address;
	211	};
	212
00f59701	213	struct hpt_iop_request_block_command {
ede1e6f8 HLT	214	struct hpt_iop_request_header header;
	215	u8 channel;
	216	u8 target;
	217	u8 lun;
	218	u8 pad1;
	219	__le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */
	220	__le16 sectors;
	221	__le64 lba;
	222	struct hpt_iopsg sg_list[1];
	223	};
	224
	225	#define IOP_BLOCK_COMMAND_READ 1
	226	#define IOP_BLOCK_COMMAND_WRITE 2
	227	#define IOP_BLOCK_COMMAND_VERIFY 3
	228	#define IOP_BLOCK_COMMAND_FLUSH 4
	229	#define IOP_BLOCK_COMMAND_SHUTDOWN 5
	230
00f59701	231	struct hpt_iop_request_scsi_command {
ede1e6f8 HLT	232	struct hpt_iop_request_header header;
	233	u8 channel;
	234	u8 target;
	235	u8 lun;
	236	u8 pad1;
	237	u8 cdb[16];
	238	__le32 dataxfer_length;
	239	struct hpt_iopsg sg_list[1];
	240	};
	241
00f59701	242	struct hpt_iop_request_ioctl_command {
ede1e6f8 HLT	243	struct hpt_iop_request_header header;
	244	__le32 ioctl_code;
	245	__le32 inbuf_size;
	246	__le32 outbuf_size;
	247	__le32 bytes_returned;
	248	u8 buf[1];
	249	/* out data should be put at buf[(inbuf_size+3)&~3] */
	250	};
	251
	252	#define HPTIOP_MAX_REQUESTS 256u
	253
	254	struct hptiop_request {
00f59701 HLT	255	struct hptiop_request *next;
	256	void *req_virt;
	257	u32 req_shifted_phy;
	258	struct scsi_cmnd *scp;
	259	int index;
ede1e6f8 HLT	260	};
	261
	262	struct hpt_scsi_pointer {
	263	int mapped;
	264	int sgcnt;
	265	dma_addr_t dma_handle;
	266	};
	267
	268	#define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp)
	269
286aa031 HLT	270	enum hptiop_family {
	271	UNKNOWN_BASED_IOP,
	272	INTEL_BASED_IOP,
	273	MV_BASED_IOP,
	274	MVFREY_BASED_IOP
	275	} ;
	276
ede1e6f8	277	struct hptiop_hba {
00f59701 HLT	278	struct hptiop_adapter_ops *ops;
	279	union {
	280	struct {
	281	struct hpt_iopmu_itl __iomem *iop;
3bfc13c2	282	void __iomem *plx;
00f59701 HLT	283	} itl;
	284	struct {
	285	struct hpt_iopmv_regs *regs;
	286	struct hpt_iopmu_mv __iomem *mu;
	287	void *internal_req;
	288	dma_addr_t internal_req_phy;
	289	} mv;
286aa031 HLT	290	struct {
	291	struct hpt_iop_request_get_config __iomem *config;
	292	struct hpt_iopmu_mvfrey __iomem *mu;
	293
	294	int internal_mem_size;
	295	struct hptiop_request internal_req;
	296	int list_count;
	297	struct mvfrey_inlist_entry *inlist;
	298	dma_addr_t inlist_phy;
	299	__le32 inlist_wptr;
	300	struct mvfrey_outlist_entry *outlist;
	301	dma_addr_t outlist_phy;
	302	__le32 outlist_cptr; / copy pointer shadow */
	303	dma_addr_t outlist_cptr_phy;
	304	__le32 outlist_rptr;
	305	} mvfrey;
00f59701 HLT	306	} u;
	307
	308	struct Scsi_Host *host;
	309	struct pci_dev *pcidev;
ede1e6f8	310
ede1e6f8	311	/* IOP config info */
db9b6e89	312	u32 interface_version;
ede1e6f8 HLT	313	u32 firmware_version;
	314	u32 sdram_size;
	315	u32 max_devices;
	316	u32 max_requests;
	317	u32 max_request_size;
	318	u32 max_sg_descriptors;
	319
	320	u32 req_size; /* host-allocated request buffer size */
db9b6e89	321
00f59701 HLT	322	u32 iopintf_v2: 1;
	323	u32 initialized: 1;
	324	u32 msg_done: 1;
ede1e6f8 HLT	325
	326	struct hptiop_request * req_list;
	327	struct hptiop_request reqs[HPTIOP_MAX_REQUESTS];
	328
	329	/* used to free allocated dma area */
a93429c3	330	void *dma_coherent[HPTIOP_MAX_REQUESTS];
a93429c3	331	dma_addr_t dma_coherent_handle[HPTIOP_MAX_REQUESTS];
ede1e6f8 HLT	332
	333	atomic_t reset_count;
	334	atomic_t resetting;
	335
	336	wait_queue_head_t reset_wq;
	337	wait_queue_head_t ioctl_wq;
	338	};
	339
00f59701	340	struct hpt_ioctl_k {
ede1e6f8 HLT	341	struct hptiop_hba * hba;
	342	u32 ioctl_code;
	343	u32 inbuf_size;
	344	u32 outbuf_size;
00f59701 HLT	345	void *inbuf;
	346	void *outbuf;
	347	u32 *bytes_returned;
ede1e6f8 HLT	348	void (done)(struct hpt_ioctl_k );
	349	int result; /* HPT_IOCTL_RESULT_ */
	350	};
	351
00f59701	352	struct hptiop_adapter_ops {
286aa031	353	enum hptiop_family family;
00f59701 HLT	354	int (iop_wait_ready)(struct hptiop_hba hba, u32 millisec);
	355	int (internal_memalloc)(struct hptiop_hba hba);
	356	int (internal_memfree)(struct hptiop_hba hba);
	357	int (map_pci_bar)(struct hptiop_hba hba);
	358	void (unmap_pci_bar)(struct hptiop_hba hba);
	359	void (enable_intr)(struct hptiop_hba hba);
	360	void (disable_intr)(struct hptiop_hba hba);
	361	int (get_config)(struct hptiop_hba hba,
	362	struct hpt_iop_request_get_config *config);
	363	int (set_config)(struct hptiop_hba hba,
	364	struct hpt_iop_request_set_config *config);
	365	int (iop_intr)(struct hptiop_hba hba);
	366	void (post_msg)(struct hptiop_hba hba, u32 msg);
	367	void (post_req)(struct hptiop_hba hba, struct hptiop_request *_req);
23f0bb47	368	int hw_dma_bit_mask;
286aa031 HLT	369	int (reset_comm)(struct hptiop_hba hba);
286aa031 HLT	370	__le64 host_phy_flag;
00f59701 HLT	371	};
00f59701 HLT	372
ede1e6f8 HLT	373	#define HPT_IOCTL_RESULT_OK 0
	374	#define HPT_IOCTL_RESULT_FAILED (-1)
	375
	376	#if 0
	377	#define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0)
	378	#else
	379	#define dprintk(fmt, args...)
	380	#endif
	381
	382	#endif