projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /****************************************************************************** |
| 2 | * QLOGIC LINUX SOFTWARE | |
| 3 | * | |
| 4 | * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver | |
| 5 | * Copyright (C) 2000 Qlogic Corporation | |
| 6 | * (www.qlogic.com) | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or modify it | |
| 9 | * under the terms of the GNU General Public License as published by the | |
| 10 | * Free Software Foundation; either version 2, or (at your option) any | |
| 11 | * later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, but | |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
| 16 | * General Public License for more details. | |
| 17 | * | |
| 18 | ******************************************************************************/ | |
| 19 | ||
| 20 | #ifndef _QLA1280_H | |
| 21 | #define _QLA1280_H | |
| 22 | ||
| 23 | /* | |
| 24 | * Data bit definitions. | |
| 25 | */ | |
| 26 | #define BIT_0 0x1 | |
| 27 | #define BIT_1 0x2 | |
| 28 | #define BIT_2 0x4 | |
| 29 | #define BIT_3 0x8 | |
| 30 | #define BIT_4 0x10 | |
| 31 | #define BIT_5 0x20 | |
| 32 | #define BIT_6 0x40 | |
| 33 | #define BIT_7 0x80 | |
| 34 | #define BIT_8 0x100 | |
| 35 | #define BIT_9 0x200 | |
| 36 | #define BIT_10 0x400 | |
| 37 | #define BIT_11 0x800 | |
| 38 | #define BIT_12 0x1000 | |
| 39 | #define BIT_13 0x2000 | |
| 40 | #define BIT_14 0x4000 | |
| 41 | #define BIT_15 0x8000 | |
| 42 | #define BIT_16 0x10000 | |
| 43 | #define BIT_17 0x20000 | |
| 44 | #define BIT_18 0x40000 | |
| 45 | #define BIT_19 0x80000 | |
| 46 | #define BIT_20 0x100000 | |
| 47 | #define BIT_21 0x200000 | |
| 48 | #define BIT_22 0x400000 | |
| 49 | #define BIT_23 0x800000 | |
| 50 | #define BIT_24 0x1000000 | |
| 51 | #define BIT_25 0x2000000 | |
| 52 | #define BIT_26 0x4000000 | |
| 53 | #define BIT_27 0x8000000 | |
| 54 | #define BIT_28 0x10000000 | |
| 55 | #define BIT_29 0x20000000 | |
| 56 | #define BIT_30 0x40000000 | |
| 57 | #define BIT_31 0x80000000 | |
| 58 | ||
| 59 | #if MEMORY_MAPPED_IO | |
| 60 | #define RD_REG_WORD(addr) readw_relaxed(addr) | |
| 61 | #define RD_REG_WORD_dmasync(addr) readw(addr) | |
| 62 | #define WRT_REG_WORD(addr, data) writew(data, addr) | |
| 63 | #else /* MEMORY_MAPPED_IO */ | |
| 64 | #define RD_REG_WORD(addr) inw((unsigned long)addr) | |
| 65 | #define RD_REG_WORD_dmasync(addr) RD_REG_WORD(addr) | |
| 66 | #define WRT_REG_WORD(addr, data) outw(data, (unsigned long)addr) | |
| 67 | #endif /* MEMORY_MAPPED_IO */ | |
| 68 | ||
| 69 | /* | |
| 70 | * Host adapter default definitions. | |
| 71 | */ | |
| 72 | #define MAX_BUSES 2 /* 2 */ | |
| 73 | #define MAX_B_BITS 1 | |
| 74 | ||
| 75 | #define MAX_TARGETS 16 /* 16 */ | |
| 76 | #define MAX_T_BITS 4 /* 4 */ | |
| 77 | ||
| 78 | #define MAX_LUNS 8 /* 32 */ | |
| 79 | #define MAX_L_BITS 3 /* 5 */ | |
| 80 | ||
| 81 | /* | |
| 82 | * Watchdog time quantum | |
| 83 | */ | |
| 84 | #define QLA1280_WDG_TIME_QUANTUM 5 /* In seconds */ | |
| 85 | ||
| 86 | /* Command retry count (0-65535) */ | |
| 87 | #define COMMAND_RETRY_COUNT 255 | |
| 88 | ||
| 89 | /* Maximum outstanding commands in ISP queues */ | |
| 90 | #define MAX_OUTSTANDING_COMMANDS 512 | |
| 413e6e18 MR |
91 | #define COMPLETED_HANDLE ((unsigned char *) \ |
| 92 | (MAX_OUTSTANDING_COMMANDS + 2)) | |
| 1da177e4 LT |
93 | |
| 94 | /* ISP request and response entry counts (37-65535) */ | |
| 20d2d3af JD |
95 | #define REQUEST_ENTRY_CNT 255 /* Number of request entries. */ |
| 96 | #define RESPONSE_ENTRY_CNT 63 /* Number of response entries. */ | |
| 1da177e4 | 97 | |
| 1da177e4 LT |
98 | /* |
| 99 | * SCSI Request Block structure (sp) that is placed | |
| 100 | * on cmd->SCp location of every I/O | |
| 101 | */ | |
| 102 | struct srb { | |
| 103 | struct list_head list; /* (8/16) LU queue */ | |
| 104 | struct scsi_cmnd *cmd; /* (4/8) SCSI command block */ | |
| 105 | /* NOTE: the sp->cmd will be NULL when this completion is | |
| 106 | * called, so you should know the scsi_cmnd when using this */ | |
| 107 | struct completion *wait; | |
| 108 | dma_addr_t saved_dma_handle; /* for unmap of single transfers */ | |
| 109 | uint8_t flags; /* (1) Status flags. */ | |
| 110 | uint8_t dir; /* direction of transfer */ | |
| 111 | }; | |
| 112 | ||
| 113 | /* | |
| 114 | * SRB flag definitions | |
| 115 | */ | |
| 116 | #define SRB_TIMEOUT (1 << 0) /* Command timed out */ | |
| 117 | #define SRB_SENT (1 << 1) /* Command sent to ISP */ | |
| 118 | #define SRB_ABORT_PENDING (1 << 2) /* Command abort sent to device */ | |
| 119 | #define SRB_ABORTED (1 << 3) /* Command aborted command already */ | |
| 120 | ||
| 121 | /* | |
| 122 | * ISP I/O Register Set structure definitions. | |
| 123 | */ | |
| 124 | struct device_reg { | |
| 125 | uint16_t id_l; /* ID low */ | |
| 126 | uint16_t id_h; /* ID high */ | |
| 127 | uint16_t cfg_0; /* Configuration 0 */ | |
| 128 | #define ISP_CFG0_HWMSK 0x000f /* Hardware revision mask */ | |
| 129 | #define ISP_CFG0_1020 BIT_0 /* ISP1020 */ | |
| 130 | #define ISP_CFG0_1020A BIT_1 /* ISP1020A */ | |
| 131 | #define ISP_CFG0_1040 BIT_2 /* ISP1040 */ | |
| 132 | #define ISP_CFG0_1040A BIT_3 /* ISP1040A */ | |
| 133 | #define ISP_CFG0_1040B BIT_4 /* ISP1040B */ | |
| 134 | #define ISP_CFG0_1040C BIT_5 /* ISP1040C */ | |
| 135 | uint16_t cfg_1; /* Configuration 1 */ | |
| 136 | #define ISP_CFG1_F128 BIT_6 /* 128-byte FIFO threshold */ | |
| 137 | #define ISP_CFG1_F64 BIT_4|BIT_5 /* 128-byte FIFO threshold */ | |
| 138 | #define ISP_CFG1_F32 BIT_5 /* 128-byte FIFO threshold */ | |
| 139 | #define ISP_CFG1_F16 BIT_4 /* 128-byte FIFO threshold */ | |
| 140 | #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */ | |
| 141 | #define ISP_CFG1_SXP BIT_0 /* SXP register select */ | |
| 142 | uint16_t ictrl; /* Interface control */ | |
| 143 | #define ISP_RESET BIT_0 /* ISP soft reset */ | |
| 144 | #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */ | |
| 145 | #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */ | |
| 146 | #define ISP_FLASH_ENABLE BIT_8 /* Flash BIOS Read/Write enable */ | |
| 147 | #define ISP_FLASH_UPPER BIT_9 /* Flash upper bank select */ | |
| 148 | uint16_t istatus; /* Interface status */ | |
| 149 | #define PCI_64BIT_SLOT BIT_14 /* PCI 64-bit slot indicator. */ | |
| 150 | #define RISC_INT BIT_2 /* RISC interrupt */ | |
| 151 | #define PCI_INT BIT_1 /* PCI interrupt */ | |
| 152 | uint16_t semaphore; /* Semaphore */ | |
| 153 | uint16_t nvram; /* NVRAM register. */ | |
| 154 | #define NV_DESELECT 0 | |
| 155 | #define NV_CLOCK BIT_0 | |
| 156 | #define NV_SELECT BIT_1 | |
| 157 | #define NV_DATA_OUT BIT_2 | |
| 158 | #define NV_DATA_IN BIT_3 | |
| 159 | uint16_t flash_data; /* Flash BIOS data */ | |
| 160 | uint16_t flash_address; /* Flash BIOS address */ | |
| 161 | ||
| 162 | uint16_t unused_1[0x06]; | |
| 163 | ||
| 164 | /* cdma_* and ddma_* are 1040 only */ | |
| 165 | uint16_t cdma_cfg; | |
| 166 | #define CDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ | |
| 167 | #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ | |
| 168 | #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */ | |
| 169 | #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ | |
| 170 | uint16_t cdma_ctrl; | |
| 171 | uint16_t cdma_status; | |
| 172 | uint16_t cdma_fifo_status; | |
| 173 | uint16_t cdma_count; | |
| 174 | uint16_t cdma_reserved; | |
| 175 | uint16_t cdma_address_count_0; | |
| 176 | uint16_t cdma_address_count_1; | |
| 177 | uint16_t cdma_address_count_2; | |
| 178 | uint16_t cdma_address_count_3; | |
| 179 | ||
| 180 | uint16_t unused_2[0x06]; | |
| 181 | ||
| 182 | uint16_t ddma_cfg; | |
| 183 | #define DDMA_CONF_SENAB BIT_3 /* SXP to DMA Data enable */ | |
| 184 | #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */ | |
| 185 | #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */ | |
| 186 | #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ | |
| 187 | uint16_t ddma_ctrl; | |
| 188 | uint16_t ddma_status; | |
| 189 | uint16_t ddma_fifo_status; | |
| 190 | uint16_t ddma_xfer_count_low; | |
| 191 | uint16_t ddma_xfer_count_high; | |
| 192 | uint16_t ddma_addr_count_0; | |
| 193 | uint16_t ddma_addr_count_1; | |
| 194 | uint16_t ddma_addr_count_2; | |
| 195 | uint16_t ddma_addr_count_3; | |
| 196 | ||
| 197 | uint16_t unused_3[0x0e]; | |
| 198 | ||
| 199 | uint16_t mailbox0; /* Mailbox 0 */ | |
| 200 | uint16_t mailbox1; /* Mailbox 1 */ | |
| 201 | uint16_t mailbox2; /* Mailbox 2 */ | |
| 202 | uint16_t mailbox3; /* Mailbox 3 */ | |
| 203 | uint16_t mailbox4; /* Mailbox 4 */ | |
| 204 | uint16_t mailbox5; /* Mailbox 5 */ | |
| 205 | uint16_t mailbox6; /* Mailbox 6 */ | |
| 206 | uint16_t mailbox7; /* Mailbox 7 */ | |
| 207 | ||
| 208 | uint16_t unused_4[0x20];/* 0x80-0xbf Gap */ | |
| 209 | ||
| 210 | uint16_t host_cmd; /* Host command and control */ | |
| 211 | #define HOST_INT BIT_7 /* host interrupt bit */ | |
| 212 | #define BIOS_ENABLE BIT_0 | |
| 213 | ||
| 214 | uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */ | |
| 215 | ||
| 216 | uint16_t gpio_data; | |
| 217 | uint16_t gpio_enable; | |
| 218 | ||
| 219 | uint16_t unused_6[0x11]; /* d0-f0 */ | |
| 220 | uint16_t scsiControlPins; /* f2 */ | |
| 221 | }; | |
| 222 | ||
| 223 | #define MAILBOX_REGISTER_COUNT 8 | |
| 224 | ||
| 225 | /* | |
| 226 | * ISP product identification definitions in mailboxes after reset. | |
| 227 | */ | |
| 228 | #define PROD_ID_1 0x4953 | |
| 229 | #define PROD_ID_2 0x0000 | |
| 230 | #define PROD_ID_2a 0x5020 | |
| 231 | #define PROD_ID_3 0x2020 | |
| 232 | #define PROD_ID_4 0x1 | |
| 233 | ||
| 234 | /* | |
| 235 | * ISP host command and control register command definitions | |
| 236 | */ | |
| 237 | #define HC_RESET_RISC 0x1000 /* Reset RISC */ | |
| 238 | #define HC_PAUSE_RISC 0x2000 /* Pause RISC */ | |
| 239 | #define HC_RELEASE_RISC 0x3000 /* Release RISC from reset. */ | |
| 240 | #define HC_SET_HOST_INT 0x5000 /* Set host interrupt */ | |
| 241 | #define HC_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */ | |
| 242 | #define HC_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */ | |
| 243 | #define HC_DISABLE_BIOS 0x9000 /* Disable BIOS. */ | |
| 244 | ||
| 245 | /* | |
| 246 | * ISP mailbox Self-Test status codes | |
| 247 | */ | |
| 248 | #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ | |
| 249 | #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ | |
| 250 | #define MBS_SHADOW_LD_ERR 2 /* Shadow Load Error. */ | |
| 251 | #define MBS_BUSY 4 /* Busy. */ | |
| 252 | ||
| 253 | /* | |
| 254 | * ISP mailbox command complete status codes | |
| 255 | */ | |
| 256 | #define MBS_CMD_CMP 0x4000 /* Command Complete. */ | |
| 257 | #define MBS_INV_CMD 0x4001 /* Invalid Command. */ | |
| 258 | #define MBS_HOST_INF_ERR 0x4002 /* Host Interface Error. */ | |
| 259 | #define MBS_TEST_FAILED 0x4003 /* Test Failed. */ | |
| 260 | #define MBS_CMD_ERR 0x4005 /* Command Error. */ | |
| 261 | #define MBS_CMD_PARAM_ERR 0x4006 /* Command Parameter Error. */ | |
| 262 | ||
| 263 | /* | |
| 264 | * ISP mailbox asynchronous event status codes | |
| 265 | */ | |
| 266 | #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ | |
| 267 | #define MBA_BUS_RESET 0x8001 /* SCSI Bus Reset. */ | |
| 268 | #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ | |
| 269 | #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ | |
| 270 | #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ | |
| 271 | #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ | |
| 272 | #define MBA_TIMEOUT_RESET 0x8006 /* Execution Timeout Reset. */ | |
| 273 | #define MBA_DEVICE_RESET 0x8007 /* Bus Device Reset. */ | |
| 274 | #define MBA_BUS_MODE_CHANGE 0x800E /* SCSI bus mode transition. */ | |
| 275 | #define MBA_SCSI_COMPLETION 0x8020 /* Completion response. */ | |
| 276 | ||
| 277 | /* | |
| 278 | * ISP mailbox commands | |
| 279 | */ | |
| 280 | #define MBC_NOP 0 /* No Operation */ | |
| 281 | #define MBC_LOAD_RAM 1 /* Load RAM */ | |
| 282 | #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware */ | |
| 283 | #define MBC_DUMP_RAM 3 /* Dump RAM contents */ | |
| 284 | #define MBC_WRITE_RAM_WORD 4 /* Write ram word */ | |
| 285 | #define MBC_READ_RAM_WORD 5 /* Read ram word */ | |
| 286 | #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ | |
| 287 | #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum */ | |
| 288 | #define MBC_ABOUT_FIRMWARE 8 /* Get firmware revision */ | |
| 289 | #define MBC_INIT_REQUEST_QUEUE 0x10 /* Initialize request queue */ | |
| 290 | #define MBC_INIT_RESPONSE_QUEUE 0x11 /* Initialize response queue */ | |
| 291 | #define MBC_EXECUTE_IOCB 0x12 /* Execute IOCB command */ | |
| 292 | #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command */ | |
| 293 | #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN) */ | |
| 294 | #define MBC_ABORT_TARGET 0x17 /* Abort target (ID) */ | |
| 295 | #define MBC_BUS_RESET 0x18 /* SCSI bus reset */ | |
| 296 | #define MBC_GET_RETRY_COUNT 0x22 /* Get retry count and delay */ | |
| 297 | #define MBC_GET_TARGET_PARAMETERS 0x28 /* Get target parameters */ | |
| 298 | #define MBC_SET_INITIATOR_ID 0x30 /* Set initiator SCSI ID */ | |
| 299 | #define MBC_SET_SELECTION_TIMEOUT 0x31 /* Set selection timeout */ | |
| 300 | #define MBC_SET_RETRY_COUNT 0x32 /* Set retry count and delay */ | |
| 301 | #define MBC_SET_TAG_AGE_LIMIT 0x33 /* Set tag age limit */ | |
| 302 | #define MBC_SET_CLOCK_RATE 0x34 /* Set clock rate */ | |
| 303 | #define MBC_SET_ACTIVE_NEGATION 0x35 /* Set active negation state */ | |
| 304 | #define MBC_SET_ASYNC_DATA_SETUP 0x36 /* Set async data setup time */ | |
| 305 | #define MBC_SET_PCI_CONTROL 0x37 /* Set BUS control parameters */ | |
| 306 | #define MBC_SET_TARGET_PARAMETERS 0x38 /* Set target parameters */ | |
| 307 | #define MBC_SET_DEVICE_QUEUE 0x39 /* Set device queue parameters */ | |
| 308 | #define MBC_SET_RESET_DELAY_PARAMETERS 0x3A /* Set reset delay parameters */ | |
| 309 | #define MBC_SET_SYSTEM_PARAMETER 0x45 /* Set system parameter word */ | |
| 310 | #define MBC_SET_FIRMWARE_FEATURES 0x4A /* Set firmware feature word */ | |
| 311 | #define MBC_INIT_REQUEST_QUEUE_A64 0x52 /* Initialize request queue A64 */ | |
| 312 | #define MBC_INIT_RESPONSE_QUEUE_A64 0x53 /* Initialize response q A64 */ | |
| 313 | #define MBC_ENABLE_TARGET_MODE 0x55 /* Enable target mode */ | |
| 314 | #define MBC_SET_DATA_OVERRUN_RECOVERY 0x5A /* Set data overrun recovery mode */ | |
| 315 | ||
| 316 | /* | |
| 317 | * ISP Get/Set Target Parameters mailbox command control flags. | |
| 318 | */ | |
| 319 | #define TP_PPR BIT_5 /* PPR */ | |
| 320 | #define TP_RENEGOTIATE BIT_8 /* Renegotiate on error. */ | |
| 321 | #define TP_STOP_QUEUE BIT_9 /* Stop que on check condition */ | |
| 322 | #define TP_AUTO_REQUEST_SENSE BIT_10 /* Automatic request sense. */ | |
| 323 | #define TP_TAGGED_QUEUE BIT_11 /* Tagged queuing. */ | |
| 324 | #define TP_SYNC BIT_12 /* Synchronous data transfers. */ | |
| 325 | #define TP_WIDE BIT_13 /* Wide data transfers. */ | |
| 326 | #define TP_PARITY BIT_14 /* Parity checking. */ | |
| 327 | #define TP_DISCONNECT BIT_15 /* Disconnect privilege. */ | |
| 328 | ||
| 329 | /* | |
| 330 | * NVRAM Command values. | |
| 331 | */ | |
| 332 | #define NV_START_BIT BIT_2 | |
| 333 | #define NV_WRITE_OP (BIT_26 | BIT_24) | |
| 334 | #define NV_READ_OP (BIT_26 | BIT_25) | |
| 335 | #define NV_ERASE_OP (BIT_26 | BIT_25 | BIT_24) | |
| 336 | #define NV_MASK_OP (BIT_26 | BIT_25 | BIT_24) | |
| 337 | #define NV_DELAY_COUNT 10 | |
| 338 | ||
| 339 | /* | |
| 340 | * QLogic ISP1280/ISP12160 NVRAM structure definition. | |
| 341 | */ | |
| 342 | struct nvram { | |
| 343 | uint8_t id0; /* 0 */ | |
| 344 | uint8_t id1; /* 1 */ | |
| 345 | uint8_t id2; /* 2 */ | |
| 346 | uint8_t id3; /* 3 */ | |
| 347 | uint8_t version; /* 4 */ | |
| 348 | ||
| 349 | struct { | |
| 350 | uint8_t bios_configuration_mode:2; | |
| 351 | uint8_t bios_disable:1; | |
| 352 | uint8_t selectable_scsi_boot_enable:1; | |
| 353 | uint8_t cd_rom_boot_enable:1; | |
| 354 | uint8_t disable_loading_risc_code:1; | |
| 355 | uint8_t enable_64bit_addressing:1; | |
| 356 | uint8_t unused_7:1; | |
| 357 | } cntr_flags_1; /* 5 */ | |
| 358 | ||
| 359 | struct { | |
| 360 | uint8_t boot_lun_number:5; | |
| 361 | uint8_t scsi_bus_number:1; | |
| 362 | uint8_t unused_6:1; | |
| 363 | uint8_t unused_7:1; | |
| 364 | } cntr_flags_2l; /* 7 */ | |
| 365 | ||
| 366 | struct { | |
| 367 | uint8_t boot_target_number:4; | |
| 368 | uint8_t unused_12:1; | |
| 369 | uint8_t unused_13:1; | |
| 370 | uint8_t unused_14:1; | |
| 371 | uint8_t unused_15:1; | |
| 372 | } cntr_flags_2h; /* 8 */ | |
| 373 | ||
| 374 | uint16_t unused_8; /* 8, 9 */ | |
| 375 | uint16_t unused_10; /* 10, 11 */ | |
| 376 | uint16_t unused_12; /* 12, 13 */ | |
| 377 | uint16_t unused_14; /* 14, 15 */ | |
| 378 | ||
| 0888f4c3 CH |
379 | struct { |
| 380 | uint8_t reserved:2; | |
| 381 | uint8_t burst_enable:1; | |
| 382 | uint8_t reserved_1:1; | |
| 383 | uint8_t fifo_threshold:4; | |
| 1da177e4 LT |
384 | } isp_config; /* 16 */ |
| 385 | ||
| 386 | /* Termination | |
| 387 | * 0 = Disable, 1 = high only, 3 = Auto term | |
| 388 | */ | |
| 0888f4c3 CH |
389 | struct { |
| 390 | uint8_t scsi_bus_1_control:2; | |
| 391 | uint8_t scsi_bus_0_control:2; | |
| 392 | uint8_t unused_0:1; | |
| 393 | uint8_t unused_1:1; | |
| 394 | uint8_t unused_2:1; | |
| 395 | uint8_t auto_term_support:1; | |
| 1da177e4 LT |
396 | } termination; /* 17 */ |
| 397 | ||
| 398 | uint16_t isp_parameter; /* 18, 19 */ | |
| 399 | ||
| 400 | union { | |
| 401 | uint16_t w; | |
| 402 | struct { | |
| 403 | uint16_t enable_fast_posting:1; | |
| 404 | uint16_t report_lvd_bus_transition:1; | |
| 405 | uint16_t unused_2:1; | |
| 406 | uint16_t unused_3:1; | |
| 407 | uint16_t disable_iosbs_with_bus_reset_status:1; | |
| 408 | uint16_t disable_synchronous_backoff:1; | |
| 409 | uint16_t unused_6:1; | |
| 410 | uint16_t synchronous_backoff_reporting:1; | |
| 411 | uint16_t disable_reselection_fairness:1; | |
| 412 | uint16_t unused_9:1; | |
| 413 | uint16_t unused_10:1; | |
| 414 | uint16_t unused_11:1; | |
| 415 | uint16_t unused_12:1; | |
| 416 | uint16_t unused_13:1; | |
| 417 | uint16_t unused_14:1; | |
| 418 | uint16_t unused_15:1; | |
| 419 | } f; | |
| 420 | } firmware_feature; /* 20, 21 */ | |
| 421 | ||
| 422 | uint16_t unused_22; /* 22, 23 */ | |
| 423 | ||
| 424 | struct { | |
| 425 | struct { | |
| 426 | uint8_t initiator_id:4; | |
| 427 | uint8_t scsi_reset_disable:1; | |
| 428 | uint8_t scsi_bus_size:1; | |
| 429 | uint8_t scsi_bus_type:1; | |
| 430 | uint8_t unused_7:1; | |
| 431 | } config_1; /* 24 */ | |
| 432 | ||
| 433 | uint8_t bus_reset_delay; /* 25 */ | |
| 434 | uint8_t retry_count; /* 26 */ | |
| 435 | uint8_t retry_delay; /* 27 */ | |
| 436 | ||
| 437 | struct { | |
| 438 | uint8_t async_data_setup_time:4; | |
| 439 | uint8_t req_ack_active_negation:1; | |
| 440 | uint8_t data_line_active_negation:1; | |
| 441 | uint8_t unused_6:1; | |
| 442 | uint8_t unused_7:1; | |
| 443 | } config_2; /* 28 */ | |
| 444 | ||
| 445 | uint8_t unused_29; /* 29 */ | |
| 446 | ||
| 447 | uint16_t selection_timeout; /* 30, 31 */ | |
| 448 | uint16_t max_queue_depth; /* 32, 33 */ | |
| 449 | ||
| 450 | uint16_t unused_34; /* 34, 35 */ | |
| 451 | uint16_t unused_36; /* 36, 37 */ | |
| 452 | uint16_t unused_38; /* 38, 39 */ | |
| 453 | ||
| 454 | struct { | |
| 7a34766f CH |
455 | struct { |
| 456 | uint8_t renegotiate_on_error:1; | |
| 457 | uint8_t stop_queue_on_check:1; | |
| 458 | uint8_t auto_request_sense:1; | |
| 459 | uint8_t tag_queuing:1; | |
| 460 | uint8_t enable_sync:1; | |
| 461 | uint8_t enable_wide:1; | |
| 462 | uint8_t parity_checking:1; | |
| 463 | uint8_t disconnect_allowed:1; | |
| 1da177e4 LT |
464 | } parameter; /* 40 */ |
| 465 | ||
| 466 | uint8_t execution_throttle; /* 41 */ | |
| 467 | uint8_t sync_period; /* 42 */ | |
| 468 | ||
| 469 | union { /* 43 */ | |
| 470 | uint8_t flags_43; | |
| 471 | struct { | |
| 472 | uint8_t sync_offset:4; | |
| 473 | uint8_t device_enable:1; | |
| 474 | uint8_t lun_disable:1; | |
| 475 | uint8_t unused_6:1; | |
| 476 | uint8_t unused_7:1; | |
| 477 | } flags1x80; | |
| 478 | struct { | |
| 479 | uint8_t sync_offset:5; | |
| 480 | uint8_t device_enable:1; | |
| 481 | uint8_t unused_6:1; | |
| 482 | uint8_t unused_7:1; | |
| 483 | } flags1x160; | |
| 484 | } flags; | |
| 485 | union { /* PPR flags for the 1x160 controllers */ | |
| 486 | uint8_t unused_44; | |
| 487 | struct { | |
| 488 | uint8_t ppr_options:4; | |
| 489 | uint8_t ppr_bus_width:2; | |
| 490 | uint8_t unused_8:1; | |
| 491 | uint8_t enable_ppr:1; | |
| 492 | } flags; /* 44 */ | |
| 493 | } ppr_1x160; | |
| 494 | uint8_t unused_45; /* 45 */ | |
| 495 | } target[MAX_TARGETS]; | |
| 496 | } bus[MAX_BUSES]; | |
| 497 | ||
| 498 | uint16_t unused_248; /* 248, 249 */ | |
| 499 | ||
| 500 | uint16_t subsystem_id[2]; /* 250, 251, 252, 253 */ | |
| 501 | ||
| 502 | union { /* 254 */ | |
| 503 | uint8_t unused_254; | |
| 504 | uint8_t system_id_pointer; | |
| 505 | } sysid_1x160; | |
| 506 | ||
| 507 | uint8_t chksum; /* 255 */ | |
| 508 | }; | |
| 509 | ||
| 510 | /* | |
| 511 | * ISP queue - command entry structure definition. | |
| 512 | */ | |
| 513 | #define MAX_CMDSZ 12 /* SCSI maximum CDB size. */ | |
| 514 | struct cmd_entry { | |
| 515 | uint8_t entry_type; /* Entry type. */ | |
| 516 | #define COMMAND_TYPE 1 /* Command entry */ | |
| 517 | uint8_t entry_count; /* Entry count. */ | |
| 518 | uint8_t sys_define; /* System defined. */ | |
| 519 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 520 | __le32 handle; /* System handle. */ |
| 1da177e4 LT |
521 | uint8_t lun; /* SCSI LUN */ |
| 522 | uint8_t target; /* SCSI ID */ | |
| 8d6810d3 CH |
523 | __le16 cdb_len; /* SCSI command length. */ |
| 524 | __le16 control_flags; /* Control flags. */ | |
| 525 | __le16 reserved; | |
| 526 | __le16 timeout; /* Command timeout. */ | |
| 527 | __le16 dseg_count; /* Data segment count. */ | |
| 1da177e4 | 528 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ |
| 8d6810d3 CH |
529 | __le32 dseg_0_address; /* Data segment 0 address. */ |
| 530 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 531 | __le32 dseg_1_address; /* Data segment 1 address. */ | |
| 532 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 533 | __le32 dseg_2_address; /* Data segment 2 address. */ | |
| 534 | __le32 dseg_2_length; /* Data segment 2 length. */ | |
| 535 | __le32 dseg_3_address; /* Data segment 3 address. */ | |
| 536 | __le32 dseg_3_length; /* Data segment 3 length. */ | |
| 1da177e4 LT |
537 | }; |
| 538 | ||
| 539 | /* | |
| 540 | * ISP queue - continuation entry structure definition. | |
| 541 | */ | |
| 542 | struct cont_entry { | |
| 543 | uint8_t entry_type; /* Entry type. */ | |
| 544 | #define CONTINUE_TYPE 2 /* Continuation entry. */ | |
| 545 | uint8_t entry_count; /* Entry count. */ | |
| 546 | uint8_t sys_define; /* System defined. */ | |
| 547 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 CH |
548 | __le32 reserved; /* Reserved */ |
| 549 | __le32 dseg_0_address; /* Data segment 0 address. */ | |
| 550 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 551 | __le32 dseg_1_address; /* Data segment 1 address. */ | |
| 552 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 553 | __le32 dseg_2_address; /* Data segment 2 address. */ | |
| 554 | __le32 dseg_2_length; /* Data segment 2 length. */ | |
| 555 | __le32 dseg_3_address; /* Data segment 3 address. */ | |
| 556 | __le32 dseg_3_length; /* Data segment 3 length. */ | |
| 557 | __le32 dseg_4_address; /* Data segment 4 address. */ | |
| 558 | __le32 dseg_4_length; /* Data segment 4 length. */ | |
| 559 | __le32 dseg_5_address; /* Data segment 5 address. */ | |
| 560 | __le32 dseg_5_length; /* Data segment 5 length. */ | |
| 561 | __le32 dseg_6_address; /* Data segment 6 address. */ | |
| 562 | __le32 dseg_6_length; /* Data segment 6 length. */ | |
| 1da177e4 LT |
563 | }; |
| 564 | ||
| 565 | /* | |
| 566 | * ISP queue - status entry structure definition. | |
| 567 | */ | |
| 568 | struct response { | |
| 569 | uint8_t entry_type; /* Entry type. */ | |
| 570 | #define STATUS_TYPE 3 /* Status entry. */ | |
| 571 | uint8_t entry_count; /* Entry count. */ | |
| 572 | uint8_t sys_define; /* System defined. */ | |
| 573 | uint8_t entry_status; /* Entry Status. */ | |
| 574 | #define RF_CONT BIT_0 /* Continuation. */ | |
| 575 | #define RF_FULL BIT_1 /* Full */ | |
| 576 | #define RF_BAD_HEADER BIT_2 /* Bad header. */ | |
| 577 | #define RF_BAD_PAYLOAD BIT_3 /* Bad payload. */ | |
| 8d6810d3 CH |
578 | __le32 handle; /* System handle. */ |
| 579 | __le16 scsi_status; /* SCSI status. */ | |
| 580 | __le16 comp_status; /* Completion status. */ | |
| 581 | __le16 state_flags; /* State flags. */ | |
| 582 | #define SF_TRANSFER_CMPL BIT_14 /* Transfer Complete. */ | |
| 583 | #define SF_GOT_SENSE BIT_13 /* Got Sense */ | |
| 584 | #define SF_GOT_STATUS BIT_12 /* Got Status */ | |
| 585 | #define SF_TRANSFERRED_DATA BIT_11 /* Transferred data */ | |
| 586 | #define SF_SENT_CDB BIT_10 /* Send CDB */ | |
| 587 | #define SF_GOT_TARGET BIT_9 /* */ | |
| 588 | #define SF_GOT_BUS BIT_8 /* */ | |
| 589 | __le16 status_flags; /* Status flags. */ | |
| 590 | __le16 time; /* Time. */ | |
| 591 | __le16 req_sense_length;/* Request sense data length. */ | |
| 592 | __le32 residual_length; /* Residual transfer length. */ | |
| 593 | __le16 reserved[4]; | |
| 1da177e4 LT |
594 | uint8_t req_sense_data[32]; /* Request sense data. */ |
| 595 | }; | |
| 596 | ||
| 597 | /* | |
| 598 | * ISP queue - marker entry structure definition. | |
| 599 | */ | |
| 600 | struct mrk_entry { | |
| 601 | uint8_t entry_type; /* Entry type. */ | |
| 602 | #define MARKER_TYPE 4 /* Marker entry. */ | |
| 603 | uint8_t entry_count; /* Entry count. */ | |
| 604 | uint8_t sys_define; /* System defined. */ | |
| 605 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 606 | __le32 reserved; |
| 1da177e4 LT |
607 | uint8_t lun; /* SCSI LUN */ |
| 608 | uint8_t target; /* SCSI ID */ | |
| 609 | uint8_t modifier; /* Modifier (7-0). */ | |
| 610 | #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */ | |
| 611 | #define MK_SYNC_ID 1 /* Synchronize ID */ | |
| 612 | #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */ | |
| 613 | uint8_t reserved_1[53]; | |
| 614 | }; | |
| 615 | ||
| 616 | /* | |
| 617 | * ISP queue - extended command entry structure definition. | |
| 618 | * | |
| 619 | * Unused by the driver! | |
| 620 | */ | |
| 621 | struct ecmd_entry { | |
| 622 | uint8_t entry_type; /* Entry type. */ | |
| 623 | #define EXTENDED_CMD_TYPE 5 /* Extended command entry. */ | |
| 624 | uint8_t entry_count; /* Entry count. */ | |
| 625 | uint8_t sys_define; /* System defined. */ | |
| 626 | uint8_t entry_status; /* Entry Status. */ | |
| 627 | uint32_t handle; /* System handle. */ | |
| 628 | uint8_t lun; /* SCSI LUN */ | |
| 629 | uint8_t target; /* SCSI ID */ | |
| 8d6810d3 CH |
630 | __le16 cdb_len; /* SCSI command length. */ |
| 631 | __le16 control_flags; /* Control flags. */ | |
| 632 | __le16 reserved; | |
| 633 | __le16 timeout; /* Command timeout. */ | |
| 634 | __le16 dseg_count; /* Data segment count. */ | |
| 1da177e4 LT |
635 | uint8_t scsi_cdb[88]; /* SCSI command words. */ |
| 636 | }; | |
| 637 | ||
| 638 | /* | |
| 639 | * ISP queue - 64-Bit addressing, command entry structure definition. | |
| 640 | */ | |
| 641 | typedef struct { | |
| 642 | uint8_t entry_type; /* Entry type. */ | |
| 643 | #define COMMAND_A64_TYPE 9 /* Command A64 entry */ | |
| 644 | uint8_t entry_count; /* Entry count. */ | |
| 645 | uint8_t sys_define; /* System defined. */ | |
| 646 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 647 | __le32 handle; /* System handle. */ |
| 1da177e4 LT |
648 | uint8_t lun; /* SCSI LUN */ |
| 649 | uint8_t target; /* SCSI ID */ | |
| 8d6810d3 CH |
650 | __le16 cdb_len; /* SCSI command length. */ |
| 651 | __le16 control_flags; /* Control flags. */ | |
| 652 | __le16 reserved; | |
| 653 | __le16 timeout; /* Command timeout. */ | |
| 654 | __le16 dseg_count; /* Data segment count. */ | |
| 1da177e4 | 655 | uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */ |
| 8d6810d3 CH |
656 | __le32 reserved_1[2]; /* unused */ |
| 657 | __le32 dseg_0_address[2]; /* Data segment 0 address. */ | |
| 658 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 659 | __le32 dseg_1_address[2]; /* Data segment 1 address. */ | |
| 660 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 1da177e4 LT |
661 | } cmd_a64_entry_t, request_t; |
| 662 | ||
| 663 | /* | |
| 664 | * ISP queue - 64-Bit addressing, continuation entry structure definition. | |
| 665 | */ | |
| 666 | struct cont_a64_entry { | |
| 667 | uint8_t entry_type; /* Entry type. */ | |
| 668 | #define CONTINUE_A64_TYPE 0xA /* Continuation A64 entry. */ | |
| 669 | uint8_t entry_count; /* Entry count. */ | |
| 670 | uint8_t sys_define; /* System defined. */ | |
| 671 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 CH |
672 | __le32 dseg_0_address[2]; /* Data segment 0 address. */ |
| 673 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 674 | __le32 dseg_1_address[2]; /* Data segment 1 address. */ | |
| 675 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 676 | __le32 dseg_2_address[2]; /* Data segment 2 address. */ | |
| 677 | __le32 dseg_2_length; /* Data segment 2 length. */ | |
| 678 | __le32 dseg_3_address[2]; /* Data segment 3 address. */ | |
| 679 | __le32 dseg_3_length; /* Data segment 3 length. */ | |
| 680 | __le32 dseg_4_address[2]; /* Data segment 4 address. */ | |
| 681 | __le32 dseg_4_length; /* Data segment 4 length. */ | |
| 1da177e4 LT |
682 | }; |
| 683 | ||
| 684 | /* | |
| 685 | * ISP queue - enable LUN entry structure definition. | |
| 686 | */ | |
| 687 | struct elun_entry { | |
| 688 | uint8_t entry_type; /* Entry type. */ | |
| 689 | #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */ | |
| 690 | uint8_t entry_count; /* Entry count. */ | |
| 691 | uint8_t reserved_1; | |
| 692 | uint8_t entry_status; /* Entry Status not used. */ | |
| 8d6810d3 CH |
693 | __le32 reserved_2; |
| 694 | __le16 lun; /* Bit 15 is bus number. */ | |
| 695 | __le16 reserved_4; | |
| 696 | __le32 option_flags; | |
| 1da177e4 LT |
697 | uint8_t status; |
| 698 | uint8_t reserved_5; | |
| 699 | uint8_t command_count; /* Number of ATIOs allocated. */ | |
| 700 | uint8_t immed_notify_count; /* Number of Immediate Notify */ | |
| 701 | /* entries allocated. */ | |
| 702 | uint8_t group_6_length; /* SCSI CDB length for group 6 */ | |
| 703 | /* commands (2-26). */ | |
| 704 | uint8_t group_7_length; /* SCSI CDB length for group 7 */ | |
| 705 | /* commands (2-26). */ | |
| 8d6810d3 CH |
706 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ |
| 707 | __le16 reserved_6[20]; | |
| 1da177e4 LT |
708 | }; |
| 709 | ||
| 710 | /* | |
| 711 | * ISP queue - modify LUN entry structure definition. | |
| 712 | * | |
| 713 | * Unused by the driver! | |
| 714 | */ | |
| 715 | struct modify_lun_entry { | |
| 716 | uint8_t entry_type; /* Entry type. */ | |
| 717 | #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */ | |
| 718 | uint8_t entry_count; /* Entry count. */ | |
| 719 | uint8_t reserved_1; | |
| 720 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 721 | __le32 reserved_2; |
| 1da177e4 LT |
722 | uint8_t lun; /* SCSI LUN */ |
| 723 | uint8_t reserved_3; | |
| 724 | uint8_t operators; | |
| 725 | uint8_t reserved_4; | |
| 8d6810d3 | 726 | __le32 option_flags; |
| 1da177e4 LT |
727 | uint8_t status; |
| 728 | uint8_t reserved_5; | |
| 729 | uint8_t command_count; /* Number of ATIOs allocated. */ | |
| 730 | uint8_t immed_notify_count; /* Number of Immediate Notify */ | |
| 731 | /* entries allocated. */ | |
| 8d6810d3 CH |
732 | __le16 reserved_6; |
| 733 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ | |
| 734 | __le16 reserved_7[20]; | |
| 1da177e4 LT |
735 | }; |
| 736 | ||
| 737 | /* | |
| 738 | * ISP queue - immediate notify entry structure definition. | |
| 739 | */ | |
| 740 | struct notify_entry { | |
| 741 | uint8_t entry_type; /* Entry type. */ | |
| 742 | #define IMMED_NOTIFY_TYPE 0xD /* Immediate notify entry. */ | |
| 743 | uint8_t entry_count; /* Entry count. */ | |
| 744 | uint8_t reserved_1; | |
| 745 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 746 | __le32 reserved_2; |
| 1da177e4 LT |
747 | uint8_t lun; |
| 748 | uint8_t initiator_id; | |
| 749 | uint8_t reserved_3; | |
| 750 | uint8_t target_id; | |
| 8d6810d3 | 751 | __le32 option_flags; |
| 1da177e4 LT |
752 | uint8_t status; |
| 753 | uint8_t reserved_4; | |
| 754 | uint8_t tag_value; /* Received queue tag message value */ | |
| 755 | uint8_t tag_type; /* Received queue tag message type */ | |
| 756 | /* entries allocated. */ | |
| 8d6810d3 | 757 | __le16 seq_id; |
| 1da177e4 | 758 | uint8_t scsi_msg[8]; /* SCSI message not handled by ISP */ |
| 8d6810d3 | 759 | __le16 reserved_5[8]; |
| 1da177e4 LT |
760 | uint8_t sense_data[18]; |
| 761 | }; | |
| 762 | ||
| 763 | /* | |
| 764 | * ISP queue - notify acknowledge entry structure definition. | |
| 765 | */ | |
| 766 | struct nack_entry { | |
| 767 | uint8_t entry_type; /* Entry type. */ | |
| 768 | #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */ | |
| 769 | uint8_t entry_count; /* Entry count. */ | |
| 770 | uint8_t reserved_1; | |
| 771 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 772 | __le32 reserved_2; |
| 1da177e4 LT |
773 | uint8_t lun; |
| 774 | uint8_t initiator_id; | |
| 775 | uint8_t reserved_3; | |
| 776 | uint8_t target_id; | |
| 8d6810d3 | 777 | __le32 option_flags; |
| 1da177e4 LT |
778 | uint8_t status; |
| 779 | uint8_t event; | |
| 8d6810d3 CH |
780 | __le16 seq_id; |
| 781 | __le16 reserved_4[22]; | |
| 1da177e4 LT |
782 | }; |
| 783 | ||
| 784 | /* | |
| 785 | * ISP queue - Accept Target I/O (ATIO) entry structure definition. | |
| 786 | */ | |
| 787 | struct atio_entry { | |
| 788 | uint8_t entry_type; /* Entry type. */ | |
| 789 | #define ACCEPT_TGT_IO_TYPE 6 /* Accept target I/O entry. */ | |
| 790 | uint8_t entry_count; /* Entry count. */ | |
| 791 | uint8_t reserved_1; | |
| 792 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 793 | __le32 reserved_2; |
| 1da177e4 LT |
794 | uint8_t lun; |
| 795 | uint8_t initiator_id; | |
| 796 | uint8_t cdb_len; | |
| 797 | uint8_t target_id; | |
| 8d6810d3 | 798 | __le32 option_flags; |
| 1da177e4 LT |
799 | uint8_t status; |
| 800 | uint8_t scsi_status; | |
| 801 | uint8_t tag_value; /* Received queue tag message value */ | |
| 802 | uint8_t tag_type; /* Received queue tag message type */ | |
| 803 | uint8_t cdb[26]; | |
| 804 | uint8_t sense_data[18]; | |
| 805 | }; | |
| 806 | ||
| 807 | /* | |
| 808 | * ISP queue - Continue Target I/O (CTIO) entry structure definition. | |
| 809 | */ | |
| 810 | struct ctio_entry { | |
| 811 | uint8_t entry_type; /* Entry type. */ | |
| 812 | #define CONTINUE_TGT_IO_TYPE 7 /* CTIO entry */ | |
| 813 | uint8_t entry_count; /* Entry count. */ | |
| 814 | uint8_t reserved_1; | |
| 815 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 816 | __le32 reserved_2; |
| 1da177e4 LT |
817 | uint8_t lun; /* SCSI LUN */ |
| 818 | uint8_t initiator_id; | |
| 819 | uint8_t reserved_3; | |
| 820 | uint8_t target_id; | |
| 8d6810d3 | 821 | __le32 option_flags; |
| 1da177e4 LT |
822 | uint8_t status; |
| 823 | uint8_t scsi_status; | |
| 824 | uint8_t tag_value; /* Received queue tag message value */ | |
| 825 | uint8_t tag_type; /* Received queue tag message type */ | |
| 8d6810d3 CH |
826 | __le32 transfer_length; |
| 827 | __le32 residual; | |
| 828 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ | |
| 829 | __le16 dseg_count; /* Data segment count. */ | |
| 830 | __le32 dseg_0_address; /* Data segment 0 address. */ | |
| 831 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 832 | __le32 dseg_1_address; /* Data segment 1 address. */ | |
| 833 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 834 | __le32 dseg_2_address; /* Data segment 2 address. */ | |
| 835 | __le32 dseg_2_length; /* Data segment 2 length. */ | |
| 836 | __le32 dseg_3_address; /* Data segment 3 address. */ | |
| 837 | __le32 dseg_3_length; /* Data segment 3 length. */ | |
| 1da177e4 LT |
838 | }; |
| 839 | ||
| 840 | /* | |
| 841 | * ISP queue - CTIO returned entry structure definition. | |
| 842 | */ | |
| 843 | struct ctio_ret_entry { | |
| 844 | uint8_t entry_type; /* Entry type. */ | |
| 845 | #define CTIO_RET_TYPE 7 /* CTIO return entry */ | |
| 846 | uint8_t entry_count; /* Entry count. */ | |
| 847 | uint8_t reserved_1; | |
| 848 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 849 | __le32 reserved_2; |
| 1da177e4 LT |
850 | uint8_t lun; /* SCSI LUN */ |
| 851 | uint8_t initiator_id; | |
| 852 | uint8_t reserved_3; | |
| 853 | uint8_t target_id; | |
| 8d6810d3 | 854 | __le32 option_flags; |
| 1da177e4 LT |
855 | uint8_t status; |
| 856 | uint8_t scsi_status; | |
| 857 | uint8_t tag_value; /* Received queue tag message value */ | |
| 858 | uint8_t tag_type; /* Received queue tag message type */ | |
| 8d6810d3 CH |
859 | __le32 transfer_length; |
| 860 | __le32 residual; | |
| 861 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ | |
| 862 | __le16 dseg_count; /* Data segment count. */ | |
| 863 | __le32 dseg_0_address; /* Data segment 0 address. */ | |
| 864 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 865 | __le32 dseg_1_address; /* Data segment 1 address. */ | |
| 866 | __le16 dseg_1_length; /* Data segment 1 length. */ | |
| 1da177e4 LT |
867 | uint8_t sense_data[18]; |
| 868 | }; | |
| 869 | ||
| 870 | /* | |
| 871 | * ISP queue - CTIO A64 entry structure definition. | |
| 872 | */ | |
| 873 | struct ctio_a64_entry { | |
| 874 | uint8_t entry_type; /* Entry type. */ | |
| 875 | #define CTIO_A64_TYPE 0xF /* CTIO A64 entry */ | |
| 876 | uint8_t entry_count; /* Entry count. */ | |
| 877 | uint8_t reserved_1; | |
| 878 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 879 | __le32 reserved_2; |
| 1da177e4 LT |
880 | uint8_t lun; /* SCSI LUN */ |
| 881 | uint8_t initiator_id; | |
| 882 | uint8_t reserved_3; | |
| 883 | uint8_t target_id; | |
| 8d6810d3 | 884 | __le32 option_flags; |
| 1da177e4 LT |
885 | uint8_t status; |
| 886 | uint8_t scsi_status; | |
| 887 | uint8_t tag_value; /* Received queue tag message value */ | |
| 888 | uint8_t tag_type; /* Received queue tag message type */ | |
| 8d6810d3 CH |
889 | __le32 transfer_length; |
| 890 | __le32 residual; | |
| 891 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ | |
| 892 | __le16 dseg_count; /* Data segment count. */ | |
| 893 | __le32 reserved_4[2]; | |
| 894 | __le32 dseg_0_address[2];/* Data segment 0 address. */ | |
| 895 | __le32 dseg_0_length; /* Data segment 0 length. */ | |
| 896 | __le32 dseg_1_address[2];/* Data segment 1 address. */ | |
| 897 | __le32 dseg_1_length; /* Data segment 1 length. */ | |
| 1da177e4 LT |
898 | }; |
| 899 | ||
| 900 | /* | |
| 901 | * ISP queue - CTIO returned entry structure definition. | |
| 902 | */ | |
| 903 | struct ctio_a64_ret_entry { | |
| 904 | uint8_t entry_type; /* Entry type. */ | |
| 905 | #define CTIO_A64_RET_TYPE 0xF /* CTIO A64 returned entry */ | |
| 906 | uint8_t entry_count; /* Entry count. */ | |
| 907 | uint8_t reserved_1; | |
| 908 | uint8_t entry_status; /* Entry Status. */ | |
| 8d6810d3 | 909 | __le32 reserved_2; |
| 1da177e4 LT |
910 | uint8_t lun; /* SCSI LUN */ |
| 911 | uint8_t initiator_id; | |
| 912 | uint8_t reserved_3; | |
| 913 | uint8_t target_id; | |
| 8d6810d3 | 914 | __le32 option_flags; |
| 1da177e4 LT |
915 | uint8_t status; |
| 916 | uint8_t scsi_status; | |
| 917 | uint8_t tag_value; /* Received queue tag message value */ | |
| 918 | uint8_t tag_type; /* Received queue tag message type */ | |
| 8d6810d3 CH |
919 | __le32 transfer_length; |
| 920 | __le32 residual; | |
| 921 | __le16 timeout; /* 0 = 30 seconds, 0xFFFF = disable */ | |
| 922 | __le16 dseg_count; /* Data segment count. */ | |
| 923 | __le16 reserved_4[7]; | |
| 1da177e4 LT |
924 | uint8_t sense_data[18]; |
| 925 | }; | |
| 926 | ||
| 927 | /* | |
| 928 | * ISP request and response queue entry sizes | |
| 929 | */ | |
| 930 | #define RESPONSE_ENTRY_SIZE (sizeof(struct response)) | |
| 931 | #define REQUEST_ENTRY_SIZE (sizeof(request_t)) | |
| 932 | ||
| 933 | /* | |
| 934 | * ISP status entry - completion status definitions. | |
| 935 | */ | |
| 936 | #define CS_COMPLETE 0x0 /* No errors */ | |
| 937 | #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */ | |
| 938 | #define CS_DMA 0x2 /* A DMA direction error. */ | |
| 939 | #define CS_TRANSPORT 0x3 /* Transport error. */ | |
| 940 | #define CS_RESET 0x4 /* SCSI bus reset occurred */ | |
| 941 | #define CS_ABORTED 0x5 /* System aborted command. */ | |
| 942 | #define CS_TIMEOUT 0x6 /* Timeout error. */ | |
| 943 | #define CS_DATA_OVERRUN 0x7 /* Data overrun. */ | |
| 944 | #define CS_COMMAND_OVERRUN 0x8 /* Command Overrun. */ | |
| 945 | #define CS_STATUS_OVERRUN 0x9 /* Status Overrun. */ | |
| 946 | #define CS_BAD_MSG 0xA /* Bad msg after status phase. */ | |
| 947 | #define CS_NO_MSG_OUT 0xB /* No msg out after selection. */ | |
| 948 | #define CS_EXTENDED_ID 0xC /* Extended ID failed. */ | |
| 949 | #define CS_IDE_MSG 0xD /* Target rejected IDE msg. */ | |
| 950 | #define CS_ABORT_MSG 0xE /* Target rejected abort msg. */ | |
| 951 | #define CS_REJECT_MSG 0xF /* Target rejected reject msg. */ | |
| 952 | #define CS_NOP_MSG 0x10 /* Target rejected NOP msg. */ | |
| 953 | #define CS_PARITY_MSG 0x11 /* Target rejected parity msg. */ | |
| 954 | #define CS_DEV_RESET_MSG 0x12 /* Target rejected dev rst msg. */ | |
| 955 | #define CS_ID_MSG 0x13 /* Target rejected ID msg. */ | |
| 956 | #define CS_FREE 0x14 /* Unexpected bus free. */ | |
| 957 | #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */ | |
| 958 | #define CS_TRANACTION_1 0x18 /* Transaction error 1 */ | |
| 959 | #define CS_TRANACTION_2 0x19 /* Transaction error 2 */ | |
| 960 | #define CS_TRANACTION_3 0x1a /* Transaction error 3 */ | |
| 961 | #define CS_INV_ENTRY_TYPE 0x1b /* Invalid entry type */ | |
| 962 | #define CS_DEV_QUEUE_FULL 0x1c /* Device queue full */ | |
| 963 | #define CS_PHASED_SKIPPED 0x1d /* SCSI phase skipped */ | |
| 964 | #define CS_ARS_FAILED 0x1e /* ARS failed */ | |
| 965 | #define CS_LVD_BUS_ERROR 0x21 /* LVD bus error */ | |
| 966 | #define CS_BAD_PAYLOAD 0x80 /* Driver defined */ | |
| 967 | #define CS_UNKNOWN 0x81 /* Driver defined */ | |
| 968 | #define CS_RETRY 0x82 /* Driver defined */ | |
| 969 | ||
| 1da177e4 LT |
970 | /* |
| 971 | * ISP target entries - Option flags bit definitions. | |
| 972 | */ | |
| 973 | #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */ | |
| 974 | #define OF_DATA_IN BIT_6 /* Data in to initiator */ | |
| 975 | /* (data from target to initiator) */ | |
| 976 | #define OF_DATA_OUT BIT_7 /* Data out from initiator */ | |
| 977 | /* (data from initiator to target) */ | |
| 978 | #define OF_NO_DATA (BIT_7 | BIT_6) | |
| 979 | #define OF_DISC_DISABLED BIT_15 /* Disconnects disabled */ | |
| 980 | #define OF_DISABLE_SDP BIT_24 /* Disable sending save data ptr */ | |
| 981 | #define OF_SEND_RDP BIT_26 /* Send restore data pointers msg */ | |
| 982 | #define OF_FORCE_DISC BIT_30 /* Disconnects mandatory */ | |
| 983 | #define OF_SSTS BIT_31 /* Send SCSI status */ | |
| 984 | ||
| 985 | ||
| 986 | /* | |
| 987 | * BUS parameters/settings structure - UNUSED | |
| 988 | */ | |
| 989 | struct bus_param { | |
| 990 | uint8_t id; /* Host adapter SCSI id */ | |
| 991 | uint8_t bus_reset_delay; /* SCSI bus reset delay. */ | |
| 992 | uint8_t failed_reset_count; /* number of time reset failed */ | |
| 993 | uint8_t unused; | |
| 994 | uint16_t device_enables; /* Device enable bits. */ | |
| 995 | uint16_t lun_disables; /* LUN disable bits. */ | |
| 996 | uint16_t qtag_enables; /* Tag queue enables. */ | |
| 997 | uint16_t hiwat; /* High water mark per device. */ | |
| 998 | uint8_t reset_marker:1; | |
| 999 | uint8_t disable_scsi_reset:1; | |
| 1000 | uint8_t scsi_bus_dead:1; /* SCSI Bus is Dead, when 5 back to back resets failed */ | |
| 1001 | }; | |
| 1002 | ||
| 1003 | ||
| 1004 | struct qla_driver_setup { | |
| 1005 | uint32_t no_sync:1; | |
| 1006 | uint32_t no_wide:1; | |
| 1007 | uint32_t no_ppr:1; | |
| 1008 | uint32_t no_nvram:1; | |
| 1009 | uint16_t sync_mask; | |
| 1010 | uint16_t wide_mask; | |
| 1011 | uint16_t ppr_mask; | |
| 1012 | }; | |
| 1013 | ||
| 1014 | ||
| 1015 | /* | |
| 1016 | * Linux Host Adapter structure | |
| 1017 | */ | |
| 1018 | struct scsi_qla_host { | |
| 1019 | /* Linux adapter configuration data */ | |
| 1020 | struct Scsi_Host *host; /* pointer to host data */ | |
| 1021 | struct scsi_qla_host *next; | |
| 1022 | struct device_reg __iomem *iobase; /* Base Memory-mapped I/O address */ | |
| 1023 | ||
| 1024 | unsigned char __iomem *mmpbase; /* memory mapped address */ | |
| 1025 | unsigned long host_no; | |
| 1026 | struct pci_dev *pdev; | |
| 1027 | uint8_t devnum; | |
| 1028 | uint8_t revision; | |
| 1029 | uint8_t ports; | |
| 1030 | ||
| 1031 | unsigned long actthreads; | |
| 1032 | unsigned long isr_count; /* Interrupt count */ | |
| 1033 | unsigned long spurious_int; | |
| 1034 | ||
| 1035 | /* Outstandings ISP commands. */ | |
| 1036 | struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS]; | |
| 1037 | ||
| 1038 | /* BUS configuration data */ | |
| 1039 | struct bus_param bus_settings[MAX_BUSES]; | |
| 1040 | ||
| 1041 | /* Received ISP mailbox data. */ | |
| 1042 | volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT]; | |
| 1043 | ||
| 1044 | dma_addr_t request_dma; /* Physical Address */ | |
| 1045 | request_t *request_ring; /* Base virtual address */ | |
| 1046 | request_t *request_ring_ptr; /* Current address. */ | |
| 1047 | uint16_t req_ring_index; /* Current index. */ | |
| 1048 | uint16_t req_q_cnt; /* Number of available entries. */ | |
| 1049 | ||
| 1050 | dma_addr_t response_dma; /* Physical address. */ | |
| 1051 | struct response *response_ring; /* Base virtual address */ | |
| 1052 | struct response *response_ring_ptr; /* Current address. */ | |
| 1053 | uint16_t rsp_ring_index; /* Current index. */ | |
| 1054 | ||
| 1055 | struct list_head done_q; /* Done queue */ | |
| 1056 | ||
| 1057 | struct completion *mailbox_wait; | |
| 1058 | ||
| 1059 | volatile struct { | |
| 1060 | uint32_t online:1; /* 0 */ | |
| 1061 | uint32_t reset_marker:1; /* 1 */ | |
| 1062 | uint32_t disable_host_adapter:1; /* 2 */ | |
| 1063 | uint32_t reset_active:1; /* 3 */ | |
| 1064 | uint32_t abort_isp_active:1; /* 4 */ | |
| 1065 | uint32_t disable_risc_code_load:1; /* 5 */ | |
| 1da177e4 LT |
1066 | #ifdef __ia64__ |
| 1067 | uint32_t use_pci_vchannel:1; | |
| 1068 | #endif | |
| 1069 | } flags; | |
| 1070 | ||
| 1071 | struct nvram nvram; | |
| 1072 | int nvram_valid; | |
| 1bfa11db JSR |
1073 | |
| 1074 | /* Firmware Info */ | |
| 1075 | unsigned short fwstart; /* start address for F/W */ | |
| 1076 | unsigned char fwver1; /* F/W version first char */ | |
| 1077 | unsigned char fwver2; /* F/W version second char */ | |
| 1078 | unsigned char fwver3; /* F/W version third char */ | |
| 1da177e4 LT |
1079 | }; |
| 1080 | ||
| 1081 | #endif /* _QLA1280_H */ |