x86/bugs: Provide boot parameters for the spec_store_bypass_disable mitigation

[mirror_ubuntu-artful-kernel.git] / Documentation / admin-guide / kernel-parameters.txt

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 1bbfe73fcd6ce7e20f9fb0ad83116223d4eef51f..0381f7bf53fe776764afbeafcb9bcfcf7df90f16 100644 (file)
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -2607,6 +2607,9 @@
                        allow data leaks with this option, which is equivalent
                        to spectre_v2=off.
 
+       nospec_store_bypass_disable
+                       [HW] Disable all mitigations for the Speculative Store Bypass vulnerability
+
        noxsave         [BUGS=X86] Disables x86 extended register state save
                        and restore using xsave. The kernel will fallback to
                        enabling legacy floating-point and sse state.
@@ -3929,6 +3932,36 @@
                        Not specifying this option is equivalent to
                        spectre_v2=auto.
 
+       spec_store_bypass_disable=
+                       [HW] Control Speculative Store Bypass (SSB) Disable mitigation
+                       (Speculative Store Bypass vulnerability)
+
+                       Certain CPUs are vulnerable to an exploit against a
+                       a common industry wide performance optimization known
+                       as "Speculative Store Bypass" in which recent stores
+                       to the same memory location may not be observed by
+                       later loads during speculative execution. The idea
+                       is that such stores are unlikely and that they can
+                       be detected prior to instruction retirement at the
+                       end of a particular speculation execution window.
+
+                       In vulnerable processors, the speculatively forwarded
+                       store can be used in a cache side channel attack, for
+                       example to read memory to which the attacker does not
+                       directly have access (e.g. inside sandboxed code).
+
+                       This parameter controls whether the Speculative Store
+                       Bypass optimization is used.
+
+                       on     - Unconditionally disable Speculative Store Bypass
+                       off    - Unconditionally enable Speculative Store Bypass
+                       auto   - Kernel detects whether the CPU model contains an
+                                implementation of Speculative Store Bypass and
+                                picks the most appropriate mitigation
+
+                       Not specifying this option is equivalent to
+                       spec_store_bypass_disable=auto.
+
        spia_io_base=   [HW,MTD]
        spia_fio_base=
        spia_pedr=