x86/bugs: Rename SSBD_NO to SSB_NO

[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 5573c75f8e4ced276c8585b71f0df9b786ea9e90..50439de62f4e10ce09af4e59807f7471f0d31b98 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -38,6 +38,15 @@
 
 /* Intel MSRs. Some also available on other CPUs */
 
+#define MSR_IA32_SPEC_CTRL             0x00000048      /* Speculation Control */
+#define SPEC_CTRL_IBRS                 (1 << 0)        /* Indirect Branch Restricted Speculation */
+#define SPEC_CTRL_STIBP                        (1 << 1)        /* Single Thread Indirect Branch Predictors */
+#define SPEC_CTRL_SSBD_SHIFT           2               /* Speculative Store Bypass Disable bit */
+#define SPEC_CTRL_SSBD                 (1 << SPEC_CTRL_SSBD_SHIFT) /* Speculative Store Bypass Disable */
+
+#define MSR_IA32_PRED_CMD              0x00000049      /* Prediction Command */
+#define PRED_CMD_IBPB                  (1 << 0)        /* Indirect Branch Prediction Barrier */
+
 #define MSR_PPIN_CTL                   0x0000004e
 #define MSR_PPIN                       0x0000004f
 
@@ -56,6 +65,16 @@
 #define SNB_C3_AUTO_UNDEMOTE           (1UL << 28)
 
 #define MSR_MTRRcap                    0x000000fe
+
+#define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
+#define ARCH_CAP_RDCL_NO               (1 << 0)        /* Not susceptible to Meltdown */
+#define ARCH_CAP_IBRS_ALL              (1 << 1)        /* Enhanced IBRS support */
+#define ARCH_CAP_SSB_NO                        (1 << 4)        /*
+                                                        * Not susceptible to Speculative Store Bypass
+                                                        * attack, so no Speculative Store Bypass
+                                                        * control required.
+                                                        */
+
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 #define MSR_IA32_BBL_CR_CTL3           0x0000011e
 
@@ -324,6 +343,8 @@
 #define MSR_AMD64_IBSOPDATA4           0xc001103d
 #define MSR_AMD64_IBS_REG_COUNT_MAX    8 /* includes MSR_AMD64_IBSBRTARGET */
 
+#define MSR_AMD64_VIRT_SPEC_CTRL       0xc001011f
+
 /* Fam 17h MSRs */
 #define MSR_F17H_IRPERF                        0xc00000e9
 
@@ -342,6 +363,7 @@
 #define MSR_F15H_NB_PERF_CTR           0xc0010241
 #define MSR_F15H_PTSC                  0xc0010280
 #define MSR_F15H_IC_CFG                        0xc0011021
+#define MSR_F15H_IC_CFG_DIS_IND                BIT_ULL(14)
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058
@@ -351,6 +373,9 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
+#define MSR_F10H_DECFG                 0xc0011029
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
+#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a
@@ -434,6 +459,8 @@
 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX       (1<<1)
 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX      (1<<2)
 #define FEATURE_CONTROL_LMCE                           (1<<20)
+#define FEATURE_ENABLE_IBRS                            (1<<0)
+#define FEATURE_SET_IBPB                               (1<<0)
 
 #define MSR_IA32_APICBASE              0x0000001b
 #define MSR_IA32_APICBASE_BSP          (1<<8)