x86/bugs/intel: Set proper CPU features and setup RDS

[mirror_ubuntu-artful-kernel.git] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 4e3438a00a5041389de8bc0daf750f55b4fb5731..ceeeadb38f925148d2a080ac6bb4764873550c7f 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -38,12 +38,17 @@
 
 /* Intel MSRs. Some also available on other CPUs */
 
+#define MSR_IA32_SPEC_CTRL             0x00000048      /* Speculation Control */
+#define SPEC_CTRL_IBRS                 (1 << 0)        /* Indirect Branch Restricted Speculation */
+#define SPEC_CTRL_STIBP                        (1 << 1)        /* Single Thread Indirect Branch Predictors */
+#define SPEC_CTRL_RDS                  (1 << 2)        /* Reduced Data Speculation */
+
+#define MSR_IA32_PRED_CMD              0x00000049      /* Prediction Command */
+#define PRED_CMD_IBPB                  (1 << 0)        /* Indirect Branch Prediction Barrier */
+
 #define MSR_PPIN_CTL                   0x0000004e
 #define MSR_PPIN                       0x0000004f
 
-#define MSR_IA32_SPEC_CTRL             0x00000048
-#define MSR_IA32_PRED_CMD              0x00000049
-
 #define MSR_IA32_PERFCTR0              0x000000c1
 #define MSR_IA32_PERFCTR1              0x000000c2
 #define MSR_FSB_FREQ                   0x000000cd
@@ -59,6 +64,16 @@
 #define SNB_C3_AUTO_UNDEMOTE           (1UL << 28)
 
 #define MSR_MTRRcap                    0x000000fe
+
+#define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
+#define ARCH_CAP_RDCL_NO               (1 << 0)        /* Not susceptible to Meltdown */
+#define ARCH_CAP_IBRS_ALL              (1 << 1)        /* Enhanced IBRS support */
+#define ARCH_CAP_RDS_NO                        (1 << 4)        /*
+                                                        * Not susceptible to Speculative Store Bypass
+                                                        * attack, so no Reduced Data Speculation control
+                                                        * required.
+                                                        */
+
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 #define MSR_IA32_BBL_CR_CTL3           0x0000011e
 
@@ -345,6 +360,7 @@
 #define MSR_F15H_NB_PERF_CTR           0xc0010241
 #define MSR_F15H_PTSC                  0xc0010280
 #define MSR_F15H_IC_CFG                        0xc0011021
+#define MSR_F15H_IC_CFG_DIS_IND                BIT_ULL(14)
 
 /* Fam 10h MSRs */
 #define MSR_FAM10H_MMIO_CONF_BASE      0xc0010058