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ARM: davinci: dm646x: fix timer interrupt generation
[mirror_ubuntu-bionic-kernel.git] / arch / arm / mach-davinci / dm646x.c
CommitLineData
e38d92fd
KH		 1/*
2 * TI DaVinci DM644x chip specific setup
3 *
4 * Author: Kevin Hilman, Deep Root Systems, LLC
5 *
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
b7f080cf 11#include <linux/dma-mapping.h>
2137d54d 12#include <linux/dmaengine.h>
e38d92fd
KH		 13#include <linux/init.h>
14#include <linux/clk.h>
65e866a9 15#include <linux/serial_8250.h>
e38d92fd 16#include <linux/platform_device.h>
3ad7a42d 17#include <linux/platform_data/edma.h>
9cc1515c 18#include <linux/platform_data/gpio-davinci.h>
e38d92fd 19
79c3c0b7
MG		 20#include <asm/mach/map.h>
21
e38d92fd 22#include <mach/cputype.h>
e38d92fd 23#include <mach/irqs.h>
3acf731c 24#include "psc.h"
e38d92fd 25#include <mach/mux.h>
f64691b3 26#include <mach/time.h>
65e866a9 27#include <mach/serial.h>
79c3c0b7 28#include <mach/common.h>
e38d92fd 29
39c6d2d1 30#include "davinci.h"
e38d92fd
KH		 31#include "clock.h"
32#include "mux.h"
896f66b7 33#include "asp.h"
e38d92fd 34
85609c1c 35#define DAVINCI_VPIF_BASE (0x01C12000)
85609c1c
MK		 36
37#define VDD3P3V_VID_MASK (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
38 BIT_MASK(0))
39#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
40 BIT_MASK(8))
41
e38d92fd
KH		 42/*
43 * Device specific clocks
44 */
56e580d7 45#define DM646X_REF_FREQ 27000000
e38d92fd
KH		 46#define DM646X_AUX_FREQ 24000000
47
3d091406
MH		 48#define DM646X_EMAC_BASE 0x01c80000
49#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
50#define DM646X_EMAC_CNTRL_OFFSET 0x0000
51#define DM646X_EMAC_CNTRL_MOD_OFFSET 0x1000
52#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
53#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
54
e38d92fd
KH		 55static struct pll_data pll1_data = {
56 .num = 1,
57 .phys_base = DAVINCI_PLL1_BASE,
58};
59
60static struct pll_data pll2_data = {
61 .num = 2,
62 .phys_base = DAVINCI_PLL2_BASE,
63};
64
65static struct clk ref_clk = {
66 .name = "ref_clk",
56e580d7
SN		 67 .rate = DM646X_REF_FREQ,
68 .set_rate = davinci_simple_set_rate,
e38d92fd
KH		 69};
70
71static struct clk aux_clkin = {
72 .name = "aux_clkin",
73 .rate = DM646X_AUX_FREQ,
74};
75
76static struct clk pll1_clk = {
77 .name = "pll1",
78 .parent = &ref_clk,
79 .pll_data = &pll1_data,
80 .flags = CLK_PLL,
81};
82
83static struct clk pll1_sysclk1 = {
84 .name = "pll1_sysclk1",
85 .parent = &pll1_clk,
86 .flags = CLK_PLL,
87 .div_reg = PLLDIV1,
88};
89
90static struct clk pll1_sysclk2 = {
91 .name = "pll1_sysclk2",
92 .parent = &pll1_clk,
93 .flags = CLK_PLL,
94 .div_reg = PLLDIV2,
95};
96
97static struct clk pll1_sysclk3 = {
98 .name = "pll1_sysclk3",
99 .parent = &pll1_clk,
100 .flags = CLK_PLL,
101 .div_reg = PLLDIV3,
102};
103
104static struct clk pll1_sysclk4 = {
105 .name = "pll1_sysclk4",
106 .parent = &pll1_clk,
107 .flags = CLK_PLL,
108 .div_reg = PLLDIV4,
109};
110
111static struct clk pll1_sysclk5 = {
112 .name = "pll1_sysclk5",
113 .parent = &pll1_clk,
114 .flags = CLK_PLL,
115 .div_reg = PLLDIV5,
116};
117
118static struct clk pll1_sysclk6 = {
119 .name = "pll1_sysclk6",
120 .parent = &pll1_clk,
121 .flags = CLK_PLL,
122 .div_reg = PLLDIV6,
123};
124
125static struct clk pll1_sysclk8 = {
126 .name = "pll1_sysclk8",
127 .parent = &pll1_clk,
128 .flags = CLK_PLL,
129 .div_reg = PLLDIV8,
130};
131
132static struct clk pll1_sysclk9 = {
133 .name = "pll1_sysclk9",
134 .parent = &pll1_clk,
135 .flags = CLK_PLL,
136 .div_reg = PLLDIV9,
137};
138
139static struct clk pll1_sysclkbp = {
140 .name = "pll1_sysclkbp",
141 .parent = &pll1_clk,
142 .flags = CLK_PLL | PRE_PLL,
143 .div_reg = BPDIV,
144};
145
146static struct clk pll1_aux_clk = {
147 .name = "pll1_aux_clk",
148 .parent = &pll1_clk,
149 .flags = CLK_PLL | PRE_PLL,
150};
151
152static struct clk pll2_clk = {
153 .name = "pll2_clk",
154 .parent = &ref_clk,
155 .pll_data = &pll2_data,
156 .flags = CLK_PLL,
157};
158
159static struct clk pll2_sysclk1 = {
160 .name = "pll2_sysclk1",
161 .parent = &pll2_clk,
162 .flags = CLK_PLL,
163 .div_reg = PLLDIV1,
164};
165
166static struct clk dsp_clk = {
167 .name = "dsp",
168 .parent = &pll1_sysclk1,
169 .lpsc = DM646X_LPSC_C64X_CPU,
e38d92fd
KH		 170 .usecount = 1, /* REVISIT how to disable? */
171};
172
173static struct clk arm_clk = {
174 .name = "arm",
175 .parent = &pll1_sysclk2,
176 .lpsc = DM646X_LPSC_ARM,
177 .flags = ALWAYS_ENABLED,
178};
179
2bcb613a
SR		 180static struct clk edma_cc_clk = {
181 .name = "edma_cc",
182 .parent = &pll1_sysclk2,
183 .lpsc = DM646X_LPSC_TPCC,
184 .flags = ALWAYS_ENABLED,
185};
186
187static struct clk edma_tc0_clk = {
188 .name = "edma_tc0",
189 .parent = &pll1_sysclk2,
190 .lpsc = DM646X_LPSC_TPTC0,
191 .flags = ALWAYS_ENABLED,
192};
193
194static struct clk edma_tc1_clk = {
195 .name = "edma_tc1",
196 .parent = &pll1_sysclk2,
197 .lpsc = DM646X_LPSC_TPTC1,
198 .flags = ALWAYS_ENABLED,
199};
200
201static struct clk edma_tc2_clk = {
202 .name = "edma_tc2",
203 .parent = &pll1_sysclk2,
204 .lpsc = DM646X_LPSC_TPTC2,
205 .flags = ALWAYS_ENABLED,
206};
207
208static struct clk edma_tc3_clk = {
209 .name = "edma_tc3",
210 .parent = &pll1_sysclk2,
211 .lpsc = DM646X_LPSC_TPTC3,
212 .flags = ALWAYS_ENABLED,
213};
214
e38d92fd
KH		 215static struct clk uart0_clk = {
216 .name = "uart0",
217 .parent = &aux_clkin,
218 .lpsc = DM646X_LPSC_UART0,
219};
220
221static struct clk uart1_clk = {
222 .name = "uart1",
223 .parent = &aux_clkin,
224 .lpsc = DM646X_LPSC_UART1,
225};
226
227static struct clk uart2_clk = {
228 .name = "uart2",
229 .parent = &aux_clkin,
230 .lpsc = DM646X_LPSC_UART2,
231};
232
233static struct clk i2c_clk = {
234 .name = "I2CCLK",
235 .parent = &pll1_sysclk3,
236 .lpsc = DM646X_LPSC_I2C,
237};
238
239static struct clk gpio_clk = {
240 .name = "gpio",
241 .parent = &pll1_sysclk3,
242 .lpsc = DM646X_LPSC_GPIO,
243};
244
75d0fa70
C		 245static struct clk mcasp0_clk = {
246 .name = "mcasp0",
247 .parent = &pll1_sysclk3,
248 .lpsc = DM646X_LPSC_McASP0,
249};
250
251static struct clk mcasp1_clk = {
252 .name = "mcasp1",
253 .parent = &pll1_sysclk3,
254 .lpsc = DM646X_LPSC_McASP1,
255};
256
e38d92fd
KH		 257static struct clk aemif_clk = {
258 .name = "aemif",
259 .parent = &pll1_sysclk3,
260 .lpsc = DM646X_LPSC_AEMIF,
261 .flags = ALWAYS_ENABLED,
262};
263
264static struct clk emac_clk = {
265 .name = "emac",
266 .parent = &pll1_sysclk3,
267 .lpsc = DM646X_LPSC_EMAC,
268};
269
270static struct clk pwm0_clk = {
271 .name = "pwm0",
272 .parent = &pll1_sysclk3,
273 .lpsc = DM646X_LPSC_PWM0,
274 .usecount = 1, /* REVIST: disabling hangs system */
275};
276
277static struct clk pwm1_clk = {
278 .name = "pwm1",
279 .parent = &pll1_sysclk3,
280 .lpsc = DM646X_LPSC_PWM1,
281 .usecount = 1, /* REVIST: disabling hangs system */
282};
283
284static struct clk timer0_clk = {
285 .name = "timer0",
286 .parent = &pll1_sysclk3,
287 .lpsc = DM646X_LPSC_TIMER0,
288};
289
290static struct clk timer1_clk = {
291 .name = "timer1",
292 .parent = &pll1_sysclk3,
293 .lpsc = DM646X_LPSC_TIMER1,
294};
295
296static struct clk timer2_clk = {
297 .name = "timer2",
298 .parent = &pll1_sysclk3,
299 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
300};
301
3e25d5f4
HP		 302
303static struct clk ide_clk = {
304 .name = "ide",
305 .parent = &pll1_sysclk4,
306 .lpsc = DAVINCI_LPSC_ATA,
307};
308
e38d92fd
KH		 309static struct clk vpif0_clk = {
310 .name = "vpif0",
311 .parent = &ref_clk,
312 .lpsc = DM646X_LPSC_VPSSMSTR,
313 .flags = ALWAYS_ENABLED,
314};
315
316static struct clk vpif1_clk = {
317 .name = "vpif1",
318 .parent = &ref_clk,
319 .lpsc = DM646X_LPSC_VPSSSLV,
320 .flags = ALWAYS_ENABLED,
321};
322
28552c2e 323static struct clk_lookup dm646x_clks[] = {
e38d92fd
KH		 324 CLK(NULL, "ref", &ref_clk),
325 CLK(NULL, "aux", &aux_clkin),
326 CLK(NULL, "pll1", &pll1_clk),
327 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
328 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
329 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
330 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
331 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
332 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
333 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
334 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
335 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
336 CLK(NULL, "pll1_aux", &pll1_aux_clk),
337 CLK(NULL, "pll2", &pll2_clk),
338 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
339 CLK(NULL, "dsp", &dsp_clk),
340 CLK(NULL, "arm", &arm_clk),
2bcb613a
SR		 341 CLK(NULL, "edma_cc", &edma_cc_clk),
342 CLK(NULL, "edma_tc0", &edma_tc0_clk),
343 CLK(NULL, "edma_tc1", &edma_tc1_clk),
344 CLK(NULL, "edma_tc2", &edma_tc2_clk),
345 CLK(NULL, "edma_tc3", &edma_tc3_clk),
19955c3d
MP		 346 CLK("serial8250.0", NULL, &uart0_clk),
347 CLK("serial8250.1", NULL, &uart1_clk),
348 CLK("serial8250.2", NULL, &uart2_clk),
e38d92fd
KH		 349 CLK("i2c_davinci.1", NULL, &i2c_clk),
350 CLK(NULL, "gpio", &gpio_clk),
61aa0732
KH		 351 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
352 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
e38d92fd
KH		 353 CLK(NULL, "aemif", &aemif_clk),
354 CLK("davinci_emac.1", NULL, &emac_clk),
46c18334 355 CLK("davinci_mdio.0", "fck", &emac_clk),
e38d92fd
KH		 356 CLK(NULL, "pwm0", &pwm0_clk),
357 CLK(NULL, "pwm1", &pwm1_clk),
358 CLK(NULL, "timer0", &timer0_clk),
359 CLK(NULL, "timer1", &timer1_clk),
84374812 360 CLK("davinci-wdt", NULL, &timer2_clk),
3e25d5f4 361 CLK("palm_bk3710", NULL, &ide_clk),
e38d92fd
KH		 362 CLK(NULL, "vpif0", &vpif0_clk),
363 CLK(NULL, "vpif1", &vpif1_clk),
364 CLK(NULL, NULL, NULL),
365};
366
972412b6
MG		 367static struct emac_platform_data dm646x_emac_pdata = {
368 .ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
369 .ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET,
370 .ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET,
972412b6
MG		 371 .ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE,
372 .version = EMAC_VERSION_2,
373};
374
ac7b75b5
KH		 375static struct resource dm646x_emac_resources[] = {
376 {
377 .start = DM646X_EMAC_BASE,
d22960c8 378 .end = DM646X_EMAC_BASE + SZ_16K - 1,
ac7b75b5
KH		 379 .flags = IORESOURCE_MEM,
380 },
381 {
382 .start = IRQ_DM646X_EMACRXTHINT,
383 .end = IRQ_DM646X_EMACRXTHINT,
384 .flags = IORESOURCE_IRQ,
385 },
386 {
387 .start = IRQ_DM646X_EMACRXINT,
388 .end = IRQ_DM646X_EMACRXINT,
389 .flags = IORESOURCE_IRQ,
390 },
391 {
392 .start = IRQ_DM646X_EMACTXINT,
393 .end = IRQ_DM646X_EMACTXINT,
394 .flags = IORESOURCE_IRQ,
395 },
396 {
397 .start = IRQ_DM646X_EMACMISCINT,
398 .end = IRQ_DM646X_EMACMISCINT,
399 .flags = IORESOURCE_IRQ,
400 },
401};
402
403static struct platform_device dm646x_emac_device = {
404 .name = "davinci_emac",
405 .id = 1,
972412b6
MG		 406 .dev = {
407 .platform_data = &dm646x_emac_pdata,
408 },
ac7b75b5
KH		 409 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
410 .resource = dm646x_emac_resources,
411};
412
d22960c8
CC		 413static struct resource dm646x_mdio_resources[] = {
414 {
415 .start = DM646X_EMAC_MDIO_BASE,
416 .end = DM646X_EMAC_MDIO_BASE + SZ_4K - 1,
417 .flags = IORESOURCE_MEM,
418 },
419};
420
421static struct platform_device dm646x_mdio_device = {
422 .name = "davinci_mdio",
423 .id = 0,
424 .num_resources = ARRAY_SIZE(dm646x_mdio_resources),
425 .resource = dm646x_mdio_resources,
426};
427
e38d92fd
KH		 428/*
429 * Device specific mux setup
430 *
431 * soc description mux mode mode mux dbg
432 * reg offset mask mode
433 */
434static const struct mux_config dm646x_pins[] = {
0e585952 435#ifdef CONFIG_DAVINCI_MUX
3e25d5f4 436MUX_CFG(DM646X, ATAEN, 0, 0, 5, 1, true)
e38d92fd
KH		 437
438MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
439
440MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
441
442MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
443
444MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
445
446MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
447
448MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
449
450MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
451
452MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
453
454MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
455
456MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
457
458MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
459
460MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
461
462MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
0e585952 463#endif
e38d92fd
KH		 464};
465
673dd36f
MG		 466static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
467 [IRQ_DM646X_VP_VERTINT0] = 7,
468 [IRQ_DM646X_VP_VERTINT1] = 7,
469 [IRQ_DM646X_VP_VERTINT2] = 7,
470 [IRQ_DM646X_VP_VERTINT3] = 7,
471 [IRQ_DM646X_VP_ERRINT] = 7,
472 [IRQ_DM646X_RESERVED_1] = 7,
473 [IRQ_DM646X_RESERVED_2] = 7,
474 [IRQ_DM646X_WDINT] = 7,
475 [IRQ_DM646X_CRGENINT0] = 7,
476 [IRQ_DM646X_CRGENINT1] = 7,
477 [IRQ_DM646X_TSIFINT0] = 7,
478 [IRQ_DM646X_TSIFINT1] = 7,
479 [IRQ_DM646X_VDCEINT] = 7,
480 [IRQ_DM646X_USBINT] = 7,
481 [IRQ_DM646X_USBDMAINT] = 7,
482 [IRQ_DM646X_PCIINT] = 7,
483 [IRQ_CCINT0] = 7, /* dma */
484 [IRQ_CCERRINT] = 7, /* dma */
485 [IRQ_TCERRINT0] = 7, /* dma */
486 [IRQ_TCERRINT] = 7, /* dma */
487 [IRQ_DM646X_TCERRINT2] = 7,
488 [IRQ_DM646X_TCERRINT3] = 7,
489 [IRQ_DM646X_IDE] = 7,
490 [IRQ_DM646X_HPIINT] = 7,
491 [IRQ_DM646X_EMACRXTHINT] = 7,
492 [IRQ_DM646X_EMACRXINT] = 7,
493 [IRQ_DM646X_EMACTXINT] = 7,
494 [IRQ_DM646X_EMACMISCINT] = 7,
495 [IRQ_DM646X_MCASP0TXINT] = 7,
496 [IRQ_DM646X_MCASP0RXINT] = 7,
673dd36f 497 [IRQ_DM646X_RESERVED_3] = 7,
076e600e
SN		 498 [IRQ_DM646X_MCASP1TXINT] = 7,
499 [IRQ_TINT0_TINT12] = 7, /* clockevent */
673dd36f
MG		 500 [IRQ_TINT0_TINT34] = 7, /* clocksource */
501 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
502 [IRQ_TINT1_TINT34] = 7, /* system tick */
503 [IRQ_PWMINT0] = 7,
504 [IRQ_PWMINT1] = 7,
505 [IRQ_DM646X_VLQINT] = 7,
506 [IRQ_I2C] = 7,
507 [IRQ_UARTINT0] = 7,
508 [IRQ_UARTINT1] = 7,
509 [IRQ_DM646X_UARTINT2] = 7,
510 [IRQ_DM646X_SPINT0] = 7,
511 [IRQ_DM646X_SPINT1] = 7,
512 [IRQ_DM646X_DSP2ARMINT] = 7,
513 [IRQ_DM646X_RESERVED_4] = 7,
514 [IRQ_DM646X_PSCINT] = 7,
515 [IRQ_DM646X_GPIO0] = 7,
516 [IRQ_DM646X_GPIO1] = 7,
517 [IRQ_DM646X_GPIO2] = 7,
518 [IRQ_DM646X_GPIO3] = 7,
519 [IRQ_DM646X_GPIO4] = 7,
520 [IRQ_DM646X_GPIO5] = 7,
521 [IRQ_DM646X_GPIO6] = 7,
522 [IRQ_DM646X_GPIO7] = 7,
523 [IRQ_DM646X_GPIOBNK0] = 7,
524 [IRQ_DM646X_GPIOBNK1] = 7,
525 [IRQ_DM646X_GPIOBNK2] = 7,
526 [IRQ_DM646X_DDRINT] = 7,
527 [IRQ_DM646X_AEMIFINT] = 7,
528 [IRQ_COMMTX] = 7,
529 [IRQ_COMMRX] = 7,
530 [IRQ_EMUINT] = 7,
531};
532
e38d92fd
KH		 533/*----------------------------------------------------------------------*/
534
60902a2c 535/* Four Transfer Controllers on DM646x */
d4cb7f40 536static s8 dm646x_queue_priority_mapping[][2] = {
60902a2c
SR		 537 /* {event queue no, Priority} */
538 {0, 4},
539 {1, 0},
540 {2, 5},
541 {3, 1},
542 {-1, -1},
543};
544
2137d54d
PU		 545static const struct dma_slave_map dm646x_edma_map[] = {
546 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 6) },
547 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 9) },
548 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 12) },
549 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
550 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
551};
552
d4cb7f40 553static struct edma_soc_info dm646x_edma_pdata = {
bc3ac9f3 554 .queue_priority_mapping = dm646x_queue_priority_mapping,
f23fe857 555 .default_queue = EVENTQ_1,
2137d54d
PU		 556 .slave_map = dm646x_edma_map,
557 .slavecnt = ARRAY_SIZE(dm646x_edma_map),
bc3ac9f3
SN		 558};
559
e38d92fd
KH		 560static struct resource edma_resources[] = {
561 {
d4cb7f40 562 .name = "edma3_cc",
e38d92fd
KH		 563 .start = 0x01c00000,
564 .end = 0x01c00000 + SZ_64K - 1,
565 .flags = IORESOURCE_MEM,
566 },
567 {
d4cb7f40 568 .name = "edma3_tc0",
e38d92fd
KH		 569 .start = 0x01c10000,
570 .end = 0x01c10000 + SZ_1K - 1,
571 .flags = IORESOURCE_MEM,
572 },
573 {
d4cb7f40 574 .name = "edma3_tc1",
e38d92fd
KH		 575 .start = 0x01c10400,
576 .end = 0x01c10400 + SZ_1K - 1,
577 .flags = IORESOURCE_MEM,
578 },
579 {
d4cb7f40 580 .name = "edma3_tc2",
e38d92fd
KH		 581 .start = 0x01c10800,
582 .end = 0x01c10800 + SZ_1K - 1,
583 .flags = IORESOURCE_MEM,
584 },
585 {
d4cb7f40 586 .name = "edma3_tc3",
e38d92fd
KH		 587 .start = 0x01c10c00,
588 .end = 0x01c10c00 + SZ_1K - 1,
589 .flags = IORESOURCE_MEM,
590 },
591 {
d4cb7f40 592 .name = "edma3_ccint",
e38d92fd
KH		 593 .start = IRQ_CCINT0,
594 .flags = IORESOURCE_IRQ,
595 },
596 {
d4cb7f40 597 .name = "edma3_ccerrint",
e38d92fd
KH		 598 .start = IRQ_CCERRINT,
599 .flags = IORESOURCE_IRQ,
600 },
601 /* not using TC*_ERR */
602};
603
7ab388e8
PU		 604static const struct platform_device_info dm646x_edma_device __initconst = {
605 .name = "edma",
606 .id = 0,
cef5b0da 607 .dma_mask = DMA_BIT_MASK(32),
7ab388e8
PU		 608 .res = edma_resources,
609 .num_res = ARRAY_SIZE(edma_resources),
610 .data = &dm646x_edma_pdata,
611 .size_data = sizeof(dm646x_edma_pdata),
e38d92fd
KH		 612};
613
25acf553
C		 614static struct resource dm646x_mcasp0_resources[] = {
615 {
ee880dbd 616 .name = "mpu",
25acf553
C		 617 .start = DAVINCI_DM646X_MCASP0_REG_BASE,
618 .end = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
619 .flags = IORESOURCE_MEM,
620 },
25acf553 621 {
256b20a5 622 .name = "tx",
25acf553
C		 623 .start = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
624 .end = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
625 .flags = IORESOURCE_DMA,
626 },
627 {
256b20a5 628 .name = "rx",
25acf553
C		 629 .start = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
630 .end = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
631 .flags = IORESOURCE_DMA,
632 },
6cfdf55b
PU		 633 {
634 .name = "tx",
635 .start = IRQ_DM646X_MCASP0TXINT,
636 .flags = IORESOURCE_IRQ,
637 },
638 {
639 .name = "rx",
640 .start = IRQ_DM646X_MCASP0RXINT,
641 .flags = IORESOURCE_IRQ,
642 },
25acf553
C		 643};
644
256b20a5 645/* DIT mode only, rx is not supported */
25acf553
C		 646static struct resource dm646x_mcasp1_resources[] = {
647 {
ee880dbd 648 .name = "mpu",
25acf553
C		 649 .start = DAVINCI_DM646X_MCASP1_REG_BASE,
650 .end = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
651 .flags = IORESOURCE_MEM,
652 },
25acf553 653 {
256b20a5 654 .name = "tx",
25acf553
C		 655 .start = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
656 .end = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
657 .flags = IORESOURCE_DMA,
658 },
6cfdf55b
PU		 659 {
660 .name = "tx",
661 .start = IRQ_DM646X_MCASP1TXINT,
662 .flags = IORESOURCE_IRQ,
663 },
25acf553
C		 664};
665
666static struct platform_device dm646x_mcasp0_device = {
667 .name = "davinci-mcasp",
668 .id = 0,
669 .num_resources = ARRAY_SIZE(dm646x_mcasp0_resources),
670 .resource = dm646x_mcasp0_resources,
671};
672
673static struct platform_device dm646x_mcasp1_device = {
674 .name = "davinci-mcasp",
675 .id = 1,
676 .num_resources = ARRAY_SIZE(dm646x_mcasp1_resources),
677 .resource = dm646x_mcasp1_resources,
678};
679
680static struct platform_device dm646x_dit_device = {
681 .name = "spdif-dit",
682 .id = -1,
683};
684
85609c1c
MK		 685static u64 vpif_dma_mask = DMA_BIT_MASK(32);
686
687static struct resource vpif_resource[] = {
688 {
689 .start = DAVINCI_VPIF_BASE,
690 .end = DAVINCI_VPIF_BASE + 0x03ff,
691 .flags = IORESOURCE_MEM,
692 }
693};
694
695static struct platform_device vpif_dev = {
696 .name = "vpif",
697 .id = -1,
698 .dev = {
699 .dma_mask = &vpif_dma_mask,
700 .coherent_dma_mask = DMA_BIT_MASK(32),
701 },
702 .resource = vpif_resource,
703 .num_resources = ARRAY_SIZE(vpif_resource),
704};
705
706static struct resource vpif_display_resource[] = {
707 {
708 .start = IRQ_DM646X_VP_VERTINT2,
709 .end = IRQ_DM646X_VP_VERTINT2,
710 .flags = IORESOURCE_IRQ,
711 },
712 {
713 .start = IRQ_DM646X_VP_VERTINT3,
714 .end = IRQ_DM646X_VP_VERTINT3,
715 .flags = IORESOURCE_IRQ,
716 },
717};
718
719static struct platform_device vpif_display_dev = {
720 .name = "vpif_display",
721 .id = -1,
722 .dev = {
723 .dma_mask = &vpif_dma_mask,
724 .coherent_dma_mask = DMA_BIT_MASK(32),
725 },
726 .resource = vpif_display_resource,
727 .num_resources = ARRAY_SIZE(vpif_display_resource),
728};
729
730static struct resource vpif_capture_resource[] = {
731 {
732 .start = IRQ_DM646X_VP_VERTINT0,
733 .end = IRQ_DM646X_VP_VERTINT0,
734 .flags = IORESOURCE_IRQ,
735 },
736 {
737 .start = IRQ_DM646X_VP_VERTINT1,
738 .end = IRQ_DM646X_VP_VERTINT1,
739 .flags = IORESOURCE_IRQ,
740 },
741};
742
743static struct platform_device vpif_capture_dev = {
744 .name = "vpif_capture",
745 .id = -1,
746 .dev = {
747 .dma_mask = &vpif_dma_mask,
748 .coherent_dma_mask = DMA_BIT_MASK(32),
749 },
750 .resource = vpif_capture_resource,
751 .num_resources = ARRAY_SIZE(vpif_capture_resource),
752};
753
9cc1515c
PA		 754static struct resource dm646x_gpio_resources[] = {
755 { /* registers */
756 .start = DAVINCI_GPIO_BASE,
757 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
758 .flags = IORESOURCE_MEM,
759 },
760 { /* interrupt */
761 .start = IRQ_DM646X_GPIOBNK0,
762 .end = IRQ_DM646X_GPIOBNK2,
763 .flags = IORESOURCE_IRQ,
764 },
765};
766
767static struct davinci_gpio_platform_data dm646x_gpio_platform_data = {
768 .ngpio = 43,
9cc1515c
PA		 769};
770
771int __init dm646x_gpio_register(void)
772{
773 return davinci_gpio_register(dm646x_gpio_resources,
e462f1f5 774 ARRAY_SIZE(dm646x_gpio_resources),
9cc1515c
PA		 775 &dm646x_gpio_platform_data);
776}
e38d92fd
KH		 777/*----------------------------------------------------------------------*/
778
79c3c0b7
MG		 779static struct map_desc dm646x_io_desc[] = {
780 {
781 .virtual = IO_VIRT,
782 .pfn = __phys_to_pfn(IO_PHYS),
783 .length = IO_SIZE,
784 .type = MT_DEVICE
785 },
786};
787
b9ab1279
MG		 788/* Contents of JTAG ID register used to identify exact cpu type */
789static struct davinci_id dm646x_ids[] = {
790 {
791 .variant = 0x0,
792 .part_no = 0xb770,
793 .manufacturer = 0x017,
794 .cpu_id = DAVINCI_CPU_ID_DM6467,
f63dd12d
HP		 795 .name = "dm6467_rev1.x",
796 },
797 {
798 .variant = 0x1,
799 .part_no = 0xb770,
800 .manufacturer = 0x017,
801 .cpu_id = DAVINCI_CPU_ID_DM6467,
802 .name = "dm6467_rev3.x",
b9ab1279
MG		 803 },
804};
805
e4c822c7 806static u32 dm646x_psc_bases[] = { DAVINCI_PWR_SLEEP_CNTRL_BASE };
d81d188c 807
f64691b3
MG		 808/*
809 * T0_BOT: Timer 0, bottom: clockevent source for hrtimers
810 * T0_TOP: Timer 0, top : clocksource for generic timekeeping
811 * T1_BOT: Timer 1, bottom: (used by DSP in TI DSPLink code)
812 * T1_TOP: Timer 1, top : <unused>
813 */
28552c2e 814static struct davinci_timer_info dm646x_timer_info = {
f64691b3
MG		 815 .timers = davinci_timer_instance,
816 .clockevent_id = T0_BOT,
817 .clocksource_id = T0_TOP,
818};
819
19955c3d 820static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
65e866a9
MG		 821 {
822 .mapbase = DAVINCI_UART0_BASE,
823 .irq = IRQ_UARTINT0,
824 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
825 UPF_IOREMAP,
826 .iotype = UPIO_MEM32,
827 .regshift = 2,
828 },
19955c3d
MP		 829 {
830 .flags = 0,
831 }
832};
833static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
65e866a9
MG		 834 {
835 .mapbase = DAVINCI_UART1_BASE,
836 .irq = IRQ_UARTINT1,
837 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
838 UPF_IOREMAP,
839 .iotype = UPIO_MEM32,
840 .regshift = 2,
841 },
19955c3d
MP		 842 {
843 .flags = 0,
844 }
845};
846static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
65e866a9
MG		 847 {
848 .mapbase = DAVINCI_UART2_BASE,
849 .irq = IRQ_DM646X_UARTINT2,
850 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
851 UPF_IOREMAP,
852 .iotype = UPIO_MEM32,
853 .regshift = 2,
854 },
855 {
19955c3d
MP		 856 .flags = 0,
857 }
65e866a9
MG		 858};
859
fcf7157b 860struct platform_device dm646x_serial_device[] = {
19955c3d
MP		 861 {
862 .name = "serial8250",
863 .id = PLAT8250_DEV_PLATFORM,
864 .dev = {
865 .platform_data = dm646x_serial0_platform_data,
866 }
867 },
868 {
869 .name = "serial8250",
870 .id = PLAT8250_DEV_PLATFORM1,
871 .dev = {
872 .platform_data = dm646x_serial1_platform_data,
873 }
65e866a9 874 },
19955c3d
MP		 875 {
876 .name = "serial8250",
877 .id = PLAT8250_DEV_PLATFORM2,
878 .dev = {
879 .platform_data = dm646x_serial2_platform_data,
880 }
881 },
882 {
883 }
65e866a9
MG		 884};
885
79c3c0b7
MG		 886static struct davinci_soc_info davinci_soc_info_dm646x = {
887 .io_desc = dm646x_io_desc,
888 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
3347db83 889 .jtag_id_reg = 0x01c40028,
b9ab1279
MG		 890 .ids = dm646x_ids,
891 .ids_num = ARRAY_SIZE(dm646x_ids),
66e0c399 892 .cpu_clks = dm646x_clks,
d81d188c
MG		 893 .psc_bases = dm646x_psc_bases,
894 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
779b0d53 895 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
0e585952
MG		 896 .pinmux_pins = dm646x_pins,
897 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
bd808947 898 .intc_base = DAVINCI_ARM_INTC_BASE,
673dd36f
MG		 899 .intc_type = DAVINCI_INTC_TYPE_AINTC,
900 .intc_irq_prios = dm646x_default_priorities,
901 .intc_irq_num = DAVINCI_N_AINTC_IRQ,
f64691b3 902 .timer_info = &dm646x_timer_info,
972412b6 903 .emac_pdata = &dm646x_emac_pdata,
0d04eb47
DB		 904 .sram_dma = 0x10010000,
905 .sram_len = SZ_32K,
79c3c0b7
MG		 906};
907
25acf553
C		 908void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
909{
910 dm646x_mcasp0_device.dev.platform_data = pdata;
911 platform_device_register(&dm646x_mcasp0_device);
912}
913
914void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
915{
916 dm646x_mcasp1_device.dev.platform_data = pdata;
917 platform_device_register(&dm646x_mcasp1_device);
918 platform_device_register(&dm646x_dit_device);
919}
920
85609c1c
MK		 921void dm646x_setup_vpif(struct vpif_display_config *display_config,
922 struct vpif_capture_config *capture_config)
923{
924 unsigned int value;
85609c1c 925
5cfb19ac 926 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 927 value &= ~VSCLKDIS_MASK;
5cfb19ac 928 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VSCLKDIS));
85609c1c 929
5cfb19ac 930 value = __raw_readl(DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c 931 value &= ~VDD3P3V_VID_MASK;
5cfb19ac 932 __raw_writel(value, DAVINCI_SYSMOD_VIRT(SYSMOD_VDD3P3VPWDN));
85609c1c
MK		 933
934 davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
935 davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
936 davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
937 davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
938
939 vpif_display_dev.dev.platform_data = display_config;
940 vpif_capture_dev.dev.platform_data = capture_config;
941 platform_device_register(&vpif_dev);
942 platform_device_register(&vpif_display_dev);
943 platform_device_register(&vpif_capture_dev);
944}
945
cce3dddb
RS		 946int __init dm646x_init_edma(struct edma_rsv_info *rsv)
947{
7ab388e8
PU		 948 struct platform_device *edma_pdev;
949
d4cb7f40 950 dm646x_edma_pdata.rsv = rsv;
cce3dddb 951
7ab388e8
PU		 952 edma_pdev = platform_device_register_full(&dm646x_edma_device);
953 return IS_ERR(edma_pdev) ? PTR_ERR(edma_pdev) : 0;
cce3dddb
RS		 954}
955
e38d92fd
KH		 956void __init dm646x_init(void)
957{
79c3c0b7 958 davinci_common_init(&davinci_soc_info_dm646x);
5cfb19ac 959 davinci_map_sysmod();
6fc9ebbd 960 davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
e38d92fd
KH		 961}
962
963static int __init dm646x_init_devices(void)
964{
1233090c
SN		 965 int ret = 0;
966
e38d92fd
KH		 967 if (!cpu_is_davinci_dm646x())
968 return 0;
969
d22960c8 970 platform_device_register(&dm646x_mdio_device);
972412b6 971 platform_device_register(&dm646x_emac_device);
d22960c8 972
1233090c
SN		 973 ret = davinci_init_wdt();
974 if (ret)
975 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
976
977 return ret;
e38d92fd
KH		 978}
979postcore_initcall(dm646x_init_devices);
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