[mirror_ubuntu-bionic-kernel.git] / arch / x86 / include / asm / intel-family.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef _ASM_X86_INTEL_FAMILY_H
#define _ASM_X86_INTEL_FAMILY_H

/*
 * "Big Core" Processors (Branded as Core, Xeon, etc...)
 *
 * The "_X" parts are generally the EP and EX Xeons, or the
 * "Extreme" ones, like Broadwell-E.
 *
 * While adding a new CPUID for a new microarchitecture, add a new
 * group to keep logically sorted out in chronological order. Within
 * that group keep the CPUID for the variants sorted by model number.
 */

#define INTEL_FAM6_CORE_YONAH		0x0E

#define INTEL_FAM6_CORE2_MEROM		0x0F
#define INTEL_FAM6_CORE2_MEROM_L	0x16
#define INTEL_FAM6_CORE2_PENRYN		0x17
#define INTEL_FAM6_CORE2_DUNNINGTON	0x1D

#define INTEL_FAM6_NEHALEM		0x1E
#define INTEL_FAM6_NEHALEM_G		0x1F /* Auburndale / Havendale */
#define INTEL_FAM6_NEHALEM_EP		0x1A
#define INTEL_FAM6_NEHALEM_EX		0x2E

#define INTEL_FAM6_WESTMERE		0x25
#define INTEL_FAM6_WESTMERE_EP		0x2C
#define INTEL_FAM6_WESTMERE_EX		0x2F

#define INTEL_FAM6_SANDYBRIDGE		0x2A
#define INTEL_FAM6_SANDYBRIDGE_X	0x2D
#define INTEL_FAM6_IVYBRIDGE		0x3A
#define INTEL_FAM6_IVYBRIDGE_X		0x3E

#define INTEL_FAM6_HASWELL_CORE		0x3C
#define INTEL_FAM6_HASWELL_X		0x3F
#define INTEL_FAM6_HASWELL_ULT		0x45
#define INTEL_FAM6_HASWELL_GT3E		0x46

#define INTEL_FAM6_BROADWELL_CORE	0x3D
#define INTEL_FAM6_BROADWELL_GT3E	0x47
#define INTEL_FAM6_BROADWELL_X		0x4F
#define INTEL_FAM6_BROADWELL_XEON_D	0x56

#define INTEL_FAM6_SKYLAKE_MOBILE	0x4E
#define INTEL_FAM6_SKYLAKE_DESKTOP	0x5E
#define INTEL_FAM6_SKYLAKE_X		0x55
#define INTEL_FAM6_KABYLAKE_MOBILE	0x8E
#define INTEL_FAM6_KABYLAKE_DESKTOP	0x9E

#define INTEL_FAM6_CANNONLAKE_MOBILE	0x66

/* "Small Core" Processors (Atom) */

#define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
#define INTEL_FAM6_ATOM_BONNELL_MID	0x26 /* Silverthorne, Lincroft */

#define INTEL_FAM6_ATOM_SALTWELL	0x36 /* Cedarview */
#define INTEL_FAM6_ATOM_SALTWELL_MID	0x27 /* Penwell */
#define INTEL_FAM6_ATOM_SALTWELL_TABLET	0x35 /* Cloverview */

#define INTEL_FAM6_ATOM_SILVERMONT	0x37 /* Bay Trail, Valleyview */
#define INTEL_FAM6_ATOM_SILVERMONT_X	0x4D /* Avaton, Rangely */
#define INTEL_FAM6_ATOM_SILVERMONT_MID	0x4A /* Merriefield */

#define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
#define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */

#define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
#define INTEL_FAM6_ATOM_GOLDMONT_X	0x5F /* Denverton */
#define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */

/* Xeon Phi */

#define INTEL_FAM6_XEON_PHI_KNL		0x57 /* Knights Landing */
#define INTEL_FAM6_XEON_PHI_KNM		0x85 /* Knights Mill */

#endif /* _ASM_X86_INTEL_FAMILY_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
970442c5 DH	2	#ifndef _ASM_X86_INTEL_FAMILY_H
	3	#define _ASM_X86_INTEL_FAMILY_H
	4
	5	/*
	6	* "Big Core" Processors (Branded as Core, Xeon, etc...)
	7	*
	8	* The "_X" parts are generally the EP and EX Xeons, or the
	9	* "Extreme" ones, like Broadwell-E.
	10	*
48729a1c RB	11	* While adding a new CPUID for a new microarchitecture, add a new
	12	* group to keep logically sorted out in chronological order. Within
	13	* that group keep the CPUID for the variants sorted by model number.
970442c5 DH	14	*/
	15
	16	#define INTEL_FAM6_CORE_YONAH 0x0E
c238f234	17
970442c5 DH	18	#define INTEL_FAM6_CORE2_MEROM 0x0F
	19	#define INTEL_FAM6_CORE2_MEROM_L 0x16
	20	#define INTEL_FAM6_CORE2_PENRYN 0x17
	21	#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
	22
	23	#define INTEL_FAM6_NEHALEM 0x1E
4b3b234f	24	#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
970442c5 DH	25	#define INTEL_FAM6_NEHALEM_EP 0x1A
970442c5 DH	26	#define INTEL_FAM6_NEHALEM_EX 0x2E
c238f234	27
970442c5	28	#define INTEL_FAM6_WESTMERE 0x25
970442c5 DH	29	#define INTEL_FAM6_WESTMERE_EP 0x2C
	30	#define INTEL_FAM6_WESTMERE_EX 0x2F
	31
	32	#define INTEL_FAM6_SANDYBRIDGE 0x2A
	33	#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
	34	#define INTEL_FAM6_IVYBRIDGE 0x3A
	35	#define INTEL_FAM6_IVYBRIDGE_X 0x3E
	36
	37	#define INTEL_FAM6_HASWELL_CORE 0x3C
	38	#define INTEL_FAM6_HASWELL_X 0x3F
	39	#define INTEL_FAM6_HASWELL_ULT 0x45
	40	#define INTEL_FAM6_HASWELL_GT3E 0x46
	41
	42	#define INTEL_FAM6_BROADWELL_CORE 0x3D
970442c5 DH	43	#define INTEL_FAM6_BROADWELL_GT3E 0x47
970442c5 DH	44	#define INTEL_FAM6_BROADWELL_X 0x4F
c238f234	45	#define INTEL_FAM6_BROADWELL_XEON_D 0x56
970442c5 DH	46
	47	#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
	48	#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
	49	#define INTEL_FAM6_SKYLAKE_X 0x55
	50	#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
	51	#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
	52
48729a1c RB	53	#define INTEL_FAM6_CANNONLAKE_MOBILE 0x66
48729a1c RB	54
970442c5 DH	55	/* "Small Core" Processors (Atom) */
970442c5 DH	56
2811e5d5 PZ	57	#define INTEL_FAM6_ATOM_BONNELL 0x1C /* Diamondville, Pineview */
	58	#define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
	59
	60	#define INTEL_FAM6_ATOM_SALTWELL 0x36 /* Cedarview */
	61	#define INTEL_FAM6_ATOM_SALTWELL_MID 0x27 /* Penwell */
	62	#define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
	63
	64	#define INTEL_FAM6_ATOM_SILVERMONT 0x37 /* Bay Trail, Valleyview */
	65	#define INTEL_FAM6_ATOM_SILVERMONT_X 0x4D /* Avaton, Rangely */
	66	#define INTEL_FAM6_ATOM_SILVERMONT_MID 0x4A /* Merriefield */
	67
	68	#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* Cherry Trail, Braswell */
	69	#define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
	70
	71	#define INTEL_FAM6_ATOM_GOLDMONT 0x5C /* Apollo Lake */
	72	#define INTEL_FAM6_ATOM_GOLDMONT_X 0x5F /* Denverton */
	73	#define INTEL_FAM6_ATOM_GOLDMONT_PLUS 0x7A /* Gemini Lake */
970442c5 DH	74
	75	/* Xeon Phi */
	76
	77	#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
0047f598	78	#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
970442c5 DH	79
970442c5 DH	80	#endif /* _ASM_X86_INTEL_FAMILY_H */