[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / amd_iommu_init.c

/*
 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
 * Author: Joerg Roedel <joerg.roedel@amd.com>
 *         Leo Duran <leo.duran@amd.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 */

#include <linux/pci.h>
#include <linux/acpi.h>
#include <linux/gfp.h>
#include <linux/list.h>
#include <asm/pci-direct.h>
#include <asm/amd_iommu_types.h>
#include <asm/gart.h>

/*
 * definitions for the ACPI scanning code
 */
#define UPDATE_LAST_BDF(x) do {\
	if ((x) > amd_iommu_last_bdf) \
		amd_iommu_last_bdf = (x); \
	} while (0);

#define DEVID(bus, devfn) (((bus) << 8) | (devfn))
#define PCI_BUS(x) (((x) >> 8) & 0xff)
#define IVRS_HEADER_LENGTH 48
#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))

#define ACPI_IVHD_TYPE                  0x10
#define ACPI_IVMD_TYPE_ALL              0x20
#define ACPI_IVMD_TYPE                  0x21
#define ACPI_IVMD_TYPE_RANGE            0x22

#define IVHD_DEV_ALL                    0x01
#define IVHD_DEV_SELECT                 0x02
#define IVHD_DEV_SELECT_RANGE_START     0x03
#define IVHD_DEV_RANGE_END              0x04
#define IVHD_DEV_ALIAS                  0x42
#define IVHD_DEV_ALIAS_RANGE            0x43
#define IVHD_DEV_EXT_SELECT             0x46
#define IVHD_DEV_EXT_SELECT_RANGE       0x47

#define IVHD_FLAG_HT_TUN_EN             0x00
#define IVHD_FLAG_PASSPW_EN             0x01
#define IVHD_FLAG_RESPASSPW_EN          0x02
#define IVHD_FLAG_ISOC_EN               0x03

#define IVMD_FLAG_EXCL_RANGE            0x08
#define IVMD_FLAG_UNITY_MAP             0x01

#define ACPI_DEVFLAG_INITPASS           0x01
#define ACPI_DEVFLAG_EXTINT             0x02
#define ACPI_DEVFLAG_NMI                0x04
#define ACPI_DEVFLAG_SYSMGT1            0x10
#define ACPI_DEVFLAG_SYSMGT2            0x20
#define ACPI_DEVFLAG_LINT0              0x40
#define ACPI_DEVFLAG_LINT1              0x80
#define ACPI_DEVFLAG_ATSDIS             0x10000000

struct ivhd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 cap_ptr;
	u64 mmio_phys;
	u16 pci_seg;
	u16 info;
	u32 reserved;
} __attribute__((packed));

struct ivhd_entry {
	u8 type;
	u16 devid;
	u8 flags;
	u32 ext;
} __attribute__((packed));

struct ivmd_header {
	u8 type;
	u8 flags;
	u16 length;
	u16 devid;
	u16 aux;
	u64 resv;
	u64 range_start;
	u64 range_length;
} __attribute__((packed));

static int __initdata amd_iommu_disable;

u16 amd_iommu_last_bdf;
struct list_head amd_iommu_unity_map;
unsigned amd_iommu_aperture_order = 26;
int amd_iommu_isolate;

struct list_head amd_iommu_list;
struct dev_table_entry *amd_iommu_dev_table;
u16 *amd_iommu_alias_table;
struct amd_iommu **amd_iommu_rlookup_table;
struct protection_domain **amd_iommu_pd_table;
unsigned long *amd_iommu_pd_alloc_bitmap;

static u32 dev_table_size;
static u32 alias_table_size;
static u32 rlookup_table_size;

static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
{
	u64 start = iommu->exclusion_start & PAGE_MASK;
	u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
	u64 entry;

	if (!iommu->exclusion_start)
		return;

	entry = start | MMIO_EXCL_ENABLE_MASK;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
			&entry, sizeof(entry));

	entry = limit;
	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
			&entry, sizeof(entry));
}

static void __init iommu_set_device_table(struct amd_iommu *iommu)
{
	u32 entry;

	BUG_ON(iommu->mmio_base == NULL);

	entry = virt_to_phys(amd_iommu_dev_table);
	entry |= (dev_table_size >> 12) - 1;
	memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
			&entry, sizeof(entry));
}

static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
{
	u32 ctrl;

	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	ctrl |= (1 << bit);
	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
{
	u32 ctrl;

	ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	ctrl &= ~(1 << bit);
	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

void __init iommu_enable(struct amd_iommu *iommu)
{
	u32 ctrl;

	printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
	print_devid(iommu->devid, 0);
	printk(" cap 0x%hx\n", iommu->cap_ptr);

	iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
}

static u8 * __init iommu_map_mmio_space(u64 address)
{
	u8 *ret;

	if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
		return NULL;

	ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
	if (ret != NULL)
		return ret;

	release_mem_region(address, MMIO_REGION_LENGTH);

	return NULL;
}

static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
{
	if (iommu->mmio_base)
		iounmap(iommu->mmio_base);
	release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
}

static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
{
	u32 cap;

	cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));

	return 0;
}

static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
{
	u8 *p = (void *)h, *end = (void *)h;
	struct ivhd_entry *dev;

	p += sizeof(*h);
	end += h->length;

	find_last_devid_on_pci(PCI_BUS(h->devid),
			PCI_SLOT(h->devid),
			PCI_FUNC(h->devid),
			h->cap_ptr);

	while (p < end) {
		dev = (struct ivhd_entry *)p;
		switch (dev->type) {
		case IVHD_DEV_SELECT:
		case IVHD_DEV_RANGE_END:
		case IVHD_DEV_ALIAS:
		case IVHD_DEV_EXT_SELECT:
			UPDATE_LAST_BDF(dev->devid);
			break;
		default:
			break;
		}
		p += 0x04 << (*p >> 6);
	}

	WARN_ON(p != end);

	return 0;
}

static int __init find_last_devid_acpi(struct acpi_table_header *table)
{
	int i;
	u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
	struct ivhd_header *h;

	/*
	 * Validate checksum here so we don't need to do it when
	 * we actually parse the table
	 */
	for (i = 0; i < table->length; ++i)
		checksum += p[i];
	if (checksum != 0)
		/* ACPI table corrupt */
		return -ENODEV;

	p += IVRS_HEADER_LENGTH;

	end += table->length;
	while (p < end) {
		h = (struct ivhd_header *)p;
		switch (h->type) {
		case ACPI_IVHD_TYPE:
			find_last_devid_from_ivhd(h);
			break;
		default:
			break;
		}
		p += h->length;
	}
	WARN_ON(p != end);

	return 0;
}

static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
{
	u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL,
			get_order(CMD_BUFFER_SIZE));
	u64 entry = 0;

	if (cmd_buf == NULL)
		return NULL;

	iommu->cmd_buf_size = CMD_BUFFER_SIZE;

	memset(cmd_buf, 0, CMD_BUFFER_SIZE);

	entry = (u64)virt_to_phys(cmd_buf);
	entry |= MMIO_CMD_SIZE_512;
	memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
			&entry, sizeof(entry));

	iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);

	return cmd_buf;
}

static void __init free_command_buffer(struct amd_iommu *iommu)
{
	if (iommu->cmd_buf)
		free_pages((unsigned long)iommu->cmd_buf,
				get_order(CMD_BUFFER_SIZE));
}

static void set_dev_entry_bit(u16 devid, u8 bit)
{
	int i = (bit >> 5) & 0x07;
	int _bit = bit & 0x1f;

	amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
}

static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
{
	if (flags & ACPI_DEVFLAG_INITPASS)
		set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
	if (flags & ACPI_DEVFLAG_EXTINT)
		set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
	if (flags & ACPI_DEVFLAG_NMI)
		set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
	if (flags & ACPI_DEVFLAG_SYSMGT1)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
	if (flags & ACPI_DEVFLAG_SYSMGT2)
		set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
	if (flags & ACPI_DEVFLAG_LINT0)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
	if (flags & ACPI_DEVFLAG_LINT1)
		set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
}

static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
{
	amd_iommu_rlookup_table[devid] = iommu;
}

static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
{
	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];

	if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
		return;

	if (iommu) {
		set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
		iommu->exclusion_start = m->range_start;
		iommu->exclusion_length = m->range_length;
	}
}

static void __init init_iommu_from_pci(struct amd_iommu *iommu)
{
	int bus = PCI_BUS(iommu->devid);
	int dev = PCI_SLOT(iommu->devid);
	int fn  = PCI_FUNC(iommu->devid);
	int cap_ptr = iommu->cap_ptr;
	u32 range;

	iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);

	range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
	iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
}

static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
					struct ivhd_header *h)
{
	u8 *p = (u8 *)h;
	u8 *end = p, flags = 0;
	u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
	u32 ext_flags = 0;
	bool alias = 0;
	struct ivhd_entry *e;

	/*
	 * First set the recommended feature enable bits from ACPI
	 * into the IOMMU control registers
	 */
	h->flags & IVHD_FLAG_HT_TUN_EN ?
		iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
		iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);

	h->flags & IVHD_FLAG_PASSPW_EN ?
		iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
		iommu_feature_disable(iommu, CONTROL_PASSPW_EN);

	h->flags & IVHD_FLAG_RESPASSPW_EN ?
		iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
		iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);

	h->flags & IVHD_FLAG_ISOC_EN ?
		iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
		iommu_feature_disable(iommu, CONTROL_ISOC_EN);

	/*
	 * make IOMMU memory accesses cache coherent
	 */
	iommu_feature_enable(iommu, CONTROL_COHERENT_EN);

	/*
	 * Done. Now parse the device entries
	 */
	p += sizeof(struct ivhd_header);
	end += h->length;

	while (p < end) {
		e = (struct ivhd_entry *)p;
		switch (e->type) {
		case IVHD_DEV_ALL:
			for (dev_i = iommu->first_device;
					dev_i <= iommu->last_device; ++dev_i)
				set_dev_entry_from_acpi(dev_i, e->flags, 0);
			break;
		case IVHD_DEV_SELECT:
			devid = e->devid;
			set_dev_entry_from_acpi(devid, e->flags, 0);
			break;
		case IVHD_DEV_SELECT_RANGE_START:
			devid_start = e->devid;
			flags = e->flags;
			ext_flags = 0;
			alias = 0;
			break;
		case IVHD_DEV_ALIAS:
			devid = e->devid;
			devid_to = e->ext >> 8;
			set_dev_entry_from_acpi(devid, e->flags, 0);
			amd_iommu_alias_table[devid] = devid_to;
			break;
		case IVHD_DEV_ALIAS_RANGE:
			devid_start = e->devid;
			flags = e->flags;
			devid_to = e->ext >> 8;
			ext_flags = 0;
			alias = 1;
			break;
		case IVHD_DEV_EXT_SELECT:
			devid = e->devid;
			set_dev_entry_from_acpi(devid, e->flags, e->ext);
			break;
		case IVHD_DEV_EXT_SELECT_RANGE:
			devid_start = e->devid;
			flags = e->flags;
			ext_flags = e->ext;
			alias = 0;
			break;
		case IVHD_DEV_RANGE_END:
			devid = e->devid;
			for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
				if (alias)
					amd_iommu_alias_table[dev_i] = devid_to;
				set_dev_entry_from_acpi(
						amd_iommu_alias_table[dev_i],
						flags, ext_flags);
			}
			break;
		default:
			break;
		}

		p += 0x04 << (e->type >> 6);
	}
}

static int __init init_iommu_devices(struct amd_iommu *iommu)
{
	u16 i;

	for (i = iommu->first_device; i <= iommu->last_device; ++i)
		set_iommu_for_device(iommu, i);

	return 0;
}

static void __init free_iommu_one(struct amd_iommu *iommu)
{
	free_command_buffer(iommu);
	iommu_unmap_mmio_space(iommu);
}

static void __init free_iommu_all(void)
{
	struct amd_iommu *iommu, *next;

	list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
		list_del(&iommu->list);
		free_iommu_one(iommu);
		kfree(iommu);
	}
}

static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
{
	spin_lock_init(&iommu->lock);
	list_add_tail(&iommu->list, &amd_iommu_list);

	/*
	 * Copy data from ACPI table entry to the iommu struct
	 */
	iommu->devid = h->devid;
	iommu->cap_ptr = h->cap_ptr;
	iommu->mmio_phys = h->mmio_phys;
	iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
	if (!iommu->mmio_base)
		return -ENOMEM;

	iommu_set_device_table(iommu);
	iommu->cmd_buf = alloc_command_buffer(iommu);
	if (!iommu->cmd_buf)
		return -ENOMEM;

	init_iommu_from_pci(iommu);
	init_iommu_from_acpi(iommu, h);
	init_iommu_devices(iommu);

	return 0;
}

static int __init init_iommu_all(struct acpi_table_header *table)
{
	u8 *p = (u8 *)table, *end = (u8 *)table;
	struct ivhd_header *h;
	struct amd_iommu *iommu;
	int ret;

	INIT_LIST_HEAD(&amd_iommu_list);

	end += table->length;
	p += IVRS_HEADER_LENGTH;

	while (p < end) {
		h = (struct ivhd_header *)p;
		switch (*p) {
		case ACPI_IVHD_TYPE:
			iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
			if (iommu == NULL)
				return -ENOMEM;
			ret = init_iommu_one(iommu, h);
			if (ret)
				return ret;
			break;
		default:
			break;
		}
		p += h->length;

	}
	WARN_ON(p != end);

	return 0;
}

static void __init free_unity_maps(void)
{
	struct unity_map_entry *entry, *next;

	list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
		list_del(&entry->list);
		kfree(entry);
	}
}

static int __init init_exclusion_range(struct ivmd_header *m)
{
	int i;

	switch (m->type) {
	case ACPI_IVMD_TYPE:
		set_device_exclusion_range(m->devid, m);
		break;
	case ACPI_IVMD_TYPE_ALL:
		for (i = 0; i < amd_iommu_last_bdf; ++i)
			set_device_exclusion_range(i, m);
		break;
	case ACPI_IVMD_TYPE_RANGE:
		for (i = m->devid; i <= m->aux; ++i)
			set_device_exclusion_range(i, m);
		break;
	default:
		break;
	}

	return 0;
}

static int __init init_unity_map_range(struct ivmd_header *m)
{
	struct unity_map_entry *e = 0;

	e = kzalloc(sizeof(*e), GFP_KERNEL);
	if (e == NULL)
		return -ENOMEM;

	switch (m->type) {
	default:
	case ACPI_IVMD_TYPE:
		e->devid_start = e->devid_end = m->devid;
		break;
	case ACPI_IVMD_TYPE_ALL:
		e->devid_start = 0;
		e->devid_end = amd_iommu_last_bdf;
		break;
	case ACPI_IVMD_TYPE_RANGE:
		e->devid_start = m->devid;
		e->devid_end = m->aux;
		break;
	}
	e->address_start = PAGE_ALIGN(m->range_start);
	e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
	e->prot = m->flags >> 1;

	list_add_tail(&e->list, &amd_iommu_unity_map);

	return 0;
}

static int __init init_memory_definitions(struct acpi_table_header *table)
{
	u8 *p = (u8 *)table, *end = (u8 *)table;
	struct ivmd_header *m;

	INIT_LIST_HEAD(&amd_iommu_unity_map);

	end += table->length;
	p += IVRS_HEADER_LENGTH;

	while (p < end) {
		m = (struct ivmd_header *)p;
		if (m->flags & IVMD_FLAG_EXCL_RANGE)
			init_exclusion_range(m);
		else if (m->flags & IVMD_FLAG_UNITY_MAP)
			init_unity_map_range(m);

		p += m->length;
	}

	return 0;
}
Commit	Line	Data
f6e2e6b6 JR	1	/*
	2	* Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
	3	* Author: Joerg Roedel <joerg.roedel@amd.com>
	4	* Leo Duran <leo.duran@amd.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	*/
	19
	20	#include <linux/pci.h>
	21	#include <linux/acpi.h>
	22	#include <linux/gfp.h>
	23	#include <linux/list.h>
	24	#include <asm/pci-direct.h>
	25	#include <asm/amd_iommu_types.h>
	26	#include <asm/gart.h>
	27
	28	/*
	29	* definitions for the ACPI scanning code
	30	*/
	31	#define UPDATE_LAST_BDF(x) do {\
	32	if ((x) > amd_iommu_last_bdf) \
	33	amd_iommu_last_bdf = (x); \
	34	} while (0);
	35
	36	#define DEVID(bus, devfn) (((bus) << 8) \| (devfn))
	37	#define PCI_BUS(x) (((x) >> 8) & 0xff)
	38	#define IVRS_HEADER_LENGTH 48
	39	#define TBL_SIZE(x) (1 << (PAGE_SHIFT + get_order(amd_iommu_last_bdf * (x))))
	40
	41	#define ACPI_IVHD_TYPE 0x10
	42	#define ACPI_IVMD_TYPE_ALL 0x20
	43	#define ACPI_IVMD_TYPE 0x21
	44	#define ACPI_IVMD_TYPE_RANGE 0x22
	45
	46	#define IVHD_DEV_ALL 0x01
	47	#define IVHD_DEV_SELECT 0x02
	48	#define IVHD_DEV_SELECT_RANGE_START 0x03
	49	#define IVHD_DEV_RANGE_END 0x04
	50	#define IVHD_DEV_ALIAS 0x42
	51	#define IVHD_DEV_ALIAS_RANGE 0x43
	52	#define IVHD_DEV_EXT_SELECT 0x46
	53	#define IVHD_DEV_EXT_SELECT_RANGE 0x47
	54
	55	#define IVHD_FLAG_HT_TUN_EN 0x00
	56	#define IVHD_FLAG_PASSPW_EN 0x01
	57	#define IVHD_FLAG_RESPASSPW_EN 0x02
	58	#define IVHD_FLAG_ISOC_EN 0x03
	59
	60	#define IVMD_FLAG_EXCL_RANGE 0x08
	61	#define IVMD_FLAG_UNITY_MAP 0x01
	62
	63	#define ACPI_DEVFLAG_INITPASS 0x01
	64	#define ACPI_DEVFLAG_EXTINT 0x02
65	#define ACPI_DEVFLAG_NMI 0x04
66	#define ACPI_DEVFLAG_SYSMGT1 0x10
67	#define ACPI_DEVFLAG_SYSMGT2 0x20
68	#define ACPI_DEVFLAG_LINT0 0x40
69	#define ACPI_DEVFLAG_LINT1 0x80
70	#define ACPI_DEVFLAG_ATSDIS 0x10000000
71
72	struct ivhd_header {
73	u8 type;
74	u8 flags;
75	u16 length;
76	u16 devid;
77	u16 cap_ptr;
78	u64 mmio_phys;
79	u16 pci_seg;
80	u16 info;
81	u32 reserved;
82	} __attribute__((packed));
83
84	struct ivhd_entry {
85	u8 type;
86	u16 devid;
87	u8 flags;
88	u32 ext;
89	} __attribute__((packed));
90
91	struct ivmd_header {
92	u8 type;
93	u8 flags;
94	u16 length;
95	u16 devid;
96	u16 aux;
97	u64 resv;
98	u64 range_start;
99	u64 range_length;
100	} __attribute__((packed));
101
928abd25 JR	102	static int __initdata amd_iommu_disable;
	103
	104	u16 amd_iommu_last_bdf;
	105	struct list_head amd_iommu_unity_map;
	106	unsigned amd_iommu_aperture_order = 26;
	107	int amd_iommu_isolate;
	108
	109	struct list_head amd_iommu_list;
	110	struct dev_table_entry *amd_iommu_dev_table;
	111	u16 *amd_iommu_alias_table;
	112	struct amd_iommu **amd_iommu_rlookup_table;
	113	struct protection_domain **amd_iommu_pd_table;
	114	unsigned long *amd_iommu_pd_alloc_bitmap;
	115
	116	static u32 dev_table_size;
	117	static u32 alias_table_size;
	118	static u32 rlookup_table_size;
3e8064ba	119
b2026aa2 JR	120	static void __init iommu_set_exclusion_range(struct amd_iommu *iommu)
	121	{
	122	u64 start = iommu->exclusion_start & PAGE_MASK;
	123	u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
	124	u64 entry;
	125
	126	if (!iommu->exclusion_start)
	127	return;
	128
	129	entry = start \| MMIO_EXCL_ENABLE_MASK;
	130	memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
	131	&entry, sizeof(entry));
	132
	133	entry = limit;
	134	memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
	135	&entry, sizeof(entry));
	136	}
	137
	138	static void __init iommu_set_device_table(struct amd_iommu *iommu)
	139	{
	140	u32 entry;
	141
	142	BUG_ON(iommu->mmio_base == NULL);
	143
	144	entry = virt_to_phys(amd_iommu_dev_table);
	145	entry \|= (dev_table_size >> 12) - 1;
	146	memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
	147	&entry, sizeof(entry));
	148	}
	149
	150	static void __init iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
	151	{
	152	u32 ctrl;
	153
	154	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	155	ctrl \|= (1 << bit);
	156	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
	157	}
	158
	159	static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
	160	{
	161	u32 ctrl;
	162
	163	ctrl = (u64)readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	164	ctrl &= ~(1 << bit);
	165	writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
	166	}
	167
	168	void __init iommu_enable(struct amd_iommu *iommu)
	169	{
	170	u32 ctrl;
	171
	172	printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at ");
	173	print_devid(iommu->devid, 0);
	174	printk(" cap 0x%hx\n", iommu->cap_ptr);
	175
	176	iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
	177	ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
	178	}
	179
6c56747b JR	180	static u8 * __init iommu_map_mmio_space(u64 address)
	181	{
	182	u8 *ret;
	183
	184	if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
	185	return NULL;
	186
	187	ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
	188	if (ret != NULL)
	189	return ret;
	190
	191	release_mem_region(address, MMIO_REGION_LENGTH);
	192
	193	return NULL;
	194	}
	195
	196	static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
	197	{
	198	if (iommu->mmio_base)
	199	iounmap(iommu->mmio_base);
	200	release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
	201	}
	202
3e8064ba JR	203	static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
	204	{
	205	u32 cap;
	206
	207	cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	208	UPDATE_LAST_BDF(DEVID(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
	209
	210	return 0;
	211	}
	212
	213	static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
	214	{
	215	u8 p = (void )h, end = (void )h;
	216	struct ivhd_entry *dev;
	217
	218	p += sizeof(*h);
	219	end += h->length;
	220
	221	find_last_devid_on_pci(PCI_BUS(h->devid),
	222	PCI_SLOT(h->devid),
	223	PCI_FUNC(h->devid),
	224	h->cap_ptr);
	225
	226	while (p < end) {
	227	dev = (struct ivhd_entry *)p;
	228	switch (dev->type) {
	229	case IVHD_DEV_SELECT:
	230	case IVHD_DEV_RANGE_END:
	231	case IVHD_DEV_ALIAS:
	232	case IVHD_DEV_EXT_SELECT:
	233	UPDATE_LAST_BDF(dev->devid);
	234	break;
	235	default:
	236	break;
	237	}
	238	p += 0x04 << (*p >> 6);
	239	}
	240
	241	WARN_ON(p != end);
	242
	243	return 0;
	244	}
	245
	246	static int __init find_last_devid_acpi(struct acpi_table_header *table)
	247	{
	248	int i;
	249	u8 checksum = 0, p = (u8 )table, end = (u8 )table;
	250	struct ivhd_header *h;
	251
	252	/*
	253	* Validate checksum here so we don't need to do it when
	254	* we actually parse the table
	255	*/
	256	for (i = 0; i < table->length; ++i)
	257	checksum += p[i];
	258	if (checksum != 0)
	259	/* ACPI table corrupt */
	260	return -ENODEV;
	261
	262	p += IVRS_HEADER_LENGTH;
	263
	264	end += table->length;
	265	while (p < end) {
	266	h = (struct ivhd_header *)p;
267	switch (h->type) {
268	case ACPI_IVHD_TYPE:
269	find_last_devid_from_ivhd(h);
270	break;
271	default:
272	break;
273	}
274	p += h->length;
275	}
276	WARN_ON(p != end);
277
278	return 0;
279	}
280
b36ca91e JR	281	static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
	282	{
	283	u8 cmd_buf = (u8 )__get_free_pages(GFP_KERNEL,
	284	get_order(CMD_BUFFER_SIZE));
	285	u64 entry = 0;
	286
	287	if (cmd_buf == NULL)
	288	return NULL;
	289
	290	iommu->cmd_buf_size = CMD_BUFFER_SIZE;
	291
	292	memset(cmd_buf, 0, CMD_BUFFER_SIZE);
	293
	294	entry = (u64)virt_to_phys(cmd_buf);
	295	entry \|= MMIO_CMD_SIZE_512;
	296	memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
	297	&entry, sizeof(entry));
	298
	299	iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
	300
	301	return cmd_buf;
	302	}
	303
	304	static void __init free_command_buffer(struct amd_iommu *iommu)
	305	{
	306	if (iommu->cmd_buf)
	307	free_pages((unsigned long)iommu->cmd_buf,
	308	get_order(CMD_BUFFER_SIZE));
	309	}
	310
3566b778 JR	311	static void set_dev_entry_bit(u16 devid, u8 bit)
	312	{
	313	int i = (bit >> 5) & 0x07;
	314	int _bit = bit & 0x1f;
	315
	316	amd_iommu_dev_table[devid].data[i] \|= (1 << _bit);
	317	}
	318
	319	static void __init set_dev_entry_from_acpi(u16 devid, u32 flags, u32 ext_flags)
	320	{
	321	if (flags & ACPI_DEVFLAG_INITPASS)
	322	set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
	323	if (flags & ACPI_DEVFLAG_EXTINT)
	324	set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
	325	if (flags & ACPI_DEVFLAG_NMI)
	326	set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
	327	if (flags & ACPI_DEVFLAG_SYSMGT1)
	328	set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
	329	if (flags & ACPI_DEVFLAG_SYSMGT2)
	330	set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
	331	if (flags & ACPI_DEVFLAG_LINT0)
	332	set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
	333	if (flags & ACPI_DEVFLAG_LINT1)
	334	set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
	335	}
	336
	337	static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
	338	{
	339	amd_iommu_rlookup_table[devid] = iommu;
	340	}
	341
	342	static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
	343	{
	344	struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
	345
	346	if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
	347	return;
	348
	349	if (iommu) {
	350	set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
	351	iommu->exclusion_start = m->range_start;
	352	iommu->exclusion_length = m->range_length;
	353	}
	354	}
	355
5d0c8e49 JR	356	static void __init init_iommu_from_pci(struct amd_iommu *iommu)
	357	{
	358	int bus = PCI_BUS(iommu->devid);
	359	int dev = PCI_SLOT(iommu->devid);
	360	int fn = PCI_FUNC(iommu->devid);
	361	int cap_ptr = iommu->cap_ptr;
	362	u32 range;
	363
	364	iommu->cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_CAP_HDR_OFFSET);
	365
	366	range = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
	367	iommu->first_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_FD(range));
	368	iommu->last_device = DEVID(MMIO_GET_BUS(range), MMIO_GET_LD(range));
	369	}
	370
	371	static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
	372	struct ivhd_header *h)
	373	{
	374	u8 p = (u8 )h;
	375	u8 *end = p, flags = 0;
	376	u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
	377	u32 ext_flags = 0;
	378	bool alias = 0;
	379	struct ivhd_entry *e;
	380
	381	/*
	382	* First set the recommended feature enable bits from ACPI
	383	* into the IOMMU control registers
	384	*/
	385	h->flags & IVHD_FLAG_HT_TUN_EN ?
	386	iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
	387	iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
	388
	389	h->flags & IVHD_FLAG_PASSPW_EN ?
	390	iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
	391	iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
	392
	393	h->flags & IVHD_FLAG_RESPASSPW_EN ?
	394	iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
	395	iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
	396
	397	h->flags & IVHD_FLAG_ISOC_EN ?
	398	iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
	399	iommu_feature_disable(iommu, CONTROL_ISOC_EN);
	400
	401	/*
	402	* make IOMMU memory accesses cache coherent
	403	*/
	404	iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
	405
	406	/*
	407	* Done. Now parse the device entries
	408	*/
	409	p += sizeof(struct ivhd_header);
	410	end += h->length;
	411
	412	while (p < end) {
	413	e = (struct ivhd_entry *)p;
	414	switch (e->type) {
	415	case IVHD_DEV_ALL:
	416	for (dev_i = iommu->first_device;
	417	dev_i <= iommu->last_device; ++dev_i)
	418	set_dev_entry_from_acpi(dev_i, e->flags, 0);
	419	break;
420	case IVHD_DEV_SELECT:
421	devid = e->devid;
422	set_dev_entry_from_acpi(devid, e->flags, 0);
423	break;
424	case IVHD_DEV_SELECT_RANGE_START:
425	devid_start = e->devid;
426	flags = e->flags;
427	ext_flags = 0;
428	alias = 0;
429	break;
430	case IVHD_DEV_ALIAS:
431	devid = e->devid;
432	devid_to = e->ext >> 8;
433	set_dev_entry_from_acpi(devid, e->flags, 0);
434	amd_iommu_alias_table[devid] = devid_to;
435	break;
436	case IVHD_DEV_ALIAS_RANGE:
437	devid_start = e->devid;
438	flags = e->flags;
439	devid_to = e->ext >> 8;
440	ext_flags = 0;
441	alias = 1;
442	break;
443	case IVHD_DEV_EXT_SELECT:
444	devid = e->devid;
445	set_dev_entry_from_acpi(devid, e->flags, e->ext);
446	break;
447	case IVHD_DEV_EXT_SELECT_RANGE:
448	devid_start = e->devid;
449	flags = e->flags;
450	ext_flags = e->ext;
451	alias = 0;
452	break;
453	case IVHD_DEV_RANGE_END:
454	devid = e->devid;
455	for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
456	if (alias)
457	amd_iommu_alias_table[dev_i] = devid_to;
458	set_dev_entry_from_acpi(
459	amd_iommu_alias_table[dev_i],
460	flags, ext_flags);
461	}
462	break;
463	default:
464	break;
465	}
466
467	p += 0x04 << (e->type >> 6);
468	}
469	}
470
471	static int __init init_iommu_devices(struct amd_iommu *iommu)
472	{
473	u16 i;
474
475	for (i = iommu->first_device; i <= iommu->last_device; ++i)
476	set_iommu_for_device(iommu, i);
477
478	return 0;
479	}
480
e47d402d JR	481	static void __init free_iommu_one(struct amd_iommu *iommu)
	482	{
	483	free_command_buffer(iommu);
	484	iommu_unmap_mmio_space(iommu);
	485	}
	486
	487	static void __init free_iommu_all(void)
	488	{
	489	struct amd_iommu iommu, next;
	490
	491	list_for_each_entry_safe(iommu, next, &amd_iommu_list, list) {
	492	list_del(&iommu->list);
	493	free_iommu_one(iommu);
	494	kfree(iommu);
	495	}
	496	}
	497
	498	static int __init init_iommu_one(struct amd_iommu iommu, struct ivhd_header h)
	499	{
	500	spin_lock_init(&iommu->lock);
	501	list_add_tail(&iommu->list, &amd_iommu_list);
	502
	503	/*
	504	* Copy data from ACPI table entry to the iommu struct
	505	*/
	506	iommu->devid = h->devid;
	507	iommu->cap_ptr = h->cap_ptr;
	508	iommu->mmio_phys = h->mmio_phys;
	509	iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
	510	if (!iommu->mmio_base)
	511	return -ENOMEM;
	512
	513	iommu_set_device_table(iommu);
	514	iommu->cmd_buf = alloc_command_buffer(iommu);
	515	if (!iommu->cmd_buf)
	516	return -ENOMEM;
	517
	518	init_iommu_from_pci(iommu);
	519	init_iommu_from_acpi(iommu, h);
	520	init_iommu_devices(iommu);
	521
	522	return 0;
	523	}
	524
	525	static int __init init_iommu_all(struct acpi_table_header *table)
	526	{
	527	u8 p = (u8 )table, end = (u8 )table;
	528	struct ivhd_header *h;
	529	struct amd_iommu *iommu;
	530	int ret;
	531
	532	INIT_LIST_HEAD(&amd_iommu_list);
	533
	534	end += table->length;
	535	p += IVRS_HEADER_LENGTH;
	536
	537	while (p < end) {
	538	h = (struct ivhd_header *)p;
	539	switch (*p) {
	540	case ACPI_IVHD_TYPE:
	541	iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
	542	if (iommu == NULL)
	543	return -ENOMEM;
	544	ret = init_iommu_one(iommu, h);
545	if (ret)
546	return ret;
547	break;
548	default:
549	break;
550	}
551	p += h->length;
552
553	}
554	WARN_ON(p != end);
555
556	return 0;
557	}
558
be2a022c JR	559	static void __init free_unity_maps(void)
	560	{
	561	struct unity_map_entry entry, next;
	562
	563	list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
	564	list_del(&entry->list);
	565	kfree(entry);
	566	}
	567	}
	568
	569	static int __init init_exclusion_range(struct ivmd_header *m)
	570	{
	571	int i;
	572
	573	switch (m->type) {
	574	case ACPI_IVMD_TYPE:
	575	set_device_exclusion_range(m->devid, m);
	576	break;
	577	case ACPI_IVMD_TYPE_ALL:
	578	for (i = 0; i < amd_iommu_last_bdf; ++i)
	579	set_device_exclusion_range(i, m);
	580	break;
	581	case ACPI_IVMD_TYPE_RANGE:
	582	for (i = m->devid; i <= m->aux; ++i)
	583	set_device_exclusion_range(i, m);
	584	break;
	585	default:
	586	break;
	587	}
	588
	589	return 0;
	590	}
	591
	592	static int __init init_unity_map_range(struct ivmd_header *m)
	593	{
	594	struct unity_map_entry *e = 0;
	595
	596	e = kzalloc(sizeof(*e), GFP_KERNEL);
	597	if (e == NULL)
	598	return -ENOMEM;
	599
	600	switch (m->type) {
	601	default:
	602	case ACPI_IVMD_TYPE:
	603	e->devid_start = e->devid_end = m->devid;
	604	break;
	605	case ACPI_IVMD_TYPE_ALL:
	606	e->devid_start = 0;
	607	e->devid_end = amd_iommu_last_bdf;
	608	break;
	609	case ACPI_IVMD_TYPE_RANGE:
	610	e->devid_start = m->devid;
	611	e->devid_end = m->aux;
	612	break;
	613	}
	614	e->address_start = PAGE_ALIGN(m->range_start);
	615	e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
	616	e->prot = m->flags >> 1;
	617
	618	list_add_tail(&e->list, &amd_iommu_unity_map);
	619
	620	return 0;
	621	}
	622
623	static int __init init_memory_definitions(struct acpi_table_header *table)
624	{
625	u8 p = (u8 )table, end = (u8 )table;
626	struct ivmd_header *m;
627
628	INIT_LIST_HEAD(&amd_iommu_unity_map);
629
630	end += table->length;
631	p += IVRS_HEADER_LENGTH;
632
633	while (p < end) {
634	m = (struct ivmd_header *)p;
635	if (m->flags & IVMD_FLAG_EXCL_RANGE)
636	init_exclusion_range(m);
637	else if (m->flags & IVMD_FLAG_UNITY_MAP)
638	init_unity_map_range(m);
639
640	p += m->length;
641	}
642
643	return 0;
644	}
645