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44380982 JL |
1 | /* |
2 | * Support of MSI, HPET and DMAR interrupts. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo | |
5 | * Moved from arch/x86/kernel/apic/io_apic.c. | |
52f518a3 JL |
6 | * Jiang Liu <jiang.liu@linux.intel.com> |
7 | * Convert to hierarchical irqdomain | |
44380982 JL |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/mm.h> | |
14 | #include <linux/interrupt.h> | |
f901f138 | 15 | #include <linux/irq.h> |
44380982 JL |
16 | #include <linux/pci.h> |
17 | #include <linux/dmar.h> | |
18 | #include <linux/hpet.h> | |
19 | #include <linux/msi.h> | |
d746d1eb | 20 | #include <asm/irqdomain.h> |
44380982 JL |
21 | #include <asm/msidef.h> |
22 | #include <asm/hpet.h> | |
23 | #include <asm/hw_irq.h> | |
24 | #include <asm/apic.h> | |
25 | #include <asm/irq_remapping.h> | |
26 | ||
52f518a3 JL |
27 | static struct irq_domain *msi_default_domain; |
28 | ||
92e06be2 | 29 | static void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg) |
3cb96f0c | 30 | { |
3cb96f0c JL |
31 | msg->address_hi = MSI_ADDR_BASE_HI; |
32 | ||
33 | if (x2apic_enabled()) | |
34 | msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); | |
35 | ||
36 | msg->address_lo = | |
37 | MSI_ADDR_BASE_LO | | |
38 | ((apic->irq_dest_mode == 0) ? | |
39 | MSI_ADDR_DEST_MODE_PHYSICAL : | |
40 | MSI_ADDR_DEST_MODE_LOGICAL) | | |
a31e58e1 | 41 | MSI_ADDR_REDIRECTION_CPU | |
3cb96f0c JL |
42 | MSI_ADDR_DEST_ID(cfg->dest_apicid); |
43 | ||
44 | msg->data = | |
45 | MSI_DATA_TRIGGER_EDGE | | |
46 | MSI_DATA_LEVEL_ASSERT | | |
a31e58e1 | 47 | MSI_DATA_DELIVERY_FIXED | |
3cb96f0c JL |
48 | MSI_DATA_VECTOR(cfg->vector); |
49 | } | |
50 | ||
92e06be2 TG |
51 | static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) |
52 | { | |
53 | __irq_msi_compose_msg(irqd_cfg(data), msg); | |
54 | } | |
55 | ||
56 | static void irq_msi_update_msg(struct irq_data *irqd, struct irq_cfg *cfg) | |
57 | { | |
58 | struct msi_msg msg[2] = { [1] = { }, }; | |
59 | ||
60 | __irq_msi_compose_msg(cfg, msg); | |
61 | irq_data_get_irq_chip(irqd)->irq_write_msi_msg(irqd, msg); | |
62 | } | |
63 | ||
64 | static int | |
65 | msi_set_affinity(struct irq_data *irqd, const struct cpumask *mask, bool force) | |
66 | { | |
67 | struct irq_cfg old_cfg, *cfg = irqd_cfg(irqd); | |
68 | struct irq_data *parent = irqd->parent_data; | |
69 | unsigned int cpu; | |
70 | int ret; | |
71 | ||
72 | /* Save the current configuration */ | |
73 | cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd)); | |
74 | old_cfg = *cfg; | |
75 | ||
76 | /* Allocate a new target vector */ | |
77 | ret = parent->chip->irq_set_affinity(parent, mask, force); | |
78 | if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE) | |
79 | return ret; | |
80 | ||
81 | /* | |
82 | * For non-maskable and non-remapped MSI interrupts the migration | |
83 | * to a different destination CPU and a different vector has to be | |
84 | * done careful to handle the possible stray interrupt which can be | |
85 | * caused by the non-atomic update of the address/data pair. | |
86 | * | |
87 | * Direct update is possible when: | |
88 | * - The MSI is maskable (remapped MSI does not use this code path)). | |
89 | * The quirk bit is not set in this case. | |
90 | * - The new vector is the same as the old vector | |
91 | * - The old vector is MANAGED_IRQ_SHUTDOWN_VECTOR (interrupt starts up) | |
92 | * - The new destination CPU is the same as the old destination CPU | |
93 | */ | |
94 | if (!irqd_msi_nomask_quirk(irqd) || | |
95 | cfg->vector == old_cfg.vector || | |
96 | old_cfg.vector == MANAGED_IRQ_SHUTDOWN_VECTOR || | |
97 | cfg->dest_apicid == old_cfg.dest_apicid) { | |
98 | irq_msi_update_msg(irqd, cfg); | |
99 | return ret; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Paranoia: Validate that the interrupt target is the local | |
104 | * CPU. | |
105 | */ | |
106 | if (WARN_ON_ONCE(cpu != smp_processor_id())) { | |
107 | irq_msi_update_msg(irqd, cfg); | |
108 | return ret; | |
109 | } | |
110 | ||
111 | /* | |
112 | * Redirect the interrupt to the new vector on the current CPU | |
113 | * first. This might cause a spurious interrupt on this vector if | |
114 | * the device raises an interrupt right between this update and the | |
115 | * update to the final destination CPU. | |
116 | * | |
117 | * If the vector is in use then the installed device handler will | |
118 | * denote it as spurious which is no harm as this is a rare event | |
119 | * and interrupt handlers have to cope with spurious interrupts | |
120 | * anyway. If the vector is unused, then it is marked so it won't | |
121 | * trigger the 'No irq handler for vector' warning in do_IRQ(). | |
122 | * | |
123 | * This requires to hold vector lock to prevent concurrent updates to | |
124 | * the affected vector. | |
125 | */ | |
126 | lock_vector_lock(); | |
127 | ||
128 | /* | |
129 | * Mark the new target vector on the local CPU if it is currently | |
130 | * unused. Reuse the VECTOR_RETRIGGERED state which is also used in | |
131 | * the CPU hotplug path for a similar purpose. This cannot be | |
132 | * undone here as the current CPU has interrupts disabled and | |
133 | * cannot handle the interrupt before the whole set_affinity() | |
134 | * section is done. In the CPU unplug case, the current CPU is | |
135 | * about to vanish and will not handle any interrupts anymore. The | |
136 | * vector is cleaned up when the CPU comes online again. | |
137 | */ | |
138 | if (IS_ERR_OR_NULL(this_cpu_read(vector_irq[cfg->vector]))) | |
139 | this_cpu_write(vector_irq[cfg->vector], VECTOR_RETRIGGERED); | |
140 | ||
141 | /* Redirect it to the new vector on the local CPU temporarily */ | |
142 | old_cfg.vector = cfg->vector; | |
143 | irq_msi_update_msg(irqd, &old_cfg); | |
144 | ||
145 | /* Now transition it to the target CPU */ | |
146 | irq_msi_update_msg(irqd, cfg); | |
147 | ||
148 | /* | |
149 | * All interrupts after this point are now targeted at the new | |
150 | * vector/CPU. | |
151 | * | |
152 | * Drop vector lock before testing whether the temporary assignment | |
153 | * to the local CPU was hit by an interrupt raised in the device, | |
154 | * because the retrigger function acquires vector lock again. | |
155 | */ | |
156 | unlock_vector_lock(); | |
157 | ||
158 | /* | |
159 | * Check whether the transition raced with a device interrupt and | |
160 | * is pending in the local APICs IRR. It is safe to do this outside | |
161 | * of vector lock as the irq_desc::lock of this interrupt is still | |
162 | * held and interrupts are disabled: The check is not accessing the | |
163 | * underlying vector store. It's just checking the local APIC's | |
164 | * IRR. | |
165 | */ | |
166 | if (lapic_vector_set_in_irr(cfg->vector)) | |
167 | irq_data_get_irq_chip(irqd)->irq_retrigger(irqd); | |
168 | ||
169 | return ret; | |
170 | } | |
171 | ||
44380982 JL |
172 | /* |
173 | * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, | |
174 | * which implement the MSI or MSI-X Capability Structure. | |
175 | */ | |
52f518a3 | 176 | static struct irq_chip pci_msi_controller = { |
44380982 JL |
177 | .name = "PCI-MSI", |
178 | .irq_unmask = pci_msi_unmask_irq, | |
179 | .irq_mask = pci_msi_mask_irq, | |
52f518a3 | 180 | .irq_ack = irq_chip_ack_parent, |
52f518a3 | 181 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
52f518a3 | 182 | .irq_compose_msi_msg = irq_msi_compose_msg, |
92e06be2 | 183 | .irq_set_affinity = msi_set_affinity, |
44380982 JL |
184 | .flags = IRQCHIP_SKIP_SET_WAKE, |
185 | }; | |
186 | ||
52f518a3 | 187 | int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) |
44380982 | 188 | { |
52f518a3 JL |
189 | struct irq_domain *domain; |
190 | struct irq_alloc_info info; | |
44380982 | 191 | |
52f518a3 JL |
192 | init_irq_alloc_info(&info, NULL); |
193 | info.type = X86_IRQ_ALLOC_TYPE_MSI; | |
194 | info.msi_dev = dev; | |
44380982 | 195 | |
52f518a3 JL |
196 | domain = irq_remapping_get_irq_domain(&info); |
197 | if (domain == NULL) | |
198 | domain = msi_default_domain; | |
199 | if (domain == NULL) | |
200 | return -ENOSYS; | |
44380982 | 201 | |
699c4cec | 202 | return msi_domain_alloc_irqs(domain, &dev->dev, nvec); |
52f518a3 | 203 | } |
44380982 | 204 | |
52f518a3 JL |
205 | void native_teardown_msi_irq(unsigned int irq) |
206 | { | |
207 | irq_domain_free_irqs(irq, 1); | |
208 | } | |
44380982 | 209 | |
52f518a3 JL |
210 | static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info, |
211 | msi_alloc_info_t *arg) | |
212 | { | |
213 | return arg->msi_hwirq; | |
214 | } | |
44380982 | 215 | |
c8f3e518 JO |
216 | int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, |
217 | msi_alloc_info_t *arg) | |
52f518a3 JL |
218 | { |
219 | struct pci_dev *pdev = to_pci_dev(dev); | |
220 | struct msi_desc *desc = first_pci_msi_entry(pdev); | |
221 | ||
222 | init_irq_alloc_info(arg, NULL); | |
223 | arg->msi_dev = pdev; | |
224 | if (desc->msi_attrib.is_msix) { | |
225 | arg->type = X86_IRQ_ALLOC_TYPE_MSIX; | |
226 | } else { | |
227 | arg->type = X86_IRQ_ALLOC_TYPE_MSI; | |
228 | arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; | |
229 | } | |
44380982 JL |
230 | |
231 | return 0; | |
232 | } | |
c8f3e518 | 233 | EXPORT_SYMBOL_GPL(pci_msi_prepare); |
44380982 | 234 | |
c8f3e518 | 235 | void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) |
44380982 | 236 | { |
52f518a3 JL |
237 | arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc); |
238 | } | |
c8f3e518 | 239 | EXPORT_SYMBOL_GPL(pci_msi_set_desc); |
44380982 | 240 | |
52f518a3 JL |
241 | static struct msi_domain_ops pci_msi_domain_ops = { |
242 | .get_hwirq = pci_msi_get_hwirq, | |
243 | .msi_prepare = pci_msi_prepare, | |
244 | .set_desc = pci_msi_set_desc, | |
245 | }; | |
44380982 | 246 | |
52f518a3 JL |
247 | static struct msi_domain_info pci_msi_domain_info = { |
248 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
68682a26 | 249 | MSI_FLAG_PCI_MSIX, |
52f518a3 JL |
250 | .ops = &pci_msi_domain_ops, |
251 | .chip = &pci_msi_controller, | |
252 | .handler = handle_edge_irq, | |
253 | .handler_name = "edge", | |
254 | }; | |
44380982 | 255 | |
f8f37ca7 | 256 | void __init arch_init_msi_domain(struct irq_domain *parent) |
52f518a3 | 257 | { |
f8f37ca7 TG |
258 | struct fwnode_handle *fn; |
259 | ||
52f518a3 JL |
260 | if (disable_apic) |
261 | return; | |
44380982 | 262 | |
f8f37ca7 TG |
263 | fn = irq_domain_alloc_named_fwnode("PCI-MSI"); |
264 | if (fn) { | |
265 | msi_default_domain = | |
266 | pci_msi_create_irq_domain(fn, &pci_msi_domain_info, | |
267 | parent); | |
268 | irq_domain_free_fwnode(fn); | |
269 | } | |
52f518a3 JL |
270 | if (!msi_default_domain) |
271 | pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n"); | |
92e06be2 TG |
272 | else |
273 | msi_default_domain->flags |= IRQ_DOMAIN_MSI_NOMASK_QUIRK; | |
44380982 JL |
274 | } |
275 | ||
52f518a3 | 276 | #ifdef CONFIG_IRQ_REMAP |
68682a26 JL |
277 | static struct irq_chip pci_msi_ir_controller = { |
278 | .name = "IR-PCI-MSI", | |
279 | .irq_unmask = pci_msi_unmask_irq, | |
280 | .irq_mask = pci_msi_mask_irq, | |
281 | .irq_ack = irq_chip_ack_parent, | |
68682a26 | 282 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
a2f1c8bd | 283 | .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, |
68682a26 JL |
284 | .flags = IRQCHIP_SKIP_SET_WAKE, |
285 | }; | |
286 | ||
287 | static struct msi_domain_info pci_msi_ir_domain_info = { | |
288 | .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | | |
289 | MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, | |
290 | .ops = &pci_msi_domain_ops, | |
291 | .chip = &pci_msi_ir_controller, | |
292 | .handler = handle_edge_irq, | |
293 | .handler_name = "edge", | |
294 | }; | |
295 | ||
667724c5 TG |
296 | struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent, |
297 | const char *name, int id) | |
298 | { | |
299 | struct fwnode_handle *fn; | |
300 | struct irq_domain *d; | |
301 | ||
302 | fn = irq_domain_alloc_named_id_fwnode(name, id); | |
303 | if (!fn) | |
304 | return NULL; | |
305 | d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent); | |
306 | irq_domain_free_fwnode(fn); | |
307 | return d; | |
308 | } | |
52f518a3 | 309 | #endif |
44380982 JL |
310 | |
311 | #ifdef CONFIG_DMAR_TABLE | |
62ac1780 JL |
312 | static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg) |
313 | { | |
314 | dmar_msi_write(data->irq, msg); | |
315 | } | |
316 | ||
0921f1da | 317 | static struct irq_chip dmar_msi_controller = { |
81dabe2e | 318 | .name = "DMAR-MSI", |
44380982 JL |
319 | .irq_unmask = dmar_msi_unmask, |
320 | .irq_mask = dmar_msi_mask, | |
0921f1da | 321 | .irq_ack = irq_chip_ack_parent, |
e390d895 | 322 | .irq_set_affinity = msi_domain_set_affinity, |
0921f1da JL |
323 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
324 | .irq_compose_msi_msg = irq_msi_compose_msg, | |
62ac1780 | 325 | .irq_write_msi_msg = dmar_msi_write_msg, |
44380982 JL |
326 | .flags = IRQCHIP_SKIP_SET_WAKE, |
327 | }; | |
328 | ||
e390d895 JL |
329 | static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info, |
330 | msi_alloc_info_t *arg) | |
0921f1da | 331 | { |
e390d895 | 332 | return arg->dmar_id; |
0921f1da JL |
333 | } |
334 | ||
e390d895 JL |
335 | static int dmar_msi_init(struct irq_domain *domain, |
336 | struct msi_domain_info *info, unsigned int virq, | |
337 | irq_hw_number_t hwirq, msi_alloc_info_t *arg) | |
0921f1da | 338 | { |
e390d895 JL |
339 | irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL, |
340 | handle_edge_irq, arg->dmar_data, "edge"); | |
0921f1da | 341 | |
e390d895 | 342 | return 0; |
0921f1da JL |
343 | } |
344 | ||
e390d895 JL |
345 | static struct msi_domain_ops dmar_msi_domain_ops = { |
346 | .get_hwirq = dmar_msi_get_hwirq, | |
347 | .msi_init = dmar_msi_init, | |
348 | }; | |
0921f1da | 349 | |
e390d895 JL |
350 | static struct msi_domain_info dmar_msi_domain_info = { |
351 | .ops = &dmar_msi_domain_ops, | |
352 | .chip = &dmar_msi_controller, | |
0921f1da JL |
353 | }; |
354 | ||
355 | static struct irq_domain *dmar_get_irq_domain(void) | |
356 | { | |
357 | static struct irq_domain *dmar_domain; | |
358 | static DEFINE_MUTEX(dmar_lock); | |
f8f37ca7 | 359 | struct fwnode_handle *fn; |
0921f1da JL |
360 | |
361 | mutex_lock(&dmar_lock); | |
f8f37ca7 TG |
362 | if (dmar_domain) |
363 | goto out; | |
364 | ||
365 | fn = irq_domain_alloc_named_fwnode("DMAR-MSI"); | |
366 | if (fn) { | |
367 | dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info, | |
e390d895 | 368 | x86_vector_domain); |
f8f37ca7 TG |
369 | irq_domain_free_fwnode(fn); |
370 | } | |
371 | out: | |
0921f1da | 372 | mutex_unlock(&dmar_lock); |
0921f1da JL |
373 | return dmar_domain; |
374 | } | |
375 | ||
376 | int dmar_alloc_hwirq(int id, int node, void *arg) | |
377 | { | |
378 | struct irq_domain *domain = dmar_get_irq_domain(); | |
379 | struct irq_alloc_info info; | |
380 | ||
381 | if (!domain) | |
382 | return -1; | |
383 | ||
384 | init_irq_alloc_info(&info, NULL); | |
385 | info.type = X86_IRQ_ALLOC_TYPE_DMAR; | |
386 | info.dmar_id = id; | |
387 | info.dmar_data = arg; | |
a62b32cd | 388 | |
0921f1da | 389 | return irq_domain_alloc_irqs(domain, 1, node, &info); |
a62b32cd JL |
390 | } |
391 | ||
392 | void dmar_free_hwirq(int irq) | |
393 | { | |
394 | irq_domain_free_irqs(irq, 1); | |
395 | } | |
44380982 JL |
396 | #endif |
397 | ||
398 | /* | |
399 | * MSI message composition | |
400 | */ | |
401 | #ifdef CONFIG_HPET_TIMER | |
3cb96f0c JL |
402 | static inline int hpet_dev_id(struct irq_domain *domain) |
403 | { | |
e390d895 | 404 | struct msi_domain_info *info = msi_get_domain_info(domain); |
44380982 | 405 | |
e390d895 | 406 | return (int)(long)info->data; |
44380982 JL |
407 | } |
408 | ||
62ac1780 JL |
409 | static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) |
410 | { | |
ff96b4d0 | 411 | hpet_msi_write(irq_data_get_irq_handler_data(data), msg); |
62ac1780 JL |
412 | } |
413 | ||
404f6aac | 414 | static struct irq_chip hpet_msi_controller __ro_after_init = { |
81dabe2e | 415 | .name = "HPET-MSI", |
44380982 JL |
416 | .irq_unmask = hpet_msi_unmask, |
417 | .irq_mask = hpet_msi_mask, | |
3cb96f0c | 418 | .irq_ack = irq_chip_ack_parent, |
e390d895 | 419 | .irq_set_affinity = msi_domain_set_affinity, |
3cb96f0c | 420 | .irq_retrigger = irq_chip_retrigger_hierarchy, |
3cb96f0c | 421 | .irq_compose_msi_msg = irq_msi_compose_msg, |
62ac1780 | 422 | .irq_write_msi_msg = hpet_msi_write_msg, |
44380982 JL |
423 | .flags = IRQCHIP_SKIP_SET_WAKE, |
424 | }; | |
425 | ||
e390d895 JL |
426 | static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info, |
427 | msi_alloc_info_t *arg) | |
3cb96f0c | 428 | { |
e390d895 | 429 | return arg->hpet_index; |
3cb96f0c JL |
430 | } |
431 | ||
e390d895 JL |
432 | static int hpet_msi_init(struct irq_domain *domain, |
433 | struct msi_domain_info *info, unsigned int virq, | |
434 | irq_hw_number_t hwirq, msi_alloc_info_t *arg) | |
3cb96f0c | 435 | { |
e390d895 JL |
436 | irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); |
437 | irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL, | |
438 | handle_edge_irq, arg->hpet_data, "edge"); | |
3cb96f0c | 439 | |
e390d895 | 440 | return 0; |
3cb96f0c JL |
441 | } |
442 | ||
e390d895 JL |
443 | static void hpet_msi_free(struct irq_domain *domain, |
444 | struct msi_domain_info *info, unsigned int virq) | |
3cb96f0c | 445 | { |
e390d895 | 446 | irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); |
3cb96f0c JL |
447 | } |
448 | ||
e390d895 JL |
449 | static struct msi_domain_ops hpet_msi_domain_ops = { |
450 | .get_hwirq = hpet_msi_get_hwirq, | |
451 | .msi_init = hpet_msi_init, | |
452 | .msi_free = hpet_msi_free, | |
453 | }; | |
454 | ||
455 | static struct msi_domain_info hpet_msi_domain_info = { | |
456 | .ops = &hpet_msi_domain_ops, | |
457 | .chip = &hpet_msi_controller, | |
3cb96f0c JL |
458 | }; |
459 | ||
460 | struct irq_domain *hpet_create_irq_domain(int hpet_id) | |
461 | { | |
e390d895 | 462 | struct msi_domain_info *domain_info; |
f8f37ca7 TG |
463 | struct irq_domain *parent, *d; |
464 | struct irq_alloc_info info; | |
465 | struct fwnode_handle *fn; | |
3cb96f0c JL |
466 | |
467 | if (x86_vector_domain == NULL) | |
468 | return NULL; | |
469 | ||
e390d895 JL |
470 | domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); |
471 | if (!domain_info) | |
472 | return NULL; | |
473 | ||
474 | *domain_info = hpet_msi_domain_info; | |
475 | domain_info->data = (void *)(long)hpet_id; | |
476 | ||
3cb96f0c JL |
477 | init_irq_alloc_info(&info, NULL); |
478 | info.type = X86_IRQ_ALLOC_TYPE_HPET; | |
479 | info.hpet_id = hpet_id; | |
480 | parent = irq_remapping_get_ir_irq_domain(&info); | |
481 | if (parent == NULL) | |
482 | parent = x86_vector_domain; | |
68682a26 JL |
483 | else |
484 | hpet_msi_controller.name = "IR-HPET-MSI"; | |
3cb96f0c | 485 | |
f8f37ca7 TG |
486 | fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, |
487 | hpet_id); | |
488 | if (!fn) { | |
489 | kfree(domain_info); | |
490 | return NULL; | |
491 | } | |
492 | ||
493 | d = msi_create_irq_domain(fn, domain_info, parent); | |
494 | irq_domain_free_fwnode(fn); | |
495 | return d; | |
3cb96f0c JL |
496 | } |
497 | ||
498 | int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev, | |
499 | int dev_num) | |
500 | { | |
501 | struct irq_alloc_info info; | |
502 | ||
503 | init_irq_alloc_info(&info, NULL); | |
504 | info.type = X86_IRQ_ALLOC_TYPE_HPET; | |
505 | info.hpet_data = dev; | |
506 | info.hpet_id = hpet_dev_id(domain); | |
507 | info.hpet_index = dev_num; | |
508 | ||
4a00c95d | 509 | return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); |
3cb96f0c | 510 | } |
44380982 | 511 | #endif |