[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kernel / cpu / bugs.c

// SPDX-License-Identifier: GPL-2.0
/*
 *  Copyright (C) 1994  Linus Torvalds
 *
 *  Cyrix stuff, June 1998 by:
 *	- Rafael R. Reilova (moved everything from head.S),
 *        <rreilova@ececs.uc.edu>
 *	- Channing Corn (tests & fixes),
 *	- Andrew D. Balsa (code cleanup).
 */
#include <linux/init.h>
#include <linux/utsname.h>
#include <linux/cpu.h>
#include <linux/module.h>

#include <asm/nospec-branch.h>
#include <asm/cmdline.h>
#include <asm/bugs.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#include <asm/fpu/internal.h>
#include <asm/msr.h>
#include <asm/paravirt.h>
#include <asm/alternative.h>
#include <asm/pgtable.h>
#include <asm/set_memory.h>
#include <asm/intel-family.h>

static void __init spectre_v2_select_mitigation(void);

/*
 * Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
 * writes to SPEC_CTRL contain whatever reserved bits have been set.
 */
static u64 __ro_after_init x86_spec_ctrl_base;

void __init check_bugs(void)
{
	identify_boot_cpu();

	if (!IS_ENABLED(CONFIG_SMP)) {
		pr_info("CPU: ");
		print_cpu_info(&boot_cpu_data);
	}

	/*
	 * Read the SPEC_CTRL MSR to account for reserved bits which may
	 * have unknown values.
	 */
	if (boot_cpu_has(X86_FEATURE_IBRS))
		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

	/* Select the proper spectre mitigation before patching alternatives */
	spectre_v2_select_mitigation();

#ifdef CONFIG_X86_32
	/*
	 * Check whether we are able to run this kernel safely on SMP.
	 *
	 * - i386 is no longer supported.
	 * - In order to run on anything without a TSC, we need to be
	 *   compiled for a i486.
	 */
	if (boot_cpu_data.x86 < 4)
		panic("Kernel requires i486+ for 'invlpg' and other features");

	init_utsname()->machine[1] =
		'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
	alternative_instructions();

	fpu__init_check_bugs();
#else /* CONFIG_X86_64 */
	alternative_instructions();

	/*
	 * Make sure the first 2MB area is not mapped by huge pages
	 * There are typically fixed size MTRRs in there and overlapping
	 * MTRRs into large pages causes slow downs.
	 *
	 * Right now we don't do that with gbpages because there seems
	 * very little benefit for that case.
	 */
	if (!direct_gbpages)
		set_memory_4k((unsigned long)__va(0), 1);
#endif
}

/* The kernel command line selection */
enum spectre_v2_mitigation_cmd {
	SPECTRE_V2_CMD_NONE,
	SPECTRE_V2_CMD_AUTO,
	SPECTRE_V2_CMD_FORCE,
	SPECTRE_V2_CMD_RETPOLINE,
	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
	SPECTRE_V2_CMD_RETPOLINE_AMD,
};

static const char *spectre_v2_strings[] = {
	[SPECTRE_V2_NONE]			= "Vulnerable",
	[SPECTRE_V2_RETPOLINE_MINIMAL]		= "Vulnerable: Minimal generic ASM retpoline",
	[SPECTRE_V2_RETPOLINE_MINIMAL_AMD]	= "Vulnerable: Minimal AMD ASM retpoline",
	[SPECTRE_V2_RETPOLINE_GENERIC]		= "Mitigation: Full generic retpoline",
	[SPECTRE_V2_RETPOLINE_AMD]		= "Mitigation: Full AMD retpoline",
};

#undef pr_fmt
#define pr_fmt(fmt)     "Spectre V2 : " fmt

static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;

void x86_spec_ctrl_set(u64 val)
{
	if (val & ~SPEC_CTRL_IBRS)
		WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
	else
		wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base | val);
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);

u64 x86_spec_ctrl_get_default(void)
{
	return x86_spec_ctrl_base;
}
EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);

#ifdef RETPOLINE
static bool spectre_v2_bad_module;

bool retpoline_module_ok(bool has_retpoline)
{
	if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline)
		return true;

	pr_err("System may be vulnerable to spectre v2\n");
	spectre_v2_bad_module = true;
	return false;
}

static inline const char *spectre_v2_module_string(void)
{
	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
}
#else
static inline const char *spectre_v2_module_string(void) { return ""; }
#endif

static void __init spec2_print_if_insecure(const char *reason)
{
	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
		pr_info("%s selected on command line.\n", reason);
}

static void __init spec2_print_if_secure(const char *reason)
{
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
		pr_info("%s selected on command line.\n", reason);
}

static inline bool retp_compiler(void)
{
	return __is_defined(RETPOLINE);
}

static inline bool match_option(const char *arg, int arglen, const char *opt)
{
	int len = strlen(opt);

	return len == arglen && !strncmp(arg, opt, len);
}

static const struct {
	const char *option;
	enum spectre_v2_mitigation_cmd cmd;
	bool secure;
} mitigation_options[] = {
	{ "off",               SPECTRE_V2_CMD_NONE,              false },
	{ "on",                SPECTRE_V2_CMD_FORCE,             true },
	{ "retpoline",         SPECTRE_V2_CMD_RETPOLINE,         false },
	{ "retpoline,amd",     SPECTRE_V2_CMD_RETPOLINE_AMD,     false },
	{ "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
	{ "auto",              SPECTRE_V2_CMD_AUTO,              false },
};

static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
{
	char arg[20];
	int ret, i;
	enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;

	if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
		return SPECTRE_V2_CMD_NONE;
	else {
		ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
		if (ret < 0)
			return SPECTRE_V2_CMD_AUTO;

		for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
			if (!match_option(arg, ret, mitigation_options[i].option))
				continue;
			cmd = mitigation_options[i].cmd;
			break;
		}

		if (i >= ARRAY_SIZE(mitigation_options)) {
			pr_err("unknown option (%s). Switching to AUTO select\n", arg);
			return SPECTRE_V2_CMD_AUTO;
		}
	}

	if ((cmd == SPECTRE_V2_CMD_RETPOLINE ||
	     cmd == SPECTRE_V2_CMD_RETPOLINE_AMD ||
	     cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
	    !IS_ENABLED(CONFIG_RETPOLINE)) {
		pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
		return SPECTRE_V2_CMD_AUTO;
	}

	if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
	    boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
		pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
		return SPECTRE_V2_CMD_AUTO;
	}

	if (mitigation_options[i].secure)
		spec2_print_if_secure(mitigation_options[i].option);
	else
		spec2_print_if_insecure(mitigation_options[i].option);

	return cmd;
}

/* Check for Skylake-like CPUs (for RSB handling) */
static bool __init is_skylake_era(void)
{
	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	    boot_cpu_data.x86 == 6) {
		switch (boot_cpu_data.x86_model) {
		case INTEL_FAM6_SKYLAKE_MOBILE:
		case INTEL_FAM6_SKYLAKE_DESKTOP:
		case INTEL_FAM6_SKYLAKE_X:
		case INTEL_FAM6_KABYLAKE_MOBILE:
		case INTEL_FAM6_KABYLAKE_DESKTOP:
			return true;
		}
	}
	return false;
}

static void __init spectre_v2_select_mitigation(void)
{
	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;

	/*
	 * If the CPU is not affected and the command line mode is NONE or AUTO
	 * then nothing to do.
	 */
	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
	    (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO))
		return;

	switch (cmd) {
	case SPECTRE_V2_CMD_NONE:
		return;

	case SPECTRE_V2_CMD_FORCE:
	case SPECTRE_V2_CMD_AUTO:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_auto;
		break;
	case SPECTRE_V2_CMD_RETPOLINE_AMD:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_amd;
		break;
	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_generic;
		break;
	case SPECTRE_V2_CMD_RETPOLINE:
		if (IS_ENABLED(CONFIG_RETPOLINE))
			goto retpoline_auto;
		break;
	}
	pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
	return;

retpoline_auto:
	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
	retpoline_amd:
		if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
			pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
			goto retpoline_generic;
		}
		mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
					 SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	} else {
	retpoline_generic:
		mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
					 SPECTRE_V2_RETPOLINE_MINIMAL;
		setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	}

	spectre_v2_enabled = mode;
	pr_info("%s\n", spectre_v2_strings[mode]);

	/*
	 * If neither SMEP nor PTI are available, there is a risk of
	 * hitting userspace addresses in the RSB after a context switch
	 * from a shallow call stack to a deeper one. To prevent this fill
	 * the entire RSB, even when using IBRS.
	 *
	 * Skylake era CPUs have a separate issue with *underflow* of the
	 * RSB, when they will predict 'ret' targets from the generic BTB.
	 * The proper mitigation for this is IBRS. If IBRS is not supported
	 * or deactivated in favour of retpolines the RSB fill on context
	 * switch is required.
	 */
	if ((!boot_cpu_has(X86_FEATURE_PTI) &&
	     !boot_cpu_has(X86_FEATURE_SMEP)) || is_skylake_era()) {
		setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
		pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
	}

	/* Initialize Indirect Branch Prediction Barrier if supported */
	if (boot_cpu_has(X86_FEATURE_IBPB)) {
		setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
		pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
	}

	/*
	 * Retpoline means the kernel is safe because it has no indirect
	 * branches. But firmware isn't, so use IBRS to protect that.
	 */
	if (boot_cpu_has(X86_FEATURE_IBRS)) {
		setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
		pr_info("Enabling Restricted Speculation for firmware calls\n");
	}
}

#undef pr_fmt

#ifdef CONFIG_SYSFS

ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr,
			char *buf, unsigned int bug)
{
	if (!boot_cpu_has_bug(bug))
		return sprintf(buf, "Not affected\n");

	switch (bug) {
	case X86_BUG_CPU_MELTDOWN:
		if (boot_cpu_has(X86_FEATURE_PTI))
			return sprintf(buf, "Mitigation: PTI\n");

		break;

	case X86_BUG_SPECTRE_V1:
		return sprintf(buf, "Mitigation: __user pointer sanitization\n");

	case X86_BUG_SPECTRE_V2:
		return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
			       boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
			       boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
			       spectre_v2_module_string());

	default:
		break;
	}

	return sprintf(buf, "Vulnerable\n");
}

ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
}

ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
}

ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf)
{
	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
}
#endif
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
1353ebb4	2	/*
1353ebb4 JF	3	* Copyright (C) 1994 Linus Torvalds
	4	*
	5	* Cyrix stuff, June 1998 by:
	6	* - Rafael R. Reilova (moved everything from head.S),
	7	* <rreilova@ececs.uc.edu>
	8	* - Channing Corn (tests & fixes),
	9	* - Andrew D. Balsa (code cleanup).
	10	*/
	11	#include <linux/init.h>
	12	#include <linux/utsname.h>
61dc0f55	13	#include <linux/cpu.h>
d280282b	14	#include <linux/module.h>
da285121 DW	15
	16	#include <asm/nospec-branch.h>
	17	#include <asm/cmdline.h>
91eb1b79	18	#include <asm/bugs.h>
1353ebb4	19	#include <asm/processor.h>
7ebad705	20	#include <asm/processor-flags.h>
952f07ec	21	#include <asm/fpu/internal.h>
1353ebb4 JF	22	#include <asm/msr.h>
	23	#include <asm/paravirt.h>
	24	#include <asm/alternative.h>
62a67e12	25	#include <asm/pgtable.h>
d1163651	26	#include <asm/set_memory.h>
c995efd5	27	#include <asm/intel-family.h>
1353ebb4	28
da285121 DW	29	static void __init spectre_v2_select_mitigation(void);
da285121 DW	30
296b454a KRW	31	/*
	32	* Our boot-time value of the SPEC_CTRL MSR. We read it once so that any
	33	* writes to SPEC_CTRL contain whatever reserved bits have been set.
	34	*/
	35	static u64 __ro_after_init x86_spec_ctrl_base;
	36
1353ebb4 JF	37	void __init check_bugs(void)
	38	{
	39	identify_boot_cpu();
55a36b65	40
62a67e12 BP	41	if (!IS_ENABLED(CONFIG_SMP)) {
	42	pr_info("CPU: ");
	43	print_cpu_info(&boot_cpu_data);
	44	}
	45
296b454a KRW	46	/*
	47	* Read the SPEC_CTRL MSR to account for reserved bits which may
	48	* have unknown values.
	49	*/
	50	if (boot_cpu_has(X86_FEATURE_IBRS))
	51	rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
	52
da285121 DW	53	/* Select the proper spectre mitigation before patching alternatives */
	54	spectre_v2_select_mitigation();
	55
62a67e12	56	#ifdef CONFIG_X86_32
55a36b65 BP	57	/*
	58	* Check whether we are able to run this kernel safely on SMP.
	59	*
	60	* - i386 is no longer supported.
	61	* - In order to run on anything without a TSC, we need to be
	62	* compiled for a i486.
	63	*/
	64	if (boot_cpu_data.x86 < 4)
	65	panic("Kernel requires i486+ for 'invlpg' and other features");
	66
bfe4bb15 MV	67	init_utsname()->machine[1] =
bfe4bb15 MV	68	'0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
1353ebb4	69	alternative_instructions();
304bceda	70
4d164092	71	fpu__init_check_bugs();
62a67e12 BP	72	#else /* CONFIG_X86_64 */
	73	alternative_instructions();
	74
	75	/*
	76	* Make sure the first 2MB area is not mapped by huge pages
	77	* There are typically fixed size MTRRs in there and overlapping
	78	* MTRRs into large pages causes slow downs.
	79	*
	80	* Right now we don't do that with gbpages because there seems
	81	* very little benefit for that case.
	82	*/
	83	if (!direct_gbpages)
	84	set_memory_4k((unsigned long)__va(0), 1);
	85	#endif
1353ebb4	86	}
61dc0f55	87
da285121 DW	88	/* The kernel command line selection */
	89	enum spectre_v2_mitigation_cmd {
	90	SPECTRE_V2_CMD_NONE,
	91	SPECTRE_V2_CMD_AUTO,
	92	SPECTRE_V2_CMD_FORCE,
	93	SPECTRE_V2_CMD_RETPOLINE,
	94	SPECTRE_V2_CMD_RETPOLINE_GENERIC,
	95	SPECTRE_V2_CMD_RETPOLINE_AMD,
	96	};
	97
	98	static const char *spectre_v2_strings[] = {
	99	[SPECTRE_V2_NONE] = "Vulnerable",
	100	[SPECTRE_V2_RETPOLINE_MINIMAL] = "Vulnerable: Minimal generic ASM retpoline",
	101	[SPECTRE_V2_RETPOLINE_MINIMAL_AMD] = "Vulnerable: Minimal AMD ASM retpoline",
	102	[SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline",
	103	[SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline",
	104	};
	105
	106	#undef pr_fmt
bbb5e08b	107	#define pr_fmt(fmt) "Spectre V2 : " fmt
da285121 DW	108
da285121 DW	109	static enum spectre_v2_mitigation spectre_v2_enabled = SPECTRE_V2_NONE;
d280282b	110
296b454a KRW	111	void x86_spec_ctrl_set(u64 val)
	112	{
	113	if (val & ~SPEC_CTRL_IBRS)
	114	WARN_ONCE(1, "SPEC_CTRL MSR value 0x%16llx is unknown.\n", val);
	115	else
	116	wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base \| val);
	117	}
	118	EXPORT_SYMBOL_GPL(x86_spec_ctrl_set);
	119
	120	u64 x86_spec_ctrl_get_default(void)
	121	{
	122	return x86_spec_ctrl_base;
	123	}
	124	EXPORT_SYMBOL_GPL(x86_spec_ctrl_get_default);
	125
d280282b	126	#ifdef RETPOLINE
bb3c2578 TG	127	static bool spectre_v2_bad_module;
bb3c2578 TG	128
d280282b AK	129	bool retpoline_module_ok(bool has_retpoline)
	130	{
	131	if (spectre_v2_enabled == SPECTRE_V2_NONE \|\| has_retpoline)
	132	return true;
	133
c8b8e109	134	pr_err("System may be vulnerable to spectre v2\n");
d280282b AK	135	spectre_v2_bad_module = true;
	136	return false;
	137	}
bb3c2578 TG	138
	139	static inline const char *spectre_v2_module_string(void)
	140	{
	141	return spectre_v2_bad_module ? " - vulnerable module loaded" : "";
	142	}
	143	#else
	144	static inline const char *spectre_v2_module_string(void) { return ""; }
d280282b	145	#endif
da285121 DW	146
	147	static void __init spec2_print_if_insecure(const char *reason)
	148	{
	149	if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
17c33e7c	150	pr_info("%s selected on command line.\n", reason);
da285121 DW	151	}
	152
	153	static void __init spec2_print_if_secure(const char *reason)
	154	{
	155	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2))
17c33e7c	156	pr_info("%s selected on command line.\n", reason);
da285121 DW	157	}
	158
	159	static inline bool retp_compiler(void)
	160	{
	161	return __is_defined(RETPOLINE);
	162	}
	163
	164	static inline bool match_option(const char arg, int arglen, const char opt)
	165	{
	166	int len = strlen(opt);
	167
	168	return len == arglen && !strncmp(arg, opt, len);
	169	}
	170
17c33e7c KA	171	static const struct {
	172	const char *option;
	173	enum spectre_v2_mitigation_cmd cmd;
	174	bool secure;
	175	} mitigation_options[] = {
	176	{ "off", SPECTRE_V2_CMD_NONE, false },
	177	{ "on", SPECTRE_V2_CMD_FORCE, true },
	178	{ "retpoline", SPECTRE_V2_CMD_RETPOLINE, false },
	179	{ "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false },
	180	{ "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false },
	181	{ "auto", SPECTRE_V2_CMD_AUTO, false },
	182	};
	183
da285121 DW	184	static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void)
	185	{
	186	char arg[20];
17c33e7c KA	187	int ret, i;
	188	enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO;
	189
	190	if (cmdline_find_option_bool(boot_command_line, "nospectre_v2"))
	191	return SPECTRE_V2_CMD_NONE;
	192	else {
713f1b95	193	ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg));
17c33e7c KA	194	if (ret < 0)
	195	return SPECTRE_V2_CMD_AUTO;
	196
	197	for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) {
	198	if (!match_option(arg, ret, mitigation_options[i].option))
	199	continue;
	200	cmd = mitigation_options[i].cmd;
	201	break;
	202	}
	203
	204	if (i >= ARRAY_SIZE(mitigation_options)) {
ecad7915	205	pr_err("unknown option (%s). Switching to AUTO select\n", arg);
da285121 DW	206	return SPECTRE_V2_CMD_AUTO;
	207	}
	208	}
	209
17c33e7c KA	210	if ((cmd == SPECTRE_V2_CMD_RETPOLINE \|\|
	211	cmd == SPECTRE_V2_CMD_RETPOLINE_AMD \|\|
	212	cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) &&
	213	!IS_ENABLED(CONFIG_RETPOLINE)) {
713f1b95	214	pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option);
da285121	215	return SPECTRE_V2_CMD_AUTO;
17c33e7c KA	216	}
	217
	218	if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD &&
	219	boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
	220	pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n");
	221	return SPECTRE_V2_CMD_AUTO;
	222	}
	223
	224	if (mitigation_options[i].secure)
	225	spec2_print_if_secure(mitigation_options[i].option);
	226	else
	227	spec2_print_if_insecure(mitigation_options[i].option);
	228
	229	return cmd;
da285121 DW	230	}
da285121 DW	231
c995efd5 DW	232	/* Check for Skylake-like CPUs (for RSB handling) */
	233	static bool __init is_skylake_era(void)
	234	{
	235	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
	236	boot_cpu_data.x86 == 6) {
	237	switch (boot_cpu_data.x86_model) {
	238	case INTEL_FAM6_SKYLAKE_MOBILE:
	239	case INTEL_FAM6_SKYLAKE_DESKTOP:
	240	case INTEL_FAM6_SKYLAKE_X:
	241	case INTEL_FAM6_KABYLAKE_MOBILE:
	242	case INTEL_FAM6_KABYLAKE_DESKTOP:
	243	return true;
	244	}
	245	}
	246	return false;
	247	}
	248
da285121 DW	249	static void __init spectre_v2_select_mitigation(void)
	250	{
	251	enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline();
	252	enum spectre_v2_mitigation mode = SPECTRE_V2_NONE;
	253
	254	/*
	255	* If the CPU is not affected and the command line mode is NONE or AUTO
	256	* then nothing to do.
	257	*/
	258	if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) &&
	259	(cmd == SPECTRE_V2_CMD_NONE \|\| cmd == SPECTRE_V2_CMD_AUTO))
	260	return;
	261
	262	switch (cmd) {
	263	case SPECTRE_V2_CMD_NONE:
	264	return;
	265
	266	case SPECTRE_V2_CMD_FORCE:
da285121	267	case SPECTRE_V2_CMD_AUTO:
d0f293e0 DL	268	if (IS_ENABLED(CONFIG_RETPOLINE))
	269	goto retpoline_auto;
	270	break;
da285121 DW	271	case SPECTRE_V2_CMD_RETPOLINE_AMD:
	272	if (IS_ENABLED(CONFIG_RETPOLINE))
	273	goto retpoline_amd;
	274	break;
	275	case SPECTRE_V2_CMD_RETPOLINE_GENERIC:
	276	if (IS_ENABLED(CONFIG_RETPOLINE))
	277	goto retpoline_generic;
	278	break;
	279	case SPECTRE_V2_CMD_RETPOLINE:
	280	if (IS_ENABLED(CONFIG_RETPOLINE))
	281	goto retpoline_auto;
	282	break;
	283	}
713f1b95	284	pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!");
da285121 DW	285	return;
	286
	287	retpoline_auto:
	288	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
	289	retpoline_amd:
	290	if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) {
713f1b95	291	pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n");
da285121 DW	292	goto retpoline_generic;
	293	}
	294	mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_AMD :
	295	SPECTRE_V2_RETPOLINE_MINIMAL_AMD;
	296	setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD);
	297	setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	298	} else {
	299	retpoline_generic:
	300	mode = retp_compiler() ? SPECTRE_V2_RETPOLINE_GENERIC :
	301	SPECTRE_V2_RETPOLINE_MINIMAL;
	302	setup_force_cpu_cap(X86_FEATURE_RETPOLINE);
	303	}
	304
	305	spectre_v2_enabled = mode;
	306	pr_info("%s\n", spectre_v2_strings[mode]);
c995efd5 DW	307
c995efd5 DW	308	/*
713f1b95	309	* If neither SMEP nor PTI are available, there is a risk of
c995efd5 DW	310	* hitting userspace addresses in the RSB after a context switch
	311	* from a shallow call stack to a deeper one. To prevent this fill
	312	* the entire RSB, even when using IBRS.
	313	*
	314	* Skylake era CPUs have a separate issue with underflow of the
	315	* RSB, when they will predict 'ret' targets from the generic BTB.
	316	* The proper mitigation for this is IBRS. If IBRS is not supported
	317	* or deactivated in favour of retpolines the RSB fill on context
	318	* switch is required.
	319	*/
	320	if ((!boot_cpu_has(X86_FEATURE_PTI) &&
	321	!boot_cpu_has(X86_FEATURE_SMEP)) \|\| is_skylake_era()) {
	322	setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW);
713f1b95	323	pr_info("Spectre v2 mitigation: Filling RSB on context switch\n");
c995efd5	324	}
bd12e896 DW	325
bd12e896 DW	326	/* Initialize Indirect Branch Prediction Barrier if supported */
581abf91 DW	327	if (boot_cpu_has(X86_FEATURE_IBPB)) {
581abf91 DW	328	setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
713f1b95	329	pr_info("Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier\n");
bd12e896	330	}
390b99c3 DW	331
	332	/*
	333	* Retpoline means the kernel is safe because it has no indirect
	334	* branches. But firmware isn't, so use IBRS to protect that.
	335	*/
	336	if (boot_cpu_has(X86_FEATURE_IBRS)) {
	337	setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW);
	338	pr_info("Enabling Restricted Speculation for firmware calls\n");
	339	}
da285121 DW	340	}
	341
	342	#undef pr_fmt
	343
61dc0f55	344	#ifdef CONFIG_SYSFS
d2b8fc2d KRW	345
	346	ssize_t cpu_show_common(struct device dev, struct device_attribute attr,
	347	char *buf, unsigned int bug)
61dc0f55	348	{
d2b8fc2d	349	if (!boot_cpu_has_bug(bug))
61dc0f55	350	return sprintf(buf, "Not affected\n");
d2b8fc2d KRW	351
	352	switch (bug) {
	353	case X86_BUG_CPU_MELTDOWN:
	354	if (boot_cpu_has(X86_FEATURE_PTI))
	355	return sprintf(buf, "Mitigation: PTI\n");
	356
	357	break;
	358
	359	case X86_BUG_SPECTRE_V1:
	360	return sprintf(buf, "Mitigation: __user pointer sanitization\n");
	361
	362	case X86_BUG_SPECTRE_V2:
	363	return sprintf(buf, "%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled],
	364	boot_cpu_has(X86_FEATURE_USE_IBPB) ? ", IBPB" : "",
	365	boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "",
	366	spectre_v2_module_string());
	367
	368	default:
	369	break;
	370	}
	371
61dc0f55 TG	372	return sprintf(buf, "Vulnerable\n");
	373	}
	374
d2b8fc2d KRW	375	ssize_t cpu_show_meltdown(struct device dev, struct device_attribute attr, char *buf)
	376	{
	377	return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN);
	378	}
	379
713f1b95	380	ssize_t cpu_show_spectre_v1(struct device dev, struct device_attribute attr, char *buf)
61dc0f55	381	{
d2b8fc2d	382	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1);
61dc0f55 TG	383	}
61dc0f55 TG	384
713f1b95	385	ssize_t cpu_show_spectre_v2(struct device dev, struct device_attribute attr, char *buf)
61dc0f55	386	{
d2b8fc2d	387	return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2);
61dc0f55 TG	388	}
61dc0f55 TG	389	#endif