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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 | 2 | * Copyright (C) 1991, 1992 Linus Torvalds |
a8c1be9d | 3 | * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs |
1da177e4 LT |
4 | * |
5 | * Pentium III FXSR, SSE support | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | */ | |
8 | ||
9 | /* | |
c1d518c8 | 10 | * Handle hardware traps and faults. |
1da177e4 | 11 | */ |
b5964405 IM |
12 | #include <linux/interrupt.h> |
13 | #include <linux/kallsyms.h> | |
14 | #include <linux/spinlock.h> | |
b5964405 IM |
15 | #include <linux/kprobes.h> |
16 | #include <linux/uaccess.h> | |
17 | #include <linux/utsname.h> | |
18 | #include <linux/kdebug.h> | |
1da177e4 | 19 | #include <linux/kernel.h> |
b5964405 IM |
20 | #include <linux/module.h> |
21 | #include <linux/ptrace.h> | |
1da177e4 | 22 | #include <linux/string.h> |
b5964405 | 23 | #include <linux/delay.h> |
1da177e4 | 24 | #include <linux/errno.h> |
b5964405 IM |
25 | #include <linux/kexec.h> |
26 | #include <linux/sched.h> | |
1da177e4 | 27 | #include <linux/timer.h> |
1da177e4 | 28 | #include <linux/init.h> |
91768d6c | 29 | #include <linux/bug.h> |
b5964405 IM |
30 | #include <linux/nmi.h> |
31 | #include <linux/mm.h> | |
c1d518c8 AH |
32 | #include <linux/smp.h> |
33 | #include <linux/io.h> | |
1da177e4 LT |
34 | |
35 | #ifdef CONFIG_EISA | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/eisa.h> | |
38 | #endif | |
39 | ||
40 | #ifdef CONFIG_MCA | |
41 | #include <linux/mca.h> | |
42 | #endif | |
43 | ||
c0d12172 DJ |
44 | #if defined(CONFIG_EDAC) |
45 | #include <linux/edac.h> | |
46 | #endif | |
47 | ||
b5964405 | 48 | #include <asm/stacktrace.h> |
1da177e4 | 49 | #include <asm/processor.h> |
1da177e4 | 50 | #include <asm/debugreg.h> |
b5964405 IM |
51 | #include <asm/atomic.h> |
52 | #include <asm/system.h> | |
c1d518c8 | 53 | #include <asm/traps.h> |
1da177e4 LT |
54 | #include <asm/desc.h> |
55 | #include <asm/i387.h> | |
c1d518c8 | 56 | |
1164dd00 | 57 | #include <asm/mach_traps.h> |
c1d518c8 | 58 | |
081f75bb AH |
59 | #ifdef CONFIG_X86_64 |
60 | #include <asm/pgalloc.h> | |
61 | #include <asm/proto.h> | |
081f75bb | 62 | #else |
c1d518c8 AH |
63 | #include <asm/processor-flags.h> |
64 | #include <asm/arch_hooks.h> | |
6ac8d51f | 65 | #include <asm/traps.h> |
1da177e4 | 66 | |
eb642f62 | 67 | #include "cpu/mcheck/mce.h" |
1da177e4 LT |
68 | |
69 | asmlinkage int system_call(void); | |
70 | ||
1da177e4 | 71 | /* Do we ignore FPU interrupts ? */ |
b5964405 | 72 | char ignore_fpu_irq; |
1da177e4 LT |
73 | |
74 | /* | |
75 | * The IDT has to be page-aligned to simplify the Pentium | |
76 | * F0 0F bug workaround.. We have a special link segment | |
77 | * for this. | |
78 | */ | |
010d4f82 | 79 | gate_desc idt_table[256] |
6842ef0e | 80 | __attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, }; |
081f75bb | 81 | #endif |
1da177e4 | 82 | |
b77b881f YL |
83 | DECLARE_BITMAP(used_vectors, NR_VECTORS); |
84 | EXPORT_SYMBOL_GPL(used_vectors); | |
85 | ||
badc7652 | 86 | static int ignore_nmis; |
e041c683 | 87 | |
762db434 AH |
88 | static inline void conditional_sti(struct pt_regs *regs) |
89 | { | |
90 | if (regs->flags & X86_EFLAGS_IF) | |
91 | local_irq_enable(); | |
92 | } | |
93 | ||
3d2a71a5 AH |
94 | static inline void preempt_conditional_sti(struct pt_regs *regs) |
95 | { | |
96 | inc_preempt_count(); | |
97 | if (regs->flags & X86_EFLAGS_IF) | |
98 | local_irq_enable(); | |
99 | } | |
100 | ||
be716615 TG |
101 | static inline void conditional_cli(struct pt_regs *regs) |
102 | { | |
103 | if (regs->flags & X86_EFLAGS_IF) | |
104 | local_irq_disable(); | |
105 | } | |
106 | ||
3d2a71a5 AH |
107 | static inline void preempt_conditional_cli(struct pt_regs *regs) |
108 | { | |
109 | if (regs->flags & X86_EFLAGS_IF) | |
110 | local_irq_disable(); | |
111 | dec_preempt_count(); | |
112 | } | |
113 | ||
081f75bb | 114 | #ifdef CONFIG_X86_32 |
b5964405 IM |
115 | static inline void |
116 | die_if_kernel(const char *str, struct pt_regs *regs, long err) | |
1da177e4 | 117 | { |
717b594a | 118 | if (!user_mode_vm(regs)) |
1da177e4 LT |
119 | die(str, regs, err); |
120 | } | |
121 | ||
ae82157b AH |
122 | /* |
123 | * Perform the lazy TSS's I/O bitmap copy. If the TSS has an | |
124 | * invalid offset set (the LAZY one) and the faulting thread has | |
125 | * a valid I/O bitmap pointer, we copy the I/O bitmap in the TSS, | |
126 | * we set the offset field correctly and return 1. | |
127 | */ | |
128 | static int lazy_iobitmap_copy(void) | |
129 | { | |
130 | struct thread_struct *thread; | |
131 | struct tss_struct *tss; | |
132 | int cpu; | |
133 | ||
134 | cpu = get_cpu(); | |
135 | tss = &per_cpu(init_tss, cpu); | |
136 | thread = ¤t->thread; | |
137 | ||
138 | if (tss->x86_tss.io_bitmap_base == INVALID_IO_BITMAP_OFFSET_LAZY && | |
139 | thread->io_bitmap_ptr) { | |
140 | memcpy(tss->io_bitmap, thread->io_bitmap_ptr, | |
141 | thread->io_bitmap_max); | |
142 | /* | |
143 | * If the previously set map was extending to higher ports | |
144 | * than the current one, pad extra space with 0xff (no access). | |
145 | */ | |
146 | if (thread->io_bitmap_max < tss->io_bitmap_max) { | |
147 | memset((char *) tss->io_bitmap + | |
148 | thread->io_bitmap_max, 0xff, | |
149 | tss->io_bitmap_max - thread->io_bitmap_max); | |
150 | } | |
151 | tss->io_bitmap_max = thread->io_bitmap_max; | |
152 | tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET; | |
153 | tss->io_bitmap_owner = thread; | |
154 | put_cpu(); | |
155 | ||
156 | return 1; | |
157 | } | |
158 | put_cpu(); | |
159 | ||
160 | return 0; | |
161 | } | |
081f75bb | 162 | #endif |
ae82157b | 163 | |
b5964405 | 164 | static void __kprobes |
3c1326f8 | 165 | do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, |
b5964405 | 166 | long error_code, siginfo_t *info) |
1da177e4 | 167 | { |
4f339ecb | 168 | struct task_struct *tsk = current; |
4f339ecb | 169 | |
081f75bb | 170 | #ifdef CONFIG_X86_32 |
6b6891f9 | 171 | if (regs->flags & X86_VM_MASK) { |
3c1326f8 AH |
172 | /* |
173 | * traps 0, 1, 3, 4, and 5 should be forwarded to vm86. | |
174 | * On nmi (interrupt 2), do_trap should not be called. | |
175 | */ | |
176 | if (trapnr < 6) | |
1da177e4 LT |
177 | goto vm86_trap; |
178 | goto trap_signal; | |
179 | } | |
081f75bb | 180 | #endif |
1da177e4 | 181 | |
717b594a | 182 | if (!user_mode(regs)) |
1da177e4 LT |
183 | goto kernel_trap; |
184 | ||
081f75bb | 185 | #ifdef CONFIG_X86_32 |
b5964405 | 186 | trap_signal: |
081f75bb | 187 | #endif |
b5964405 IM |
188 | /* |
189 | * We want error_code and trap_no set for userspace faults and | |
190 | * kernelspace faults which result in die(), but not | |
191 | * kernelspace faults which are fixed up. die() gives the | |
192 | * process no chance to handle the signal and notice the | |
193 | * kernel fault information, so that won't result in polluting | |
194 | * the information about previously queued, but not yet | |
195 | * delivered, faults. See also do_general_protection below. | |
196 | */ | |
197 | tsk->thread.error_code = error_code; | |
198 | tsk->thread.trap_no = trapnr; | |
d1895183 | 199 | |
081f75bb AH |
200 | #ifdef CONFIG_X86_64 |
201 | if (show_unhandled_signals && unhandled_signal(tsk, signr) && | |
202 | printk_ratelimit()) { | |
203 | printk(KERN_INFO | |
204 | "%s[%d] trap %s ip:%lx sp:%lx error:%lx", | |
205 | tsk->comm, tsk->pid, str, | |
206 | regs->ip, regs->sp, error_code); | |
207 | print_vma_addr(" in ", regs->ip); | |
208 | printk("\n"); | |
209 | } | |
210 | #endif | |
211 | ||
b5964405 IM |
212 | if (info) |
213 | force_sig_info(signr, info, tsk); | |
214 | else | |
215 | force_sig(signr, tsk); | |
216 | return; | |
1da177e4 | 217 | |
b5964405 IM |
218 | kernel_trap: |
219 | if (!fixup_exception(regs)) { | |
220 | tsk->thread.error_code = error_code; | |
221 | tsk->thread.trap_no = trapnr; | |
222 | die(str, regs, error_code); | |
1da177e4 | 223 | } |
b5964405 | 224 | return; |
1da177e4 | 225 | |
081f75bb | 226 | #ifdef CONFIG_X86_32 |
b5964405 IM |
227 | vm86_trap: |
228 | if (handle_vm86_trap((struct kernel_vm86_regs *) regs, | |
229 | error_code, trapnr)) | |
230 | goto trap_signal; | |
231 | return; | |
081f75bb | 232 | #endif |
1da177e4 LT |
233 | } |
234 | ||
b5964405 | 235 | #define DO_ERROR(trapnr, signr, str, name) \ |
e407d620 | 236 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
237 | { \ |
238 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ | |
a8c1be9d | 239 | == NOTIFY_STOP) \ |
b5964405 | 240 | return; \ |
61aef7d2 | 241 | conditional_sti(regs); \ |
3c1326f8 | 242 | do_trap(trapnr, signr, str, regs, error_code, NULL); \ |
1da177e4 LT |
243 | } |
244 | ||
3c1326f8 | 245 | #define DO_ERROR_INFO(trapnr, signr, str, name, sicode, siaddr) \ |
e407d620 | 246 | dotraplinkage void do_##name(struct pt_regs *regs, long error_code) \ |
b5964405 IM |
247 | { \ |
248 | siginfo_t info; \ | |
249 | info.si_signo = signr; \ | |
250 | info.si_errno = 0; \ | |
251 | info.si_code = sicode; \ | |
252 | info.si_addr = (void __user *)siaddr; \ | |
b5964405 | 253 | if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) \ |
a8c1be9d | 254 | == NOTIFY_STOP) \ |
b5964405 | 255 | return; \ |
61aef7d2 | 256 | conditional_sti(regs); \ |
3c1326f8 | 257 | do_trap(trapnr, signr, str, regs, error_code, &info); \ |
1da177e4 LT |
258 | } |
259 | ||
3c1326f8 AH |
260 | DO_ERROR_INFO(0, SIGFPE, "divide error", divide_error, FPE_INTDIV, regs->ip) |
261 | DO_ERROR(4, SIGSEGV, "overflow", overflow) | |
262 | DO_ERROR(5, SIGSEGV, "bounds", bounds) | |
263 | DO_ERROR_INFO(6, SIGILL, "invalid opcode", invalid_op, ILL_ILLOPN, regs->ip) | |
51bc1ed6 | 264 | DO_ERROR(9, SIGFPE, "coprocessor segment overrun", coprocessor_segment_overrun) |
6bf77bf9 | 265 | DO_ERROR(10, SIGSEGV, "invalid TSS", invalid_TSS) |
36d936c7 | 266 | DO_ERROR(11, SIGBUS, "segment not present", segment_not_present) |
081f75bb | 267 | #ifdef CONFIG_X86_32 |
f5ca8187 | 268 | DO_ERROR(12, SIGBUS, "stack segment", stack_segment) |
081f75bb | 269 | #endif |
3c1326f8 | 270 | DO_ERROR_INFO(17, SIGBUS, "alignment check", alignment_check, BUS_ADRALN, 0) |
1da177e4 | 271 | |
081f75bb AH |
272 | #ifdef CONFIG_X86_64 |
273 | /* Runs on IST stack */ | |
274 | dotraplinkage void do_stack_segment(struct pt_regs *regs, long error_code) | |
275 | { | |
276 | if (notify_die(DIE_TRAP, "stack segment", regs, error_code, | |
277 | 12, SIGBUS) == NOTIFY_STOP) | |
278 | return; | |
279 | preempt_conditional_sti(regs); | |
280 | do_trap(12, SIGBUS, "stack segment", regs, error_code, NULL); | |
281 | preempt_conditional_cli(regs); | |
282 | } | |
283 | ||
284 | dotraplinkage void do_double_fault(struct pt_regs *regs, long error_code) | |
285 | { | |
286 | static const char str[] = "double fault"; | |
287 | struct task_struct *tsk = current; | |
288 | ||
289 | /* Return not checked because double check cannot be ignored */ | |
290 | notify_die(DIE_TRAP, str, regs, error_code, 8, SIGSEGV); | |
291 | ||
292 | tsk->thread.error_code = error_code; | |
293 | tsk->thread.trap_no = 8; | |
294 | ||
bd8b96df IM |
295 | /* |
296 | * This is always a kernel trap and never fixable (and thus must | |
297 | * never return). | |
298 | */ | |
081f75bb AH |
299 | for (;;) |
300 | die(str, regs, error_code); | |
301 | } | |
302 | #endif | |
303 | ||
e407d620 | 304 | dotraplinkage void __kprobes |
13485ab5 | 305 | do_general_protection(struct pt_regs *regs, long error_code) |
1da177e4 | 306 | { |
13485ab5 | 307 | struct task_struct *tsk; |
b5964405 | 308 | |
c6df0d71 AH |
309 | conditional_sti(regs); |
310 | ||
081f75bb | 311 | #ifdef CONFIG_X86_32 |
ae82157b AH |
312 | if (lazy_iobitmap_copy()) { |
313 | /* restart the faulting instruction */ | |
1da177e4 LT |
314 | return; |
315 | } | |
1da177e4 | 316 | |
6b6891f9 | 317 | if (regs->flags & X86_VM_MASK) |
1da177e4 | 318 | goto gp_in_vm86; |
081f75bb | 319 | #endif |
1da177e4 | 320 | |
13485ab5 | 321 | tsk = current; |
717b594a | 322 | if (!user_mode(regs)) |
1da177e4 LT |
323 | goto gp_in_kernel; |
324 | ||
13485ab5 AH |
325 | tsk->thread.error_code = error_code; |
326 | tsk->thread.trap_no = 13; | |
b5964405 | 327 | |
13485ab5 AH |
328 | if (show_unhandled_signals && unhandled_signal(tsk, SIGSEGV) && |
329 | printk_ratelimit()) { | |
abd4f750 | 330 | printk(KERN_INFO |
13485ab5 AH |
331 | "%s[%d] general protection ip:%lx sp:%lx error:%lx", |
332 | tsk->comm, task_pid_nr(tsk), | |
333 | regs->ip, regs->sp, error_code); | |
03252919 AK |
334 | print_vma_addr(" in ", regs->ip); |
335 | printk("\n"); | |
336 | } | |
abd4f750 | 337 | |
13485ab5 | 338 | force_sig(SIGSEGV, tsk); |
1da177e4 LT |
339 | return; |
340 | ||
081f75bb | 341 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
342 | gp_in_vm86: |
343 | local_irq_enable(); | |
344 | handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); | |
345 | return; | |
081f75bb | 346 | #endif |
1da177e4 LT |
347 | |
348 | gp_in_kernel: | |
13485ab5 AH |
349 | if (fixup_exception(regs)) |
350 | return; | |
351 | ||
352 | tsk->thread.error_code = error_code; | |
353 | tsk->thread.trap_no = 13; | |
354 | if (notify_die(DIE_GPF, "general protection fault", regs, | |
1da177e4 | 355 | error_code, 13, SIGSEGV) == NOTIFY_STOP) |
13485ab5 AH |
356 | return; |
357 | die("general protection fault", regs, error_code); | |
1da177e4 LT |
358 | } |
359 | ||
5deb45e3 | 360 | static notrace __kprobes void |
b5964405 | 361 | mem_parity_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 | 362 | { |
b5964405 IM |
363 | printk(KERN_EMERG |
364 | "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", | |
365 | reason, smp_processor_id()); | |
366 | ||
367 | printk(KERN_EMERG | |
368 | "You have some hardware problem, likely on the PCI bus.\n"); | |
c0d12172 DJ |
369 | |
370 | #if defined(CONFIG_EDAC) | |
b5964405 | 371 | if (edac_handler_set()) { |
c0d12172 DJ |
372 | edac_atomic_assert_error(); |
373 | return; | |
374 | } | |
375 | #endif | |
376 | ||
8da5adda | 377 | if (panic_on_unrecovered_nmi) |
b5964405 | 378 | panic("NMI: Not continuing"); |
1da177e4 | 379 | |
c41c5cd3 | 380 | printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); |
1da177e4 LT |
381 | |
382 | /* Clear and disable the memory parity error line. */ | |
7970479c AH |
383 | reason = (reason & 0xf) | 4; |
384 | outb(reason, 0x61); | |
1da177e4 LT |
385 | } |
386 | ||
5deb45e3 | 387 | static notrace __kprobes void |
b5964405 | 388 | io_check_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 LT |
389 | { |
390 | unsigned long i; | |
391 | ||
9c107805 | 392 | printk(KERN_EMERG "NMI: IOCK error (debug interrupt?)\n"); |
1da177e4 LT |
393 | show_registers(regs); |
394 | ||
395 | /* Re-enable the IOCK line, wait for a few seconds */ | |
396 | reason = (reason & 0xf) | 8; | |
397 | outb(reason, 0x61); | |
b5964405 | 398 | |
1da177e4 | 399 | i = 2000; |
b5964405 IM |
400 | while (--i) |
401 | udelay(1000); | |
402 | ||
1da177e4 LT |
403 | reason &= ~8; |
404 | outb(reason, 0x61); | |
405 | } | |
406 | ||
5deb45e3 | 407 | static notrace __kprobes void |
b5964405 | 408 | unknown_nmi_error(unsigned char reason, struct pt_regs *regs) |
1da177e4 | 409 | { |
c1d518c8 AH |
410 | if (notify_die(DIE_NMIUNKNOWN, "nmi", regs, reason, 2, SIGINT) == |
411 | NOTIFY_STOP) | |
d3597524 | 412 | return; |
1da177e4 | 413 | #ifdef CONFIG_MCA |
b5964405 IM |
414 | /* |
415 | * Might actually be able to figure out what the guilty party | |
416 | * is: | |
417 | */ | |
418 | if (MCA_bus) { | |
1da177e4 LT |
419 | mca_handle_nmi(); |
420 | return; | |
421 | } | |
422 | #endif | |
b5964405 IM |
423 | printk(KERN_EMERG |
424 | "Uhhuh. NMI received for unknown reason %02x on CPU %d.\n", | |
425 | reason, smp_processor_id()); | |
426 | ||
c41c5cd3 | 427 | printk(KERN_EMERG "Do you have a strange power saving mode enabled?\n"); |
8da5adda | 428 | if (panic_on_unrecovered_nmi) |
b5964405 | 429 | panic("NMI: Not continuing"); |
8da5adda | 430 | |
c41c5cd3 | 431 | printk(KERN_EMERG "Dazed and confused, but trying to continue\n"); |
1da177e4 LT |
432 | } |
433 | ||
5deb45e3 | 434 | static notrace __kprobes void default_do_nmi(struct pt_regs *regs) |
1da177e4 LT |
435 | { |
436 | unsigned char reason = 0; | |
abd34807 AH |
437 | int cpu; |
438 | ||
439 | cpu = smp_processor_id(); | |
1da177e4 | 440 | |
abd34807 AH |
441 | /* Only the BSP gets external NMIs from the system. */ |
442 | if (!cpu) | |
1da177e4 | 443 | reason = get_nmi_reason(); |
b5964405 | 444 | |
1da177e4 | 445 | if (!(reason & 0xc0)) { |
20c0d2d4 | 446 | if (notify_die(DIE_NMI_IPI, "nmi_ipi", regs, reason, 2, SIGINT) |
a8c1be9d | 447 | == NOTIFY_STOP) |
1da177e4 LT |
448 | return; |
449 | #ifdef CONFIG_X86_LOCAL_APIC | |
450 | /* | |
451 | * Ok, so this is none of the documented NMI sources, | |
452 | * so it must be the NMI watchdog. | |
453 | */ | |
3adbbcce | 454 | if (nmi_watchdog_tick(regs, reason)) |
1da177e4 | 455 | return; |
abd34807 | 456 | if (!do_nmi_callback(regs, cpu)) |
3adbbcce | 457 | unknown_nmi_error(reason, regs); |
b5964405 IM |
458 | #else |
459 | unknown_nmi_error(reason, regs); | |
460 | #endif | |
2fbe7b25 | 461 | |
1da177e4 LT |
462 | return; |
463 | } | |
20c0d2d4 | 464 | if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT) == NOTIFY_STOP) |
1da177e4 | 465 | return; |
a8c1be9d AH |
466 | |
467 | /* AK: following checks seem to be broken on modern chipsets. FIXME */ | |
1da177e4 LT |
468 | if (reason & 0x80) |
469 | mem_parity_error(reason, regs); | |
470 | if (reason & 0x40) | |
471 | io_check_error(reason, regs); | |
081f75bb | 472 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
473 | /* |
474 | * Reassert NMI in case it became active meanwhile | |
b5964405 | 475 | * as it's edge-triggered: |
1da177e4 LT |
476 | */ |
477 | reassert_nmi(); | |
081f75bb | 478 | #endif |
1da177e4 LT |
479 | } |
480 | ||
e407d620 AH |
481 | dotraplinkage notrace __kprobes void |
482 | do_nmi(struct pt_regs *regs, long error_code) | |
1da177e4 | 483 | { |
1da177e4 LT |
484 | nmi_enter(); |
485 | ||
915b0d01 | 486 | inc_irq_stat(__nmi_count); |
1da177e4 | 487 | |
8f4e956b AK |
488 | if (!ignore_nmis) |
489 | default_do_nmi(regs); | |
1da177e4 LT |
490 | |
491 | nmi_exit(); | |
492 | } | |
493 | ||
8f4e956b AK |
494 | void stop_nmi(void) |
495 | { | |
496 | acpi_nmi_disable(); | |
497 | ignore_nmis++; | |
498 | } | |
499 | ||
500 | void restart_nmi(void) | |
501 | { | |
502 | ignore_nmis--; | |
503 | acpi_nmi_enable(); | |
504 | } | |
505 | ||
c1d518c8 | 506 | /* May run on IST stack. */ |
e407d620 | 507 | dotraplinkage void __kprobes do_int3(struct pt_regs *regs, long error_code) |
1da177e4 | 508 | { |
b94da1e4 | 509 | #ifdef CONFIG_KPROBES |
1da177e4 LT |
510 | if (notify_die(DIE_INT3, "int3", regs, error_code, 3, SIGTRAP) |
511 | == NOTIFY_STOP) | |
48c88211 | 512 | return; |
b94da1e4 AH |
513 | #else |
514 | if (notify_die(DIE_TRAP, "int3", regs, error_code, 3, SIGTRAP) | |
515 | == NOTIFY_STOP) | |
516 | return; | |
517 | #endif | |
b5964405 | 518 | |
4915a35e | 519 | preempt_conditional_sti(regs); |
3c1326f8 | 520 | do_trap(3, SIGTRAP, "int3", regs, error_code, NULL); |
4915a35e | 521 | preempt_conditional_cli(regs); |
1da177e4 | 522 | } |
1da177e4 | 523 | |
081f75bb | 524 | #ifdef CONFIG_X86_64 |
bd8b96df IM |
525 | /* |
526 | * Help handler running on IST stack to switch back to user stack | |
527 | * for scheduling or signal handling. The actual stack switch is done in | |
528 | * entry.S | |
529 | */ | |
081f75bb AH |
530 | asmlinkage __kprobes struct pt_regs *sync_regs(struct pt_regs *eregs) |
531 | { | |
532 | struct pt_regs *regs = eregs; | |
533 | /* Did already sync */ | |
534 | if (eregs == (struct pt_regs *)eregs->sp) | |
535 | ; | |
536 | /* Exception from user space */ | |
537 | else if (user_mode(eregs)) | |
538 | regs = task_pt_regs(current); | |
bd8b96df IM |
539 | /* |
540 | * Exception from kernel and interrupts are enabled. Move to | |
541 | * kernel process stack. | |
542 | */ | |
081f75bb AH |
543 | else if (eregs->flags & X86_EFLAGS_IF) |
544 | regs = (struct pt_regs *)(eregs->sp -= sizeof(struct pt_regs)); | |
545 | if (eregs != regs) | |
546 | *regs = *eregs; | |
547 | return regs; | |
548 | } | |
549 | #endif | |
550 | ||
1da177e4 LT |
551 | /* |
552 | * Our handling of the processor debug registers is non-trivial. | |
553 | * We do not clear them on entry and exit from the kernel. Therefore | |
554 | * it is possible to get a watchpoint trap here from inside the kernel. | |
555 | * However, the code in ./ptrace.c has ensured that the user can | |
556 | * only set watchpoints on userspace addresses. Therefore the in-kernel | |
557 | * watchpoint trap can only occur in code which is reading/writing | |
558 | * from user space. Such code must not hold kernel locks (since it | |
559 | * can equally take a page fault), therefore it is safe to call | |
560 | * force_sig_info even though that claims and releases locks. | |
b5964405 | 561 | * |
1da177e4 LT |
562 | * Code in ./signal.c ensures that the debug control register |
563 | * is restored before we deliver any signal, and therefore that | |
564 | * user code runs with the correct debug control register even though | |
565 | * we clear it here. | |
566 | * | |
567 | * Being careful here means that we don't have to be as careful in a | |
568 | * lot of more complicated places (task switching can be a bit lazy | |
569 | * about restoring all the debug state, and ptrace doesn't have to | |
570 | * find every occurrence of the TF bit that could be saved away even | |
571 | * by user code) | |
c1d518c8 AH |
572 | * |
573 | * May run on IST stack. | |
1da177e4 | 574 | */ |
e407d620 | 575 | dotraplinkage void __kprobes do_debug(struct pt_regs *regs, long error_code) |
1da177e4 | 576 | { |
1da177e4 | 577 | struct task_struct *tsk = current; |
3d2a71a5 | 578 | unsigned long condition; |
da654b74 | 579 | int si_code; |
1da177e4 | 580 | |
1cc6f12e | 581 | get_debugreg(condition, 6); |
1da177e4 | 582 | |
10faa81e RM |
583 | /* |
584 | * The processor cleared BTF, so don't mark that we need it set. | |
585 | */ | |
586 | clear_tsk_thread_flag(tsk, TIF_DEBUGCTLMSR); | |
587 | tsk->thread.debugctlmsr = 0; | |
588 | ||
1da177e4 | 589 | if (notify_die(DIE_DEBUG, "debug", regs, condition, error_code, |
a8c1be9d | 590 | SIGTRAP) == NOTIFY_STOP) |
1da177e4 | 591 | return; |
3d2a71a5 | 592 | |
1da177e4 | 593 | /* It's safe to allow irq's after DR6 has been saved */ |
3d2a71a5 | 594 | preempt_conditional_sti(regs); |
1da177e4 LT |
595 | |
596 | /* Mask out spurious debug traps due to lazy DR7 setting */ | |
597 | if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)) { | |
0f534093 | 598 | if (!tsk->thread.debugreg7) |
1da177e4 LT |
599 | goto clear_dr7; |
600 | } | |
601 | ||
081f75bb | 602 | #ifdef CONFIG_X86_32 |
6b6891f9 | 603 | if (regs->flags & X86_VM_MASK) |
1da177e4 | 604 | goto debug_vm86; |
081f75bb | 605 | #endif |
1da177e4 LT |
606 | |
607 | /* Save debug status register where ptrace can see it */ | |
0f534093 | 608 | tsk->thread.debugreg6 = condition; |
1da177e4 LT |
609 | |
610 | /* | |
611 | * Single-stepping through TF: make sure we ignore any events in | |
612 | * kernel space (but re-enable TF when returning to user mode). | |
613 | */ | |
614 | if (condition & DR_STEP) { | |
717b594a | 615 | if (!user_mode(regs)) |
1da177e4 LT |
616 | goto clear_TF_reenable; |
617 | } | |
618 | ||
3d2a71a5 | 619 | si_code = get_si_code(condition); |
1da177e4 | 620 | /* Ok, finally something we can handle */ |
da654b74 | 621 | send_sigtrap(tsk, regs, error_code, si_code); |
1da177e4 | 622 | |
b5964405 IM |
623 | /* |
624 | * Disable additional traps. They'll be re-enabled when | |
1da177e4 LT |
625 | * the signal is delivered. |
626 | */ | |
627 | clear_dr7: | |
1cc6f12e | 628 | set_debugreg(0, 7); |
3d2a71a5 | 629 | preempt_conditional_cli(regs); |
1da177e4 LT |
630 | return; |
631 | ||
081f75bb | 632 | #ifdef CONFIG_X86_32 |
1da177e4 | 633 | debug_vm86: |
be716615 TG |
634 | /* reenable preemption: handle_vm86_trap() might sleep */ |
635 | dec_preempt_count(); | |
1da177e4 | 636 | handle_vm86_trap((struct kernel_vm86_regs *) regs, error_code, 1); |
be716615 | 637 | conditional_cli(regs); |
1da177e4 | 638 | return; |
081f75bb | 639 | #endif |
1da177e4 LT |
640 | |
641 | clear_TF_reenable: | |
642 | set_tsk_thread_flag(tsk, TIF_SINGLESTEP); | |
6093015d | 643 | regs->flags &= ~X86_EFLAGS_TF; |
3d2a71a5 | 644 | preempt_conditional_cli(regs); |
1da177e4 LT |
645 | return; |
646 | } | |
647 | ||
081f75bb AH |
648 | #ifdef CONFIG_X86_64 |
649 | static int kernel_math_error(struct pt_regs *regs, const char *str, int trapnr) | |
650 | { | |
651 | if (fixup_exception(regs)) | |
652 | return 1; | |
653 | ||
654 | notify_die(DIE_GPF, str, regs, 0, trapnr, SIGFPE); | |
655 | /* Illegal floating point operation in the kernel */ | |
656 | current->thread.trap_no = trapnr; | |
657 | die(str, regs, 0); | |
658 | return 0; | |
659 | } | |
660 | #endif | |
661 | ||
1da177e4 LT |
662 | /* |
663 | * Note that we play around with the 'TS' bit in an attempt to get | |
664 | * the correct behaviour even in the presence of the asynchronous | |
665 | * IRQ13 behaviour | |
666 | */ | |
65ea5b03 | 667 | void math_error(void __user *ip) |
1da177e4 | 668 | { |
b5964405 | 669 | struct task_struct *task; |
1da177e4 | 670 | siginfo_t info; |
adf77bac | 671 | unsigned short cwd, swd, err; |
1da177e4 LT |
672 | |
673 | /* | |
674 | * Save the info for the exception handler and clear the error. | |
675 | */ | |
676 | task = current; | |
677 | save_init_fpu(task); | |
678 | task->thread.trap_no = 16; | |
679 | task->thread.error_code = 0; | |
680 | info.si_signo = SIGFPE; | |
681 | info.si_errno = 0; | |
65ea5b03 | 682 | info.si_addr = ip; |
1da177e4 LT |
683 | /* |
684 | * (~cwd & swd) will mask out exceptions that are not set to unmasked | |
685 | * status. 0x3f is the exception bits in these regs, 0x200 is the | |
686 | * C1 reg you need in case of a stack fault, 0x040 is the stack | |
687 | * fault bit. We should only be taking one exception at a time, | |
688 | * so if this combination doesn't produce any single exception, | |
a8c1be9d | 689 | * then we have a bad program that isn't synchronizing its FPU usage |
1da177e4 LT |
690 | * and it will suffer the consequences since we won't be able to |
691 | * fully reproduce the context of the exception | |
692 | */ | |
693 | cwd = get_fpu_cwd(task); | |
694 | swd = get_fpu_swd(task); | |
adf77bac | 695 | |
a73ad333 | 696 | err = swd & ~cwd; |
adf77bac PA |
697 | |
698 | if (err & 0x001) { /* Invalid op */ | |
b5964405 IM |
699 | /* |
700 | * swd & 0x240 == 0x040: Stack Underflow | |
701 | * swd & 0x240 == 0x240: Stack Overflow | |
702 | * User must clear the SF bit (0x40) if set | |
703 | */ | |
704 | info.si_code = FPE_FLTINV; | |
adf77bac | 705 | } else if (err & 0x004) { /* Divide by Zero */ |
b5964405 | 706 | info.si_code = FPE_FLTDIV; |
adf77bac | 707 | } else if (err & 0x008) { /* Overflow */ |
b5964405 | 708 | info.si_code = FPE_FLTOVF; |
adf77bac PA |
709 | } else if (err & 0x012) { /* Denormal, Underflow */ |
710 | info.si_code = FPE_FLTUND; | |
711 | } else if (err & 0x020) { /* Precision */ | |
b5964405 | 712 | info.si_code = FPE_FLTRES; |
adf77bac | 713 | } else { |
bd8b96df IM |
714 | /* |
715 | * If we're using IRQ 13, or supposedly even some trap 16 | |
716 | * implementations, it's possible we get a spurious trap... | |
717 | */ | |
a73ad333 | 718 | return; /* Spurious trap, no error */ |
1da177e4 LT |
719 | } |
720 | force_sig_info(SIGFPE, &info, task); | |
721 | } | |
722 | ||
e407d620 | 723 | dotraplinkage void do_coprocessor_error(struct pt_regs *regs, long error_code) |
1da177e4 | 724 | { |
252d28fe | 725 | conditional_sti(regs); |
081f75bb AH |
726 | |
727 | #ifdef CONFIG_X86_32 | |
1da177e4 | 728 | ignore_fpu_irq = 1; |
081f75bb AH |
729 | #else |
730 | if (!user_mode(regs) && | |
731 | kernel_math_error(regs, "kernel x87 math error", 16)) | |
732 | return; | |
733 | #endif | |
734 | ||
65ea5b03 | 735 | math_error((void __user *)regs->ip); |
1da177e4 LT |
736 | } |
737 | ||
65ea5b03 | 738 | static void simd_math_error(void __user *ip) |
1da177e4 | 739 | { |
b5964405 | 740 | struct task_struct *task; |
b5964405 | 741 | siginfo_t info; |
7b4fd4bb | 742 | unsigned short mxcsr; |
1da177e4 LT |
743 | |
744 | /* | |
745 | * Save the info for the exception handler and clear the error. | |
746 | */ | |
747 | task = current; | |
748 | save_init_fpu(task); | |
749 | task->thread.trap_no = 19; | |
750 | task->thread.error_code = 0; | |
751 | info.si_signo = SIGFPE; | |
752 | info.si_errno = 0; | |
753 | info.si_code = __SI_FAULT; | |
65ea5b03 | 754 | info.si_addr = ip; |
1da177e4 LT |
755 | /* |
756 | * The SIMD FPU exceptions are handled a little differently, as there | |
757 | * is only a single status/control register. Thus, to determine which | |
758 | * unmasked exception was caught we must mask the exception mask bits | |
759 | * at 0x1f80, and then use these to mask the exception bits at 0x3f. | |
760 | */ | |
761 | mxcsr = get_fpu_mxcsr(task); | |
762 | switch (~((mxcsr & 0x1f80) >> 7) & (mxcsr & 0x3f)) { | |
b5964405 IM |
763 | case 0x000: |
764 | default: | |
765 | break; | |
766 | case 0x001: /* Invalid Op */ | |
767 | info.si_code = FPE_FLTINV; | |
768 | break; | |
769 | case 0x002: /* Denormalize */ | |
770 | case 0x010: /* Underflow */ | |
771 | info.si_code = FPE_FLTUND; | |
772 | break; | |
773 | case 0x004: /* Zero Divide */ | |
774 | info.si_code = FPE_FLTDIV; | |
775 | break; | |
776 | case 0x008: /* Overflow */ | |
777 | info.si_code = FPE_FLTOVF; | |
778 | break; | |
779 | case 0x020: /* Precision */ | |
780 | info.si_code = FPE_FLTRES; | |
781 | break; | |
1da177e4 LT |
782 | } |
783 | force_sig_info(SIGFPE, &info, task); | |
784 | } | |
785 | ||
e407d620 AH |
786 | dotraplinkage void |
787 | do_simd_coprocessor_error(struct pt_regs *regs, long error_code) | |
1da177e4 | 788 | { |
b939bde2 AH |
789 | conditional_sti(regs); |
790 | ||
081f75bb | 791 | #ifdef CONFIG_X86_32 |
1da177e4 LT |
792 | if (cpu_has_xmm) { |
793 | /* Handle SIMD FPU exceptions on PIII+ processors. */ | |
794 | ignore_fpu_irq = 1; | |
65ea5b03 | 795 | simd_math_error((void __user *)regs->ip); |
b5964405 IM |
796 | return; |
797 | } | |
798 | /* | |
799 | * Handle strange cache flush from user space exception | |
800 | * in all other cases. This is undocumented behaviour. | |
801 | */ | |
6b6891f9 | 802 | if (regs->flags & X86_VM_MASK) { |
b5964405 IM |
803 | handle_vm86_fault((struct kernel_vm86_regs *)regs, error_code); |
804 | return; | |
1da177e4 | 805 | } |
b5964405 IM |
806 | current->thread.trap_no = 19; |
807 | current->thread.error_code = error_code; | |
808 | die_if_kernel("cache flush denied", regs, error_code); | |
809 | force_sig(SIGSEGV, current); | |
081f75bb AH |
810 | #else |
811 | if (!user_mode(regs) && | |
812 | kernel_math_error(regs, "kernel simd math error", 19)) | |
813 | return; | |
814 | simd_math_error((void __user *)regs->ip); | |
815 | #endif | |
1da177e4 LT |
816 | } |
817 | ||
e407d620 AH |
818 | dotraplinkage void |
819 | do_spurious_interrupt_bug(struct pt_regs *regs, long error_code) | |
1da177e4 | 820 | { |
cf81978d | 821 | conditional_sti(regs); |
1da177e4 LT |
822 | #if 0 |
823 | /* No need to warn about this any longer. */ | |
b5964405 | 824 | printk(KERN_INFO "Ignoring P6 Local APIC Spurious Interrupt Bug...\n"); |
1da177e4 LT |
825 | #endif |
826 | } | |
827 | ||
081f75bb | 828 | #ifdef CONFIG_X86_32 |
b5964405 | 829 | unsigned long patch_espfix_desc(unsigned long uesp, unsigned long kesp) |
1da177e4 | 830 | { |
736f12bf | 831 | struct desc_struct *gdt = get_cpu_gdt_table(smp_processor_id()); |
be44d2aa SS |
832 | unsigned long base = (kesp - uesp) & -THREAD_SIZE; |
833 | unsigned long new_kesp = kesp - base; | |
834 | unsigned long lim_pages = (new_kesp | (THREAD_SIZE - 1)) >> PAGE_SHIFT; | |
835 | __u64 desc = *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS]; | |
b5964405 | 836 | |
be44d2aa | 837 | /* Set up base for espfix segment */ |
b5964405 IM |
838 | desc &= 0x00f0ff0000000000ULL; |
839 | desc |= ((((__u64)base) << 16) & 0x000000ffffff0000ULL) | | |
be44d2aa SS |
840 | ((((__u64)base) << 32) & 0xff00000000000000ULL) | |
841 | ((((__u64)lim_pages) << 32) & 0x000f000000000000ULL) | | |
842 | (lim_pages & 0xffff); | |
843 | *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS] = desc; | |
b5964405 | 844 | |
be44d2aa | 845 | return new_kesp; |
1da177e4 | 846 | } |
081f75bb AH |
847 | #else |
848 | asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void) | |
849 | { | |
850 | } | |
851 | ||
852 | asmlinkage void __attribute__((weak)) mce_threshold_interrupt(void) | |
853 | { | |
854 | } | |
855 | #endif | |
1da177e4 LT |
856 | |
857 | /* | |
b5964405 | 858 | * 'math_state_restore()' saves the current math information in the |
1da177e4 LT |
859 | * old math state array, and gets the new ones from the current task |
860 | * | |
861 | * Careful.. There are problems with IBM-designed IRQ13 behaviour. | |
862 | * Don't touch unless you *really* know how it works. | |
863 | * | |
864 | * Must be called with kernel preemption disabled (in this case, | |
865 | * local interrupts are disabled at the call-site in entry.S). | |
866 | */ | |
acc20761 | 867 | asmlinkage void math_state_restore(void) |
1da177e4 LT |
868 | { |
869 | struct thread_info *thread = current_thread_info(); | |
870 | struct task_struct *tsk = thread->task; | |
871 | ||
aa283f49 SS |
872 | if (!tsk_used_math(tsk)) { |
873 | local_irq_enable(); | |
874 | /* | |
875 | * does a slab alloc which can sleep | |
876 | */ | |
877 | if (init_fpu(tsk)) { | |
878 | /* | |
879 | * ran out of memory! | |
880 | */ | |
881 | do_group_exit(SIGKILL); | |
882 | return; | |
883 | } | |
884 | local_irq_disable(); | |
885 | } | |
886 | ||
b5964405 | 887 | clts(); /* Allow maths ops (or we recurse) */ |
081f75bb | 888 | #ifdef CONFIG_X86_32 |
1da177e4 | 889 | restore_fpu(tsk); |
081f75bb AH |
890 | #else |
891 | /* | |
892 | * Paranoid restore. send a SIGSEGV if we fail to restore the state. | |
893 | */ | |
894 | if (unlikely(restore_fpu_checking(tsk))) { | |
895 | stts(); | |
896 | force_sig(SIGSEGV, tsk); | |
897 | return; | |
898 | } | |
899 | #endif | |
1da177e4 | 900 | thread->status |= TS_USEDFPU; /* So we fnsave on switch_to() */ |
acc20761 | 901 | tsk->fpu_counter++; |
1da177e4 | 902 | } |
5992b6da | 903 | EXPORT_SYMBOL_GPL(math_state_restore); |
1da177e4 LT |
904 | |
905 | #ifndef CONFIG_MATH_EMULATION | |
d315760f | 906 | void math_emulate(struct math_emu_info *info) |
1da177e4 | 907 | { |
b5964405 IM |
908 | printk(KERN_EMERG |
909 | "math-emulation not enabled and no coprocessor found.\n"); | |
910 | printk(KERN_EMERG "killing %s.\n", current->comm); | |
911 | force_sig(SIGFPE, current); | |
1da177e4 LT |
912 | schedule(); |
913 | } | |
1da177e4 LT |
914 | #endif /* CONFIG_MATH_EMULATION */ |
915 | ||
e407d620 | 916 | dotraplinkage void __kprobes |
aa78bcfa | 917 | do_device_not_available(struct pt_regs *regs, long error_code) |
7643e9b9 | 918 | { |
081f75bb | 919 | #ifdef CONFIG_X86_32 |
7643e9b9 | 920 | if (read_cr0() & X86_CR0_EM) { |
d315760f TH |
921 | struct math_emu_info info = { }; |
922 | ||
7643e9b9 | 923 | conditional_sti(regs); |
d315760f | 924 | |
aa78bcfa | 925 | info.regs = regs; |
d315760f | 926 | math_emulate(&info); |
7643e9b9 AH |
927 | } else { |
928 | math_state_restore(); /* interrupts still off */ | |
929 | conditional_sti(regs); | |
930 | } | |
081f75bb AH |
931 | #else |
932 | math_state_restore(); | |
933 | #endif | |
7643e9b9 AH |
934 | } |
935 | ||
081f75bb | 936 | #ifdef CONFIG_X86_32 |
e407d620 | 937 | dotraplinkage void do_iret_error(struct pt_regs *regs, long error_code) |
f8e0870f AH |
938 | { |
939 | siginfo_t info; | |
940 | local_irq_enable(); | |
941 | ||
942 | info.si_signo = SIGILL; | |
943 | info.si_errno = 0; | |
944 | info.si_code = ILL_BADSTK; | |
945 | info.si_addr = 0; | |
946 | if (notify_die(DIE_TRAP, "iret exception", | |
947 | regs, error_code, 32, SIGILL) == NOTIFY_STOP) | |
948 | return; | |
3c1326f8 | 949 | do_trap(32, SIGILL, "iret exception", regs, error_code, &info); |
f8e0870f | 950 | } |
081f75bb | 951 | #endif |
f8e0870f | 952 | |
1da177e4 LT |
953 | void __init trap_init(void) |
954 | { | |
dbeb2be2 RR |
955 | int i; |
956 | ||
1da177e4 | 957 | #ifdef CONFIG_EISA |
927222b1 | 958 | void __iomem *p = early_ioremap(0x0FFFD9, 4); |
b5964405 IM |
959 | |
960 | if (readl(p) == 'E' + ('I'<<8) + ('S'<<16) + ('A'<<24)) | |
1da177e4 | 961 | EISA_bus = 1; |
927222b1 | 962 | early_iounmap(p, 4); |
1da177e4 LT |
963 | #endif |
964 | ||
976382dc | 965 | set_intr_gate(0, ÷_error); |
699d2937 AH |
966 | set_intr_gate_ist(1, &debug, DEBUG_STACK); |
967 | set_intr_gate_ist(2, &nmi, NMI_STACK); | |
968 | /* int3 can be called from all */ | |
969 | set_system_intr_gate_ist(3, &int3, DEBUG_STACK); | |
970 | /* int4 can be called from all */ | |
971 | set_system_intr_gate(4, &overflow); | |
64f644c0 | 972 | set_intr_gate(5, &bounds); |
12394cf5 | 973 | set_intr_gate(6, &invalid_op); |
7643e9b9 | 974 | set_intr_gate(7, &device_not_available); |
081f75bb | 975 | #ifdef CONFIG_X86_32 |
a8c1be9d | 976 | set_task_gate(8, GDT_ENTRY_DOUBLEFAULT_TSS); |
081f75bb AH |
977 | #else |
978 | set_intr_gate_ist(8, &double_fault, DOUBLEFAULT_STACK); | |
979 | #endif | |
51bc1ed6 | 980 | set_intr_gate(9, &coprocessor_segment_overrun); |
6bf77bf9 | 981 | set_intr_gate(10, &invalid_TSS); |
36d936c7 | 982 | set_intr_gate(11, &segment_not_present); |
699d2937 | 983 | set_intr_gate_ist(12, &stack_segment, STACKFAULT_STACK); |
c6df0d71 | 984 | set_intr_gate(13, &general_protection); |
b5964405 | 985 | set_intr_gate(14, &page_fault); |
cf81978d | 986 | set_intr_gate(15, &spurious_interrupt_bug); |
252d28fe | 987 | set_intr_gate(16, &coprocessor_error); |
5feedfd4 | 988 | set_intr_gate(17, &alignment_check); |
1da177e4 | 989 | #ifdef CONFIG_X86_MCE |
699d2937 | 990 | set_intr_gate_ist(18, &machine_check, MCE_STACK); |
1da177e4 | 991 | #endif |
b939bde2 | 992 | set_intr_gate(19, &simd_coprocessor_error); |
1da177e4 | 993 | |
081f75bb AH |
994 | #ifdef CONFIG_IA32_EMULATION |
995 | set_system_intr_gate(IA32_SYSCALL_VECTOR, ia32_syscall); | |
996 | #endif | |
997 | ||
998 | #ifdef CONFIG_X86_32 | |
d43c6e80 | 999 | if (cpu_has_fxsr) { |
d43c6e80 JB |
1000 | printk(KERN_INFO "Enabling fast FPU save and restore... "); |
1001 | set_in_cr4(X86_CR4_OSFXSR); | |
1002 | printk("done.\n"); | |
1003 | } | |
1004 | if (cpu_has_xmm) { | |
b5964405 IM |
1005 | printk(KERN_INFO |
1006 | "Enabling unmasked SIMD FPU exception support... "); | |
d43c6e80 JB |
1007 | set_in_cr4(X86_CR4_OSXMMEXCPT); |
1008 | printk("done.\n"); | |
1009 | } | |
1010 | ||
699d2937 | 1011 | set_system_trap_gate(SYSCALL_VECTOR, &system_call); |
b77b881f | 1012 | #endif |
1da177e4 | 1013 | |
b5964405 | 1014 | /* Reserve all the builtin and the syscall vector: */ |
dbeb2be2 RR |
1015 | for (i = 0; i < FIRST_EXTERNAL_VECTOR; i++) |
1016 | set_bit(i, used_vectors); | |
b5964405 | 1017 | |
b77b881f YL |
1018 | #ifdef CONFIG_X86_64 |
1019 | set_bit(IA32_SYSCALL_VECTOR, used_vectors); | |
1020 | #else | |
dbeb2be2 | 1021 | set_bit(SYSCALL_VECTOR, used_vectors); |
081f75bb | 1022 | #endif |
1da177e4 | 1023 | /* |
b5964405 | 1024 | * Should be a barrier for any external CPU state: |
1da177e4 LT |
1025 | */ |
1026 | cpu_init(); | |
1027 | ||
081f75bb | 1028 | #ifdef CONFIG_X86_32 |
1da177e4 | 1029 | trap_init_hook(); |
081f75bb | 1030 | #endif |
1da177e4 | 1031 | } |