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KVM: Fallback support for MSR_VM_HSAVE_PA
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
043405e1
CO		 39
40#include <asm/uaccess.h>
d825ed0a 41#include <asm/msr.h>
a5f61300 42#include <asm/desc.h>
0bed3b56 43#include <asm/mtrr.h>
043405e1 44
313a3dc7 45#define MAX_IO_MSRS 256
a03490ed
CO		 46#define CR0_RESERVED_BITS \
47 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
48 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
49 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
50#define CR4_RESERVED_BITS \
51 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
52 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
53 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
54 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
55
56#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
50a37eb4
JR		 57/* EFER defaults:
58 * - enable syscall per default because its emulated by KVM
59 * - enable LME and LMA per default on 64 bit KVM
60 */
61#ifdef CONFIG_X86_64
62static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
63#else
64static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
65#endif
313a3dc7 66
ba1389b7
AK		 67#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
68#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 69
674eea0f
AK		 70static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
71 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 72struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
73 u32 function, u32 index);
674eea0f 74
97896d04 75struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 76EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 77
417bc304 78struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 79 { "pf_fixed", VCPU_STAT(pf_fixed) },
80 { "pf_guest", VCPU_STAT(pf_guest) },
81 { "tlb_flush", VCPU_STAT(tlb_flush) },
82 { "invlpg", VCPU_STAT(invlpg) },
83 { "exits", VCPU_STAT(exits) },
84 { "io_exits", VCPU_STAT(io_exits) },
85 { "mmio_exits", VCPU_STAT(mmio_exits) },
86 { "signal_exits", VCPU_STAT(signal_exits) },
87 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 88 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 89 { "halt_exits", VCPU_STAT(halt_exits) },
90 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 91 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7 92 { "request_irq", VCPU_STAT(request_irq_exits) },
c4abb7c9 93 { "request_nmi", VCPU_STAT(request_nmi_exits) },
ba1389b7
AK		 94 { "irq_exits", VCPU_STAT(irq_exits) },
95 { "host_state_reload", VCPU_STAT(host_state_reload) },
96 { "efer_reload", VCPU_STAT(efer_reload) },
97 { "fpu_reload", VCPU_STAT(fpu_reload) },
98 { "insn_emulation", VCPU_STAT(insn_emulation) },
99 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 100 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 101 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 102 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
103 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
104 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
105 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
106 { "mmu_flooded", VM_STAT(mmu_flooded) },
107 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 108 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 109 { "mmu_unsync", VM_STAT(mmu_unsync) },
6cffe8ca 110 { "mmu_unsync_global", VM_STAT(mmu_unsync_global) },
0f74a24c 111 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 112 { "largepages", VM_STAT(lpages) },
417bc304
HB		 113 { NULL }
114};
115
5fb76f9b
CO		 116unsigned long segment_base(u16 selector)
117{
118 struct descriptor_table gdt;
a5f61300 119 struct desc_struct *d;
5fb76f9b
CO		 120 unsigned long table_base;
121 unsigned long v;
122
123 if (selector == 0)
124 return 0;
125
126 asm("sgdt %0" : "=m"(gdt));
127 table_base = gdt.base;
128
129 if (selector & 4) { /* from ldt */
130 u16 ldt_selector;
131
132 asm("sldt %0" : "=g"(ldt_selector));
133 table_base = segment_base(ldt_selector);
134 }
a5f61300
AK		 135 d = (struct desc_struct *)(table_base + (selector & ~7));
136 v = d->base0 | ((unsigned long)d->base1 << 16) |
137 ((unsigned long)d->base2 << 24);
5fb76f9b 138#ifdef CONFIG_X86_64
a5f61300
AK		 139 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
140 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 141#endif
142 return v;
143}
144EXPORT_SYMBOL_GPL(segment_base);
145
6866b83e
CO		 146u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
147{
148 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 149 return vcpu->arch.apic_base;
6866b83e 150 else
ad312c7c 151 return vcpu->arch.apic_base;
6866b83e
CO		 152}
153EXPORT_SYMBOL_GPL(kvm_get_apic_base);
154
155void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
156{
157 /* TODO: reserve bits check */
158 if (irqchip_in_kernel(vcpu->kvm))
159 kvm_lapic_set_base(vcpu, data);
160 else
ad312c7c 161 vcpu->arch.apic_base = data;
6866b83e
CO		 162}
163EXPORT_SYMBOL_GPL(kvm_set_apic_base);
164
298101da
AK		 165void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
166{
ad312c7c
ZX		 167 WARN_ON(vcpu->arch.exception.pending);
168 vcpu->arch.exception.pending = true;
169 vcpu->arch.exception.has_error_code = false;
170 vcpu->arch.exception.nr = nr;
298101da
AK		 171}
172EXPORT_SYMBOL_GPL(kvm_queue_exception);
173
c3c91fee
AK		 174void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
175 u32 error_code)
176{
177 ++vcpu->stat.pf_guest;
d8017474 178
71c4dfaf
JR		 179 if (vcpu->arch.exception.pending) {
180 if (vcpu->arch.exception.nr == PF_VECTOR) {
181 printk(KERN_DEBUG "kvm: inject_page_fault:"
182 " double fault 0x%lx\n", addr);
183 vcpu->arch.exception.nr = DF_VECTOR;
184 vcpu->arch.exception.error_code = 0;
185 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
186 /* triple fault -> shutdown */
187 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
188 }
c3c91fee
AK		 189 return;
190 }
ad312c7c 191 vcpu->arch.cr2 = addr;
c3c91fee
AK		 192 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
193}
194
3419ffc8
SY		 195void kvm_inject_nmi(struct kvm_vcpu *vcpu)
196{
197 vcpu->arch.nmi_pending = 1;
198}
199EXPORT_SYMBOL_GPL(kvm_inject_nmi);
200
298101da
AK		 201void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
202{
ad312c7c
ZX		 203 WARN_ON(vcpu->arch.exception.pending);
204 vcpu->arch.exception.pending = true;
205 vcpu->arch.exception.has_error_code = true;
206 vcpu->arch.exception.nr = nr;
207 vcpu->arch.exception.error_code = error_code;
298101da
AK		 208}
209EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
210
211static void __queue_exception(struct kvm_vcpu *vcpu)
212{
ad312c7c
ZX		 213 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
214 vcpu->arch.exception.has_error_code,
215 vcpu->arch.exception.error_code);
298101da
AK		 216}
217
a03490ed
CO		 218/*
219 * Load the pae pdptrs. Return true is they are all valid.
220 */
221int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
222{
223 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
224 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
225 int i;
226 int ret;
ad312c7c 227 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 228
a03490ed
CO		 229 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
230 offset * sizeof(u64), sizeof(pdpte));
231 if (ret < 0) {
232 ret = 0;
233 goto out;
234 }
235 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
236 if ((pdpte[i] & 1) && (pdpte[i] & 0xfffffff0000001e6ull)) {
237 ret = 0;
238 goto out;
239 }
240 }
241 ret = 1;
242
ad312c7c 243 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
a03490ed 244out:
a03490ed
CO		 245
246 return ret;
247}
cc4b6871 248EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 249
d835dfec
AK		 250static bool pdptrs_changed(struct kvm_vcpu *vcpu)
251{
ad312c7c 252 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 253 bool changed = true;
254 int r;
255
256 if (is_long_mode(vcpu) || !is_pae(vcpu))
257 return false;
258
ad312c7c 259 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 260 if (r < 0)
261 goto out;
ad312c7c 262 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 263out:
d835dfec
AK		 264
265 return changed;
266}
267
2d3ad1f4 268void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 269{
270 if (cr0 & CR0_RESERVED_BITS) {
271 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 272 cr0, vcpu->arch.cr0);
c1a5d4f9 273 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 274 return;
275 }
276
277 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
278 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 279 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 280 return;
281 }
282
283 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
284 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
285 "and a clear PE flag\n");
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
291#ifdef CONFIG_X86_64
ad312c7c 292 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 293 int cs_db, cs_l;
294
295 if (!is_pae(vcpu)) {
296 printk(KERN_DEBUG "set_cr0: #GP, start paging "
297 "in long mode while PAE is disabled\n");
c1a5d4f9 298 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 299 return;
300 }
301 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
302 if (cs_l) {
303 printk(KERN_DEBUG "set_cr0: #GP, start paging "
304 "in long mode while CS.L == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307
308 }
309 } else
310#endif
ad312c7c 311 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 312 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
313 "reserved bits\n");
c1a5d4f9 314 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 315 return;
316 }
317
318 }
319
320 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 321 vcpu->arch.cr0 = cr0;
a03490ed 322
6cffe8ca 323 kvm_mmu_sync_global(vcpu);
a03490ed 324 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 325 return;
326}
2d3ad1f4 327EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 328
2d3ad1f4 329void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 330{
2d3ad1f4 331 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 332 KVMTRACE_1D(LMSW, vcpu,
333 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
334 handler);
a03490ed 335}
2d3ad1f4 336EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 337
2d3ad1f4 338void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed
CO		 339{
340 if (cr4 & CR4_RESERVED_BITS) {
341 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 342 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 343 return;
344 }
345
346 if (is_long_mode(vcpu)) {
347 if (!(cr4 & X86_CR4_PAE)) {
348 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
349 "in long mode\n");
c1a5d4f9 350 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 351 return;
352 }
353 } else if (is_paging(vcpu) && !is_pae(vcpu) && (cr4 & X86_CR4_PAE)
ad312c7c 354 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 355 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 356 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 357 return;
358 }
359
360 if (cr4 & X86_CR4_VMXE) {
361 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 362 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 363 return;
364 }
365 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 366 vcpu->arch.cr4 = cr4;
2f0b3d60 367 vcpu->arch.mmu.base_role.cr4_pge = !!(cr4 & X86_CR4_PGE);
6cffe8ca 368 kvm_mmu_sync_global(vcpu);
a03490ed 369 kvm_mmu_reset_context(vcpu);
a03490ed 370}
2d3ad1f4 371EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 372
2d3ad1f4 373void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 374{
ad312c7c 375 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 376 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 377 kvm_mmu_flush_tlb(vcpu);
378 return;
379 }
380
a03490ed
CO		 381 if (is_long_mode(vcpu)) {
382 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
383 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 384 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 385 return;
386 }
387 } else {
388 if (is_pae(vcpu)) {
389 if (cr3 & CR3_PAE_RESERVED_BITS) {
390 printk(KERN_DEBUG
391 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 392 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 393 return;
394 }
395 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
396 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
397 "reserved bits\n");
c1a5d4f9 398 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 399 return;
400 }
401 }
402 /*
403 * We don't check reserved bits in nonpae mode, because
404 * this isn't enforced, and VMware depends on this.
405 */
406 }
407
a03490ed
CO		 408 /*
409 * Does the new cr3 value map to physical memory? (Note, we
410 * catch an invalid cr3 even in real-mode, because it would
411 * cause trouble later on when we turn on paging anyway.)
412 *
413 * A real CPU would silently accept an invalid cr3 and would
414 * attempt to use it - with largely undefined (and often hard
415 * to debug) behavior on the guest side.
416 */
417 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 418 kvm_inject_gp(vcpu, 0);
a03490ed 419 else {
ad312c7c
ZX		 420 vcpu->arch.cr3 = cr3;
421 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 422 }
a03490ed 423}
2d3ad1f4 424EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 425
2d3ad1f4 426void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 427{
428 if (cr8 & CR8_RESERVED_BITS) {
429 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 430 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 431 return;
432 }
433 if (irqchip_in_kernel(vcpu->kvm))
434 kvm_lapic_set_tpr(vcpu, cr8);
435 else
ad312c7c 436 vcpu->arch.cr8 = cr8;
a03490ed 437}
2d3ad1f4 438EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 439
2d3ad1f4 440unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 441{
442 if (irqchip_in_kernel(vcpu->kvm))
443 return kvm_lapic_get_cr8(vcpu);
444 else
ad312c7c 445 return vcpu->arch.cr8;
a03490ed 446}
2d3ad1f4 447EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 448
d8017474
AG		 449static inline u32 bit(int bitno)
450{
451 return 1 << (bitno & 31);
452}
453
043405e1
CO		 454/*
455 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
456 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
457 *
458 * This list is modified at module load time to reflect the
459 * capabilities of the host cpu.
460 */
461static u32 msrs_to_save[] = {
462 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
463 MSR_K6_STAR,
464#ifdef CONFIG_X86_64
465 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
466#endif
18068523 467 MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 468 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 469};
470
471static unsigned num_msrs_to_save;
472
473static u32 emulated_msrs[] = {
474 MSR_IA32_MISC_ENABLE,
475};
476
15c4a640
CO		 477static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
478{
f2b4b7dd 479 if (efer & efer_reserved_bits) {
15c4a640
CO		 480 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
481 efer);
c1a5d4f9 482 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 483 return;
484 }
485
486 if (is_paging(vcpu)
ad312c7c 487 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 488 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 489 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 490 return;
491 }
492
d8017474
AG		 493 if (efer & EFER_SVME) {
494 struct kvm_cpuid_entry2 *feat;
495
496 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
497 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
498 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
499 kvm_inject_gp(vcpu, 0);
500 return;
501 }
502 }
503
15c4a640
CO		 504 kvm_x86_ops->set_efer(vcpu, efer);
505
506 efer &= ~EFER_LMA;
ad312c7c 507 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 508
ad312c7c 509 vcpu->arch.shadow_efer = efer;
15c4a640
CO		 510}
511
f2b4b7dd
JR		 512void kvm_enable_efer_bits(u64 mask)
513{
514 efer_reserved_bits &= ~mask;
515}
516EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
517
518
15c4a640
CO		 519/*
520 * Writes msr value into into the appropriate "register".
521 * Returns 0 on success, non-0 otherwise.
522 * Assumes vcpu_load() was already called.
523 */
524int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
525{
526 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
527}
528
313a3dc7
CO		 529/*
530 * Adapt set_msr() to msr_io()'s calling convention
531 */
532static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
533{
534 return kvm_set_msr(vcpu, index, *data);
535}
536
18068523
GOC		 537static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
538{
539 static int version;
50d0a0f9
GH		 540 struct pvclock_wall_clock wc;
541 struct timespec now, sys, boot;
18068523
GOC		 542
543 if (!wall_clock)
544 return;
545
546 version++;
547
18068523
GOC		 548 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
549
50d0a0f9
GH		 550 /*
551 * The guest calculates current wall clock time by adding
552 * system time (updated by kvm_write_guest_time below) to the
553 * wall clock specified here. guest system time equals host
554 * system time for us, thus we must fill in host boot time here.
555 */
556 now = current_kernel_time();
557 ktime_get_ts(&sys);
558 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
559
560 wc.sec = boot.tv_sec;
561 wc.nsec = boot.tv_nsec;
562 wc.version = version;
18068523
GOC		 563
564 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
565
566 version++;
567 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 568}
569
50d0a0f9
GH		 570static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
571{
572 uint32_t quotient, remainder;
573
574 /* Don't try to replace with do_div(), this one calculates
575 * "(dividend << 32) / divisor" */
576 __asm__ ( "divl %4"
577 : "=a" (quotient), "=d" (remainder)
578 : "0" (0), "1" (dividend), "r" (divisor) );
579 return quotient;
580}
581
582static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
583{
584 uint64_t nsecs = 1000000000LL;
585 int32_t shift = 0;
586 uint64_t tps64;
587 uint32_t tps32;
588
589 tps64 = tsc_khz * 1000LL;
590 while (tps64 > nsecs*2) {
591 tps64 >>= 1;
592 shift--;
593 }
594
595 tps32 = (uint32_t)tps64;
596 while (tps32 <= (uint32_t)nsecs) {
597 tps32 <<= 1;
598 shift++;
599 }
600
601 hv_clock->tsc_shift = shift;
602 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
603
604 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 605 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 606 hv_clock->tsc_to_system_mul);
607}
608
18068523
GOC		 609static void kvm_write_guest_time(struct kvm_vcpu *v)
610{
611 struct timespec ts;
612 unsigned long flags;
613 struct kvm_vcpu_arch *vcpu = &v->arch;
614 void *shared_kaddr;
615
616 if ((!vcpu->time_page))
617 return;
618
50d0a0f9
GH		 619 if (unlikely(vcpu->hv_clock_tsc_khz != tsc_khz)) {
620 kvm_set_time_scale(tsc_khz, &vcpu->hv_clock);
621 vcpu->hv_clock_tsc_khz = tsc_khz;
622 }
623
18068523
GOC		 624 /* Keep irq disabled to prevent changes to the clock */
625 local_irq_save(flags);
626 kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
627 &vcpu->hv_clock.tsc_timestamp);
628 ktime_get_ts(&ts);
629 local_irq_restore(flags);
630
631 /* With all the info we got, fill in the values */
632
633 vcpu->hv_clock.system_time = ts.tv_nsec +
634 (NSEC_PER_SEC * (u64)ts.tv_sec);
635 /*
636 * The interface expects us to write an even number signaling that the
637 * update is finished. Since the guest won't see the intermediate
50d0a0f9 638 * state, we just increase by 2 at the end.
18068523 639 */
50d0a0f9 640 vcpu->hv_clock.version += 2;
18068523
GOC		 641
642 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
643
644 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 645 sizeof(vcpu->hv_clock));
18068523
GOC		 646
647 kunmap_atomic(shared_kaddr, KM_USER0);
648
649 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
650}
651
9ba075a6
AK		 652static bool msr_mtrr_valid(unsigned msr)
653{
654 switch (msr) {
655 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
656 case MSR_MTRRfix64K_00000:
657 case MSR_MTRRfix16K_80000:
658 case MSR_MTRRfix16K_A0000:
659 case MSR_MTRRfix4K_C0000:
660 case MSR_MTRRfix4K_C8000:
661 case MSR_MTRRfix4K_D0000:
662 case MSR_MTRRfix4K_D8000:
663 case MSR_MTRRfix4K_E0000:
664 case MSR_MTRRfix4K_E8000:
665 case MSR_MTRRfix4K_F0000:
666 case MSR_MTRRfix4K_F8000:
667 case MSR_MTRRdefType:
668 case MSR_IA32_CR_PAT:
669 return true;
670 case 0x2f8:
671 return true;
672 }
673 return false;
674}
675
676static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
677{
0bed3b56
SY		 678 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
679
9ba075a6
AK		 680 if (!msr_mtrr_valid(msr))
681 return 1;
682
0bed3b56
SY		 683 if (msr == MSR_MTRRdefType) {
684 vcpu->arch.mtrr_state.def_type = data;
685 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
686 } else if (msr == MSR_MTRRfix64K_00000)
687 p[0] = data;
688 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
689 p[1 + msr - MSR_MTRRfix16K_80000] = data;
690 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
691 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
692 else if (msr == MSR_IA32_CR_PAT)
693 vcpu->arch.pat = data;
694 else { /* Variable MTRRs */
695 int idx, is_mtrr_mask;
696 u64 *pt;
697
698 idx = (msr - 0x200) / 2;
699 is_mtrr_mask = msr - 0x200 - 2 * idx;
700 if (!is_mtrr_mask)
701 pt =
702 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
703 else
704 pt =
705 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
706 *pt = data;
707 }
708
709 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 710 return 0;
711}
15c4a640
CO		 712
713int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
714{
715 switch (msr) {
15c4a640
CO		 716 case MSR_EFER:
717 set_efer(vcpu, data);
718 break;
15c4a640
CO		 719 case MSR_IA32_MC0_STATUS:
720 pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
b8688d51 721 __func__, data);
15c4a640
CO		 722 break;
723 case MSR_IA32_MCG_STATUS:
724 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
b8688d51 725 __func__, data);
15c4a640 726 break;
c7ac679c
JR		 727 case MSR_IA32_MCG_CTL:
728 pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
b8688d51 729 __func__, data);
c7ac679c 730 break;
b5e2fec0
AG		 731 case MSR_IA32_DEBUGCTLMSR:
732 if (!data) {
733 /* We support the non-activated case already */
734 break;
735 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
736 /* Values other than LBR and BTF are vendor-specific,
737 thus reserved and should throw a #GP */
738 return 1;
739 }
740 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
741 __func__, data);
742 break;
15c4a640
CO		 743 case MSR_IA32_UCODE_REV:
744 case MSR_IA32_UCODE_WRITE:
61a6bd67 745 case MSR_VM_HSAVE_PA:
15c4a640 746 break;
9ba075a6
AK		 747 case 0x200 ... 0x2ff:
748 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 749 case MSR_IA32_APICBASE:
750 kvm_set_apic_base(vcpu, data);
751 break;
752 case MSR_IA32_MISC_ENABLE:
ad312c7c 753 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 754 break;
18068523
GOC		 755 case MSR_KVM_WALL_CLOCK:
756 vcpu->kvm->arch.wall_clock = data;
757 kvm_write_wall_clock(vcpu->kvm, data);
758 break;
759 case MSR_KVM_SYSTEM_TIME: {
760 if (vcpu->arch.time_page) {
761 kvm_release_page_dirty(vcpu->arch.time_page);
762 vcpu->arch.time_page = NULL;
763 }
764
765 vcpu->arch.time = data;
766
767 /* we verify if the enable bit is set... */
768 if (!(data & 1))
769 break;
770
771 /* ...but clean it before doing the actual write */
772 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
773
18068523
GOC		 774 vcpu->arch.time_page =
775 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 776
777 if (is_error_page(vcpu->arch.time_page)) {
778 kvm_release_page_clean(vcpu->arch.time_page);
779 vcpu->arch.time_page = NULL;
780 }
781
782 kvm_write_guest_time(vcpu);
783 break;
784 }
15c4a640 785 default:
565f1fbd 786 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 787 return 1;
788 }
789 return 0;
790}
791EXPORT_SYMBOL_GPL(kvm_set_msr_common);
792
793
794/*
795 * Reads an msr value (of 'msr_index') into 'pdata'.
796 * Returns 0 on success, non-0 otherwise.
797 * Assumes vcpu_load() was already called.
798 */
799int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
800{
801 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
802}
803
9ba075a6
AK		 804static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
805{
0bed3b56
SY		 806 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
807
9ba075a6
AK		 808 if (!msr_mtrr_valid(msr))
809 return 1;
810
0bed3b56
SY		 811 if (msr == MSR_MTRRdefType)
812 *pdata = vcpu->arch.mtrr_state.def_type +
813 (vcpu->arch.mtrr_state.enabled << 10);
814 else if (msr == MSR_MTRRfix64K_00000)
815 *pdata = p[0];
816 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
817 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
818 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
819 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
820 else if (msr == MSR_IA32_CR_PAT)
821 *pdata = vcpu->arch.pat;
822 else { /* Variable MTRRs */
823 int idx, is_mtrr_mask;
824 u64 *pt;
825
826 idx = (msr - 0x200) / 2;
827 is_mtrr_mask = msr - 0x200 - 2 * idx;
828 if (!is_mtrr_mask)
829 pt =
830 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
831 else
832 pt =
833 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
834 *pdata = *pt;
835 }
836
9ba075a6
AK		 837 return 0;
838}
839
15c4a640
CO		 840int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
841{
842 u64 data;
843
844 switch (msr) {
845 case 0xc0010010: /* SYSCFG */
846 case 0xc0010015: /* HWCR */
847 case MSR_IA32_PLATFORM_ID:
848 case MSR_IA32_P5_MC_ADDR:
849 case MSR_IA32_P5_MC_TYPE:
850 case MSR_IA32_MC0_CTL:
851 case MSR_IA32_MCG_STATUS:
852 case MSR_IA32_MCG_CAP:
c7ac679c 853 case MSR_IA32_MCG_CTL:
15c4a640
CO		 854 case MSR_IA32_MC0_MISC:
855 case MSR_IA32_MC0_MISC+4:
856 case MSR_IA32_MC0_MISC+8:
857 case MSR_IA32_MC0_MISC+12:
858 case MSR_IA32_MC0_MISC+16:
a89c1ad2 859 case MSR_IA32_MC0_MISC+20:
15c4a640 860 case MSR_IA32_UCODE_REV:
15c4a640 861 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 862 case MSR_IA32_DEBUGCTLMSR:
863 case MSR_IA32_LASTBRANCHFROMIP:
864 case MSR_IA32_LASTBRANCHTOIP:
865 case MSR_IA32_LASTINTFROMIP:
866 case MSR_IA32_LASTINTTOIP:
61a6bd67 867 case MSR_VM_HSAVE_PA:
15c4a640
CO		 868 data = 0;
869 break;
9ba075a6
AK		 870 case MSR_MTRRcap:
871 data = 0x500 | KVM_NR_VAR_MTRR;
872 break;
873 case 0x200 ... 0x2ff:
874 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 875 case 0xcd: /* fsb frequency */
876 data = 3;
877 break;
878 case MSR_IA32_APICBASE:
879 data = kvm_get_apic_base(vcpu);
880 break;
881 case MSR_IA32_MISC_ENABLE:
ad312c7c 882 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 883 break;
847f0ad8
AG		 884 case MSR_IA32_PERF_STATUS:
885 /* TSC increment by tick */
886 data = 1000ULL;
887 /* CPU multiplier */
888 data |= (((uint64_t)4ULL) << 40);
889 break;
15c4a640 890 case MSR_EFER:
ad312c7c 891 data = vcpu->arch.shadow_efer;
15c4a640 892 break;
18068523
GOC		 893 case MSR_KVM_WALL_CLOCK:
894 data = vcpu->kvm->arch.wall_clock;
895 break;
896 case MSR_KVM_SYSTEM_TIME:
897 data = vcpu->arch.time;
898 break;
15c4a640
CO		 899 default:
900 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
901 return 1;
902 }
903 *pdata = data;
904 return 0;
905}
906EXPORT_SYMBOL_GPL(kvm_get_msr_common);
907
313a3dc7
CO		 908/*
909 * Read or write a bunch of msrs. All parameters are kernel addresses.
910 *
911 * @return number of msrs set successfully.
912 */
913static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
914 struct kvm_msr_entry *entries,
915 int (*do_msr)(struct kvm_vcpu *vcpu,
916 unsigned index, u64 *data))
917{
918 int i;
919
920 vcpu_load(vcpu);
921
3200f405 922 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 923 for (i = 0; i < msrs->nmsrs; ++i)
924 if (do_msr(vcpu, entries[i].index, &entries[i].data))
925 break;
3200f405 926 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 927
928 vcpu_put(vcpu);
929
930 return i;
931}
932
933/*
934 * Read or write a bunch of msrs. Parameters are user addresses.
935 *
936 * @return number of msrs set successfully.
937 */
938static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
939 int (*do_msr)(struct kvm_vcpu *vcpu,
940 unsigned index, u64 *data),
941 int writeback)
942{
943 struct kvm_msrs msrs;
944 struct kvm_msr_entry *entries;
945 int r, n;
946 unsigned size;
947
948 r = -EFAULT;
949 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
950 goto out;
951
952 r = -E2BIG;
953 if (msrs.nmsrs >= MAX_IO_MSRS)
954 goto out;
955
956 r = -ENOMEM;
957 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
958 entries = vmalloc(size);
959 if (!entries)
960 goto out;
961
962 r = -EFAULT;
963 if (copy_from_user(entries, user_msrs->entries, size))
964 goto out_free;
965
966 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
967 if (r < 0)
968 goto out_free;
969
970 r = -EFAULT;
971 if (writeback && copy_to_user(user_msrs->entries, entries, size))
972 goto out_free;
973
974 r = n;
975
976out_free:
977 vfree(entries);
978out:
979 return r;
980}
981
018d00d2
ZX		 982int kvm_dev_ioctl_check_extension(long ext)
983{
984 int r;
985
986 switch (ext) {
987 case KVM_CAP_IRQCHIP:
988 case KVM_CAP_HLT:
989 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 990 case KVM_CAP_SET_TSS_ADDR:
07716717 991 case KVM_CAP_EXT_CPUID:
7837699f 992 case KVM_CAP_PIT:
a28e4f5a 993 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 994 case KVM_CAP_MP_STATE:
ed848624 995 case KVM_CAP_SYNC_MMU:
018d00d2
ZX		 996 r = 1;
997 break;
542472b5
LV		 998 case KVM_CAP_COALESCED_MMIO:
999 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1000 break;
774ead3a
AK		 1001 case KVM_CAP_VAPIC:
1002 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1003 break;
f725230a
AK		 1004 case KVM_CAP_NR_VCPUS:
1005 r = KVM_MAX_VCPUS;
1006 break;
a988b910
AK		 1007 case KVM_CAP_NR_MEMSLOTS:
1008 r = KVM_MEMORY_SLOTS;
1009 break;
2f333bcb
MT		 1010 case KVM_CAP_PV_MMU:
1011 r = !tdp_enabled;
1012 break;
62c476c7 1013 case KVM_CAP_IOMMU:
19de40a8 1014 r = iommu_found();
62c476c7 1015 break;
abe6655d
MT		 1016 case KVM_CAP_CLOCKSOURCE:
1017 r = boot_cpu_has(X86_FEATURE_CONSTANT_TSC);
1018 break;
018d00d2
ZX		 1019 default:
1020 r = 0;
1021 break;
1022 }
1023 return r;
1024
1025}
1026
043405e1
CO		 1027long kvm_arch_dev_ioctl(struct file *filp,
1028 unsigned int ioctl, unsigned long arg)
1029{
1030 void __user *argp = (void __user *)arg;
1031 long r;
1032
1033 switch (ioctl) {
1034 case KVM_GET_MSR_INDEX_LIST: {
1035 struct kvm_msr_list __user *user_msr_list = argp;
1036 struct kvm_msr_list msr_list;
1037 unsigned n;
1038
1039 r = -EFAULT;
1040 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1041 goto out;
1042 n = msr_list.nmsrs;
1043 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1044 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1045 goto out;
1046 r = -E2BIG;
1047 if (n < num_msrs_to_save)
1048 goto out;
1049 r = -EFAULT;
1050 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1051 num_msrs_to_save * sizeof(u32)))
1052 goto out;
1053 if (copy_to_user(user_msr_list->indices
1054 + num_msrs_to_save * sizeof(u32),
1055 &emulated_msrs,
1056 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1057 goto out;
1058 r = 0;
1059 break;
1060 }
674eea0f
AK		 1061 case KVM_GET_SUPPORTED_CPUID: {
1062 struct kvm_cpuid2 __user *cpuid_arg = argp;
1063 struct kvm_cpuid2 cpuid;
1064
1065 r = -EFAULT;
1066 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1067 goto out;
1068 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
1069 cpuid_arg->entries);
1070 if (r)
1071 goto out;
1072
1073 r = -EFAULT;
1074 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1075 goto out;
1076 r = 0;
1077 break;
1078 }
043405e1
CO		 1079 default:
1080 r = -EINVAL;
1081 }
1082out:
1083 return r;
1084}
1085
313a3dc7
CO		 1086void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1087{
1088 kvm_x86_ops->vcpu_load(vcpu, cpu);
18068523 1089 kvm_write_guest_time(vcpu);
313a3dc7
CO		 1090}
1091
1092void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1093{
1094 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1095 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1096}
1097
07716717 1098static int is_efer_nx(void)
313a3dc7
CO		 1099{
1100 u64 efer;
313a3dc7
CO		 1101
1102 rdmsrl(MSR_EFER, efer);
07716717
DK		 1103 return efer & EFER_NX;
1104}
1105
1106static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1107{
1108 int i;
1109 struct kvm_cpuid_entry2 *e, *entry;
1110
313a3dc7 1111 entry = NULL;
ad312c7c
ZX		 1112 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1113 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1114 if (e->function == 0x80000001) {
1115 entry = e;
1116 break;
1117 }
1118 }
07716717 1119 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1120 entry->edx &= ~(1 << 20);
1121 printk(KERN_INFO "kvm: guest NX capability removed\n");
1122 }
1123}
1124
07716717 1125/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1126static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1127 struct kvm_cpuid *cpuid,
1128 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1129{
1130 int r, i;
1131 struct kvm_cpuid_entry *cpuid_entries;
1132
1133 r = -E2BIG;
1134 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1135 goto out;
1136 r = -ENOMEM;
1137 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1138 if (!cpuid_entries)
1139 goto out;
1140 r = -EFAULT;
1141 if (copy_from_user(cpuid_entries, entries,
1142 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1143 goto out_free;
1144 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1145 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1146 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1147 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1148 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1149 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1150 vcpu->arch.cpuid_entries[i].index = 0;
1151 vcpu->arch.cpuid_entries[i].flags = 0;
1152 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1153 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1154 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1155 }
1156 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1157 cpuid_fix_nx_cap(vcpu);
1158 r = 0;
1159
1160out_free:
1161 vfree(cpuid_entries);
1162out:
1163 return r;
1164}
1165
1166static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
1167 struct kvm_cpuid2 *cpuid,
1168 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1169{
1170 int r;
1171
1172 r = -E2BIG;
1173 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1174 goto out;
1175 r = -EFAULT;
ad312c7c 1176 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1177 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1178 goto out;
ad312c7c 1179 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1180 return 0;
1181
1182out:
1183 return r;
1184}
1185
07716717
DK		 1186static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
1187 struct kvm_cpuid2 *cpuid,
1188 struct kvm_cpuid_entry2 __user *entries)
1189{
1190 int r;
1191
1192 r = -E2BIG;
ad312c7c 1193 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1194 goto out;
1195 r = -EFAULT;
ad312c7c
ZX		 1196 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
1197 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1198 goto out;
1199 return 0;
1200
1201out:
ad312c7c 1202 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1203 return r;
1204}
1205
07716717
DK		 1206static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1207 u32 index)
1208{
1209 entry->function = function;
1210 entry->index = index;
1211 cpuid_count(entry->function, entry->index,
1212 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
1213 entry->flags = 0;
1214}
1215
1216static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1217 u32 index, int *nent, int maxnent)
1218{
1219 const u32 kvm_supported_word0_x86_features = bit(X86_FEATURE_FPU) |
1220 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1221 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1222 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1223 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1224 bit(X86_FEATURE_SEP) | bit(X86_FEATURE_PGE) |
1225 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1226 bit(X86_FEATURE_CLFLSH) | bit(X86_FEATURE_MMX) |
1227 bit(X86_FEATURE_FXSR) | bit(X86_FEATURE_XMM) |
1228 bit(X86_FEATURE_XMM2) | bit(X86_FEATURE_SELFSNOOP);
1229 const u32 kvm_supported_word1_x86_features = bit(X86_FEATURE_FPU) |
1230 bit(X86_FEATURE_VME) | bit(X86_FEATURE_DE) |
1231 bit(X86_FEATURE_PSE) | bit(X86_FEATURE_TSC) |
1232 bit(X86_FEATURE_MSR) | bit(X86_FEATURE_PAE) |
1233 bit(X86_FEATURE_CX8) | bit(X86_FEATURE_APIC) |
1234 bit(X86_FEATURE_PGE) |
1235 bit(X86_FEATURE_CMOV) | bit(X86_FEATURE_PSE36) |
1236 bit(X86_FEATURE_MMX) | bit(X86_FEATURE_FXSR) |
1237 bit(X86_FEATURE_SYSCALL) |
1238 (bit(X86_FEATURE_NX) && is_efer_nx()) |
1239#ifdef CONFIG_X86_64
1240 bit(X86_FEATURE_LM) |
1241#endif
1242 bit(X86_FEATURE_MMXEXT) |
1243 bit(X86_FEATURE_3DNOWEXT) |
1244 bit(X86_FEATURE_3DNOW);
1245 const u32 kvm_supported_word3_x86_features =
1246 bit(X86_FEATURE_XMM3) | bit(X86_FEATURE_CX16);
1247 const u32 kvm_supported_word6_x86_features =
d8017474
AG		 1248 bit(X86_FEATURE_LAHF_LM) | bit(X86_FEATURE_CMP_LEGACY) |
1249 bit(X86_FEATURE_SVM);
07716717
DK		 1250
1251 /* all func 2 cpuid_count() should be called on the same cpu */
1252 get_cpu();
1253 do_cpuid_1_ent(entry, function, index);
1254 ++*nent;
1255
1256 switch (function) {
1257 case 0:
1258 entry->eax = min(entry->eax, (u32)0xb);
1259 break;
1260 case 1:
1261 entry->edx &= kvm_supported_word0_x86_features;
1262 entry->ecx &= kvm_supported_word3_x86_features;
1263 break;
1264 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1265 * may return different values. This forces us to get_cpu() before
1266 * issuing the first command, and also to emulate this annoying behavior
1267 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1268 case 2: {
1269 int t, times = entry->eax & 0xff;
1270
1271 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1272 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1273 for (t = 1; t < times && *nent < maxnent; ++t) {
1274 do_cpuid_1_ent(&entry[t], function, 0);
1275 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1276 ++*nent;
1277 }
1278 break;
1279 }
1280 /* function 4 and 0xb have additional index. */
1281 case 4: {
14af3f3c 1282 int i, cache_type;
07716717
DK		 1283
1284 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1285 /* read more entries until cache_type is zero */
14af3f3c
HH		 1286 for (i = 1; *nent < maxnent; ++i) {
1287 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1288 if (!cache_type)
1289 break;
14af3f3c
HH		 1290 do_cpuid_1_ent(&entry[i], function, i);
1291 entry[i].flags |=
07716717
DK		 1292 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1293 ++*nent;
1294 }
1295 break;
1296 }
1297 case 0xb: {
14af3f3c 1298 int i, level_type;
07716717
DK		 1299
1300 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1301 /* read more entries until level_type is zero */
14af3f3c 1302 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1303 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1304 if (!level_type)
1305 break;
14af3f3c
HH		 1306 do_cpuid_1_ent(&entry[i], function, i);
1307 entry[i].flags |=
07716717
DK		 1308 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1309 ++*nent;
1310 }
1311 break;
1312 }
1313 case 0x80000000:
1314 entry->eax = min(entry->eax, 0x8000001a);
1315 break;
1316 case 0x80000001:
1317 entry->edx &= kvm_supported_word1_x86_features;
1318 entry->ecx &= kvm_supported_word6_x86_features;
1319 break;
1320 }
1321 put_cpu();
1322}
1323
674eea0f 1324static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
07716717
DK		 1325 struct kvm_cpuid_entry2 __user *entries)
1326{
1327 struct kvm_cpuid_entry2 *cpuid_entries;
1328 int limit, nent = 0, r = -E2BIG;
1329 u32 func;
1330
1331 if (cpuid->nent < 1)
1332 goto out;
1333 r = -ENOMEM;
1334 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1335 if (!cpuid_entries)
1336 goto out;
1337
1338 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1339 limit = cpuid_entries[0].eax;
1340 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1341 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1342 &nent, cpuid->nent);
1343 r = -E2BIG;
1344 if (nent >= cpuid->nent)
1345 goto out_free;
1346
1347 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1348 limit = cpuid_entries[nent - 1].eax;
1349 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1350 do_cpuid_ent(&cpuid_entries[nent], func, 0,
1351 &nent, cpuid->nent);
1352 r = -EFAULT;
1353 if (copy_to_user(entries, cpuid_entries,
1354 nent * sizeof(struct kvm_cpuid_entry2)))
1355 goto out_free;
1356 cpuid->nent = nent;
1357 r = 0;
1358
1359out_free:
1360 vfree(cpuid_entries);
1361out:
1362 return r;
1363}
1364
313a3dc7
CO		 1365static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1366 struct kvm_lapic_state *s)
1367{
1368 vcpu_load(vcpu);
ad312c7c 1369 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1370 vcpu_put(vcpu);
1371
1372 return 0;
1373}
1374
1375static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1376 struct kvm_lapic_state *s)
1377{
1378 vcpu_load(vcpu);
ad312c7c 1379 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1380 kvm_apic_post_state_restore(vcpu);
1381 vcpu_put(vcpu);
1382
1383 return 0;
1384}
1385
f77bc6a4
ZX		 1386static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1387 struct kvm_interrupt *irq)
1388{
1389 if (irq->irq < 0 || irq->irq >= 256)
1390 return -EINVAL;
1391 if (irqchip_in_kernel(vcpu->kvm))
1392 return -ENXIO;
1393 vcpu_load(vcpu);
1394
ad312c7c
ZX		 1395 set_bit(irq->irq, vcpu->arch.irq_pending);
1396 set_bit(irq->irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
f77bc6a4
ZX		 1397
1398 vcpu_put(vcpu);
1399
1400 return 0;
1401}
1402
c4abb7c9
JK		 1403static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1404{
1405 vcpu_load(vcpu);
1406 kvm_inject_nmi(vcpu);
1407 vcpu_put(vcpu);
1408
1409 return 0;
1410}
1411
b209749f
AK		 1412static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1413 struct kvm_tpr_access_ctl *tac)
1414{
1415 if (tac->flags)
1416 return -EINVAL;
1417 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1418 return 0;
1419}
1420
313a3dc7
CO		 1421long kvm_arch_vcpu_ioctl(struct file *filp,
1422 unsigned int ioctl, unsigned long arg)
1423{
1424 struct kvm_vcpu *vcpu = filp->private_data;
1425 void __user *argp = (void __user *)arg;
1426 int r;
b772ff36 1427 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1428
1429 switch (ioctl) {
1430 case KVM_GET_LAPIC: {
b772ff36 1431 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1432
b772ff36
DH		 1433 r = -ENOMEM;
1434 if (!lapic)
1435 goto out;
1436 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1437 if (r)
1438 goto out;
1439 r = -EFAULT;
b772ff36 1440 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1441 goto out;
1442 r = 0;
1443 break;
1444 }
1445 case KVM_SET_LAPIC: {
b772ff36
DH		 1446 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1447 r = -ENOMEM;
1448 if (!lapic)
1449 goto out;
313a3dc7 1450 r = -EFAULT;
b772ff36 1451 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1452 goto out;
b772ff36 1453 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1454 if (r)
1455 goto out;
1456 r = 0;
1457 break;
1458 }
f77bc6a4
ZX		 1459 case KVM_INTERRUPT: {
1460 struct kvm_interrupt irq;
1461
1462 r = -EFAULT;
1463 if (copy_from_user(&irq, argp, sizeof irq))
1464 goto out;
1465 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1466 if (r)
1467 goto out;
1468 r = 0;
1469 break;
1470 }
c4abb7c9
JK		 1471 case KVM_NMI: {
1472 r = kvm_vcpu_ioctl_nmi(vcpu);
1473 if (r)
1474 goto out;
1475 r = 0;
1476 break;
1477 }
313a3dc7
CO		 1478 case KVM_SET_CPUID: {
1479 struct kvm_cpuid __user *cpuid_arg = argp;
1480 struct kvm_cpuid cpuid;
1481
1482 r = -EFAULT;
1483 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1484 goto out;
1485 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1486 if (r)
1487 goto out;
1488 break;
1489 }
07716717
DK		 1490 case KVM_SET_CPUID2: {
1491 struct kvm_cpuid2 __user *cpuid_arg = argp;
1492 struct kvm_cpuid2 cpuid;
1493
1494 r = -EFAULT;
1495 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1496 goto out;
1497 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
1498 cpuid_arg->entries);
1499 if (r)
1500 goto out;
1501 break;
1502 }
1503 case KVM_GET_CPUID2: {
1504 struct kvm_cpuid2 __user *cpuid_arg = argp;
1505 struct kvm_cpuid2 cpuid;
1506
1507 r = -EFAULT;
1508 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1509 goto out;
1510 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
1511 cpuid_arg->entries);
1512 if (r)
1513 goto out;
1514 r = -EFAULT;
1515 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1516 goto out;
1517 r = 0;
1518 break;
1519 }
313a3dc7
CO		 1520 case KVM_GET_MSRS:
1521 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1522 break;
1523 case KVM_SET_MSRS:
1524 r = msr_io(vcpu, argp, do_set_msr, 0);
1525 break;
b209749f
AK		 1526 case KVM_TPR_ACCESS_REPORTING: {
1527 struct kvm_tpr_access_ctl tac;
1528
1529 r = -EFAULT;
1530 if (copy_from_user(&tac, argp, sizeof tac))
1531 goto out;
1532 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1533 if (r)
1534 goto out;
1535 r = -EFAULT;
1536 if (copy_to_user(argp, &tac, sizeof tac))
1537 goto out;
1538 r = 0;
1539 break;
1540 };
b93463aa
AK		 1541 case KVM_SET_VAPIC_ADDR: {
1542 struct kvm_vapic_addr va;
1543
1544 r = -EINVAL;
1545 if (!irqchip_in_kernel(vcpu->kvm))
1546 goto out;
1547 r = -EFAULT;
1548 if (copy_from_user(&va, argp, sizeof va))
1549 goto out;
1550 r = 0;
1551 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1552 break;
1553 }
313a3dc7
CO		 1554 default:
1555 r = -EINVAL;
1556 }
1557out:
b772ff36
DH		 1558 if (lapic)
1559 kfree(lapic);
313a3dc7
CO		 1560 return r;
1561}
1562
1fe779f8
CO		 1563static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1564{
1565 int ret;
1566
1567 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1568 return -1;
1569 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1570 return ret;
1571}
1572
1573static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1574 u32 kvm_nr_mmu_pages)
1575{
1576 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1577 return -EINVAL;
1578
72dc67a6 1579 down_write(&kvm->slots_lock);
1fe779f8
CO		 1580
1581 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1582 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1583
72dc67a6 1584 up_write(&kvm->slots_lock);
1fe779f8
CO		 1585 return 0;
1586}
1587
1588static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1589{
f05e70ac 1590 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1591}
1592
e9f85cde
ZX		 1593gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1594{
1595 int i;
1596 struct kvm_mem_alias *alias;
1597
d69fb81f
ZX		 1598 for (i = 0; i < kvm->arch.naliases; ++i) {
1599 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1600 if (gfn >= alias->base_gfn
1601 && gfn < alias->base_gfn + alias->npages)
1602 return alias->target_gfn + gfn - alias->base_gfn;
1603 }
1604 return gfn;
1605}
1606
1fe779f8
CO		 1607/*
1608 * Set a new alias region. Aliases map a portion of physical memory into
1609 * another portion. This is useful for memory windows, for example the PC
1610 * VGA region.
1611 */
1612static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1613 struct kvm_memory_alias *alias)
1614{
1615 int r, n;
1616 struct kvm_mem_alias *p;
1617
1618 r = -EINVAL;
1619 /* General sanity checks */
1620 if (alias->memory_size & (PAGE_SIZE - 1))
1621 goto out;
1622 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1623 goto out;
1624 if (alias->slot >= KVM_ALIAS_SLOTS)
1625 goto out;
1626 if (alias->guest_phys_addr + alias->memory_size
1627 < alias->guest_phys_addr)
1628 goto out;
1629 if (alias->target_phys_addr + alias->memory_size
1630 < alias->target_phys_addr)
1631 goto out;
1632
72dc67a6 1633 down_write(&kvm->slots_lock);
a1708ce8 1634 spin_lock(&kvm->mmu_lock);
1fe779f8 1635
d69fb81f 1636 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1637 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1638 p->npages = alias->memory_size >> PAGE_SHIFT;
1639 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1640
1641 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1642 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1643 break;
d69fb81f 1644 kvm->arch.naliases = n;
1fe779f8 1645
a1708ce8 1646 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1647 kvm_mmu_zap_all(kvm);
1648
72dc67a6 1649 up_write(&kvm->slots_lock);
1fe779f8
CO		 1650
1651 return 0;
1652
1653out:
1654 return r;
1655}
1656
1657static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1658{
1659 int r;
1660
1661 r = 0;
1662 switch (chip->chip_id) {
1663 case KVM_IRQCHIP_PIC_MASTER:
1664 memcpy(&chip->chip.pic,
1665 &pic_irqchip(kvm)->pics[0],
1666 sizeof(struct kvm_pic_state));
1667 break;
1668 case KVM_IRQCHIP_PIC_SLAVE:
1669 memcpy(&chip->chip.pic,
1670 &pic_irqchip(kvm)->pics[1],
1671 sizeof(struct kvm_pic_state));
1672 break;
1673 case KVM_IRQCHIP_IOAPIC:
1674 memcpy(&chip->chip.ioapic,
1675 ioapic_irqchip(kvm),
1676 sizeof(struct kvm_ioapic_state));
1677 break;
1678 default:
1679 r = -EINVAL;
1680 break;
1681 }
1682 return r;
1683}
1684
1685static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1686{
1687 int r;
1688
1689 r = 0;
1690 switch (chip->chip_id) {
1691 case KVM_IRQCHIP_PIC_MASTER:
1692 memcpy(&pic_irqchip(kvm)->pics[0],
1693 &chip->chip.pic,
1694 sizeof(struct kvm_pic_state));
1695 break;
1696 case KVM_IRQCHIP_PIC_SLAVE:
1697 memcpy(&pic_irqchip(kvm)->pics[1],
1698 &chip->chip.pic,
1699 sizeof(struct kvm_pic_state));
1700 break;
1701 case KVM_IRQCHIP_IOAPIC:
1702 memcpy(ioapic_irqchip(kvm),
1703 &chip->chip.ioapic,
1704 sizeof(struct kvm_ioapic_state));
1705 break;
1706 default:
1707 r = -EINVAL;
1708 break;
1709 }
1710 kvm_pic_update_irq(pic_irqchip(kvm));
1711 return r;
1712}
1713
e0f63cb9
SY		 1714static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1715{
1716 int r = 0;
1717
1718 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
1719 return r;
1720}
1721
1722static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
1723{
1724 int r = 0;
1725
1726 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
1727 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
1728 return r;
1729}
1730
5bb064dc
ZX		 1731/*
1732 * Get (and clear) the dirty memory log for a memory slot.
1733 */
1734int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
1735 struct kvm_dirty_log *log)
1736{
1737 int r;
1738 int n;
1739 struct kvm_memory_slot *memslot;
1740 int is_dirty = 0;
1741
72dc67a6 1742 down_write(&kvm->slots_lock);
5bb064dc
ZX		 1743
1744 r = kvm_get_dirty_log(kvm, log, &is_dirty);
1745 if (r)
1746 goto out;
1747
1748 /* If nothing is dirty, don't bother messing with page tables. */
1749 if (is_dirty) {
1750 kvm_mmu_slot_remove_write_access(kvm, log->slot);
1751 kvm_flush_remote_tlbs(kvm);
1752 memslot = &kvm->memslots[log->slot];
1753 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
1754 memset(memslot->dirty_bitmap, 0, n);
1755 }
1756 r = 0;
1757out:
72dc67a6 1758 up_write(&kvm->slots_lock);
5bb064dc
ZX		 1759 return r;
1760}
1761
1fe779f8
CO		 1762long kvm_arch_vm_ioctl(struct file *filp,
1763 unsigned int ioctl, unsigned long arg)
1764{
1765 struct kvm *kvm = filp->private_data;
1766 void __user *argp = (void __user *)arg;
1767 int r = -EINVAL;
f0d66275
DH		 1768 /*
1769 * This union makes it completely explicit to gcc-3.x
1770 * that these two variables' stack usage should be
1771 * combined, not added together.
1772 */
1773 union {
1774 struct kvm_pit_state ps;
1775 struct kvm_memory_alias alias;
1776 } u;
1fe779f8
CO		 1777
1778 switch (ioctl) {
1779 case KVM_SET_TSS_ADDR:
1780 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1781 if (r < 0)
1782 goto out;
1783 break;
1784 case KVM_SET_MEMORY_REGION: {
1785 struct kvm_memory_region kvm_mem;
1786 struct kvm_userspace_memory_region kvm_userspace_mem;
1787
1788 r = -EFAULT;
1789 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
1790 goto out;
1791 kvm_userspace_mem.slot = kvm_mem.slot;
1792 kvm_userspace_mem.flags = kvm_mem.flags;
1793 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
1794 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
1795 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
1796 if (r)
1797 goto out;
1798 break;
1799 }
1800 case KVM_SET_NR_MMU_PAGES:
1801 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1802 if (r)
1803 goto out;
1804 break;
1805 case KVM_GET_NR_MMU_PAGES:
1806 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
1807 break;
f0d66275 1808 case KVM_SET_MEMORY_ALIAS:
1fe779f8 1809 r = -EFAULT;
f0d66275 1810 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 1811 goto out;
f0d66275 1812 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 1813 if (r)
1814 goto out;
1815 break;
1fe779f8
CO		 1816 case KVM_CREATE_IRQCHIP:
1817 r = -ENOMEM;
d7deeeb0
ZX		 1818 kvm->arch.vpic = kvm_create_pic(kvm);
1819 if (kvm->arch.vpic) {
1fe779f8
CO		 1820 r = kvm_ioapic_init(kvm);
1821 if (r) {
d7deeeb0
ZX		 1822 kfree(kvm->arch.vpic);
1823 kvm->arch.vpic = NULL;
1fe779f8
CO		 1824 goto out;
1825 }
1826 } else
1827 goto out;
1828 break;
7837699f
SY		 1829 case KVM_CREATE_PIT:
1830 r = -ENOMEM;
1831 kvm->arch.vpit = kvm_create_pit(kvm);
1832 if (kvm->arch.vpit)
1833 r = 0;
1834 break;
1fe779f8
CO		 1835 case KVM_IRQ_LINE: {
1836 struct kvm_irq_level irq_event;
1837
1838 r = -EFAULT;
1839 if (copy_from_user(&irq_event, argp, sizeof irq_event))
1840 goto out;
1841 if (irqchip_in_kernel(kvm)) {
1842 mutex_lock(&kvm->lock);
5550af4d
SY		 1843 kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
1844 irq_event.irq, irq_event.level);
1fe779f8
CO		 1845 mutex_unlock(&kvm->lock);
1846 r = 0;
1847 }
1848 break;
1849 }
1850 case KVM_GET_IRQCHIP: {
1851 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1852 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1853
f0d66275
DH		 1854 r = -ENOMEM;
1855 if (!chip)
1fe779f8 1856 goto out;
f0d66275
DH		 1857 r = -EFAULT;
1858 if (copy_from_user(chip, argp, sizeof *chip))
1859 goto get_irqchip_out;
1fe779f8
CO		 1860 r = -ENXIO;
1861 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1862 goto get_irqchip_out;
1863 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 1864 if (r)
f0d66275 1865 goto get_irqchip_out;
1fe779f8 1866 r = -EFAULT;
f0d66275
DH		 1867 if (copy_to_user(argp, chip, sizeof *chip))
1868 goto get_irqchip_out;
1fe779f8 1869 r = 0;
f0d66275
DH		 1870 get_irqchip_out:
1871 kfree(chip);
1872 if (r)
1873 goto out;
1fe779f8
CO		 1874 break;
1875 }
1876 case KVM_SET_IRQCHIP: {
1877 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 1878 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 1879
f0d66275
DH		 1880 r = -ENOMEM;
1881 if (!chip)
1fe779f8 1882 goto out;
f0d66275
DH		 1883 r = -EFAULT;
1884 if (copy_from_user(chip, argp, sizeof *chip))
1885 goto set_irqchip_out;
1fe779f8
CO		 1886 r = -ENXIO;
1887 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 1888 goto set_irqchip_out;
1889 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 1890 if (r)
f0d66275 1891 goto set_irqchip_out;
1fe779f8 1892 r = 0;
f0d66275
DH		 1893 set_irqchip_out:
1894 kfree(chip);
1895 if (r)
1896 goto out;
1fe779f8
CO		 1897 break;
1898 }
e0f63cb9 1899 case KVM_GET_PIT: {
e0f63cb9 1900 r = -EFAULT;
f0d66275 1901 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1902 goto out;
1903 r = -ENXIO;
1904 if (!kvm->arch.vpit)
1905 goto out;
f0d66275 1906 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 1907 if (r)
1908 goto out;
1909 r = -EFAULT;
f0d66275 1910 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 1911 goto out;
1912 r = 0;
1913 break;
1914 }
1915 case KVM_SET_PIT: {
e0f63cb9 1916 r = -EFAULT;
f0d66275 1917 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 1918 goto out;
1919 r = -ENXIO;
1920 if (!kvm->arch.vpit)
1921 goto out;
f0d66275 1922 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 1923 if (r)
1924 goto out;
1925 r = 0;
1926 break;
1927 }
1fe779f8
CO		 1928 default:
1929 ;
1930 }
1931out:
1932 return r;
1933}
1934
a16b043c 1935static void kvm_init_msr_list(void)
043405e1
CO		 1936{
1937 u32 dummy[2];
1938 unsigned i, j;
1939
1940 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
1941 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
1942 continue;
1943 if (j < i)
1944 msrs_to_save[j] = msrs_to_save[i];
1945 j++;
1946 }
1947 num_msrs_to_save = j;
1948}
1949
bbd9b64e
CO		 1950/*
1951 * Only apic need an MMIO device hook, so shortcut now..
1952 */
1953static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1954 gpa_t addr, int len,
1955 int is_write)
bbd9b64e
CO		 1956{
1957 struct kvm_io_device *dev;
1958
ad312c7c
ZX		 1959 if (vcpu->arch.apic) {
1960 dev = &vcpu->arch.apic->dev;
92760499 1961 if (dev->in_range(dev, addr, len, is_write))
bbd9b64e
CO		 1962 return dev;
1963 }
1964 return NULL;
1965}
1966
1967
1968static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 1969 gpa_t addr, int len,
1970 int is_write)
bbd9b64e
CO		 1971{
1972 struct kvm_io_device *dev;
1973
92760499 1974 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 1975 if (dev == NULL)
92760499
LV		 1976 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
1977 is_write);
bbd9b64e
CO		 1978 return dev;
1979}
1980
77c2002e
IE		 1981int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
1982 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 1983{
1984 void *data = val;
10589a46 1985 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 1986
1987 while (bytes) {
ad312c7c 1988 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 1989 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 1990 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 1991 int ret;
1992
10589a46
MT		 1993 if (gpa == UNMAPPED_GVA) {
1994 r = X86EMUL_PROPAGATE_FAULT;
1995 goto out;
1996 }
77c2002e 1997 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 1998 if (ret < 0) {
1999 r = X86EMUL_UNHANDLEABLE;
2000 goto out;
2001 }
bbd9b64e 2002
77c2002e
IE		 2003 bytes -= toread;
2004 data += toread;
2005 addr += toread;
bbd9b64e 2006 }
10589a46 2007out:
10589a46 2008 return r;
bbd9b64e 2009}
77c2002e
IE		 2010
2011int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2012 struct kvm_vcpu *vcpu)
2013{
2014 void *data = val;
2015 int r = X86EMUL_CONTINUE;
2016
2017 while (bytes) {
2018 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2019 unsigned offset = addr & (PAGE_SIZE-1);
2020 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2021 int ret;
2022
2023 if (gpa == UNMAPPED_GVA) {
2024 r = X86EMUL_PROPAGATE_FAULT;
2025 goto out;
2026 }
2027 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2028 if (ret < 0) {
2029 r = X86EMUL_UNHANDLEABLE;
2030 goto out;
2031 }
2032
2033 bytes -= towrite;
2034 data += towrite;
2035 addr += towrite;
2036 }
2037out:
2038 return r;
2039}
2040
bbd9b64e 2041
bbd9b64e
CO		 2042static int emulator_read_emulated(unsigned long addr,
2043 void *val,
2044 unsigned int bytes,
2045 struct kvm_vcpu *vcpu)
2046{
2047 struct kvm_io_device *mmio_dev;
2048 gpa_t gpa;
2049
2050 if (vcpu->mmio_read_completed) {
2051 memcpy(val, vcpu->mmio_data, bytes);
2052 vcpu->mmio_read_completed = 0;
2053 return X86EMUL_CONTINUE;
2054 }
2055
ad312c7c 2056 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2057
2058 /* For APIC access vmexit */
2059 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2060 goto mmio;
2061
77c2002e
IE		 2062 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2063 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2064 return X86EMUL_CONTINUE;
2065 if (gpa == UNMAPPED_GVA)
2066 return X86EMUL_PROPAGATE_FAULT;
2067
2068mmio:
2069 /*
2070 * Is this MMIO handled locally?
2071 */
10589a46 2072 mutex_lock(&vcpu->kvm->lock);
92760499 2073 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
bbd9b64e
CO		 2074 if (mmio_dev) {
2075 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
10589a46 2076 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2077 return X86EMUL_CONTINUE;
2078 }
10589a46 2079 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2080
2081 vcpu->mmio_needed = 1;
2082 vcpu->mmio_phys_addr = gpa;
2083 vcpu->mmio_size = bytes;
2084 vcpu->mmio_is_write = 0;
2085
2086 return X86EMUL_UNHANDLEABLE;
2087}
2088
3200f405 2089int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2090 const void *val, int bytes)
bbd9b64e
CO		 2091{
2092 int ret;
2093
2094 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2095 if (ret < 0)
bbd9b64e 2096 return 0;
ad218f85 2097 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2098 return 1;
2099}
2100
2101static int emulator_write_emulated_onepage(unsigned long addr,
2102 const void *val,
2103 unsigned int bytes,
2104 struct kvm_vcpu *vcpu)
2105{
2106 struct kvm_io_device *mmio_dev;
10589a46
MT		 2107 gpa_t gpa;
2108
10589a46 2109 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2110
2111 if (gpa == UNMAPPED_GVA) {
c3c91fee 2112 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2113 return X86EMUL_PROPAGATE_FAULT;
2114 }
2115
2116 /* For APIC access vmexit */
2117 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2118 goto mmio;
2119
2120 if (emulator_write_phys(vcpu, gpa, val, bytes))
2121 return X86EMUL_CONTINUE;
2122
2123mmio:
2124 /*
2125 * Is this MMIO handled locally?
2126 */
10589a46 2127 mutex_lock(&vcpu->kvm->lock);
92760499 2128 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
bbd9b64e
CO		 2129 if (mmio_dev) {
2130 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
10589a46 2131 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2132 return X86EMUL_CONTINUE;
2133 }
10589a46 2134 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2135
2136 vcpu->mmio_needed = 1;
2137 vcpu->mmio_phys_addr = gpa;
2138 vcpu->mmio_size = bytes;
2139 vcpu->mmio_is_write = 1;
2140 memcpy(vcpu->mmio_data, val, bytes);
2141
2142 return X86EMUL_CONTINUE;
2143}
2144
2145int emulator_write_emulated(unsigned long addr,
2146 const void *val,
2147 unsigned int bytes,
2148 struct kvm_vcpu *vcpu)
2149{
2150 /* Crossing a page boundary? */
2151 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2152 int rc, now;
2153
2154 now = -addr & ~PAGE_MASK;
2155 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2156 if (rc != X86EMUL_CONTINUE)
2157 return rc;
2158 addr += now;
2159 val += now;
2160 bytes -= now;
2161 }
2162 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2163}
2164EXPORT_SYMBOL_GPL(emulator_write_emulated);
2165
2166static int emulator_cmpxchg_emulated(unsigned long addr,
2167 const void *old,
2168 const void *new,
2169 unsigned int bytes,
2170 struct kvm_vcpu *vcpu)
2171{
2172 static int reported;
2173
2174 if (!reported) {
2175 reported = 1;
2176 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2177 }
2bacc55c
MT		 2178#ifndef CONFIG_X86_64
2179 /* guests cmpxchg8b have to be emulated atomically */
2180 if (bytes == 8) {
10589a46 2181 gpa_t gpa;
2bacc55c 2182 struct page *page;
c0b49b0d 2183 char *kaddr;
2bacc55c
MT		 2184 u64 val;
2185
10589a46
MT		 2186 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2187
2bacc55c
MT		 2188 if (gpa == UNMAPPED_GVA ||
2189 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2190 goto emul_write;
2191
2192 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2193 goto emul_write;
2194
2195 val = *(u64 *)new;
72dc67a6 2196
2bacc55c 2197 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2198
c0b49b0d
AM		 2199 kaddr = kmap_atomic(page, KM_USER0);
2200 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2201 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2202 kvm_release_page_dirty(page);
2203 }
3200f405 2204emul_write:
2bacc55c
MT		 2205#endif
2206
bbd9b64e
CO		 2207 return emulator_write_emulated(addr, new, bytes, vcpu);
2208}
2209
2210static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2211{
2212 return kvm_x86_ops->get_segment_base(vcpu, seg);
2213}
2214
2215int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2216{
a7052897 2217 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2218 return X86EMUL_CONTINUE;
2219}
2220
2221int emulate_clts(struct kvm_vcpu *vcpu)
2222{
54e445ca 2223 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2224 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2225 return X86EMUL_CONTINUE;
2226}
2227
2228int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2229{
2230 struct kvm_vcpu *vcpu = ctxt->vcpu;
2231
2232 switch (dr) {
2233 case 0 ... 3:
2234 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2235 return X86EMUL_CONTINUE;
2236 default:
b8688d51 2237 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2238 return X86EMUL_UNHANDLEABLE;
2239 }
2240}
2241
2242int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2243{
2244 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2245 int exception;
2246
2247 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2248 if (exception) {
2249 /* FIXME: better handling */
2250 return X86EMUL_UNHANDLEABLE;
2251 }
2252 return X86EMUL_CONTINUE;
2253}
2254
2255void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2256{
bbd9b64e 2257 u8 opcodes[4];
5fdbf976 2258 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2259 unsigned long rip_linear;
2260
f76c710d 2261 if (!printk_ratelimit())
bbd9b64e
CO		 2262 return;
2263
25be4608
GC		 2264 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2265
77c2002e 2266 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2267
2268 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2269 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2270}
2271EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2272
14af3f3c 2273static struct x86_emulate_ops emulate_ops = {
77c2002e 2274 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2275 .read_emulated = emulator_read_emulated,
2276 .write_emulated = emulator_write_emulated,
2277 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2278};
2279
5fdbf976
MT		 2280static void cache_all_regs(struct kvm_vcpu *vcpu)
2281{
2282 kvm_register_read(vcpu, VCPU_REGS_RAX);
2283 kvm_register_read(vcpu, VCPU_REGS_RSP);
2284 kvm_register_read(vcpu, VCPU_REGS_RIP);
2285 vcpu->arch.regs_dirty = ~0;
2286}
2287
bbd9b64e
CO		 2288int emulate_instruction(struct kvm_vcpu *vcpu,
2289 struct kvm_run *run,
2290 unsigned long cr2,
2291 u16 error_code,
571008da 2292 int emulation_type)
bbd9b64e
CO		 2293{
2294 int r;
571008da 2295 struct decode_cache *c;
bbd9b64e 2296
26eef70c 2297 kvm_clear_exception_queue(vcpu);
ad312c7c 2298 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2299 /*
2300 * TODO: fix x86_emulate.c to use guest_read/write_register
2301 * instead of direct ->regs accesses, can save hundred cycles
2302 * on Intel for instructions that don't read/change RSP, for
2303 * for example.
2304 */
2305 cache_all_regs(vcpu);
bbd9b64e
CO		 2306
2307 vcpu->mmio_is_write = 0;
ad312c7c 2308 vcpu->arch.pio.string = 0;
bbd9b64e 2309
571008da 2310 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2311 int cs_db, cs_l;
2312 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2313
ad312c7c
ZX		 2314 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2315 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2316 vcpu->arch.emulate_ctxt.mode =
2317 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2318 ? X86EMUL_MODE_REAL : cs_l
2319 ? X86EMUL_MODE_PROT64 : cs_db
2320 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2321
ad312c7c 2322 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2323
2324 /* Reject the instructions other than VMCALL/VMMCALL when
2325 * try to emulate invalid opcode */
2326 c = &vcpu->arch.emulate_ctxt.decode;
2327 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2328 (!(c->twobyte && c->b == 0x01 &&
2329 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2330 c->modrm_mod == 3 && c->modrm_rm == 1)))
2331 return EMULATE_FAIL;
2332
f2b5756b 2333 ++vcpu->stat.insn_emulation;
bbd9b64e 2334 if (r) {
f2b5756b 2335 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2336 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2337 return EMULATE_DONE;
2338 return EMULATE_FAIL;
2339 }
2340 }
2341
ad312c7c 2342 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
bbd9b64e 2343
ad312c7c 2344 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2345 return EMULATE_DO_MMIO;
2346
2347 if ((r || vcpu->mmio_is_write) && run) {
2348 run->exit_reason = KVM_EXIT_MMIO;
2349 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2350 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2351 run->mmio.len = vcpu->mmio_size;
2352 run->mmio.is_write = vcpu->mmio_is_write;
2353 }
2354
2355 if (r) {
2356 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2357 return EMULATE_DONE;
2358 if (!vcpu->mmio_needed) {
2359 kvm_report_emulation_failure(vcpu, "mmio");
2360 return EMULATE_FAIL;
2361 }
2362 return EMULATE_DO_MMIO;
2363 }
2364
ad312c7c 2365 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2366
2367 if (vcpu->mmio_is_write) {
2368 vcpu->mmio_needed = 0;
2369 return EMULATE_DO_MMIO;
2370 }
2371
2372 return EMULATE_DONE;
2373}
2374EXPORT_SYMBOL_GPL(emulate_instruction);
2375
de7d789a
CO		 2376static int pio_copy_data(struct kvm_vcpu *vcpu)
2377{
ad312c7c 2378 void *p = vcpu->arch.pio_data;
0f346074 2379 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2380 unsigned bytes;
0f346074 2381 int ret;
de7d789a 2382
ad312c7c
ZX		 2383 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2384 if (vcpu->arch.pio.in)
0f346074 2385 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2386 else
0f346074
IE		 2387 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2388 return ret;
de7d789a
CO		 2389}
2390
2391int complete_pio(struct kvm_vcpu *vcpu)
2392{
ad312c7c 2393 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2394 long delta;
2395 int r;
5fdbf976 2396 unsigned long val;
de7d789a
CO		 2397
2398 if (!io->string) {
5fdbf976
MT		 2399 if (io->in) {
2400 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2401 memcpy(&val, vcpu->arch.pio_data, io->size);
2402 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2403 }
de7d789a
CO		 2404 } else {
2405 if (io->in) {
2406 r = pio_copy_data(vcpu);
5fdbf976 2407 if (r)
de7d789a 2408 return r;
de7d789a
CO		 2409 }
2410
2411 delta = 1;
2412 if (io->rep) {
2413 delta *= io->cur_count;
2414 /*
2415 * The size of the register should really depend on
2416 * current address size.
2417 */
5fdbf976
MT		 2418 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2419 val -= delta;
2420 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2421 }
2422 if (io->down)
2423 delta = -delta;
2424 delta *= io->size;
5fdbf976
MT		 2425 if (io->in) {
2426 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2427 val += delta;
2428 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2429 } else {
2430 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2431 val += delta;
2432 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2433 }
de7d789a
CO		 2434 }
2435
de7d789a
CO		 2436 io->count -= io->cur_count;
2437 io->cur_count = 0;
2438
2439 return 0;
2440}
2441
2442static void kernel_pio(struct kvm_io_device *pio_dev,
2443 struct kvm_vcpu *vcpu,
2444 void *pd)
2445{
2446 /* TODO: String I/O for in kernel device */
2447
2448 mutex_lock(&vcpu->kvm->lock);
ad312c7c
ZX		 2449 if (vcpu->arch.pio.in)
2450 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2451 vcpu->arch.pio.size,
de7d789a
CO		 2452 pd);
2453 else
ad312c7c
ZX		 2454 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2455 vcpu->arch.pio.size,
de7d789a
CO		 2456 pd);
2457 mutex_unlock(&vcpu->kvm->lock);
2458}
2459
2460static void pio_string_write(struct kvm_io_device *pio_dev,
2461 struct kvm_vcpu *vcpu)
2462{
ad312c7c
ZX		 2463 struct kvm_pio_request *io = &vcpu->arch.pio;
2464 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2465 int i;
2466
2467 mutex_lock(&vcpu->kvm->lock);
2468 for (i = 0; i < io->cur_count; i++) {
2469 kvm_iodevice_write(pio_dev, io->port,
2470 io->size,
2471 pd);
2472 pd += io->size;
2473 }
2474 mutex_unlock(&vcpu->kvm->lock);
2475}
2476
2477static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2478 gpa_t addr, int len,
2479 int is_write)
de7d789a 2480{
92760499 2481 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2482}
2483
2484int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2485 int size, unsigned port)
2486{
2487 struct kvm_io_device *pio_dev;
5fdbf976 2488 unsigned long val;
de7d789a
CO		 2489
2490 vcpu->run->exit_reason = KVM_EXIT_IO;
2491 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2492 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2493 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2494 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2495 vcpu->run->io.port = vcpu->arch.pio.port = port;
2496 vcpu->arch.pio.in = in;
2497 vcpu->arch.pio.string = 0;
2498 vcpu->arch.pio.down = 0;
ad312c7c 2499 vcpu->arch.pio.rep = 0;
de7d789a 2500
2714d1d3
FEL		 2501 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2502 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2503 handler);
2504 else
2505 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2506 handler);
2507
5fdbf976
MT		 2508 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2509 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2510
92760499 2511 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
de7d789a 2512 if (pio_dev) {
ad312c7c 2513 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2514 complete_pio(vcpu);
2515 return 1;
2516 }
2517 return 0;
2518}
2519EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2520
2521int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2522 int size, unsigned long count, int down,
2523 gva_t address, int rep, unsigned port)
2524{
2525 unsigned now, in_page;
0f346074 2526 int ret = 0;
de7d789a
CO		 2527 struct kvm_io_device *pio_dev;
2528
2529 vcpu->run->exit_reason = KVM_EXIT_IO;
2530 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2531 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2532 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2533 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2534 vcpu->run->io.port = vcpu->arch.pio.port = port;
2535 vcpu->arch.pio.in = in;
2536 vcpu->arch.pio.string = 1;
2537 vcpu->arch.pio.down = down;
ad312c7c 2538 vcpu->arch.pio.rep = rep;
de7d789a 2539
2714d1d3
FEL		 2540 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2541 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2542 handler);
2543 else
2544 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2545 handler);
2546
de7d789a
CO		 2547 if (!count) {
2548 kvm_x86_ops->skip_emulated_instruction(vcpu);
2549 return 1;
2550 }
2551
2552 if (!down)
2553 in_page = PAGE_SIZE - offset_in_page(address);
2554 else
2555 in_page = offset_in_page(address) + size;
2556 now = min(count, (unsigned long)in_page / size);
0f346074 2557 if (!now)
de7d789a 2558 now = 1;
de7d789a
CO		 2559 if (down) {
2560 /*
2561 * String I/O in reverse. Yuck. Kill the guest, fix later.
2562 */
2563 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2564 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2565 return 1;
2566 }
2567 vcpu->run->io.count = now;
ad312c7c 2568 vcpu->arch.pio.cur_count = now;
de7d789a 2569
ad312c7c 2570 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2571 kvm_x86_ops->skip_emulated_instruction(vcpu);
2572
0f346074 2573 vcpu->arch.pio.guest_gva = address;
de7d789a 2574
92760499
LV		 2575 pio_dev = vcpu_find_pio_dev(vcpu, port,
2576 vcpu->arch.pio.cur_count,
2577 !vcpu->arch.pio.in);
ad312c7c 2578 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2579 /* string PIO write */
2580 ret = pio_copy_data(vcpu);
0f346074
IE		 2581 if (ret == X86EMUL_PROPAGATE_FAULT) {
2582 kvm_inject_gp(vcpu, 0);
2583 return 1;
2584 }
2585 if (ret == 0 && pio_dev) {
de7d789a
CO		 2586 pio_string_write(pio_dev, vcpu);
2587 complete_pio(vcpu);
ad312c7c 2588 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2589 ret = 1;
2590 }
2591 } else if (pio_dev)
2592 pr_unimpl(vcpu, "no string pio read support yet, "
2593 "port %x size %d count %ld\n",
2594 port, size, count);
2595
2596 return ret;
2597}
2598EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2599
f8c16bba 2600int kvm_arch_init(void *opaque)
043405e1 2601{
56c6d28a 2602 int r;
f8c16bba
ZX		 2603 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
2604
f8c16bba
ZX		 2605 if (kvm_x86_ops) {
2606 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 2607 r = -EEXIST;
2608 goto out;
f8c16bba
ZX		 2609 }
2610
2611 if (!ops->cpu_has_kvm_support()) {
2612 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 2613 r = -EOPNOTSUPP;
2614 goto out;
f8c16bba
ZX		 2615 }
2616 if (ops->disabled_by_bios()) {
2617 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 2618 r = -EOPNOTSUPP;
2619 goto out;
f8c16bba
ZX		 2620 }
2621
97db56ce
AK		 2622 r = kvm_mmu_module_init();
2623 if (r)
2624 goto out;
2625
2626 kvm_init_msr_list();
2627
f8c16bba 2628 kvm_x86_ops = ops;
56c6d28a 2629 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 2630 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
2631 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
64d4d521 2632 PT_DIRTY_MASK, PT64_NX_MASK, 0, 0);
f8c16bba 2633 return 0;
56c6d28a
ZX		 2634
2635out:
56c6d28a 2636 return r;
043405e1 2637}
8776e519 2638
f8c16bba
ZX		 2639void kvm_arch_exit(void)
2640{
2641 kvm_x86_ops = NULL;
56c6d28a
ZX		 2642 kvm_mmu_module_exit();
2643}
f8c16bba 2644
8776e519
HB		 2645int kvm_emulate_halt(struct kvm_vcpu *vcpu)
2646{
2647 ++vcpu->stat.halt_exits;
2714d1d3 2648 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 2649 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 2650 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 2651 return 1;
2652 } else {
2653 vcpu->run->exit_reason = KVM_EXIT_HLT;
2654 return 0;
2655 }
2656}
2657EXPORT_SYMBOL_GPL(kvm_emulate_halt);
2658
2f333bcb
MT		 2659static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
2660 unsigned long a1)
2661{
2662 if (is_long_mode(vcpu))
2663 return a0;
2664 else
2665 return a0 | ((gpa_t)a1 << 32);
2666}
2667
8776e519
HB		 2668int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
2669{
2670 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 2671 int r = 1;
8776e519 2672
5fdbf976
MT		 2673 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
2674 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
2675 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
2676 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
2677 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 2678
2714d1d3
FEL		 2679 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
2680
8776e519
HB		 2681 if (!is_long_mode(vcpu)) {
2682 nr &= 0xFFFFFFFF;
2683 a0 &= 0xFFFFFFFF;
2684 a1 &= 0xFFFFFFFF;
2685 a2 &= 0xFFFFFFFF;
2686 a3 &= 0xFFFFFFFF;
2687 }
2688
2689 switch (nr) {
b93463aa
AK		 2690 case KVM_HC_VAPIC_POLL_IRQ:
2691 ret = 0;
2692 break;
2f333bcb
MT		 2693 case KVM_HC_MMU_OP:
2694 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
2695 break;
8776e519
HB		 2696 default:
2697 ret = -KVM_ENOSYS;
2698 break;
2699 }
5fdbf976 2700 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 2701 ++vcpu->stat.hypercalls;
2f333bcb 2702 return r;
8776e519
HB		 2703}
2704EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
2705
2706int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
2707{
2708 char instruction[3];
2709 int ret = 0;
5fdbf976 2710 unsigned long rip = kvm_rip_read(vcpu);
8776e519 2711
8776e519
HB		 2712
2713 /*
2714 * Blow out the MMU to ensure that no other VCPU has an active mapping
2715 * to ensure that the updated hypercall appears atomically across all
2716 * VCPUs.
2717 */
2718 kvm_mmu_zap_all(vcpu->kvm);
2719
8776e519 2720 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 2721 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 2722 != X86EMUL_CONTINUE)
2723 ret = -EFAULT;
2724
8776e519
HB		 2725 return ret;
2726}
2727
2728static u64 mk_cr_64(u64 curr_cr, u32 new_val)
2729{
2730 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
2731}
2732
2733void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2734{
2735 struct descriptor_table dt = { limit, base };
2736
2737 kvm_x86_ops->set_gdt(vcpu, &dt);
2738}
2739
2740void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
2741{
2742 struct descriptor_table dt = { limit, base };
2743
2744 kvm_x86_ops->set_idt(vcpu, &dt);
2745}
2746
2747void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
2748 unsigned long *rflags)
2749{
2d3ad1f4 2750 kvm_lmsw(vcpu, msw);
8776e519
HB		 2751 *rflags = kvm_x86_ops->get_rflags(vcpu);
2752}
2753
2754unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
2755{
54e445ca
JR		 2756 unsigned long value;
2757
8776e519
HB		 2758 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
2759 switch (cr) {
2760 case 0:
54e445ca
JR		 2761 value = vcpu->arch.cr0;
2762 break;
8776e519 2763 case 2:
54e445ca
JR		 2764 value = vcpu->arch.cr2;
2765 break;
8776e519 2766 case 3:
54e445ca
JR		 2767 value = vcpu->arch.cr3;
2768 break;
8776e519 2769 case 4:
54e445ca
JR		 2770 value = vcpu->arch.cr4;
2771 break;
152ff9be 2772 case 8:
54e445ca
JR		 2773 value = kvm_get_cr8(vcpu);
2774 break;
8776e519 2775 default:
b8688d51 2776 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2777 return 0;
2778 }
54e445ca
JR		 2779 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
2780 (u32)((u64)value >> 32), handler);
2781
2782 return value;
8776e519
HB		 2783}
2784
2785void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
2786 unsigned long *rflags)
2787{
54e445ca
JR		 2788 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
2789 (u32)((u64)val >> 32), handler);
2790
8776e519
HB		 2791 switch (cr) {
2792 case 0:
2d3ad1f4 2793 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 2794 *rflags = kvm_x86_ops->get_rflags(vcpu);
2795 break;
2796 case 2:
ad312c7c 2797 vcpu->arch.cr2 = val;
8776e519
HB		 2798 break;
2799 case 3:
2d3ad1f4 2800 kvm_set_cr3(vcpu, val);
8776e519
HB		 2801 break;
2802 case 4:
2d3ad1f4 2803 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 2804 break;
152ff9be 2805 case 8:
2d3ad1f4 2806 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 2807 break;
8776e519 2808 default:
b8688d51 2809 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 2810 }
2811}
2812
07716717
DK		 2813static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
2814{
ad312c7c
ZX		 2815 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
2816 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 2817
2818 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
2819 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 2820 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 2821 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 2822 if (ej->function == e->function) {
2823 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
2824 return j;
2825 }
2826 }
2827 return 0; /* silence gcc, even though control never reaches here */
2828}
2829
2830/* find an entry with matching function, matching index (if needed), and that
2831 * should be read next (if it's stateful) */
2832static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
2833 u32 function, u32 index)
2834{
2835 if (e->function != function)
2836 return 0;
2837 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
2838 return 0;
2839 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
2840 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
2841 return 0;
2842 return 1;
2843}
2844
d8017474
AG		 2845struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
2846 u32 function, u32 index)
8776e519
HB		 2847{
2848 int i;
d8017474 2849 struct kvm_cpuid_entry2 *best = NULL;
8776e519 2850
ad312c7c 2851 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 2852 struct kvm_cpuid_entry2 *e;
2853
ad312c7c 2854 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 2855 if (is_matching_cpuid_entry(e, function, index)) {
2856 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
2857 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 2858 best = e;
2859 break;
2860 }
2861 /*
2862 * Both basic or both extended?
2863 */
2864 if (((e->function ^ function) & 0x80000000) == 0)
2865 if (!best || e->function > best->function)
2866 best = e;
2867 }
d8017474
AG		 2868
2869 return best;
2870}
2871
2872void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
2873{
2874 u32 function, index;
2875 struct kvm_cpuid_entry2 *best;
2876
2877 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
2878 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
2879 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
2880 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
2881 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
2882 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
2883 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 2884 if (best) {
5fdbf976
MT		 2885 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
2886 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
2887 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
2888 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 2889 }
8776e519 2890 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 2891 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 2892 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
2893 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
2894 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
2895 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 2896}
2897EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 2898
b6c7a5dc
HB		 2899/*
2900 * Check if userspace requested an interrupt window, and that the
2901 * interrupt window is open.
2902 *
2903 * No need to exit to userspace if we already have an interrupt queued.
2904 */
2905static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
2906 struct kvm_run *kvm_run)
2907{
ad312c7c 2908 return (!vcpu->arch.irq_summary &&
b6c7a5dc 2909 kvm_run->request_interrupt_window &&
ad312c7c 2910 vcpu->arch.interrupt_window_open &&
b6c7a5dc
HB		 2911 (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF));
2912}
2913
2914static void post_kvm_run_save(struct kvm_vcpu *vcpu,
2915 struct kvm_run *kvm_run)
2916{
2917 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 2918 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 2919 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 2920 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 2921 kvm_run->ready_for_interrupt_injection = 1;
4531220b 2922 else
b6c7a5dc 2923 kvm_run->ready_for_interrupt_injection =
ad312c7c
ZX		 2924 (vcpu->arch.interrupt_window_open &&
2925 vcpu->arch.irq_summary == 0);
b6c7a5dc
HB		 2926}
2927
b93463aa
AK		 2928static void vapic_enter(struct kvm_vcpu *vcpu)
2929{
2930 struct kvm_lapic *apic = vcpu->arch.apic;
2931 struct page *page;
2932
2933 if (!apic || !apic->vapic_addr)
2934 return;
2935
2936 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 2937
2938 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 2939}
2940
2941static void vapic_exit(struct kvm_vcpu *vcpu)
2942{
2943 struct kvm_lapic *apic = vcpu->arch.apic;
2944
2945 if (!apic || !apic->vapic_addr)
2946 return;
2947
f8b78fa3 2948 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2949 kvm_release_page_dirty(apic->vapic_page);
2950 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 2951 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 2952}
2953
d7690175 2954static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 2955{
2956 int r;
2957
2e53d63a
MT		 2958 if (vcpu->requests)
2959 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
2960 kvm_mmu_unload(vcpu);
2961
b6c7a5dc
HB		 2962 r = kvm_mmu_reload(vcpu);
2963 if (unlikely(r))
2964 goto out;
2965
2f52d58c
AK		 2966 if (vcpu->requests) {
2967 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 2968 __kvm_migrate_timers(vcpu);
4731d4c7
MT		 2969 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
2970 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 2971 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
2972 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 2973 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
2974 &vcpu->requests)) {
2975 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
2976 r = 0;
2977 goto out;
2978 }
71c4dfaf
JR		 2979 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
2980 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2981 r = 0;
2982 goto out;
2983 }
2f52d58c 2984 }
b93463aa 2985
06e05645 2986 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
b6c7a5dc
HB		 2987 kvm_inject_pending_timer_irqs(vcpu);
2988
2989 preempt_disable();
2990
2991 kvm_x86_ops->prepare_guest_switch(vcpu);
2992 kvm_load_guest_fpu(vcpu);
2993
2994 local_irq_disable();
2995
d7690175 2996 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 2997 local_irq_enable();
2998 preempt_enable();
2999 r = 1;
3000 goto out;
3001 }
3002
e9571ed5
MT		 3003 vcpu->guest_mode = 1;
3004 /*
3005 * Make sure that guest_mode assignment won't happen after
3006 * testing the pending IRQ vector bitmap.
3007 */
3008 smp_wmb();
3009
ad312c7c 3010 if (vcpu->arch.exception.pending)
298101da
AK		 3011 __queue_exception(vcpu);
3012 else if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3013 kvm_x86_ops->inject_pending_irq(vcpu);
eb9774f0 3014 else
b6c7a5dc
HB		 3015 kvm_x86_ops->inject_pending_vectors(vcpu, kvm_run);
3016
b93463aa
AK		 3017 kvm_lapic_sync_to_vapic(vcpu);
3018
3200f405
MT		 3019 up_read(&vcpu->kvm->slots_lock);
3020
b6c7a5dc
HB		 3021 kvm_guest_enter();
3022
42dbaa5a
JK		 3023 get_debugreg(vcpu->arch.host_dr6, 6);
3024 get_debugreg(vcpu->arch.host_dr7, 7);
3025 if (unlikely(vcpu->arch.switch_db_regs)) {
3026 get_debugreg(vcpu->arch.host_db[0], 0);
3027 get_debugreg(vcpu->arch.host_db[1], 1);
3028 get_debugreg(vcpu->arch.host_db[2], 2);
3029 get_debugreg(vcpu->arch.host_db[3], 3);
3030
3031 set_debugreg(0, 7);
3032 set_debugreg(vcpu->arch.eff_db[0], 0);
3033 set_debugreg(vcpu->arch.eff_db[1], 1);
3034 set_debugreg(vcpu->arch.eff_db[2], 2);
3035 set_debugreg(vcpu->arch.eff_db[3], 3);
3036 }
b6c7a5dc 3037
2714d1d3 3038 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3039 kvm_x86_ops->run(vcpu, kvm_run);
3040
42dbaa5a
JK		 3041 if (unlikely(vcpu->arch.switch_db_regs)) {
3042 set_debugreg(0, 7);
3043 set_debugreg(vcpu->arch.host_db[0], 0);
3044 set_debugreg(vcpu->arch.host_db[1], 1);
3045 set_debugreg(vcpu->arch.host_db[2], 2);
3046 set_debugreg(vcpu->arch.host_db[3], 3);
3047 }
3048 set_debugreg(vcpu->arch.host_dr6, 6);
3049 set_debugreg(vcpu->arch.host_dr7, 7);
3050
b6c7a5dc
HB		 3051 vcpu->guest_mode = 0;
3052 local_irq_enable();
3053
3054 ++vcpu->stat.exits;
3055
3056 /*
3057 * We must have an instruction between local_irq_enable() and
3058 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3059 * the interrupt shadow. The stat.exits increment will do nicely.
3060 * But we need to prevent reordering, hence this barrier():
3061 */
3062 barrier();
3063
3064 kvm_guest_exit();
3065
3066 preempt_enable();
3067
3200f405
MT		 3068 down_read(&vcpu->kvm->slots_lock);
3069
b6c7a5dc
HB		 3070 /*
3071 * Profile KVM exit RIPs:
3072 */
3073 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3074 unsigned long rip = kvm_rip_read(vcpu);
3075 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3076 }
3077
ad312c7c
ZX		 3078 if (vcpu->arch.exception.pending && kvm_x86_ops->exception_injected(vcpu))
3079 vcpu->arch.exception.pending = false;
298101da 3080
b93463aa
AK		 3081 kvm_lapic_sync_from_vapic(vcpu);
3082
b6c7a5dc 3083 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3084out:
3085 return r;
3086}
b6c7a5dc 3087
d7690175
MT		 3088static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3089{
3090 int r;
3091
3092 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3093 pr_debug("vcpu %d received sipi with vector # %x\n",
3094 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3095 kvm_lapic_reset(vcpu);
5f179287 3096 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3097 if (r)
3098 return r;
3099 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3100 }
3101
d7690175
MT		 3102 down_read(&vcpu->kvm->slots_lock);
3103 vapic_enter(vcpu);
3104
3105 r = 1;
3106 while (r > 0) {
af2152f5 3107 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3108 r = vcpu_enter_guest(vcpu, kvm_run);
3109 else {
3110 up_read(&vcpu->kvm->slots_lock);
3111 kvm_vcpu_block(vcpu);
3112 down_read(&vcpu->kvm->slots_lock);
3113 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
3114 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
3115 vcpu->arch.mp_state =
3116 KVM_MP_STATE_RUNNABLE;
3117 if (vcpu->arch.mp_state != KVM_MP_STATE_RUNNABLE)
3118 r = -EINTR;
3119 }
3120
3121 if (r > 0) {
3122 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3123 r = -EINTR;
3124 kvm_run->exit_reason = KVM_EXIT_INTR;
3125 ++vcpu->stat.request_irq_exits;
3126 }
3127 if (signal_pending(current)) {
3128 r = -EINTR;
3129 kvm_run->exit_reason = KVM_EXIT_INTR;
3130 ++vcpu->stat.signal_exits;
3131 }
3132 if (need_resched()) {
3133 up_read(&vcpu->kvm->slots_lock);
3134 kvm_resched(vcpu);
3135 down_read(&vcpu->kvm->slots_lock);
3136 }
3137 }
b6c7a5dc
HB		 3138 }
3139
d7690175 3140 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3141 post_kvm_run_save(vcpu, kvm_run);
3142
b93463aa
AK		 3143 vapic_exit(vcpu);
3144
b6c7a5dc
HB		 3145 return r;
3146}
3147
3148int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3149{
3150 int r;
3151 sigset_t sigsaved;
3152
3153 vcpu_load(vcpu);
3154
ac9f6dc0
AK		 3155 if (vcpu->sigset_active)
3156 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3157
a4535290 3158 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3159 kvm_vcpu_block(vcpu);
d7690175 3160 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3161 r = -EAGAIN;
3162 goto out;
b6c7a5dc
HB		 3163 }
3164
b6c7a5dc
HB		 3165 /* re-sync apic's tpr */
3166 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3167 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3168
ad312c7c 3169 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3170 r = complete_pio(vcpu);
3171 if (r)
3172 goto out;
3173 }
3174#if CONFIG_HAS_IOMEM
3175 if (vcpu->mmio_needed) {
3176 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3177 vcpu->mmio_read_completed = 1;
3178 vcpu->mmio_needed = 0;
3200f405
MT		 3179
3180 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3181 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3182 vcpu->arch.mmio_fault_cr2, 0,
3183 EMULTYPE_NO_DECODE);
3200f405 3184 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3185 if (r == EMULATE_DO_MMIO) {
3186 /*
3187 * Read-modify-write. Back to userspace.
3188 */
3189 r = 0;
3190 goto out;
3191 }
3192 }
3193#endif
5fdbf976
MT		 3194 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3195 kvm_register_write(vcpu, VCPU_REGS_RAX,
3196 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3197
3198 r = __vcpu_run(vcpu, kvm_run);
3199
3200out:
3201 if (vcpu->sigset_active)
3202 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3203
3204 vcpu_put(vcpu);
3205 return r;
3206}
3207
3208int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3209{
3210 vcpu_load(vcpu);
3211
5fdbf976
MT		 3212 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3213 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3214 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3215 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3216 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3217 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3218 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3219 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3220#ifdef CONFIG_X86_64
5fdbf976
MT		 3221 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3222 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3223 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3224 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3225 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3226 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3227 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3228 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3229#endif
3230
5fdbf976 3231 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3232 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3233
3234 /*
3235 * Don't leak debug flags in case they were set for guest debugging
3236 */
d0bfb940 3237 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3238 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3239
3240 vcpu_put(vcpu);
3241
3242 return 0;
3243}
3244
3245int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3246{
3247 vcpu_load(vcpu);
3248
5fdbf976
MT		 3249 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3250 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3251 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3252 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3253 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3254 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3255 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3256 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3257#ifdef CONFIG_X86_64
5fdbf976
MT		 3258 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3259 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3260 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3261 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3262 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3263 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3264 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3265 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3266
b6c7a5dc
HB		 3267#endif
3268
5fdbf976 3269 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3270 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3271
b6c7a5dc 3272
b4f14abd
JK		 3273 vcpu->arch.exception.pending = false;
3274
b6c7a5dc
HB		 3275 vcpu_put(vcpu);
3276
3277 return 0;
3278}
3279
3e6e0aab
GT		 3280void kvm_get_segment(struct kvm_vcpu *vcpu,
3281 struct kvm_segment *var, int seg)
b6c7a5dc 3282{
14af3f3c 3283 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3284}
3285
3286void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3287{
3288 struct kvm_segment cs;
3289
3e6e0aab 3290 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3291 *db = cs.db;
3292 *l = cs.l;
3293}
3294EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3295
3296int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3297 struct kvm_sregs *sregs)
3298{
3299 struct descriptor_table dt;
3300 int pending_vec;
3301
3302 vcpu_load(vcpu);
3303
3e6e0aab
GT		 3304 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3305 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3306 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3307 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3308 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3309 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3310
3e6e0aab
GT		 3311 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3312 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3313
3314 kvm_x86_ops->get_idt(vcpu, &dt);
3315 sregs->idt.limit = dt.limit;
3316 sregs->idt.base = dt.base;
3317 kvm_x86_ops->get_gdt(vcpu, &dt);
3318 sregs->gdt.limit = dt.limit;
3319 sregs->gdt.base = dt.base;
3320
3321 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3322 sregs->cr0 = vcpu->arch.cr0;
3323 sregs->cr2 = vcpu->arch.cr2;
3324 sregs->cr3 = vcpu->arch.cr3;
3325 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3326 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3327 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3328 sregs->apic_base = kvm_get_apic_base(vcpu);
3329
3330 if (irqchip_in_kernel(vcpu->kvm)) {
3331 memset(sregs->interrupt_bitmap, 0,
3332 sizeof sregs->interrupt_bitmap);
3333 pending_vec = kvm_x86_ops->get_irq(vcpu);
3334 if (pending_vec >= 0)
3335 set_bit(pending_vec,
3336 (unsigned long *)sregs->interrupt_bitmap);
3337 } else
ad312c7c 3338 memcpy(sregs->interrupt_bitmap, vcpu->arch.irq_pending,
b6c7a5dc
HB		 3339 sizeof sregs->interrupt_bitmap);
3340
3341 vcpu_put(vcpu);
3342
3343 return 0;
3344}
3345
62d9f0db
MT		 3346int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3347 struct kvm_mp_state *mp_state)
3348{
3349 vcpu_load(vcpu);
3350 mp_state->mp_state = vcpu->arch.mp_state;
3351 vcpu_put(vcpu);
3352 return 0;
3353}
3354
3355int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3356 struct kvm_mp_state *mp_state)
3357{
3358 vcpu_load(vcpu);
3359 vcpu->arch.mp_state = mp_state->mp_state;
3360 vcpu_put(vcpu);
3361 return 0;
3362}
3363
3e6e0aab 3364static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3365 struct kvm_segment *var, int seg)
3366{
14af3f3c 3367 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3368}
3369
37817f29
IE		 3370static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3371 struct kvm_segment *kvm_desct)
3372{
3373 kvm_desct->base = seg_desc->base0;
3374 kvm_desct->base |= seg_desc->base1 << 16;
3375 kvm_desct->base |= seg_desc->base2 << 24;
3376 kvm_desct->limit = seg_desc->limit0;
3377 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3378 if (seg_desc->g) {
3379 kvm_desct->limit <<= 12;
3380 kvm_desct->limit |= 0xfff;
3381 }
37817f29
IE		 3382 kvm_desct->selector = selector;
3383 kvm_desct->type = seg_desc->type;
3384 kvm_desct->present = seg_desc->p;
3385 kvm_desct->dpl = seg_desc->dpl;
3386 kvm_desct->db = seg_desc->d;
3387 kvm_desct->s = seg_desc->s;
3388 kvm_desct->l = seg_desc->l;
3389 kvm_desct->g = seg_desc->g;
3390 kvm_desct->avl = seg_desc->avl;
3391 if (!selector)
3392 kvm_desct->unusable = 1;
3393 else
3394 kvm_desct->unusable = 0;
3395 kvm_desct->padding = 0;
3396}
3397
b8222ad2
AS		 3398static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3399 u16 selector,
3400 struct descriptor_table *dtable)
37817f29
IE		 3401{
3402 if (selector & 1 << 2) {
3403 struct kvm_segment kvm_seg;
3404
3e6e0aab 3405 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3406
3407 if (kvm_seg.unusable)
3408 dtable->limit = 0;
3409 else
3410 dtable->limit = kvm_seg.limit;
3411 dtable->base = kvm_seg.base;
3412 }
3413 else
3414 kvm_x86_ops->get_gdt(vcpu, dtable);
3415}
3416
3417/* allowed just for 8 bytes segments */
3418static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3419 struct desc_struct *seg_desc)
3420{
98899aa0 3421 gpa_t gpa;
37817f29
IE		 3422 struct descriptor_table dtable;
3423 u16 index = selector >> 3;
3424
b8222ad2 3425 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3426
3427 if (dtable.limit < index * 8 + 7) {
3428 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3429 return 1;
3430 }
98899aa0
MT		 3431 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3432 gpa += index * 8;
3433 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3434}
3435
3436/* allowed just for 8 bytes segments */
3437static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3438 struct desc_struct *seg_desc)
3439{
98899aa0 3440 gpa_t gpa;
37817f29
IE		 3441 struct descriptor_table dtable;
3442 u16 index = selector >> 3;
3443
b8222ad2 3444 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3445
3446 if (dtable.limit < index * 8 + 7)
3447 return 1;
98899aa0
MT		 3448 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3449 gpa += index * 8;
3450 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3451}
3452
3453static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3454 struct desc_struct *seg_desc)
3455{
3456 u32 base_addr;
3457
3458 base_addr = seg_desc->base0;
3459 base_addr |= (seg_desc->base1 << 16);
3460 base_addr |= (seg_desc->base2 << 24);
3461
98899aa0 3462 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3463}
3464
37817f29
IE		 3465static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3466{
3467 struct kvm_segment kvm_seg;
3468
3e6e0aab 3469 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3470 return kvm_seg.selector;
3471}
3472
3473static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3474 u16 selector,
3475 struct kvm_segment *kvm_seg)
3476{
3477 struct desc_struct seg_desc;
3478
3479 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3480 return 1;
3481 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3482 return 0;
3483}
3484
2259e3a7 3485static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3486{
3487 struct kvm_segment segvar = {
3488 .base = selector << 4,
3489 .limit = 0xffff,
3490 .selector = selector,
3491 .type = 3,
3492 .present = 1,
3493 .dpl = 3,
3494 .db = 0,
3495 .s = 1,
3496 .l = 0,
3497 .g = 0,
3498 .avl = 0,
3499 .unusable = 0,
3500 };
3501 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3502 return 0;
3503}
3504
3e6e0aab
GT		 3505int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3506 int type_bits, int seg)
37817f29
IE		 3507{
3508 struct kvm_segment kvm_seg;
3509
f4bbd9aa
AK		 3510 if (!(vcpu->arch.cr0 & X86_CR0_PE))
3511 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 3512 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
3513 return 1;
3514 kvm_seg.type |= type_bits;
3515
3516 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
3517 seg != VCPU_SREG_LDTR)
3518 if (!kvm_seg.s)
3519 kvm_seg.unusable = 1;
3520
3e6e0aab 3521 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3522 return 0;
3523}
3524
3525static void save_state_to_tss32(struct kvm_vcpu *vcpu,
3526 struct tss_segment_32 *tss)
3527{
3528 tss->cr3 = vcpu->arch.cr3;
5fdbf976 3529 tss->eip = kvm_rip_read(vcpu);
37817f29 3530 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3531 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3532 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3533 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3534 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3535 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3536 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3537 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3538 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3539 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3540 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3541 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3542 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3543 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
3544 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
3545 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3546 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3547}
3548
3549static int load_state_from_tss32(struct kvm_vcpu *vcpu,
3550 struct tss_segment_32 *tss)
3551{
3552 kvm_set_cr3(vcpu, tss->cr3);
3553
5fdbf976 3554 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 3555 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
3556
5fdbf976
MT		 3557 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
3558 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
3559 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
3560 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
3561 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
3562 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
3563 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
3564 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 3565
3e6e0aab 3566 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 3567 return 1;
3568
3e6e0aab 3569 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3570 return 1;
3571
3e6e0aab 3572 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3573 return 1;
3574
3e6e0aab 3575 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3576 return 1;
3577
3e6e0aab 3578 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3579 return 1;
3580
3e6e0aab 3581 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 3582 return 1;
3583
3e6e0aab 3584 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 3585 return 1;
3586 return 0;
3587}
3588
3589static void save_state_to_tss16(struct kvm_vcpu *vcpu,
3590 struct tss_segment_16 *tss)
3591{
5fdbf976 3592 tss->ip = kvm_rip_read(vcpu);
37817f29 3593 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 3594 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3595 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3596 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3597 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3598 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3599 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
3600 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
3601 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 3602
3603 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
3604 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
3605 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
3606 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
3607 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
3608 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
3609}
3610
3611static int load_state_from_tss16(struct kvm_vcpu *vcpu,
3612 struct tss_segment_16 *tss)
3613{
5fdbf976 3614 kvm_rip_write(vcpu, tss->ip);
37817f29 3615 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 3616 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
3617 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
3618 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
3619 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
3620 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
3621 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
3622 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
3623 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 3624
3e6e0aab 3625 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 3626 return 1;
3627
3e6e0aab 3628 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 3629 return 1;
3630
3e6e0aab 3631 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 3632 return 1;
3633
3e6e0aab 3634 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 3635 return 1;
3636
3e6e0aab 3637 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 3638 return 1;
3639 return 0;
3640}
3641
8b2cf73c 3642static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3643 u32 old_tss_base,
37817f29
IE		 3644 struct desc_struct *nseg_desc)
3645{
3646 struct tss_segment_16 tss_segment_16;
3647 int ret = 0;
3648
34198bf8
MT		 3649 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3650 sizeof tss_segment_16))
37817f29
IE		 3651 goto out;
3652
3653 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 3654
34198bf8
MT		 3655 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
3656 sizeof tss_segment_16))
37817f29 3657 goto out;
34198bf8
MT		 3658
3659 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3660 &tss_segment_16, sizeof tss_segment_16))
3661 goto out;
3662
37817f29
IE		 3663 if (load_state_from_tss16(vcpu, &tss_segment_16))
3664 goto out;
3665
3666 ret = 1;
3667out:
3668 return ret;
3669}
3670
8b2cf73c 3671static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
34198bf8 3672 u32 old_tss_base,
37817f29
IE		 3673 struct desc_struct *nseg_desc)
3674{
3675 struct tss_segment_32 tss_segment_32;
3676 int ret = 0;
3677
34198bf8
MT		 3678 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3679 sizeof tss_segment_32))
37817f29
IE		 3680 goto out;
3681
3682 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 3683
34198bf8
MT		 3684 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
3685 sizeof tss_segment_32))
3686 goto out;
3687
3688 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
3689 &tss_segment_32, sizeof tss_segment_32))
37817f29 3690 goto out;
34198bf8 3691
37817f29
IE		 3692 if (load_state_from_tss32(vcpu, &tss_segment_32))
3693 goto out;
3694
3695 ret = 1;
3696out:
3697 return ret;
3698}
3699
3700int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
3701{
3702 struct kvm_segment tr_seg;
3703 struct desc_struct cseg_desc;
3704 struct desc_struct nseg_desc;
3705 int ret = 0;
34198bf8
MT		 3706 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
3707 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 3708
34198bf8 3709 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 3710
34198bf8
MT		 3711 /* FIXME: Handle errors. Failure to read either TSS or their
3712 * descriptors should generate a pagefault.
3713 */
37817f29
IE		 3714 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
3715 goto out;
3716
34198bf8 3717 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 3718 goto out;
3719
37817f29
IE		 3720 if (reason != TASK_SWITCH_IRET) {
3721 int cpl;
3722
3723 cpl = kvm_x86_ops->get_cpl(vcpu);
3724 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
3725 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
3726 return 1;
3727 }
3728 }
3729
3730 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
3731 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
3732 return 1;
3733 }
3734
3735 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 3736 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 3737 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 3738 }
3739
3740 if (reason == TASK_SWITCH_IRET) {
3741 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3742 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
3743 }
3744
3745 kvm_x86_ops->skip_emulated_instruction(vcpu);
37817f29
IE		 3746
3747 if (nseg_desc.type & 8)
34198bf8 3748 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3749 &nseg_desc);
3750 else
34198bf8 3751 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_base,
37817f29
IE		 3752 &nseg_desc);
3753
3754 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
3755 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
3756 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
3757 }
3758
3759 if (reason != TASK_SWITCH_IRET) {
3fe913e7 3760 nseg_desc.type |= (1 << 1);
37817f29
IE		 3761 save_guest_segment_descriptor(vcpu, tss_selector,
3762 &nseg_desc);
3763 }
3764
3765 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
3766 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
3767 tr_seg.type = 11;
3e6e0aab 3768 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 3769out:
37817f29
IE		 3770 return ret;
3771}
3772EXPORT_SYMBOL_GPL(kvm_task_switch);
3773
b6c7a5dc
HB		 3774int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
3775 struct kvm_sregs *sregs)
3776{
3777 int mmu_reset_needed = 0;
3778 int i, pending_vec, max_bits;
3779 struct descriptor_table dt;
3780
3781 vcpu_load(vcpu);
3782
3783 dt.limit = sregs->idt.limit;
3784 dt.base = sregs->idt.base;
3785 kvm_x86_ops->set_idt(vcpu, &dt);
3786 dt.limit = sregs->gdt.limit;
3787 dt.base = sregs->gdt.base;
3788 kvm_x86_ops->set_gdt(vcpu, &dt);
3789
ad312c7c
ZX		 3790 vcpu->arch.cr2 = sregs->cr2;
3791 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
3792 vcpu->arch.cr3 = sregs->cr3;
b6c7a5dc 3793
2d3ad1f4 3794 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 3795
ad312c7c 3796 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 3797 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 3798 kvm_set_apic_base(vcpu, sregs->apic_base);
3799
3800 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3801
ad312c7c 3802 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 3803 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 3804 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 3805
ad312c7c 3806 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 3807 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3808 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 3809 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 3810
3811 if (mmu_reset_needed)
3812 kvm_mmu_reset_context(vcpu);
3813
3814 if (!irqchip_in_kernel(vcpu->kvm)) {
ad312c7c
ZX		 3815 memcpy(vcpu->arch.irq_pending, sregs->interrupt_bitmap,
3816 sizeof vcpu->arch.irq_pending);
3817 vcpu->arch.irq_summary = 0;
3818 for (i = 0; i < ARRAY_SIZE(vcpu->arch.irq_pending); ++i)
3819 if (vcpu->arch.irq_pending[i])
3820 __set_bit(i, &vcpu->arch.irq_summary);
b6c7a5dc
HB		 3821 } else {
3822 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
3823 pending_vec = find_first_bit(
3824 (const unsigned long *)sregs->interrupt_bitmap,
3825 max_bits);
3826 /* Only pending external irq is handled here */
3827 if (pending_vec < max_bits) {
3828 kvm_x86_ops->set_irq(vcpu, pending_vec);
3829 pr_debug("Set back pending irq %d\n",
3830 pending_vec);
3831 }
e4825800 3832 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 3833 }
3834
3e6e0aab
GT		 3835 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3836 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3837 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3838 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3839 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3840 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3841
3e6e0aab
GT		 3842 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3843 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 3844
9c3e4aab
MT		 3845 /* Older userspace won't unhalt the vcpu on reset. */
3846 if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
3847 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3848 !(vcpu->arch.cr0 & X86_CR0_PE))
3849 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3850
b6c7a5dc
HB		 3851 vcpu_put(vcpu);
3852
3853 return 0;
3854}
3855
d0bfb940
JK		 3856int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
3857 struct kvm_guest_debug *dbg)
b6c7a5dc 3858{
ae675ef0 3859 int i, r;
b6c7a5dc
HB		 3860
3861 vcpu_load(vcpu);
3862
ae675ef0
JK		 3863 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
3864 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
3865 for (i = 0; i < KVM_NR_DB_REGS; ++i)
3866 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
3867 vcpu->arch.switch_db_regs =
3868 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
3869 } else {
3870 for (i = 0; i < KVM_NR_DB_REGS; i++)
3871 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
3872 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
3873 }
3874
b6c7a5dc
HB		 3875 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
3876
d0bfb940
JK		 3877 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
3878 kvm_queue_exception(vcpu, DB_VECTOR);
3879 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
3880 kvm_queue_exception(vcpu, BP_VECTOR);
3881
b6c7a5dc
HB		 3882 vcpu_put(vcpu);
3883
3884 return r;
3885}
3886
d0752060
HB		 3887/*
3888 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
3889 * we have asm/x86/processor.h
3890 */
3891struct fxsave {
3892 u16 cwd;
3893 u16 swd;
3894 u16 twd;
3895 u16 fop;
3896 u64 rip;
3897 u64 rdp;
3898 u32 mxcsr;
3899 u32 mxcsr_mask;
3900 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
3901#ifdef CONFIG_X86_64
3902 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
3903#else
3904 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
3905#endif
3906};
3907
8b006791
ZX		 3908/*
3909 * Translate a guest virtual address to a guest physical address.
3910 */
3911int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
3912 struct kvm_translation *tr)
3913{
3914 unsigned long vaddr = tr->linear_address;
3915 gpa_t gpa;
3916
3917 vcpu_load(vcpu);
72dc67a6 3918 down_read(&vcpu->kvm->slots_lock);
ad312c7c 3919 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 3920 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 3921 tr->physical_address = gpa;
3922 tr->valid = gpa != UNMAPPED_GVA;
3923 tr->writeable = 1;
3924 tr->usermode = 0;
8b006791
ZX		 3925 vcpu_put(vcpu);
3926
3927 return 0;
3928}
3929
d0752060
HB		 3930int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3931{
ad312c7c 3932 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3933
3934 vcpu_load(vcpu);
3935
3936 memcpy(fpu->fpr, fxsave->st_space, 128);
3937 fpu->fcw = fxsave->cwd;
3938 fpu->fsw = fxsave->swd;
3939 fpu->ftwx = fxsave->twd;
3940 fpu->last_opcode = fxsave->fop;
3941 fpu->last_ip = fxsave->rip;
3942 fpu->last_dp = fxsave->rdp;
3943 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
3944
3945 vcpu_put(vcpu);
3946
3947 return 0;
3948}
3949
3950int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
3951{
ad312c7c 3952 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 3953
3954 vcpu_load(vcpu);
3955
3956 memcpy(fxsave->st_space, fpu->fpr, 128);
3957 fxsave->cwd = fpu->fcw;
3958 fxsave->swd = fpu->fsw;
3959 fxsave->twd = fpu->ftwx;
3960 fxsave->fop = fpu->last_opcode;
3961 fxsave->rip = fpu->last_ip;
3962 fxsave->rdp = fpu->last_dp;
3963 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
3964
3965 vcpu_put(vcpu);
3966
3967 return 0;
3968}
3969
3970void fx_init(struct kvm_vcpu *vcpu)
3971{
3972 unsigned after_mxcsr_mask;
3973
bc1a34f1
AA		 3974 /*
3975 * Touch the fpu the first time in non atomic context as if
3976 * this is the first fpu instruction the exception handler
3977 * will fire before the instruction returns and it'll have to
3978 * allocate ram with GFP_KERNEL.
3979 */
3980 if (!used_math())
d6e88aec 3981 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 3982
d0752060
HB		 3983 /* Initialize guest FPU by resetting ours and saving into guest's */
3984 preempt_disable();
d6e88aec
AK		 3985 kvm_fx_save(&vcpu->arch.host_fx_image);
3986 kvm_fx_finit();
3987 kvm_fx_save(&vcpu->arch.guest_fx_image);
3988 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 3989 preempt_enable();
3990
ad312c7c 3991 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 3992 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 3993 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
3994 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 3995 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
3996}
3997EXPORT_SYMBOL_GPL(fx_init);
3998
3999void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4000{
4001 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4002 return;
4003
4004 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4005 kvm_fx_save(&vcpu->arch.host_fx_image);
4006 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4007}
4008EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4009
4010void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4011{
4012 if (!vcpu->guest_fpu_loaded)
4013 return;
4014
4015 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4016 kvm_fx_save(&vcpu->arch.guest_fx_image);
4017 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4018 ++vcpu->stat.fpu_reload;
d0752060
HB		 4019}
4020EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4021
4022void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4023{
4024 kvm_x86_ops->vcpu_free(vcpu);
4025}
4026
4027struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4028 unsigned int id)
4029{
26e5215f
AK		 4030 return kvm_x86_ops->vcpu_create(kvm, id);
4031}
e9b11c17 4032
26e5215f
AK		 4033int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4034{
4035 int r;
e9b11c17
ZX		 4036
4037 /* We do fxsave: this must be aligned. */
ad312c7c 4038 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4039
0bed3b56 4040 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4041 vcpu_load(vcpu);
4042 r = kvm_arch_vcpu_reset(vcpu);
4043 if (r == 0)
4044 r = kvm_mmu_setup(vcpu);
4045 vcpu_put(vcpu);
4046 if (r < 0)
4047 goto free_vcpu;
4048
26e5215f 4049 return 0;
e9b11c17
ZX		 4050free_vcpu:
4051 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4052 return r;
e9b11c17
ZX		 4053}
4054
d40ccc62 4055void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4056{
4057 vcpu_load(vcpu);
4058 kvm_mmu_unload(vcpu);
4059 vcpu_put(vcpu);
4060
4061 kvm_x86_ops->vcpu_free(vcpu);
4062}
4063
4064int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4065{
448fa4a9
JK		 4066 vcpu->arch.nmi_pending = false;
4067 vcpu->arch.nmi_injected = false;
4068
42dbaa5a
JK		 4069 vcpu->arch.switch_db_regs = 0;
4070 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4071 vcpu->arch.dr6 = DR6_FIXED_1;
4072 vcpu->arch.dr7 = DR7_FIXED_1;
4073
e9b11c17
ZX		 4074 return kvm_x86_ops->vcpu_reset(vcpu);
4075}
4076
4077void kvm_arch_hardware_enable(void *garbage)
4078{
4079 kvm_x86_ops->hardware_enable(garbage);
4080}
4081
4082void kvm_arch_hardware_disable(void *garbage)
4083{
4084 kvm_x86_ops->hardware_disable(garbage);
4085}
4086
4087int kvm_arch_hardware_setup(void)
4088{
4089 return kvm_x86_ops->hardware_setup();
4090}
4091
4092void kvm_arch_hardware_unsetup(void)
4093{
4094 kvm_x86_ops->hardware_unsetup();
4095}
4096
4097void kvm_arch_check_processor_compat(void *rtn)
4098{
4099 kvm_x86_ops->check_processor_compatibility(rtn);
4100}
4101
4102int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4103{
4104 struct page *page;
4105 struct kvm *kvm;
4106 int r;
4107
4108 BUG_ON(vcpu->kvm == NULL);
4109 kvm = vcpu->kvm;
4110
ad312c7c 4111 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
e9b11c17 4112 if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
a4535290 4113 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4114 else
a4535290 4115 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4116
4117 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4118 if (!page) {
4119 r = -ENOMEM;
4120 goto fail;
4121 }
ad312c7c 4122 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4123
4124 r = kvm_mmu_create(vcpu);
4125 if (r < 0)
4126 goto fail_free_pio_data;
4127
4128 if (irqchip_in_kernel(kvm)) {
4129 r = kvm_create_lapic(vcpu);
4130 if (r < 0)
4131 goto fail_mmu_destroy;
4132 }
4133
4134 return 0;
4135
4136fail_mmu_destroy:
4137 kvm_mmu_destroy(vcpu);
4138fail_free_pio_data:
ad312c7c 4139 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4140fail:
4141 return r;
4142}
4143
4144void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4145{
4146 kvm_free_lapic(vcpu);
3200f405 4147 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4148 kvm_mmu_destroy(vcpu);
3200f405 4149 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4150 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4151}
d19a9cd2
ZX		 4152
4153struct kvm *kvm_arch_create_vm(void)
4154{
4155 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4156
4157 if (!kvm)
4158 return ERR_PTR(-ENOMEM);
4159
f05e70ac 4160 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
6cffe8ca 4161 INIT_LIST_HEAD(&kvm->arch.oos_global_pages);
4d5c5d0f 4162 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4163
5550af4d
SY		 4164 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4165 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4166
53f658b3
MT		 4167 rdtscll(kvm->arch.vm_init_tsc);
4168
d19a9cd2
ZX		 4169 return kvm;
4170}
4171
4172static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4173{
4174 vcpu_load(vcpu);
4175 kvm_mmu_unload(vcpu);
4176 vcpu_put(vcpu);
4177}
4178
4179static void kvm_free_vcpus(struct kvm *kvm)
4180{
4181 unsigned int i;
4182
4183 /*
4184 * Unpin any mmu pages first.
4185 */
4186 for (i = 0; i < KVM_MAX_VCPUS; ++i)
4187 if (kvm->vcpus[i])
4188 kvm_unload_vcpu_mmu(kvm->vcpus[i]);
4189 for (i = 0; i < KVM_MAX_VCPUS; ++i) {
4190 if (kvm->vcpus[i]) {
4191 kvm_arch_vcpu_free(kvm->vcpus[i]);
4192 kvm->vcpus[i] = NULL;
4193 }
4194 }
4195
4196}
4197
ad8ba2cd
SY		 4198void kvm_arch_sync_events(struct kvm *kvm)
4199{
ba4cef31 4200 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4201}
4202
d19a9cd2
ZX		 4203void kvm_arch_destroy_vm(struct kvm *kvm)
4204{
6eb55818 4205 kvm_iommu_unmap_guest(kvm);
7837699f 4206 kvm_free_pit(kvm);
d7deeeb0
ZX		 4207 kfree(kvm->arch.vpic);
4208 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4209 kvm_free_vcpus(kvm);
4210 kvm_free_physmem(kvm);
3d45830c
AK		 4211 if (kvm->arch.apic_access_page)
4212 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4213 if (kvm->arch.ept_identity_pagetable)
4214 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4215 kfree(kvm);
4216}
0de10343
ZX		 4217
4218int kvm_arch_set_memory_region(struct kvm *kvm,
4219 struct kvm_userspace_memory_region *mem,
4220 struct kvm_memory_slot old,
4221 int user_alloc)
4222{
4223 int npages = mem->memory_size >> PAGE_SHIFT;
4224 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4225
4226 /*To keep backward compatibility with older userspace,
4227 *x86 needs to hanlde !user_alloc case.
4228 */
4229 if (!user_alloc) {
4230 if (npages && !old.rmap) {
604b38ac
AA		 4231 unsigned long userspace_addr;
4232
72dc67a6 4233 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4234 userspace_addr = do_mmap(NULL, 0,
4235 npages * PAGE_SIZE,
4236 PROT_READ | PROT_WRITE,
acee3c04 4237 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4238 0);
72dc67a6 4239 up_write(&current->mm->mmap_sem);
0de10343 4240
604b38ac
AA		 4241 if (IS_ERR((void *)userspace_addr))
4242 return PTR_ERR((void *)userspace_addr);
4243
4244 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4245 spin_lock(&kvm->mmu_lock);
4246 memslot->userspace_addr = userspace_addr;
4247 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4248 } else {
4249 if (!old.user_alloc && old.rmap) {
4250 int ret;
4251
72dc67a6 4252 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4253 ret = do_munmap(current->mm, old.userspace_addr,
4254 old.npages * PAGE_SIZE);
72dc67a6 4255 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4256 if (ret < 0)
4257 printk(KERN_WARNING
4258 "kvm_vm_ioctl_set_memory_region: "
4259 "failed to munmap memory\n");
4260 }
4261 }
4262 }
4263
f05e70ac 4264 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4265 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4266 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4267 }
4268
4269 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
4270 kvm_flush_remote_tlbs(kvm);
4271
4272 return 0;
4273}
1d737c8a 4274
34d4cb8f
MT		 4275void kvm_arch_flush_shadow(struct kvm *kvm)
4276{
4277 kvm_mmu_zap_all(kvm);
4278}
4279
1d737c8a
ZX		 4280int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4281{
a4535290 4282 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4283 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4284 || vcpu->arch.nmi_pending;
1d737c8a 4285}
5736199a
ZX		 4286
4287static void vcpu_kick_intr(void *info)
4288{
4289#ifdef DEBUG
4290 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)info;
4291 printk(KERN_DEBUG "vcpu_kick_intr %p \n", vcpu);
4292#endif
4293}
4294
4295void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4296{
4297 int ipi_pcpu = vcpu->cpu;
e9571ed5 4298 int cpu = get_cpu();
5736199a
ZX		 4299
4300 if (waitqueue_active(&vcpu->wq)) {
4301 wake_up_interruptible(&vcpu->wq);
4302 ++vcpu->stat.halt_wakeup;
4303 }
e9571ed5
MT		 4304 /*
4305 * We may be called synchronously with irqs disabled in guest mode,
4306 * So need not to call smp_call_function_single() in that case.
4307 */
4308 if (vcpu->guest_mode && vcpu->cpu != cpu)
8691e5a8 4309 smp_call_function_single(ipi_pcpu, vcpu_kick_intr, vcpu, 0);
e9571ed5 4310 put_cpu();
5736199a 4311}
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