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Commit | Line | Data |
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f58b082a RW |
1 | /* |
2 | * ACPI support for Intel Lynxpoint LPSS. | |
3 | * | |
3df2da96 | 4 | * Copyright (C) 2013, Intel Corporation |
f58b082a RW |
5 | * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> |
6 | * Rafael J. Wysocki <rafael.j.wysocki@intel.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/acpi.h> | |
f58b082a RW |
14 | #include <linux/clkdev.h> |
15 | #include <linux/clk-provider.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/io.h> | |
eebb3e8d | 18 | #include <linux/mutex.h> |
f58b082a RW |
19 | #include <linux/platform_device.h> |
20 | #include <linux/platform_data/clk-lpss.h> | |
80a7581f | 21 | #include <linux/platform_data/x86/pmc_atom.h> |
989561de | 22 | #include <linux/pm_domain.h> |
2e0f8822 | 23 | #include <linux/pm_runtime.h> |
bf7696a1 | 24 | #include <linux/pwm.h> |
def76401 | 25 | #include <linux/suspend.h> |
c78b0830 | 26 | #include <linux/delay.h> |
f58b082a RW |
27 | |
28 | #include "internal.h" | |
29 | ||
30 | ACPI_MODULE_NAME("acpi_lpss"); | |
31 | ||
d6ddaaac RW |
32 | #ifdef CONFIG_X86_INTEL_LPSS |
33 | ||
eebb3e8d | 34 | #include <asm/cpu_device_id.h> |
4626d840 | 35 | #include <asm/intel-family.h> |
eebb3e8d | 36 | #include <asm/iosf_mbi.h> |
eebb3e8d | 37 | |
d6ddaaac RW |
38 | #define LPSS_ADDR(desc) ((unsigned long)&desc) |
39 | ||
f58b082a | 40 | #define LPSS_CLK_SIZE 0x04 |
2e0f8822 RW |
41 | #define LPSS_LTR_SIZE 0x18 |
42 | ||
43 | /* Offsets relative to LPSS_PRIVATE_OFFSET */ | |
ed3a872e | 44 | #define LPSS_CLK_DIVIDER_DEF_MASK (BIT(1) | BIT(16)) |
765bdd4e MW |
45 | #define LPSS_RESETS 0x04 |
46 | #define LPSS_RESETS_RESET_FUNC BIT(0) | |
47 | #define LPSS_RESETS_RESET_APB BIT(1) | |
2e0f8822 RW |
48 | #define LPSS_GENERAL 0x08 |
49 | #define LPSS_GENERAL_LTR_MODE_SW BIT(2) | |
088f1fd2 | 50 | #define LPSS_GENERAL_UART_RTS_OVRD BIT(3) |
2e0f8822 RW |
51 | #define LPSS_SW_LTR 0x10 |
52 | #define LPSS_AUTO_LTR 0x14 | |
1a8f8351 RW |
53 | #define LPSS_LTR_SNOOP_REQ BIT(15) |
54 | #define LPSS_LTR_SNOOP_MASK 0x0000FFFF | |
55 | #define LPSS_LTR_SNOOP_LAT_1US 0x800 | |
56 | #define LPSS_LTR_SNOOP_LAT_32US 0xC00 | |
57 | #define LPSS_LTR_SNOOP_LAT_SHIFT 5 | |
58 | #define LPSS_LTR_SNOOP_LAT_CUTOFF 3000 | |
59 | #define LPSS_LTR_MAX_VAL 0x3FF | |
06d86415 HK |
60 | #define LPSS_TX_INT 0x20 |
61 | #define LPSS_TX_INT_MASK BIT(1) | |
f58b082a | 62 | |
c78b0830 HK |
63 | #define LPSS_PRV_REG_COUNT 9 |
64 | ||
ff8c1af5 HK |
65 | /* LPSS Flags */ |
66 | #define LPSS_CLK BIT(0) | |
67 | #define LPSS_CLK_GATE BIT(1) | |
68 | #define LPSS_CLK_DIVIDER BIT(2) | |
69 | #define LPSS_LTR BIT(3) | |
70 | #define LPSS_SAVE_CTX BIT(4) | |
b00855ae | 71 | #define LPSS_NO_D3_DELAY BIT(5) |
f6272170 | 72 | |
8f47745c HG |
73 | /* Crystal Cove PMIC shares same ACPI ID between different platforms */ |
74 | #define BYT_CRC_HRV 2 | |
75 | #define CHT_CRC_HRV 3 | |
76 | ||
06d86415 | 77 | struct lpss_private_data; |
f58b082a RW |
78 | |
79 | struct lpss_device_desc { | |
ff8c1af5 | 80 | unsigned int flags; |
fcf0789a | 81 | const char *clk_con_id; |
2e0f8822 | 82 | unsigned int prv_offset; |
958c4eb2 | 83 | size_t prv_size_override; |
a5565cf2 | 84 | struct property_entry *properties; |
06d86415 | 85 | void (*setup)(struct lpss_private_data *pdata); |
f58b082a RW |
86 | }; |
87 | ||
eebb3e8d | 88 | static const struct lpss_device_desc lpss_dma_desc = { |
3df2da96 | 89 | .flags = LPSS_CLK, |
b59cc200 RW |
90 | }; |
91 | ||
f58b082a | 92 | struct lpss_private_data { |
dd242a08 | 93 | struct acpi_device *adev; |
f58b082a RW |
94 | void __iomem *mmio_base; |
95 | resource_size_t mmio_size; | |
03f09f73 | 96 | unsigned int fixed_clk_rate; |
f58b082a RW |
97 | struct clk *clk; |
98 | const struct lpss_device_desc *dev_desc; | |
c78b0830 | 99 | u32 prv_reg_ctx[LPSS_PRV_REG_COUNT]; |
f58b082a RW |
100 | }; |
101 | ||
eebb3e8d AS |
102 | /* LPSS run time quirks */ |
103 | static unsigned int lpss_quirks; | |
104 | ||
105 | /* | |
106 | * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device. | |
107 | * | |
fa9e93b1 | 108 | * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover |
eebb3e8d AS |
109 | * it can be powered off automatically whenever the last LPSS device goes down. |
110 | * In case of no power any access to the DMA controller will hang the system. | |
111 | * The behaviour is reproduced on some HP laptops based on Intel BayTrail as | |
112 | * well as on ASuS T100TA transformer. | |
113 | * | |
114 | * This quirk overrides power state of entire LPSS island to keep DMA powered | |
115 | * on whenever we have at least one other device in use. | |
116 | */ | |
117 | #define LPSS_QUIRK_ALWAYS_POWER_ON BIT(0) | |
118 | ||
1f47a77c HK |
119 | /* UART Component Parameter Register */ |
120 | #define LPSS_UART_CPR 0xF4 | |
121 | #define LPSS_UART_CPR_AFCE BIT(4) | |
122 | ||
06d86415 HK |
123 | static void lpss_uart_setup(struct lpss_private_data *pdata) |
124 | { | |
088f1fd2 | 125 | unsigned int offset; |
1f47a77c | 126 | u32 val; |
06d86415 | 127 | |
088f1fd2 | 128 | offset = pdata->dev_desc->prv_offset + LPSS_TX_INT; |
1f47a77c HK |
129 | val = readl(pdata->mmio_base + offset); |
130 | writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset); | |
131 | ||
132 | val = readl(pdata->mmio_base + LPSS_UART_CPR); | |
133 | if (!(val & LPSS_UART_CPR_AFCE)) { | |
134 | offset = pdata->dev_desc->prv_offset + LPSS_GENERAL; | |
135 | val = readl(pdata->mmio_base + offset); | |
136 | val |= LPSS_GENERAL_UART_RTS_OVRD; | |
137 | writel(val, pdata->mmio_base + offset); | |
138 | } | |
06d86415 HK |
139 | } |
140 | ||
3095794a | 141 | static void lpss_deassert_reset(struct lpss_private_data *pdata) |
765bdd4e MW |
142 | { |
143 | unsigned int offset; | |
144 | u32 val; | |
145 | ||
146 | offset = pdata->dev_desc->prv_offset + LPSS_RESETS; | |
147 | val = readl(pdata->mmio_base + offset); | |
148 | val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC; | |
149 | writel(val, pdata->mmio_base + offset); | |
3095794a MW |
150 | } |
151 | ||
04434ab5 HG |
152 | /* |
153 | * BYT PWM used for backlight control by the i915 driver on systems without | |
154 | * the Crystal Cove PMIC. | |
155 | */ | |
156 | static struct pwm_lookup byt_pwm_lookup[] = { | |
157 | PWM_LOOKUP_WITH_MODULE("80860F09:00", 0, "0000:00:02.0", | |
158 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
159 | "pwm-lpss-platform"), | |
160 | }; | |
161 | ||
162 | static void byt_pwm_setup(struct lpss_private_data *pdata) | |
163 | { | |
dd242a08 HG |
164 | struct acpi_device *adev = pdata->adev; |
165 | ||
166 | /* Only call pwm_add_table for the first PWM controller */ | |
167 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
168 | return; | |
169 | ||
8f47745c | 170 | if (!acpi_dev_present("INT33FD", NULL, BYT_CRC_HRV)) |
04434ab5 HG |
171 | pwm_add_table(byt_pwm_lookup, ARRAY_SIZE(byt_pwm_lookup)); |
172 | } | |
173 | ||
3095794a MW |
174 | #define LPSS_I2C_ENABLE 0x6c |
175 | ||
176 | static void byt_i2c_setup(struct lpss_private_data *pdata) | |
177 | { | |
178 | lpss_deassert_reset(pdata); | |
765bdd4e | 179 | |
03f09f73 HK |
180 | if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset)) |
181 | pdata->fixed_clk_rate = 133000000; | |
3293c7b8 MW |
182 | |
183 | writel(0, pdata->mmio_base + LPSS_I2C_ENABLE); | |
765bdd4e | 184 | } |
43218a1b | 185 | |
bf7696a1 HG |
186 | /* BSW PWM used for backlight control by the i915 driver */ |
187 | static struct pwm_lookup bsw_pwm_lookup[] = { | |
188 | PWM_LOOKUP_WITH_MODULE("80862288:00", 0, "0000:00:02.0", | |
189 | "pwm_backlight", 0, PWM_POLARITY_NORMAL, | |
190 | "pwm-lpss-platform"), | |
191 | }; | |
192 | ||
193 | static void bsw_pwm_setup(struct lpss_private_data *pdata) | |
194 | { | |
dd242a08 HG |
195 | struct acpi_device *adev = pdata->adev; |
196 | ||
197 | /* Only call pwm_add_table for the first PWM controller */ | |
198 | if (!adev->pnp.unique_id || strcmp(adev->pnp.unique_id, "1")) | |
199 | return; | |
200 | ||
bf7696a1 HG |
201 | pwm_add_table(bsw_pwm_lookup, ARRAY_SIZE(bsw_pwm_lookup)); |
202 | } | |
203 | ||
b2687cd7 | 204 | static const struct lpss_device_desc lpt_dev_desc = { |
ff8c1af5 | 205 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
ed3a872e | 206 | .prv_offset = 0x800, |
ed3a872e HK |
207 | }; |
208 | ||
b2687cd7 | 209 | static const struct lpss_device_desc lpt_i2c_dev_desc = { |
ff8c1af5 | 210 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR, |
2e0f8822 | 211 | .prv_offset = 0x800, |
2e0f8822 RW |
212 | }; |
213 | ||
a5565cf2 HK |
214 | static struct property_entry uart_properties[] = { |
215 | PROPERTY_ENTRY_U32("reg-io-width", 4), | |
216 | PROPERTY_ENTRY_U32("reg-shift", 2), | |
217 | PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"), | |
218 | { }, | |
219 | }; | |
220 | ||
b2687cd7 | 221 | static const struct lpss_device_desc lpt_uart_dev_desc = { |
ff8c1af5 | 222 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR, |
fcf0789a | 223 | .clk_con_id = "baudclk", |
06d86415 | 224 | .prv_offset = 0x800, |
06d86415 | 225 | .setup = lpss_uart_setup, |
a5565cf2 | 226 | .properties = uart_properties, |
2e0f8822 RW |
227 | }; |
228 | ||
b2687cd7 | 229 | static const struct lpss_device_desc lpt_sdio_dev_desc = { |
ff8c1af5 | 230 | .flags = LPSS_LTR, |
2e0f8822 | 231 | .prv_offset = 0x1000, |
958c4eb2 | 232 | .prv_size_override = 0x1018, |
e1c74817 CCE |
233 | }; |
234 | ||
b2687cd7 | 235 | static const struct lpss_device_desc byt_pwm_dev_desc = { |
3f56bf3e | 236 | .flags = LPSS_SAVE_CTX, |
b3a16539 | 237 | .prv_offset = 0x800, |
04434ab5 | 238 | .setup = byt_pwm_setup, |
e1c74817 CCE |
239 | }; |
240 | ||
b00855ae SK |
241 | static const struct lpss_device_desc bsw_pwm_dev_desc = { |
242 | .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
b3a16539 | 243 | .prv_offset = 0x800, |
bf7696a1 | 244 | .setup = bsw_pwm_setup, |
b00855ae SK |
245 | }; |
246 | ||
b2687cd7 | 247 | static const struct lpss_device_desc byt_uart_dev_desc = { |
3df2da96 | 248 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
fcf0789a | 249 | .clk_con_id = "baudclk", |
f6272170 | 250 | .prv_offset = 0x800, |
06d86415 | 251 | .setup = lpss_uart_setup, |
a5565cf2 | 252 | .properties = uart_properties, |
f6272170 MW |
253 | }; |
254 | ||
b00855ae SK |
255 | static const struct lpss_device_desc bsw_uart_dev_desc = { |
256 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX | |
257 | | LPSS_NO_D3_DELAY, | |
258 | .clk_con_id = "baudclk", | |
259 | .prv_offset = 0x800, | |
260 | .setup = lpss_uart_setup, | |
a5565cf2 | 261 | .properties = uart_properties, |
b00855ae SK |
262 | }; |
263 | ||
b2687cd7 | 264 | static const struct lpss_device_desc byt_spi_dev_desc = { |
3df2da96 | 265 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX, |
f6272170 | 266 | .prv_offset = 0x400, |
f6272170 MW |
267 | }; |
268 | ||
b2687cd7 | 269 | static const struct lpss_device_desc byt_sdio_dev_desc = { |
3df2da96 | 270 | .flags = LPSS_CLK, |
f6272170 MW |
271 | }; |
272 | ||
b2687cd7 | 273 | static const struct lpss_device_desc byt_i2c_dev_desc = { |
3df2da96 | 274 | .flags = LPSS_CLK | LPSS_SAVE_CTX, |
f6272170 | 275 | .prv_offset = 0x800, |
03f09f73 | 276 | .setup = byt_i2c_setup, |
1bfbd8eb AC |
277 | }; |
278 | ||
b00855ae SK |
279 | static const struct lpss_device_desc bsw_i2c_dev_desc = { |
280 | .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY, | |
281 | .prv_offset = 0x800, | |
282 | .setup = byt_i2c_setup, | |
283 | }; | |
284 | ||
eebb3e8d | 285 | static const struct lpss_device_desc bsw_spi_dev_desc = { |
b00855ae SK |
286 | .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX |
287 | | LPSS_NO_D3_DELAY, | |
3095794a MW |
288 | .prv_offset = 0x400, |
289 | .setup = lpss_deassert_reset, | |
290 | }; | |
291 | ||
eebb3e8d AS |
292 | #define ICPU(model) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, } |
293 | ||
294 | static const struct x86_cpu_id lpss_cpu_ids[] = { | |
2811e5d5 | 295 | ICPU(INTEL_FAM6_ATOM_SILVERMONT), /* Valleyview, Bay Trail */ |
4626d840 | 296 | ICPU(INTEL_FAM6_ATOM_AIRMONT), /* Braswell, Cherry Trail */ |
eebb3e8d AS |
297 | {} |
298 | }; | |
299 | ||
d6ddaaac RW |
300 | #else |
301 | ||
302 | #define LPSS_ADDR(desc) (0UL) | |
303 | ||
304 | #endif /* CONFIG_X86_INTEL_LPSS */ | |
305 | ||
f58b082a | 306 | static const struct acpi_device_id acpi_lpss_device_ids[] = { |
b59cc200 | 307 | /* Generic LPSS devices */ |
d6ddaaac | 308 | { "INTL9C60", LPSS_ADDR(lpss_dma_desc) }, |
b59cc200 | 309 | |
f58b082a | 310 | /* Lynxpoint LPSS devices */ |
d6ddaaac RW |
311 | { "INT33C0", LPSS_ADDR(lpt_dev_desc) }, |
312 | { "INT33C1", LPSS_ADDR(lpt_dev_desc) }, | |
313 | { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
314 | { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
315 | { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) }, | |
316 | { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) }, | |
317 | { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
f58b082a RW |
318 | { "INT33C7", }, |
319 | ||
f6272170 | 320 | /* BayTrail LPSS devices */ |
d6ddaaac RW |
321 | { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) }, |
322 | { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) }, | |
323 | { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) }, | |
324 | { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) }, | |
325 | { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) }, | |
f6272170 | 326 | { "INT33B2", }, |
20482d32 | 327 | { "INT33FC", }, |
f6272170 | 328 | |
1bfbd8eb | 329 | /* Braswell LPSS devices */ |
b00855ae SK |
330 | { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) }, |
331 | { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) }, | |
3095794a | 332 | { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) }, |
b00855ae | 333 | { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) }, |
1bfbd8eb | 334 | |
b00855ae | 335 | /* Broadwell LPSS devices */ |
d6ddaaac RW |
336 | { "INT3430", LPSS_ADDR(lpt_dev_desc) }, |
337 | { "INT3431", LPSS_ADDR(lpt_dev_desc) }, | |
338 | { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
339 | { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) }, | |
340 | { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) }, | |
341 | { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) }, | |
342 | { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) }, | |
a4d97536 MW |
343 | { "INT3437", }, |
344 | ||
ff8c1af5 HK |
345 | /* Wildcat Point LPSS devices */ |
346 | { "INT3438", LPSS_ADDR(lpt_dev_desc) }, | |
43218a1b | 347 | |
f58b082a RW |
348 | { } |
349 | }; | |
350 | ||
d6ddaaac RW |
351 | #ifdef CONFIG_X86_INTEL_LPSS |
352 | ||
f58b082a RW |
353 | static int is_memory(struct acpi_resource *res, void *not_used) |
354 | { | |
355 | struct resource r; | |
356 | return !acpi_dev_resource_memory(res, &r); | |
357 | } | |
358 | ||
359 | /* LPSS main clock device. */ | |
360 | static struct platform_device *lpss_clk_dev; | |
361 | ||
362 | static inline void lpt_register_clock_device(void) | |
363 | { | |
364 | lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0); | |
365 | } | |
366 | ||
367 | static int register_device_clock(struct acpi_device *adev, | |
368 | struct lpss_private_data *pdata) | |
369 | { | |
370 | const struct lpss_device_desc *dev_desc = pdata->dev_desc; | |
ed3a872e | 371 | const char *devname = dev_name(&adev->dev); |
71c50dbe | 372 | struct clk *clk; |
b59cc200 | 373 | struct lpss_clk_data *clk_data; |
ed3a872e HK |
374 | const char *parent, *clk_name; |
375 | void __iomem *prv_base; | |
f58b082a RW |
376 | |
377 | if (!lpss_clk_dev) | |
378 | lpt_register_clock_device(); | |
379 | ||
b59cc200 RW |
380 | clk_data = platform_get_drvdata(lpss_clk_dev); |
381 | if (!clk_data) | |
382 | return -ENODEV; | |
b0d00f8b | 383 | clk = clk_data->clk; |
b59cc200 RW |
384 | |
385 | if (!pdata->mmio_base | |
2e0f8822 | 386 | || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE) |
f58b082a RW |
387 | return -ENODATA; |
388 | ||
f6272170 | 389 | parent = clk_data->name; |
ed3a872e | 390 | prv_base = pdata->mmio_base + dev_desc->prv_offset; |
f6272170 | 391 | |
03f09f73 HK |
392 | if (pdata->fixed_clk_rate) { |
393 | clk = clk_register_fixed_rate(NULL, devname, parent, 0, | |
394 | pdata->fixed_clk_rate); | |
395 | goto out; | |
f6272170 MW |
396 | } |
397 | ||
ff8c1af5 | 398 | if (dev_desc->flags & LPSS_CLK_GATE) { |
ed3a872e HK |
399 | clk = clk_register_gate(NULL, devname, parent, 0, |
400 | prv_base, 0, 0, NULL); | |
401 | parent = devname; | |
402 | } | |
403 | ||
ff8c1af5 | 404 | if (dev_desc->flags & LPSS_CLK_DIVIDER) { |
ed3a872e HK |
405 | /* Prevent division by zero */ |
406 | if (!readl(prv_base)) | |
407 | writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base); | |
408 | ||
409 | clk_name = kasprintf(GFP_KERNEL, "%s-div", devname); | |
410 | if (!clk_name) | |
411 | return -ENOMEM; | |
412 | clk = clk_register_fractional_divider(NULL, clk_name, parent, | |
413 | 0, prv_base, | |
414 | 1, 15, 16, 15, 0, NULL); | |
415 | parent = clk_name; | |
416 | ||
417 | clk_name = kasprintf(GFP_KERNEL, "%s-update", devname); | |
418 | if (!clk_name) { | |
419 | kfree(parent); | |
420 | return -ENOMEM; | |
421 | } | |
422 | clk = clk_register_gate(NULL, clk_name, parent, | |
423 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, | |
424 | prv_base, 31, 0, NULL); | |
425 | kfree(parent); | |
426 | kfree(clk_name); | |
f6272170 | 427 | } |
03f09f73 | 428 | out: |
f6272170 MW |
429 | if (IS_ERR(clk)) |
430 | return PTR_ERR(clk); | |
f58b082a | 431 | |
ed3a872e | 432 | pdata->clk = clk; |
fcf0789a | 433 | clk_register_clkdev(clk, dev_desc->clk_con_id, devname); |
f58b082a RW |
434 | return 0; |
435 | } | |
436 | ||
437 | static int acpi_lpss_create_device(struct acpi_device *adev, | |
438 | const struct acpi_device_id *id) | |
439 | { | |
b2687cd7 | 440 | const struct lpss_device_desc *dev_desc; |
f58b082a | 441 | struct lpss_private_data *pdata; |
90e97820 | 442 | struct resource_entry *rentry; |
f58b082a | 443 | struct list_head resource_list; |
8ce62f85 | 444 | struct platform_device *pdev; |
f58b082a RW |
445 | int ret; |
446 | ||
b2687cd7 | 447 | dev_desc = (const struct lpss_device_desc *)id->driver_data; |
8ce62f85 | 448 | if (!dev_desc) { |
1571875b | 449 | pdev = acpi_create_platform_device(adev, NULL); |
8ce62f85 RW |
450 | return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1; |
451 | } | |
f58b082a RW |
452 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); |
453 | if (!pdata) | |
454 | return -ENOMEM; | |
455 | ||
456 | INIT_LIST_HEAD(&resource_list); | |
457 | ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL); | |
458 | if (ret < 0) | |
459 | goto err_out; | |
460 | ||
461 | list_for_each_entry(rentry, &resource_list, node) | |
90e97820 | 462 | if (resource_type(rentry->res) == IORESOURCE_MEM) { |
958c4eb2 MW |
463 | if (dev_desc->prv_size_override) |
464 | pdata->mmio_size = dev_desc->prv_size_override; | |
465 | else | |
90e97820 JL |
466 | pdata->mmio_size = resource_size(rentry->res); |
467 | pdata->mmio_base = ioremap(rentry->res->start, | |
f58b082a | 468 | pdata->mmio_size); |
f58b082a RW |
469 | break; |
470 | } | |
471 | ||
472 | acpi_dev_free_resource_list(&resource_list); | |
473 | ||
d3e13ff3 | 474 | if (!pdata->mmio_base) { |
bebbabc3 HG |
475 | /* Avoid acpi_bus_attach() instantiating a pdev for this dev. */ |
476 | adev->pnp.type.platform_id = 0; | |
a4bb2b49 RT |
477 | /* Skip the device, but continue the namespace scan. */ |
478 | ret = 0; | |
d3e13ff3 RW |
479 | goto err_out; |
480 | } | |
481 | ||
dd242a08 | 482 | pdata->adev = adev; |
af65cfe9 MW |
483 | pdata->dev_desc = dev_desc; |
484 | ||
03f09f73 HK |
485 | if (dev_desc->setup) |
486 | dev_desc->setup(pdata); | |
487 | ||
ff8c1af5 | 488 | if (dev_desc->flags & LPSS_CLK) { |
f58b082a RW |
489 | ret = register_device_clock(adev, pdata); |
490 | if (ret) { | |
b9e95fc6 RW |
491 | /* Skip the device, but continue the namespace scan. */ |
492 | ret = 0; | |
493 | goto err_out; | |
f58b082a RW |
494 | } |
495 | } | |
496 | ||
b9e95fc6 RW |
497 | /* |
498 | * This works around a known issue in ACPI tables where LPSS devices | |
499 | * have _PS0 and _PS3 without _PSC (and no power resources), so | |
500 | * acpi_bus_init_power() will assume that the BIOS has put them into D0. | |
501 | */ | |
502 | ret = acpi_device_fix_up_power(adev); | |
503 | if (ret) { | |
504 | /* Skip the device, but continue the namespace scan. */ | |
505 | ret = 0; | |
506 | goto err_out; | |
507 | } | |
508 | ||
f58b082a | 509 | adev->driver_data = pdata; |
1571875b | 510 | pdev = acpi_create_platform_device(adev, dev_desc->properties); |
8ce62f85 | 511 | if (!IS_ERR_OR_NULL(pdev)) { |
8ce62f85 RW |
512 | return 1; |
513 | } | |
f58b082a | 514 | |
8ce62f85 | 515 | ret = PTR_ERR(pdev); |
f58b082a RW |
516 | adev->driver_data = NULL; |
517 | ||
518 | err_out: | |
519 | kfree(pdata); | |
520 | return ret; | |
521 | } | |
522 | ||
1a8f8351 RW |
523 | static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg) |
524 | { | |
525 | return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
526 | } | |
527 | ||
528 | static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata, | |
529 | unsigned int reg) | |
530 | { | |
531 | writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg); | |
532 | } | |
533 | ||
2e0f8822 RW |
534 | static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val) |
535 | { | |
536 | struct acpi_device *adev; | |
537 | struct lpss_private_data *pdata; | |
538 | unsigned long flags; | |
539 | int ret; | |
540 | ||
541 | ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev); | |
542 | if (WARN_ON(ret)) | |
543 | return ret; | |
544 | ||
545 | spin_lock_irqsave(&dev->power.lock, flags); | |
546 | if (pm_runtime_suspended(dev)) { | |
547 | ret = -EAGAIN; | |
548 | goto out; | |
549 | } | |
550 | pdata = acpi_driver_data(adev); | |
551 | if (WARN_ON(!pdata || !pdata->mmio_base)) { | |
552 | ret = -ENODEV; | |
553 | goto out; | |
554 | } | |
1a8f8351 | 555 | *val = __lpss_reg_read(pdata, reg); |
2e0f8822 RW |
556 | |
557 | out: | |
558 | spin_unlock_irqrestore(&dev->power.lock, flags); | |
559 | return ret; | |
560 | } | |
561 | ||
562 | static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr, | |
563 | char *buf) | |
564 | { | |
565 | u32 ltr_value = 0; | |
566 | unsigned int reg; | |
567 | int ret; | |
568 | ||
569 | reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR; | |
570 | ret = lpss_reg_read(dev, reg, <r_value); | |
571 | if (ret) | |
572 | return ret; | |
573 | ||
574 | return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value); | |
575 | } | |
576 | ||
577 | static ssize_t lpss_ltr_mode_show(struct device *dev, | |
578 | struct device_attribute *attr, char *buf) | |
579 | { | |
580 | u32 ltr_mode = 0; | |
581 | char *outstr; | |
582 | int ret; | |
583 | ||
584 | ret = lpss_reg_read(dev, LPSS_GENERAL, <r_mode); | |
585 | if (ret) | |
586 | return ret; | |
587 | ||
588 | outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto"; | |
589 | return sprintf(buf, "%s\n", outstr); | |
590 | } | |
591 | ||
592 | static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
593 | static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL); | |
594 | static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL); | |
595 | ||
596 | static struct attribute *lpss_attrs[] = { | |
597 | &dev_attr_auto_ltr.attr, | |
598 | &dev_attr_sw_ltr.attr, | |
599 | &dev_attr_ltr_mode.attr, | |
600 | NULL, | |
601 | }; | |
602 | ||
31945d0e | 603 | static const struct attribute_group lpss_attr_group = { |
2e0f8822 RW |
604 | .attrs = lpss_attrs, |
605 | .name = "lpss_ltr", | |
606 | }; | |
607 | ||
1a8f8351 RW |
608 | static void acpi_lpss_set_ltr(struct device *dev, s32 val) |
609 | { | |
610 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
611 | u32 ltr_mode, ltr_val; | |
612 | ||
613 | ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL); | |
614 | if (val < 0) { | |
615 | if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) { | |
616 | ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW; | |
617 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
618 | } | |
619 | return; | |
620 | } | |
621 | ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK; | |
622 | if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) { | |
623 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US; | |
624 | val = LPSS_LTR_MAX_VAL; | |
625 | } else if (val > LPSS_LTR_MAX_VAL) { | |
626 | ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ; | |
627 | val >>= LPSS_LTR_SNOOP_LAT_SHIFT; | |
628 | } else { | |
629 | ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ; | |
630 | } | |
631 | ltr_val |= val; | |
632 | __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR); | |
633 | if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) { | |
634 | ltr_mode |= LPSS_GENERAL_LTR_MODE_SW; | |
635 | __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL); | |
636 | } | |
637 | } | |
638 | ||
c78b0830 HK |
639 | #ifdef CONFIG_PM |
640 | /** | |
641 | * acpi_lpss_save_ctx() - Save the private registers of LPSS device | |
642 | * @dev: LPSS device | |
cb39dcdd | 643 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
644 | * |
645 | * Most LPSS devices have private registers which may loose their context when | |
646 | * the device is powered down. acpi_lpss_save_ctx() saves those registers into | |
647 | * prv_reg_ctx array. | |
648 | */ | |
cb39dcdd AS |
649 | static void acpi_lpss_save_ctx(struct device *dev, |
650 | struct lpss_private_data *pdata) | |
c78b0830 | 651 | { |
c78b0830 HK |
652 | unsigned int i; |
653 | ||
654 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { | |
655 | unsigned long offset = i * sizeof(u32); | |
656 | ||
657 | pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset); | |
658 | dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n", | |
659 | pdata->prv_reg_ctx[i], offset); | |
660 | } | |
661 | } | |
662 | ||
663 | /** | |
664 | * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device | |
665 | * @dev: LPSS device | |
cb39dcdd | 666 | * @pdata: pointer to the private data of the LPSS device |
c78b0830 HK |
667 | * |
668 | * Restores the registers that were previously stored with acpi_lpss_save_ctx(). | |
669 | */ | |
cb39dcdd AS |
670 | static void acpi_lpss_restore_ctx(struct device *dev, |
671 | struct lpss_private_data *pdata) | |
c78b0830 | 672 | { |
c78b0830 HK |
673 | unsigned int i; |
674 | ||
02b98540 AS |
675 | for (i = 0; i < LPSS_PRV_REG_COUNT; i++) { |
676 | unsigned long offset = i * sizeof(u32); | |
677 | ||
678 | __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset); | |
679 | dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n", | |
680 | pdata->prv_reg_ctx[i], offset); | |
681 | } | |
682 | } | |
683 | ||
684 | static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata) | |
685 | { | |
c78b0830 HK |
686 | /* |
687 | * The following delay is needed or the subsequent write operations may | |
688 | * fail. The LPSS devices are actually PCI devices and the PCI spec | |
689 | * expects 10ms delay before the device can be accessed after D3 to D0 | |
b00855ae | 690 | * transition. However some platforms like BSW does not need this delay. |
c78b0830 | 691 | */ |
b00855ae SK |
692 | unsigned int delay = 10; /* default 10ms delay */ |
693 | ||
694 | if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY) | |
695 | delay = 0; | |
696 | ||
697 | msleep(delay); | |
c78b0830 HK |
698 | } |
699 | ||
c3a49cf3 AS |
700 | static int acpi_lpss_activate(struct device *dev) |
701 | { | |
702 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
703 | int ret; | |
704 | ||
63705c40 | 705 | ret = acpi_dev_resume(dev); |
c3a49cf3 AS |
706 | if (ret) |
707 | return ret; | |
708 | ||
709 | acpi_lpss_d3_to_d0_delay(pdata); | |
710 | ||
711 | /* | |
712 | * This is called only on ->probe() stage where a device is either in | |
713 | * known state defined by BIOS or most likely powered off. Due to this | |
714 | * we have to deassert reset line to be sure that ->probe() will | |
715 | * recognize the device. | |
716 | */ | |
717 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) | |
718 | lpss_deassert_reset(pdata); | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | static void acpi_lpss_dismiss(struct device *dev) | |
724 | { | |
cbe25ce3 | 725 | acpi_dev_suspend(dev, false); |
c3a49cf3 AS |
726 | } |
727 | ||
eebb3e8d AS |
728 | /* IOSF SB for LPSS island */ |
729 | #define LPSS_IOSF_UNIT_LPIOEP 0xA0 | |
730 | #define LPSS_IOSF_UNIT_LPIO1 0xAB | |
731 | #define LPSS_IOSF_UNIT_LPIO2 0xAC | |
732 | ||
733 | #define LPSS_IOSF_PMCSR 0x84 | |
734 | #define LPSS_PMCSR_D0 0 | |
735 | #define LPSS_PMCSR_D3hot 3 | |
736 | #define LPSS_PMCSR_Dx_MASK GENMASK(1, 0) | |
737 | ||
738 | #define LPSS_IOSF_GPIODEF0 0x154 | |
739 | #define LPSS_GPIODEF0_DMA1_D3 BIT(2) | |
740 | #define LPSS_GPIODEF0_DMA2_D3 BIT(3) | |
741 | #define LPSS_GPIODEF0_DMA_D3_MASK GENMASK(3, 2) | |
d132d6d5 | 742 | #define LPSS_GPIODEF0_DMA_LLP BIT(13) |
eebb3e8d AS |
743 | |
744 | static DEFINE_MUTEX(lpss_iosf_mutex); | |
a3911dfe | 745 | static bool lpss_iosf_d3_entered = true; |
eebb3e8d AS |
746 | |
747 | static void lpss_iosf_enter_d3_state(void) | |
748 | { | |
749 | u32 value1 = 0; | |
d132d6d5 | 750 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; |
eebb3e8d AS |
751 | u32 value2 = LPSS_PMCSR_D3hot; |
752 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
753 | /* | |
754 | * PMC provides an information about actual status of the LPSS devices. | |
755 | * Here we read the values related to LPSS power island, i.e. LPSS | |
756 | * devices, excluding both LPSS DMA controllers, along with SCC domain. | |
757 | */ | |
758 | u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe; | |
759 | int ret; | |
760 | ||
761 | ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis); | |
762 | if (ret) | |
763 | return; | |
764 | ||
765 | mutex_lock(&lpss_iosf_mutex); | |
766 | ||
767 | ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0); | |
768 | if (ret) | |
769 | goto exit; | |
770 | ||
771 | /* | |
772 | * Get the status of entire LPSS power island per device basis. | |
773 | * Shutdown both LPSS DMA controllers if and only if all other devices | |
774 | * are already in D3hot. | |
775 | */ | |
776 | pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask; | |
777 | if (pmc_status) | |
778 | goto exit; | |
779 | ||
780 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
781 | LPSS_IOSF_PMCSR, value2, mask2); | |
782 | ||
783 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
784 | LPSS_IOSF_PMCSR, value2, mask2); | |
785 | ||
786 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, | |
787 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
771bd060 RW |
788 | |
789 | lpss_iosf_d3_entered = true; | |
790 | ||
eebb3e8d AS |
791 | exit: |
792 | mutex_unlock(&lpss_iosf_mutex); | |
793 | } | |
794 | ||
795 | static void lpss_iosf_exit_d3_state(void) | |
796 | { | |
d132d6d5 AS |
797 | u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3 | |
798 | LPSS_GPIODEF0_DMA_LLP; | |
799 | u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK | LPSS_GPIODEF0_DMA_LLP; | |
eebb3e8d AS |
800 | u32 value2 = LPSS_PMCSR_D0; |
801 | u32 mask2 = LPSS_PMCSR_Dx_MASK; | |
802 | ||
803 | mutex_lock(&lpss_iosf_mutex); | |
804 | ||
771bd060 RW |
805 | if (!lpss_iosf_d3_entered) |
806 | goto exit; | |
807 | ||
808 | lpss_iosf_d3_entered = false; | |
809 | ||
eebb3e8d AS |
810 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE, |
811 | LPSS_IOSF_GPIODEF0, value1, mask1); | |
812 | ||
813 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE, | |
814 | LPSS_IOSF_PMCSR, value2, mask2); | |
815 | ||
816 | iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE, | |
817 | LPSS_IOSF_PMCSR, value2, mask2); | |
818 | ||
771bd060 | 819 | exit: |
eebb3e8d AS |
820 | mutex_unlock(&lpss_iosf_mutex); |
821 | } | |
822 | ||
771bd060 | 823 | static int acpi_lpss_suspend(struct device *dev, bool wakeup) |
c78b0830 | 824 | { |
cb39dcdd AS |
825 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
826 | int ret; | |
c78b0830 | 827 | |
cb39dcdd AS |
828 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
829 | acpi_lpss_save_ctx(dev, pdata); | |
830 | ||
a192aa92 | 831 | ret = acpi_dev_suspend(dev, wakeup); |
eebb3e8d AS |
832 | |
833 | /* | |
834 | * This call must be last in the sequence, otherwise PMC will return | |
835 | * wrong status for devices being about to be powered off. See | |
836 | * lpss_iosf_enter_d3_state() for further information. | |
837 | */ | |
771bd060 | 838 | if (acpi_target_system_state() == ACPI_STATE_S0 && |
def76401 | 839 | lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
840 | lpss_iosf_enter_d3_state(); |
841 | ||
842 | return ret; | |
c78b0830 HK |
843 | } |
844 | ||
771bd060 | 845 | static int acpi_lpss_resume(struct device *dev) |
c78b0830 | 846 | { |
cb39dcdd AS |
847 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); |
848 | int ret; | |
c78b0830 | 849 | |
eebb3e8d AS |
850 | /* |
851 | * This call is kept first to be in symmetry with | |
852 | * acpi_lpss_runtime_suspend() one. | |
853 | */ | |
771bd060 | 854 | if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available()) |
eebb3e8d AS |
855 | lpss_iosf_exit_d3_state(); |
856 | ||
63705c40 | 857 | ret = acpi_dev_resume(dev); |
c78b0830 HK |
858 | if (ret) |
859 | return ret; | |
860 | ||
02b98540 AS |
861 | acpi_lpss_d3_to_d0_delay(pdata); |
862 | ||
cb39dcdd AS |
863 | if (pdata->dev_desc->flags & LPSS_SAVE_CTX) |
864 | acpi_lpss_restore_ctx(dev, pdata); | |
865 | ||
a192aa92 RW |
866 | return 0; |
867 | } | |
868 | ||
869 | #ifdef CONFIG_PM_SLEEP | |
870 | static int acpi_lpss_suspend_late(struct device *dev) | |
871 | { | |
05087360 RW |
872 | int ret; |
873 | ||
874 | if (dev_pm_smart_suspend_and_suspended(dev)) | |
875 | return 0; | |
a192aa92 | 876 | |
05087360 | 877 | ret = pm_generic_suspend_late(dev); |
771bd060 | 878 | return ret ? ret : acpi_lpss_suspend(dev, device_may_wakeup(dev)); |
a192aa92 RW |
879 | } |
880 | ||
881 | static int acpi_lpss_resume_early(struct device *dev) | |
882 | { | |
771bd060 | 883 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
884 | |
885 | return ret ? ret : pm_generic_resume_early(dev); | |
886 | } | |
887 | #endif /* CONFIG_PM_SLEEP */ | |
888 | ||
889 | static int acpi_lpss_runtime_suspend(struct device *dev) | |
890 | { | |
891 | int ret = pm_generic_runtime_suspend(dev); | |
892 | ||
893 | return ret ? ret : acpi_lpss_suspend(dev, true); | |
894 | } | |
895 | ||
896 | static int acpi_lpss_runtime_resume(struct device *dev) | |
897 | { | |
771bd060 | 898 | int ret = acpi_lpss_resume(dev); |
a192aa92 RW |
899 | |
900 | return ret ? ret : pm_generic_runtime_resume(dev); | |
c78b0830 | 901 | } |
c78b0830 HK |
902 | #endif /* CONFIG_PM */ |
903 | ||
904 | static struct dev_pm_domain acpi_lpss_pm_domain = { | |
c3a49cf3 AS |
905 | #ifdef CONFIG_PM |
906 | .activate = acpi_lpss_activate, | |
907 | .dismiss = acpi_lpss_dismiss, | |
908 | #endif | |
c78b0830 | 909 | .ops = { |
5de21bb9 | 910 | #ifdef CONFIG_PM |
c78b0830 | 911 | #ifdef CONFIG_PM_SLEEP |
c78b0830 | 912 | .prepare = acpi_subsys_prepare, |
e4da817d | 913 | .complete = acpi_subsys_complete, |
c78b0830 | 914 | .suspend = acpi_subsys_suspend, |
f4168b61 | 915 | .suspend_late = acpi_lpss_suspend_late, |
05087360 RW |
916 | .suspend_noirq = acpi_subsys_suspend_noirq, |
917 | .resume_noirq = acpi_subsys_resume_noirq, | |
f4168b61 | 918 | .resume_early = acpi_lpss_resume_early, |
c78b0830 | 919 | .freeze = acpi_subsys_freeze, |
05087360 RW |
920 | .freeze_late = acpi_subsys_freeze_late, |
921 | .freeze_noirq = acpi_subsys_freeze_noirq, | |
922 | .thaw_noirq = acpi_subsys_thaw_noirq, | |
c78b0830 | 923 | .poweroff = acpi_subsys_suspend, |
f4168b61 | 924 | .poweroff_late = acpi_lpss_suspend_late, |
05087360 RW |
925 | .poweroff_noirq = acpi_subsys_suspend_noirq, |
926 | .restore_noirq = acpi_subsys_resume_noirq, | |
f4168b61 | 927 | .restore_early = acpi_lpss_resume_early, |
c78b0830 | 928 | #endif |
c78b0830 HK |
929 | .runtime_suspend = acpi_lpss_runtime_suspend, |
930 | .runtime_resume = acpi_lpss_runtime_resume, | |
931 | #endif | |
932 | }, | |
933 | }; | |
934 | ||
2e0f8822 RW |
935 | static int acpi_lpss_platform_notify(struct notifier_block *nb, |
936 | unsigned long action, void *data) | |
937 | { | |
938 | struct platform_device *pdev = to_platform_device(data); | |
939 | struct lpss_private_data *pdata; | |
940 | struct acpi_device *adev; | |
941 | const struct acpi_device_id *id; | |
2e0f8822 RW |
942 | |
943 | id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev); | |
944 | if (!id || !id->driver_data) | |
945 | return 0; | |
946 | ||
947 | if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev)) | |
948 | return 0; | |
949 | ||
950 | pdata = acpi_driver_data(adev); | |
cb39dcdd | 951 | if (!pdata) |
2e0f8822 RW |
952 | return 0; |
953 | ||
cb39dcdd AS |
954 | if (pdata->mmio_base && |
955 | pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) { | |
2e0f8822 RW |
956 | dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n"); |
957 | return 0; | |
958 | } | |
959 | ||
c78b0830 | 960 | switch (action) { |
de16d552 | 961 | case BUS_NOTIFY_BIND_DRIVER: |
989561de | 962 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
b5f88dd1 | 963 | break; |
de16d552 | 964 | case BUS_NOTIFY_DRIVER_NOT_BOUND: |
b5f88dd1 | 965 | case BUS_NOTIFY_UNBOUND_DRIVER: |
5be6ada3 | 966 | dev_pm_domain_set(&pdev->dev, NULL); |
b5f88dd1 AS |
967 | break; |
968 | case BUS_NOTIFY_ADD_DEVICE: | |
989561de | 969 | dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain); |
ff8c1af5 | 970 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 HK |
971 | return sysfs_create_group(&pdev->dev.kobj, |
972 | &lpss_attr_group); | |
01ac170b | 973 | break; |
c78b0830 | 974 | case BUS_NOTIFY_DEL_DEVICE: |
ff8c1af5 | 975 | if (pdata->dev_desc->flags & LPSS_LTR) |
c78b0830 | 976 | sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group); |
989561de | 977 | dev_pm_domain_set(&pdev->dev, NULL); |
01ac170b | 978 | break; |
c78b0830 HK |
979 | default: |
980 | break; | |
981 | } | |
2e0f8822 | 982 | |
c78b0830 | 983 | return 0; |
2e0f8822 RW |
984 | } |
985 | ||
986 | static struct notifier_block acpi_lpss_nb = { | |
987 | .notifier_call = acpi_lpss_platform_notify, | |
988 | }; | |
989 | ||
1a8f8351 RW |
990 | static void acpi_lpss_bind(struct device *dev) |
991 | { | |
992 | struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev)); | |
993 | ||
ff8c1af5 | 994 | if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR)) |
1a8f8351 RW |
995 | return; |
996 | ||
997 | if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) | |
998 | dev->power.set_latency_tolerance = acpi_lpss_set_ltr; | |
999 | else | |
1000 | dev_err(dev, "MMIO size insufficient to access LTR\n"); | |
1001 | } | |
1002 | ||
1003 | static void acpi_lpss_unbind(struct device *dev) | |
1004 | { | |
1005 | dev->power.set_latency_tolerance = NULL; | |
1006 | } | |
1007 | ||
f58b082a RW |
1008 | static struct acpi_scan_handler lpss_handler = { |
1009 | .ids = acpi_lpss_device_ids, | |
1010 | .attach = acpi_lpss_create_device, | |
1a8f8351 RW |
1011 | .bind = acpi_lpss_bind, |
1012 | .unbind = acpi_lpss_unbind, | |
f58b082a RW |
1013 | }; |
1014 | ||
1015 | void __init acpi_lpss_init(void) | |
1016 | { | |
eebb3e8d AS |
1017 | const struct x86_cpu_id *id; |
1018 | int ret; | |
1019 | ||
1020 | ret = lpt_clk_init(); | |
1021 | if (ret) | |
1022 | return; | |
1023 | ||
1024 | id = x86_match_cpu(lpss_cpu_ids); | |
1025 | if (id) | |
1026 | lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON; | |
1027 | ||
1028 | bus_register_notifier(&platform_bus_type, &acpi_lpss_nb); | |
1029 | acpi_scan_add_handler(&lpss_handler); | |
f58b082a | 1030 | } |
d6ddaaac RW |
1031 | |
1032 | #else | |
1033 | ||
1034 | static struct acpi_scan_handler lpss_handler = { | |
1035 | .ids = acpi_lpss_device_ids, | |
1036 | }; | |
1037 | ||
1038 | void __init acpi_lpss_init(void) | |
1039 | { | |
1040 | acpi_scan_add_handler(&lpss_handler); | |
1041 | } | |
1042 | ||
1043 | #endif /* CONFIG_X86_INTEL_LPSS */ |