[mirror_ubuntu-bionic-kernel.git] / drivers / ata / pata_hpt366.c

/*
 * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
 *
 * This driver is heavily based upon:
 *
 * linux/drivers/ide/pci/hpt366.c		Version 0.36	April 25, 2003
 *
 * Copyright (C) 1999-2003		Andre Hedrick <andre@linux-ide.org>
 * Portions Copyright (C) 2001	        Sun Microsystems, Inc.
 * Portions Copyright (C) 2003		Red Hat Inc
 *
 *
 * TODO
 *	Look into engine reset on timeout errors. Should not be required.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt366"
#define DRV_VERSION	"0.6.11"

struct hpt_clock {
	u8	xfer_mode;
	u32	timing;
};

/* key for bus clock timings
 * bit
 * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 *        cycles = value + 1
 * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 *        register access.
 * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 *        register access.
 * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 *        register access.
 * 28     UDMA enable.
 * 29     DMA  enable.
 * 30     PIO_MST enable. If set, the chip is in bus master mode during
 *        PIO xfer.
 * 31     FIFO enable.
 */

static const struct hpt_clock hpt366_40[] = {
	{	XFER_UDMA_4,	0x900fd943	},
	{	XFER_UDMA_3,	0x900ad943	},
	{	XFER_UDMA_2,	0x900bd943	},
	{	XFER_UDMA_1,	0x9008d943	},
	{	XFER_UDMA_0,	0x9008d943	},

	{	XFER_MW_DMA_2,	0xa008d943	},
	{	XFER_MW_DMA_1,	0xa010d955	},
	{	XFER_MW_DMA_0,	0xa010d9fc	},

	{	XFER_PIO_4,	0xc008d963	},
	{	XFER_PIO_3,	0xc010d974	},
	{	XFER_PIO_2,	0xc010d997	},
	{	XFER_PIO_1,	0xc010d9c7	},
	{	XFER_PIO_0,	0xc018d9d9	},
	{	0,		0x0120d9d9	}
};

static const struct hpt_clock hpt366_33[] = {
	{	XFER_UDMA_4,	0x90c9a731	},
	{	XFER_UDMA_3,	0x90cfa731	},
	{	XFER_UDMA_2,	0x90caa731	},
	{	XFER_UDMA_1,	0x90cba731	},
	{	XFER_UDMA_0,	0x90c8a731	},

	{	XFER_MW_DMA_2,	0xa0c8a731	},
	{	XFER_MW_DMA_1,	0xa0c8a732	},	/* 0xa0c8a733 */
	{	XFER_MW_DMA_0,	0xa0c8a797	},

	{	XFER_PIO_4,	0xc0c8a731	},
	{	XFER_PIO_3,	0xc0c8a742	},
	{	XFER_PIO_2,	0xc0d0a753	},
	{	XFER_PIO_1,	0xc0d0a7a3	},	/* 0xc0d0a793 */
	{	XFER_PIO_0,	0xc0d0a7aa	},	/* 0xc0d0a7a7 */
	{	0,		0x0120a7a7	}
};

static const struct hpt_clock hpt366_25[] = {
	{	XFER_UDMA_4,	0x90c98521	},
	{	XFER_UDMA_3,	0x90cf8521	},
	{	XFER_UDMA_2,	0x90cf8521	},
	{	XFER_UDMA_1,	0x90cb8521	},
	{	XFER_UDMA_0,	0x90cb8521	},

	{	XFER_MW_DMA_2,	0xa0ca8521	},
	{	XFER_MW_DMA_1,	0xa0ca8532	},
	{	XFER_MW_DMA_0,	0xa0ca8575	},

	{	XFER_PIO_4,	0xc0ca8521	},
	{	XFER_PIO_3,	0xc0ca8532	},
	{	XFER_PIO_2,	0xc0ca8542	},
	{	XFER_PIO_1,	0xc0d08572	},
	{	XFER_PIO_0,	0xc0d08585	},
	{	0,		0x01208585	}
};

/**
 *	hpt36x_find_mode	-	find the hpt36x timing
 *	@ap: ATA port
 *	@speed: transfer mode
 *
 *	Return the 32bit register programming information for this channel
 *	that matches the speed provided.
 */

static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
{
	struct hpt_clock *clocks = ap->host->private_data;

	while (clocks->xfer_mode) {
		if (clocks->xfer_mode == speed)
			return clocks->timing;
		clocks++;
	}
	BUG();
	return 0xffffffffU;	/* silence compiler warning */
}

static const char * const bad_ata33[] = {
	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	"Maxtor 90845U3", "Maxtor 90650U2",
	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
	"Maxtor 90510D4",
	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
	NULL
};

static const char * const bad_ata66_4[] = {
	"IBM-DTLA-307075",
	"IBM-DTLA-307060",
	"IBM-DTLA-307045",
	"IBM-DTLA-307030",
	"IBM-DTLA-307020",
	"IBM-DTLA-307015",
	"IBM-DTLA-305040",
	"IBM-DTLA-305030",
	"IBM-DTLA-305020",
	"IC35L010AVER07-0",
	"IC35L020AVER07-0",
	"IC35L030AVER07-0",
	"IC35L040AVER07-0",
	"IC35L060AVER07-0",
	"WDC AC310200R",
	NULL
};

static const char * const bad_ata66_3[] = {
	"WDC AC310200R",
	NULL
};

static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
			       const char * const list[])
{
	unsigned char model_num[ATA_ID_PROD_LEN + 1];
	int i;

	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));

	i = match_string(list, -1, model_num);
	if (i >= 0) {
		pr_warn("%s is not supported for %s\n", modestr, list[i]);
		return 1;
	}
	return 0;
}

/**
 *	hpt366_filter	-	mode selection filter
 *	@adev: ATA device
 *
 *	Block UDMA on devices that cause trouble with this controller.
 */

static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
{
	if (adev->class == ATA_DEV_ATA) {
		if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
			mask &= ~ATA_MASK_UDMA;
		if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
			mask &= ~(0xF8 << ATA_SHIFT_UDMA);
		if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
			mask &= ~(0xF0 << ATA_SHIFT_UDMA);
	} else if (adev->class == ATA_DEV_ATAPI)
		mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);

	return mask;
}

static int hpt36x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u8 ata66;

	/*
	 * Each channel of pata_hpt366 occupies separate PCI function
	 * as the primary channel and bit1 indicates the cable type.
	 */
	pci_read_config_byte(pdev, 0x5A, &ata66);
	if (ata66 & 2)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
			    u8 mode)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 addr = 0x40 + 4 * adev->devno;
	u32 mask, reg, t;

	/* determine timing mask and find matching clock entry */
	if (mode < XFER_MW_DMA_0)
		mask = 0xc1f8ffff;
	else if (mode < XFER_UDMA_0)
		mask = 0x303800ff;
	else
		mask = 0x30070000;

	t = hpt36x_find_mode(ap, mode);

	/*
	 * Combine new mode bits with old config bits and disable
	 * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	 * problems handling I/O errors later.
	 */
	pci_read_config_dword(pdev, addr, &reg);
	reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
	pci_write_config_dword(pdev, addr, reg);
}

/**
 *	hpt366_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Perform PIO mode setup.
 */

static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->pio_mode);
}

/**
 *	hpt366_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 */

static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	hpt366_set_mode(ap, adev, adev->dma_mode);
}

static struct scsi_host_template hpt36x_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

/*
 *	Configuration for HPT366/68
 */

static struct ata_port_operations hpt366_port_ops = {
	.inherits	= &ata_bmdma_port_ops,
	.cable_detect	= hpt36x_cable_detect,
	.mode_filter	= hpt366_filter,
	.set_piomode	= hpt366_set_piomode,
	.set_dmamode	= hpt366_set_dmamode,
};

/**
 *	hpt36x_init_chipset	-	common chip setup
 *	@dev: PCI device
 *
 *	Perform the chip setup work that must be done at both init and
 *	resume time
 */

static void hpt36x_init_chipset(struct pci_dev *dev)
{
	u8 drive_fast;

	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);

	pci_read_config_byte(dev, 0x51, &drive_fast);
	if (drive_fast & 0x80)
		pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
}

/**
 *	hpt36x_init_one		-	Initialise an HPT366/368
 *	@dev: PCI device
 *	@id: Entry in match table
 *
 *	Initialise an HPT36x device. There are some interesting complications
 *	here. Firstly the chip may report 366 and be one of several variants.
 *	Secondly all the timings depend on the clock for the chip which we must
 *	detect and look up
 *
 *	This is the known chip mappings. It may be missing a couple of later
 *	releases.
 *
 *	Chip version		PCI		Rev	Notes
 *	HPT366			4 (HPT366)	0	UDMA66
 *	HPT366			4 (HPT366)	1	UDMA66
 *	HPT368			4 (HPT366)	2	UDMA66
 *	HPT37x/30x		4 (HPT366)	3+	Other driver
 *
 */

static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info_hpt366 = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA4,
		.port_ops = &hpt366_port_ops
	};
	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };

	const void *hpriv = NULL;
	u32 reg1;
	int rc;

	rc = pcim_enable_device(dev);
	if (rc)
		return rc;

	/* May be a later chip in disguise. Check */
	/* Newer chips are not in the HPT36x driver. Ignore them */
	if (dev->revision > 2)
		return -ENODEV;

	hpt36x_init_chipset(dev);

	pci_read_config_dword(dev, 0x40,  &reg1);

	/* PCI clocking determines the ATA timing values to use */
	/* info_hpt366 is safe against re-entry so we can scribble on it */
	switch ((reg1 & 0xf00) >> 8) {
	case 9:
		hpriv = &hpt366_40;
		break;
	case 5:
		hpriv = &hpt366_25;
		break;
	default:
		hpriv = &hpt366_33;
		break;
	}
	/* Now kick off ATA set up */
	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
}

#ifdef CONFIG_PM_SLEEP
static int hpt36x_reinit_one(struct pci_dev *dev)
{
	struct ata_host *host = pci_get_drvdata(dev);
	int rc;

	rc = ata_pci_device_do_resume(dev);
	if (rc)
		return rc;
	hpt36x_init_chipset(dev);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id hpt36x[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
	{ },
};

static struct pci_driver hpt36x_pci_driver = {
	.name		= DRV_NAME,
	.id_table	= hpt36x,
	.probe		= hpt36x_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt36x_reinit_one,
#endif
};

module_pci_driver(hpt36x_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt36x);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
	3	*
	4	* This driver is heavily based upon:
	5	*
	6	* linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
	7	*
	8	* Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
	9	* Portions Copyright (C) 2001 Sun Microsystems, Inc.
	10	* Portions Copyright (C) 2003 Red Hat Inc
	11	*
	12	*
	13	* TODO
d817898c	14	* Look into engine reset on timeout errors. Should not be required.
669a5db4 JG	15	*/
669a5db4 JG	16
8d7b1c70	17	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
669a5db4 JG	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/pci.h>
669a5db4 JG	22	#include <linux/blkdev.h>
	23	#include <linux/delay.h>
	24	#include <scsi/scsi_host.h>
	25	#include <linux/libata.h>
	26
	27	#define DRV_NAME "pata_hpt366"
8d7b1c70	28	#define DRV_VERSION "0.6.11"
669a5db4 JG	29
669a5db4 JG	30	struct hpt_clock {
6ecb6f25	31	u8 xfer_mode;
669a5db4 JG	32	u32 timing;
	33	};
	34
	35	/* key for bus clock timings
	36	* bit
82beb5d8 SS	37	* 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
	38	* cycles = value + 1
	39	* 4:7 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
	40	* cycles = value + 1
	41	* 8:11 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
669a5db4	42	* register access.
82beb5d8	43	* 12:15 cmd_low_time. Active time of DIOW_/DIOR_ during task file
669a5db4	44	* register access.
82beb5d8 SS	45	* 16:18 udma_cycle_time. Clock cycles for UDMA xfer?
	46	* 19:21 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
	47	* 22:24 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
669a5db4	48	* register access.
82beb5d8 SS	49	* 28 UDMA enable.
	50	* 29 DMA enable.
	51	* 30 PIO_MST enable. If set, the chip is in bus master mode during
	52	* PIO xfer.
669a5db4 JG	53	* 31 FIFO enable.
	54	*/
	55
	56	static const struct hpt_clock hpt366_40[] = {
	57	{ XFER_UDMA_4, 0x900fd943 },
	58	{ XFER_UDMA_3, 0x900ad943 },
	59	{ XFER_UDMA_2, 0x900bd943 },
	60	{ XFER_UDMA_1, 0x9008d943 },
	61	{ XFER_UDMA_0, 0x9008d943 },
	62
	63	{ XFER_MW_DMA_2, 0xa008d943 },
	64	{ XFER_MW_DMA_1, 0xa010d955 },
	65	{ XFER_MW_DMA_0, 0xa010d9fc },
	66
	67	{ XFER_PIO_4, 0xc008d963 },
	68	{ XFER_PIO_3, 0xc010d974 },
	69	{ XFER_PIO_2, 0xc010d997 },
	70	{ XFER_PIO_1, 0xc010d9c7 },
	71	{ XFER_PIO_0, 0xc018d9d9 },
	72	{ 0, 0x0120d9d9 }
	73	};
	74
	75	static const struct hpt_clock hpt366_33[] = {
	76	{ XFER_UDMA_4, 0x90c9a731 },
	77	{ XFER_UDMA_3, 0x90cfa731 },
	78	{ XFER_UDMA_2, 0x90caa731 },
	79	{ XFER_UDMA_1, 0x90cba731 },
	80	{ XFER_UDMA_0, 0x90c8a731 },
	81
	82	{ XFER_MW_DMA_2, 0xa0c8a731 },
	83	{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
	84	{ XFER_MW_DMA_0, 0xa0c8a797 },
	85
	86	{ XFER_PIO_4, 0xc0c8a731 },
	87	{ XFER_PIO_3, 0xc0c8a742 },
	88	{ XFER_PIO_2, 0xc0d0a753 },
	89	{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
	90	{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
	91	{ 0, 0x0120a7a7 }
	92	};
	93
	94	static const struct hpt_clock hpt366_25[] = {
	95	{ XFER_UDMA_4, 0x90c98521 },
	96	{ XFER_UDMA_3, 0x90cf8521 },
	97	{ XFER_UDMA_2, 0x90cf8521 },
	98	{ XFER_UDMA_1, 0x90cb8521 },
	99	{ XFER_UDMA_0, 0x90cb8521 },
	100
	101	{ XFER_MW_DMA_2, 0xa0ca8521 },
	102	{ XFER_MW_DMA_1, 0xa0ca8532 },
	103	{ XFER_MW_DMA_0, 0xa0ca8575 },
	104
	105	{ XFER_PIO_4, 0xc0ca8521 },
	106	{ XFER_PIO_3, 0xc0ca8532 },
	107	{ XFER_PIO_2, 0xc0ca8542 },
	108	{ XFER_PIO_1, 0xc0d08572 },
	109	{ XFER_PIO_0, 0xc0d08585 },
	110	{ 0, 0x01208585 }
	111	};
	112
dc5e44ec BZ	113	/**
	114	* hpt36x_find_mode - find the hpt36x timing
	115	* @ap: ATA port
	116	* @speed: transfer mode
	117	*
	118	* Return the 32bit register programming information for this channel
	119	* that matches the speed provided.
	120	*/
	121
	122	static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
	123	{
	124	struct hpt_clock *clocks = ap->host->private_data;
	125
	126	while (clocks->xfer_mode) {
	127	if (clocks->xfer_mode == speed)
	128	return clocks->timing;
	129	clocks++;
	130	}
	131	BUG();
	132	return 0xffffffffU; /* silence compiler warning */
	133	}
	134
28cd4b6b SS	135	static const char * const bad_ata33[] = {
	136	"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
	137	"Maxtor 90845U3", "Maxtor 90650U2",
	138	"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
	139	"Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
	140	"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
	141	"Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
669a5db4 JG	142	"Maxtor 90510D4",
669a5db4 JG	143	"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
28cd4b6b SS	144	"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
	145	"Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
	146	"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
	147	"Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
669a5db4 JG	148	NULL
	149	};
	150
28cd4b6b	151	static const char * const bad_ata66_4[] = {
669a5db4 JG	152	"IBM-DTLA-307075",
	153	"IBM-DTLA-307060",
	154	"IBM-DTLA-307045",
	155	"IBM-DTLA-307030",
	156	"IBM-DTLA-307020",
	157	"IBM-DTLA-307015",
	158	"IBM-DTLA-305040",
	159	"IBM-DTLA-305030",
	160	"IBM-DTLA-305020",
	161	"IC35L010AVER07-0",
	162	"IC35L020AVER07-0",
	163	"IC35L030AVER07-0",
	164	"IC35L040AVER07-0",
	165	"IC35L060AVER07-0",
	166	"WDC AC310200R",
	167	NULL
	168	};
	169
28cd4b6b	170	static const char * const bad_ata66_3[] = {
669a5db4 JG	171	"WDC AC310200R",
	172	NULL
	173	};
	174
28cd4b6b SS	175	static int hpt_dma_blacklisted(const struct ata_device dev, char modestr,
28cd4b6b SS	176	const char * const list[])
669a5db4	177	{
8bfa79fc	178	unsigned char model_num[ATA_ID_PROD_LEN + 1];
908913bd	179	int i;
669a5db4	180
8bfa79fc	181	ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
669a5db4	182
908913bd AS	183	i = match_string(list, -1, model_num);
	184	if (i >= 0) {
	185	pr_warn("%s is not supported for %s\n", modestr, list[i]);
	186	return 1;
669a5db4 JG	187	}
	188	return 0;
	189	}
	190
	191	/**
	192	* hpt366_filter - mode selection filter
669a5db4 JG	193	* @adev: ATA device
	194	*
	195	* Block UDMA on devices that cause trouble with this controller.
	196	*/
85cd7251	197
a76b62ca	198	static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
669a5db4 JG	199	{
	200	if (adev->class == ATA_DEV_ATA) {
	201	if (hpt_dma_blacklisted(adev, "UDMA", bad_ata33))
	202	mask &= ~ATA_MASK_UDMA;
	203	if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
6ddd6861	204	mask &= ~(0xF8 << ATA_SHIFT_UDMA);
669a5db4	205	if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
6ddd6861	206	mask &= ~(0xF0 << ATA_SHIFT_UDMA);
3ee89f17 TH	207	} else if (adev->class == ATA_DEV_ATAPI)
	208	mask &= ~(ATA_MASK_MWDMA \| ATA_MASK_UDMA);
	209
c7087652	210	return mask;
669a5db4 JG	211	}
669a5db4 JG	212
fecfda5d AC	213	static int hpt36x_cable_detect(struct ata_port *ap)
fecfda5d AC	214	{
fecfda5d	215	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
bab5b32a	216	u8 ata66;
fecfda5d	217
bab5b32a TH	218	/*
	219	* Each channel of pata_hpt366 occupies separate PCI function
	220	* as the primary channel and bit1 indicates the cable type.
	221	*/
fecfda5d	222	pci_read_config_byte(pdev, 0x5A, &ata66);
bab5b32a	223	if (ata66 & 2)
fecfda5d AC	224	return ATA_CBL_PATA40;
	225	return ATA_CBL_PATA80;
	226	}
	227
6ecb6f25 TH	228	static void hpt366_set_mode(struct ata_port ap, struct ata_device adev,
6ecb6f25 TH	229	u8 mode)
669a5db4 JG	230	{
669a5db4 JG	231	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
859faa87	232	u32 addr = 0x40 + 4 * adev->devno;
dc5e44ec	233	u32 mask, reg, t;
85cd7251	234
6ecb6f25 TH	235	/* determine timing mask and find matching clock entry */
	236	if (mode < XFER_MW_DMA_0)
	237	mask = 0xc1f8ffff;
	238	else if (mode < XFER_UDMA_0)
	239	mask = 0x303800ff;
	240	else
	241	mask = 0x30070000;
	242
dc5e44ec	243	t = hpt36x_find_mode(ap, mode);
6ecb6f25 TH	244
	245	/*
	246	* Combine new mode bits with old config bits and disable
	247	* on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
	248	* problems handling I/O errors later.
	249	*/
859faa87	250	pci_read_config_dword(pdev, addr, &reg);
dc5e44ec	251	reg = ((reg & ~mask) \| (t & mask)) & ~0xc0000000;
859faa87	252	pci_write_config_dword(pdev, addr, reg);
6ecb6f25 TH	253	}
	254
	255	/**
	256	* hpt366_set_piomode - PIO setup
	257	* @ap: ATA interface
	258	* @adev: device on the interface
	259	*
	260	* Perform PIO mode setup.
	261	*/
	262
	263	static void hpt366_set_piomode(struct ata_port ap, struct ata_device adev)
	264	{
	265	hpt366_set_mode(ap, adev, adev->pio_mode);
669a5db4 JG	266	}
	267
	268	/**
	269	* hpt366_set_dmamode - DMA timing setup
	270	* @ap: ATA interface
	271	* @adev: Device being configured
	272	*
	273	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	274	* PIO, load the mode number and then set MWDMA or UDMA flag.
	275	*/
85cd7251	276
669a5db4 JG	277	static void hpt366_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	278	{
6ecb6f25	279	hpt366_set_mode(ap, adev, adev->dma_mode);
669a5db4 JG	280	}
	281
	282	static struct scsi_host_template hpt36x_sht = {
68d1d07b	283	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	284	};
	285
	286	/*
	287	* Configuration for HPT366/68
	288	*/
85cd7251	289
669a5db4	290	static struct ata_port_operations hpt366_port_ops = {
029cfd6b TH	291	.inherits = &ata_bmdma_port_ops,
	292	.cable_detect = hpt36x_cable_detect,
	293	.mode_filter = hpt366_filter,
669a5db4 JG	294	.set_piomode = hpt366_set_piomode,
669a5db4 JG	295	.set_dmamode = hpt366_set_dmamode,
85cd7251	296	};
669a5db4	297
aa54ab1e AC	298	/**
	299	* hpt36x_init_chipset - common chip setup
	300	* @dev: PCI device
	301	*
	302	* Perform the chip setup work that must be done at both init and
	303	* resume time
	304	*/
	305
	306	static void hpt36x_init_chipset(struct pci_dev *dev)
	307	{
	308	u8 drive_fast;
28cd4b6b	309
aa54ab1e AC	310	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
	311	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
	312	pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
	313	pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
	314
	315	pci_read_config_byte(dev, 0x51, &drive_fast);
	316	if (drive_fast & 0x80)
	317	pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
	318	}
	319
669a5db4 JG	320	/**
	321	* hpt36x_init_one - Initialise an HPT366/368
	322	* @dev: PCI device
	323	* @id: Entry in match table
	324	*
	325	* Initialise an HPT36x device. There are some interesting complications
	326	* here. Firstly the chip may report 366 and be one of several variants.
	327	* Secondly all the timings depend on the clock for the chip which we must
	328	* detect and look up
	329	*
	330	* This is the known chip mappings. It may be missing a couple of later
	331	* releases.
	332	*
	333	* Chip version PCI Rev Notes
	334	* HPT366 4 (HPT366) 0 UDMA66
	335	* HPT366 4 (HPT366) 1 UDMA66
	336	* HPT368 4 (HPT366) 2 UDMA66
	337	* HPT37x/30x 4 (HPT366) 3+ Other driver
	338	*
	339	*/
85cd7251	340
669a5db4 JG	341	static int hpt36x_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4 JG	342	{
1626aeb8	343	static const struct ata_port_info info_hpt366 = {
1d2808fd	344	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	345	.pio_mask = ATA_PIO4,
14bdef98 EIB	346	.mwdma_mask = ATA_MWDMA2,
bf6263a8	347	.udma_mask = ATA_UDMA4,
669a5db4 JG	348	.port_ops = &hpt366_port_ops
669a5db4 JG	349	};
887125e3	350	const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
669a5db4	351
6ec0a86c	352	const void *hpriv = NULL;
669a5db4	353	u32 reg1;
f08048e9 TH	354	int rc;
	355
	356	rc = pcim_enable_device(dev);
	357	if (rc)
	358	return rc;
669a5db4	359
669a5db4 JG	360	/* May be a later chip in disguise. Check */
669a5db4 JG	361	/* Newer chips are not in the HPT36x driver. Ignore them */
89d3b360 SS	362	if (dev->revision > 2)
89d3b360 SS	363	return -ENODEV;
669a5db4	364
aa54ab1e	365	hpt36x_init_chipset(dev);
669a5db4 JG	366
669a5db4 JG	367	pci_read_config_dword(dev, 0x40, &reg1);
85cd7251	368
669a5db4 JG	369	/* PCI clocking determines the ATA timing values to use */
669a5db4 JG	370	/* info_hpt366 is safe against re-entry so we can scribble on it */
a548cc00	371	switch ((reg1 & 0xf00) >> 8) {
28cd4b6b SS	372	case 9:
	373	hpriv = &hpt366_40;
	374	break;
	375	case 5:
	376	hpriv = &hpt366_25;
	377	break;
	378	default:
	379	hpriv = &hpt366_33;
	380	break;
669a5db4 JG	381	}
669a5db4 JG	382	/* Now kick off ATA set up */
6ec0a86c	383	return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, (void *)hpriv, 0);
669a5db4 JG	384	}
669a5db4 JG	385
58eb8cd5	386	#ifdef CONFIG_PM_SLEEP
aa54ab1e AC	387	static int hpt36x_reinit_one(struct pci_dev *dev)
aa54ab1e AC	388	{
0a86e1c8	389	struct ata_host *host = pci_get_drvdata(dev);
f08048e9 TH	390	int rc;
	391
	392	rc = ata_pci_device_do_resume(dev);
	393	if (rc)
	394	return rc;
aa54ab1e	395	hpt36x_init_chipset(dev);
f08048e9 TH	396	ata_host_resume(host);
f08048e9 TH	397	return 0;
aa54ab1e	398	}
438ac6d5	399	#endif
aa54ab1e	400
2d2744fc JG	401	static const struct pci_device_id hpt36x[] = {
2d2744fc JG	402	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
2d2744fc	403	{ },
669a5db4 JG	404	};
	405
	406	static struct pci_driver hpt36x_pci_driver = {
28cd4b6b	407	.name = DRV_NAME,
669a5db4	408	.id_table = hpt36x,
28cd4b6b	409	.probe = hpt36x_init_one,
aa54ab1e	410	.remove = ata_pci_remove_one,
58eb8cd5	411	#ifdef CONFIG_PM_SLEEP
aa54ab1e AC	412	.suspend = ata_pci_device_suspend,
aa54ab1e AC	413	.resume = hpt36x_reinit_one,
438ac6d5	414	#endif
669a5db4 JG	415	};
669a5db4 JG	416
2fc75da0	417	module_pci_driver(hpt36x_pci_driver);
669a5db4	418
669a5db4 JG	419	MODULE_AUTHOR("Alan Cox");
	420	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
	421	MODULE_LICENSE("GPL");
	422	MODULE_DEVICE_TABLE(pci, hpt36x);
	423	MODULE_VERSION(DRV_VERSION);