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bec9e8ac
BVA		 1/*
2 * Driver for sTec s1120 PCIe SSDs. sTec was acquired in 2013 by HGST and HGST
3 * was acquired by Western Digital in 2012.
e67f86b3 4 *
bec9e8ac
BVA		 5 * Copyright 2012 sTec, Inc.
6 * Copyright (c) 2017 Western Digital Corporation or its affiliates.
7 *
8 * This file is part of the Linux kernel, and is made available under
9 * the terms of the GNU General Public License version 2.
e67f86b3
AB		 10 */
11
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/pci.h>
16#include <linux/slab.h>
17#include <linux/spinlock.h>
18#include <linux/blkdev.h>
f18c17c8 19#include <linux/blk-mq.h>
e67f86b3
AB		 20#include <linux/sched.h>
21#include <linux/interrupt.h>
22#include <linux/compiler.h>
23#include <linux/workqueue.h>
e67f86b3
AB		 24#include <linux/delay.h>
25#include <linux/time.h>
26#include <linux/hdreg.h>
27#include <linux/dma-mapping.h>
28#include <linux/completion.h>
29#include <linux/scatterlist.h>
30#include <linux/version.h>
31#include <linux/err.h>
e67f86b3 32#include <linux/aer.h>
e67f86b3 33#include <linux/wait.h>
2da7b403 34#include <linux/stringify.h>
a3db102d 35#include <linux/slab_def.h>
e67f86b3 36#include <scsi/scsi.h>
e67f86b3
AB		 37#include <scsi/sg.h>
38#include <linux/io.h>
39#include <linux/uaccess.h>
4ca90b53 40#include <asm/unaligned.h>
e67f86b3
AB		 41
42#include "skd_s1120.h"
43
44static int skd_dbg_level;
45static int skd_isr_comp_limit = 4;
46
e67f86b3
AB		 47#define SKD_ASSERT(expr) \
48 do { \
49 if (unlikely(!(expr))) { \
50 pr_err("Assertion failed! %s,%s,%s,line=%d\n", \
51 # expr, __FILE__, __func__, __LINE__); \
52 } \
53 } while (0)
54
e67f86b3 55#define DRV_NAME "skd"
e67f86b3 56#define PFX DRV_NAME ": "
e67f86b3 57
bec9e8ac 58MODULE_LICENSE("GPL");
e67f86b3 59
bb9f7dd3 60MODULE_DESCRIPTION("STEC s1120 PCIe SSD block driver");
e67f86b3
AB		 61
62#define PCI_VENDOR_ID_STEC 0x1B39
63#define PCI_DEVICE_ID_S1120 0x0001
64
65#define SKD_FUA_NV (1 << 1)
66#define SKD_MINORS_PER_DEVICE 16
67
68#define SKD_MAX_QUEUE_DEPTH 200u
69
70#define SKD_PAUSE_TIMEOUT (5 * 1000)
71
72#define SKD_N_FITMSG_BYTES (512u)
2da7b403 73#define SKD_MAX_REQ_PER_MSG 14
e67f86b3 74
e67f86b3
AB		 75#define SKD_N_SPECIAL_FITMSG_BYTES (128u)
76
77/* SG elements are 32 bytes, so we can make this 4096 and still be under the
78 * 128KB limit. That allows 4096*4K = 16M xfer size
79 */
80#define SKD_N_SG_PER_REQ_DEFAULT 256u
e67f86b3
AB		 81
82#define SKD_N_COMPLETION_ENTRY 256u
83#define SKD_N_READ_CAP_BYTES (8u)
84
85#define SKD_N_INTERNAL_BYTES (512u)
86
6f7c7675
BVA		 87#define SKD_SKCOMP_SIZE \
88 ((sizeof(struct fit_completion_entry_v1) + \
89 sizeof(struct fit_comp_error_info)) * SKD_N_COMPLETION_ENTRY)
90
e67f86b3 91/* 5 bits of uniqifier, 0xF800 */
e67f86b3
AB		 92#define SKD_ID_TABLE_MASK (3u << 8u)
93#define SKD_ID_RW_REQUEST (0u << 8u)
94#define SKD_ID_INTERNAL (1u << 8u)
e67f86b3
AB		 95#define SKD_ID_FIT_MSG (3u << 8u)
96#define SKD_ID_SLOT_MASK 0x00FFu
97#define SKD_ID_SLOT_AND_TABLE_MASK 0x03FFu
98
e67f86b3
AB		 99#define SKD_N_MAX_SECTORS 2048u
100
101#define SKD_MAX_RETRIES 2u
102
103#define SKD_TIMER_SECONDS(seconds) (seconds)
104#define SKD_TIMER_MINUTES(minutes) ((minutes) * (60))
105
106#define INQ_STD_NBYTES 36
e67f86b3
AB		 107
108enum skd_drvr_state {
109 SKD_DRVR_STATE_LOAD,
110 SKD_DRVR_STATE_IDLE,
111 SKD_DRVR_STATE_BUSY,
112 SKD_DRVR_STATE_STARTING,
113 SKD_DRVR_STATE_ONLINE,
114 SKD_DRVR_STATE_PAUSING,
115 SKD_DRVR_STATE_PAUSED,
e67f86b3
AB		 116 SKD_DRVR_STATE_RESTARTING,
117 SKD_DRVR_STATE_RESUMING,
118 SKD_DRVR_STATE_STOPPING,
119 SKD_DRVR_STATE_FAULT,
120 SKD_DRVR_STATE_DISAPPEARED,
121 SKD_DRVR_STATE_PROTOCOL_MISMATCH,
122 SKD_DRVR_STATE_BUSY_ERASE,
123 SKD_DRVR_STATE_BUSY_SANITIZE,
124 SKD_DRVR_STATE_BUSY_IMMINENT,
125 SKD_DRVR_STATE_WAIT_BOOT,
126 SKD_DRVR_STATE_SYNCING,
127};
128
129#define SKD_WAIT_BOOT_TIMO SKD_TIMER_SECONDS(90u)
130#define SKD_STARTING_TIMO SKD_TIMER_SECONDS(8u)
131#define SKD_RESTARTING_TIMO SKD_TIMER_MINUTES(4u)
e67f86b3
AB		 132#define SKD_BUSY_TIMO SKD_TIMER_MINUTES(20u)
133#define SKD_STARTED_BUSY_TIMO SKD_TIMER_SECONDS(60u)
134#define SKD_START_WAIT_SECONDS 90u
135
136enum skd_req_state {
137 SKD_REQ_STATE_IDLE,
138 SKD_REQ_STATE_SETUP,
139 SKD_REQ_STATE_BUSY,
140 SKD_REQ_STATE_COMPLETED,
141 SKD_REQ_STATE_TIMEOUT,
e67f86b3
AB		 142};
143
e67f86b3
AB		 144enum skd_check_status_action {
145 SKD_CHECK_STATUS_REPORT_GOOD,
146 SKD_CHECK_STATUS_REPORT_SMART_ALERT,
147 SKD_CHECK_STATUS_REQUEUE_REQUEST,
148 SKD_CHECK_STATUS_REPORT_ERROR,
149 SKD_CHECK_STATUS_BUSY_IMMINENT,
150};
151
d891fe60
BVA		 152struct skd_msg_buf {
153 struct fit_msg_hdr fmh;
154 struct skd_scsi_request scsi[SKD_MAX_REQ_PER_MSG];
155};
156
e67f86b3 157struct skd_fitmsg_context {
e67f86b3 158 u32 id;
e67f86b3
AB		 159
160 u32 length;
e67f86b3 161
d891fe60 162 struct skd_msg_buf *msg_buf;
e67f86b3
AB		 163 dma_addr_t mb_dma_address;
164};
165
166struct skd_request_context {
167 enum skd_req_state state;
168
e67f86b3
AB		 169 u16 id;
170 u32 fitmsg_id;
171
e67f86b3 172 u8 flush_cmd;
e67f86b3 173
b1824eef 174 enum dma_data_direction data_dir;
e67f86b3
AB		 175 struct scatterlist *sg;
176 u32 n_sg;
177 u32 sg_byte_count;
178
179 struct fit_sg_descriptor *sksg_list;
180 dma_addr_t sksg_dma_address;
181
182 struct fit_completion_entry_v1 completion;
183
184 struct fit_comp_error_info err_info;
185
f2fe4459 186 blk_status_t status;
e67f86b3 187};
e67f86b3
AB		 188
189struct skd_special_context {
190 struct skd_request_context req;
191
e67f86b3
AB		 192 void *data_buf;
193 dma_addr_t db_dma_address;
194
d891fe60 195 struct skd_msg_buf *msg_buf;
e67f86b3
AB		 196 dma_addr_t mb_dma_address;
197};
198
e67f86b3
AB		 199typedef enum skd_irq_type {
200 SKD_IRQ_LEGACY,
201 SKD_IRQ_MSI,
202 SKD_IRQ_MSIX
203} skd_irq_type_t;
204
205#define SKD_MAX_BARS 2
206
207struct skd_device {
85e34112 208 void __iomem *mem_map[SKD_MAX_BARS];
e67f86b3
AB		 209 resource_size_t mem_phys[SKD_MAX_BARS];
210 u32 mem_size[SKD_MAX_BARS];
211
e67f86b3
AB		 212 struct skd_msix_entry *msix_entries;
213
214 struct pci_dev *pdev;
215 int pcie_error_reporting_is_enabled;
216
217 spinlock_t lock;
218 struct gendisk *disk;
ca33dd92 219 struct blk_mq_tag_set tag_set;
e67f86b3 220 struct request_queue *queue;
91f85da4 221 struct skd_fitmsg_context *skmsg;
e67f86b3
AB		 222 struct device *class_dev;
223 int gendisk_on;
224 int sync_done;
225
e67f86b3
AB		 226 u32 devno;
227 u32 major;
e67f86b3
AB		 228 char isr_name[30];
229
230 enum skd_drvr_state state;
231 u32 drive_state;
232
e67f86b3
AB		 233 u32 cur_max_queue_depth;
234 u32 queue_low_water_mark;
235 u32 dev_max_queue_depth;
236
237 u32 num_fitmsg_context;
238 u32 num_req_context;
239
e67f86b3
AB		 240 struct skd_fitmsg_context *skmsg_table;
241
e67f86b3
AB		 242 struct skd_special_context internal_skspcl;
243 u32 read_cap_blocksize;
244 u32 read_cap_last_lba;
245 int read_cap_is_valid;
246 int inquiry_is_valid;
247 u8 inq_serial_num[13]; /*12 chars plus null term */
e67f86b3
AB		 248
249 u8 skcomp_cycle;
250 u32 skcomp_ix;
a3db102d
BVA		 251 struct kmem_cache *msgbuf_cache;
252 struct kmem_cache *sglist_cache;
253 struct kmem_cache *databuf_cache;
e67f86b3
AB		 254 struct fit_completion_entry_v1 *skcomp_table;
255 struct fit_comp_error_info *skerr_table;
256 dma_addr_t cq_dma_address;
257
258 wait_queue_head_t waitq;
259
260 struct timer_list timer;
261 u32 timer_countdown;
262 u32 timer_substate;
263
e67f86b3
AB		 264 int sgs_per_request;
265 u32 last_mtd;
266
267 u32 proto_ver;
268
269 int dbg_level;
270 u32 connect_time_stamp;
271 int connect_retries;
272#define SKD_MAX_CONNECT_RETRIES 16
273 u32 drive_jiffies;
274
275 u32 timo_slot;
276
ca33dd92 277 struct work_struct start_queue;
38d4a1bb 278 struct work_struct completion_worker;
e67f86b3
AB		 279};
280
281#define SKD_WRITEL(DEV, VAL, OFF) skd_reg_write32(DEV, VAL, OFF)
282#define SKD_READL(DEV, OFF) skd_reg_read32(DEV, OFF)
283#define SKD_WRITEQ(DEV, VAL, OFF) skd_reg_write64(DEV, VAL, OFF)
284
285static inline u32 skd_reg_read32(struct skd_device *skdev, u32 offset)
286{
14262a4b 287 u32 val = readl(skdev->mem_map[1] + offset);
e67f86b3 288
14262a4b 289 if (unlikely(skdev->dbg_level >= 2))
f98806d6 290 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
14262a4b 291 return val;
e67f86b3
AB		 292}
293
294static inline void skd_reg_write32(struct skd_device *skdev, u32 val,
295 u32 offset)
296{
14262a4b
BVA		 297 writel(val, skdev->mem_map[1] + offset);
298 if (unlikely(skdev->dbg_level >= 2))
f98806d6 299 dev_dbg(&skdev->pdev->dev, "offset %x = %x\n", offset, val);
e67f86b3
AB		 300}
301
302static inline void skd_reg_write64(struct skd_device *skdev, u64 val,
303 u32 offset)
304{
14262a4b
BVA		 305 writeq(val, skdev->mem_map[1] + offset);
306 if (unlikely(skdev->dbg_level >= 2))
f98806d6
BVA		 307 dev_dbg(&skdev->pdev->dev, "offset %x = %016llx\n", offset,
308 val);
e67f86b3
AB		 309}
310
311
744353b6 312#define SKD_IRQ_DEFAULT SKD_IRQ_MSIX
e67f86b3
AB		 313static int skd_isr_type = SKD_IRQ_DEFAULT;
314
315module_param(skd_isr_type, int, 0444);
316MODULE_PARM_DESC(skd_isr_type, "Interrupt type capability."
317 " (0==legacy, 1==MSI, 2==MSI-X, default==1)");
318
319#define SKD_MAX_REQ_PER_MSG_DEFAULT 1
320static int skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT;
321
322module_param(skd_max_req_per_msg, int, 0444);
323MODULE_PARM_DESC(skd_max_req_per_msg,
324 "Maximum SCSI requests packed in a single message."
2da7b403 325 " (1-" __stringify(SKD_MAX_REQ_PER_MSG) ", default==1)");
e67f86b3
AB		 326
327#define SKD_MAX_QUEUE_DEPTH_DEFAULT 64
328#define SKD_MAX_QUEUE_DEPTH_DEFAULT_STR "64"
329static int skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT;
330
331module_param(skd_max_queue_depth, int, 0444);
332MODULE_PARM_DESC(skd_max_queue_depth,
333 "Maximum SCSI requests issued to s1120."
334 " (1-200, default==" SKD_MAX_QUEUE_DEPTH_DEFAULT_STR ")");
335
336static int skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT;
337module_param(skd_sgs_per_request, int, 0444);
338MODULE_PARM_DESC(skd_sgs_per_request,
339 "Maximum SG elements per block request."
340 " (1-4096, default==256)");
341
63214121 342static int skd_max_pass_thru = 1;
e67f86b3
AB		 343module_param(skd_max_pass_thru, int, 0444);
344MODULE_PARM_DESC(skd_max_pass_thru,
63214121 345 "Maximum SCSI pass-thru at a time. IGNORED");
e67f86b3
AB		 346
347module_param(skd_dbg_level, int, 0444);
348MODULE_PARM_DESC(skd_dbg_level, "s1120 debug level (0,1,2)");
349
350module_param(skd_isr_comp_limit, int, 0444);
351MODULE_PARM_DESC(skd_isr_comp_limit, "s1120 isr comp limit (0=none) default=4");
352
e67f86b3
AB		 353/* Major device number dynamically assigned. */
354static u32 skd_major;
355
e67f86b3
AB		 356static void skd_destruct(struct skd_device *skdev);
357static const struct block_device_operations skd_blockdev_ops;
358static void skd_send_fitmsg(struct skd_device *skdev,
359 struct skd_fitmsg_context *skmsg);
360static void skd_send_special_fitmsg(struct skd_device *skdev,
361 struct skd_special_context *skspcl);
2a842aca 362static bool skd_preop_sg_list(struct skd_device *skdev,
e67f86b3
AB		 363 struct skd_request_context *skreq);
364static void skd_postop_sg_list(struct skd_device *skdev,
365 struct skd_request_context *skreq);
366
367static void skd_restart_device(struct skd_device *skdev);
368static int skd_quiesce_dev(struct skd_device *skdev);
369static int skd_unquiesce_dev(struct skd_device *skdev);
e67f86b3
AB		 370static void skd_disable_interrupts(struct skd_device *skdev);
371static void skd_isr_fwstate(struct skd_device *skdev);
79ce12a8 372static void skd_recover_requests(struct skd_device *skdev);
e67f86b3
AB		 373static void skd_soft_reset(struct skd_device *skdev);
374
e67f86b3
AB		 375const char *skd_drive_state_to_str(int state);
376const char *skd_skdev_state_to_str(enum skd_drvr_state state);
377static void skd_log_skdev(struct skd_device *skdev, const char *event);
e67f86b3
AB		 378static void skd_log_skreq(struct skd_device *skdev,
379 struct skd_request_context *skreq, const char *event);
380
e67f86b3
AB		 381/*
382 *****************************************************************************
383 * READ/WRITE REQUESTS
384 *****************************************************************************
385 */
d4d0f5fc
BVA		 386static void skd_inc_in_flight(struct request *rq, void *data, bool reserved)
387{
388 int *count = data;
389
390 count++;
391}
392
393static int skd_in_flight(struct skd_device *skdev)
394{
395 int count = 0;
396
397 blk_mq_tagset_busy_iter(&skdev->tag_set, skd_inc_in_flight, &count);
398
399 return count;
400}
401
e67f86b3
AB		 402static void
403skd_prep_rw_cdb(struct skd_scsi_request *scsi_req,
404 int data_dir, unsigned lba,
405 unsigned count)
406{
407 if (data_dir == READ)
fb4844b8 408 scsi_req->cdb[0] = READ_10;
e67f86b3 409 else
fb4844b8 410 scsi_req->cdb[0] = WRITE_10;
e67f86b3
AB		 411
412 scsi_req->cdb[1] = 0;
413 scsi_req->cdb[2] = (lba & 0xff000000) >> 24;
414 scsi_req->cdb[3] = (lba & 0xff0000) >> 16;
415 scsi_req->cdb[4] = (lba & 0xff00) >> 8;
416 scsi_req->cdb[5] = (lba & 0xff);
417 scsi_req->cdb[6] = 0;
418 scsi_req->cdb[7] = (count & 0xff00) >> 8;
419 scsi_req->cdb[8] = count & 0xff;
420 scsi_req->cdb[9] = 0;
421}
422
423static void
424skd_prep_zerosize_flush_cdb(struct skd_scsi_request *scsi_req,
38d4a1bb 425 struct skd_request_context *skreq)
e67f86b3
AB		 426{
427 skreq->flush_cmd = 1;
428
fb4844b8 429 scsi_req->cdb[0] = SYNCHRONIZE_CACHE;
e67f86b3
AB		 430 scsi_req->cdb[1] = 0;
431 scsi_req->cdb[2] = 0;
432 scsi_req->cdb[3] = 0;
433 scsi_req->cdb[4] = 0;
434 scsi_req->cdb[5] = 0;
435 scsi_req->cdb[6] = 0;
436 scsi_req->cdb[7] = 0;
437 scsi_req->cdb[8] = 0;
438 scsi_req->cdb[9] = 0;
439}
440
3d17a679
BVA		 441/*
442 * Return true if and only if all pending requests should be failed.
443 */
444static bool skd_fail_all(struct request_queue *q)
cb6981b9
BVA		 445{
446 struct skd_device *skdev = q->queuedata;
447
448 SKD_ASSERT(skdev->state != SKD_DRVR_STATE_ONLINE);
449
450 skd_log_skdev(skdev, "req_not_online");
451 switch (skdev->state) {
452 case SKD_DRVR_STATE_PAUSING:
453 case SKD_DRVR_STATE_PAUSED:
454 case SKD_DRVR_STATE_STARTING:
455 case SKD_DRVR_STATE_RESTARTING:
456 case SKD_DRVR_STATE_WAIT_BOOT:
457 /* In case of starting, we haven't started the queue,
458 * so we can't get here... but requests are
459 * possibly hanging out waiting for us because we
460 * reported the dev/skd0 already. They'll wait
461 * forever if connect doesn't complete.
462 * What to do??? delay dev/skd0 ??
463 */
464 case SKD_DRVR_STATE_BUSY:
465 case SKD_DRVR_STATE_BUSY_IMMINENT:
466 case SKD_DRVR_STATE_BUSY_ERASE:
3d17a679 467 return false;
cb6981b9
BVA		 468
469 case SKD_DRVR_STATE_BUSY_SANITIZE:
470 case SKD_DRVR_STATE_STOPPING:
471 case SKD_DRVR_STATE_SYNCING:
472 case SKD_DRVR_STATE_FAULT:
473 case SKD_DRVR_STATE_DISAPPEARED:
474 default:
3d17a679 475 return true;
cb6981b9 476 }
cb6981b9 477}
e67f86b3 478
c39c6c77
BVA		 479static blk_status_t skd_mq_queue_rq(struct blk_mq_hw_ctx *hctx,
480 const struct blk_mq_queue_data *mqd)
e67f86b3 481{
c39c6c77 482 struct request *const req = mqd->rq;
91f85da4 483 struct request_queue *const q = req->q;
e67f86b3 484 struct skd_device *skdev = q->queuedata;
91f85da4
BVA		 485 struct skd_fitmsg_context *skmsg;
486 struct fit_msg_hdr *fmh;
487 const u32 tag = blk_mq_unique_tag(req);
e7278a8b 488 struct skd_request_context *const skreq = blk_mq_rq_to_pdu(req);
e67f86b3 489 struct skd_scsi_request *scsi_req;
74c74282 490 unsigned long flags = 0;
e2bb5548
BVA		 491 const u32 lba = blk_rq_pos(req);
492 const u32 count = blk_rq_sectors(req);
493 const int data_dir = rq_data_dir(req);
91f85da4 494
c39c6c77
BVA		 495 if (unlikely(skdev->state != SKD_DRVR_STATE_ONLINE))
496 return skd_fail_all(q) ? BLK_STS_IOERR : BLK_STS_RESOURCE;
497
498 blk_mq_start_request(req);
499
91f85da4
BVA		 500 WARN_ONCE(tag >= skd_max_queue_depth, "%#x > %#x (nr_requests = %lu)\n",
501 tag, skd_max_queue_depth, q->nr_requests);
502
503 SKD_ASSERT(skreq->state == SKD_REQ_STATE_IDLE);
504
91f85da4
BVA		 505 dev_dbg(&skdev->pdev->dev,
506 "new req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba,
507 lba, count, count, data_dir);
508
509 skreq->id = tag + SKD_ID_RW_REQUEST;
510 skreq->flush_cmd = 0;
511 skreq->n_sg = 0;
512 skreq->sg_byte_count = 0;
513
91f85da4
BVA		 514 skreq->fitmsg_id = 0;
515
516 skreq->data_dir = data_dir == READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
517
518 if (req->bio && !skd_preop_sg_list(skdev, skreq)) {
519 dev_dbg(&skdev->pdev->dev, "error Out\n");
795bc1b5
BVA		 520 skreq->status = BLK_STS_RESOURCE;
521 blk_mq_complete_request(req);
c39c6c77 522 return BLK_STS_OK;
91f85da4
BVA		 523 }
524
a3db102d
BVA		 525 dma_sync_single_for_device(&skdev->pdev->dev, skreq->sksg_dma_address,
526 skreq->n_sg *
527 sizeof(struct fit_sg_descriptor),
528 DMA_TO_DEVICE);
529
91f85da4 530 /* Either a FIT msg is in progress or we have to start one. */
74c74282
BVA		 531 if (skd_max_req_per_msg == 1) {
532 skmsg = NULL;
533 } else {
534 spin_lock_irqsave(&skdev->lock, flags);
535 skmsg = skdev->skmsg;
536 }
91f85da4
BVA		 537 if (!skmsg) {
538 skmsg = &skdev->skmsg_table[tag];
539 skdev->skmsg = skmsg;
540
541 /* Initialize the FIT msg header */
542 fmh = &skmsg->msg_buf->fmh;
543 memset(fmh, 0, sizeof(*fmh));
544 fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT;
545 skmsg->length = sizeof(*fmh);
546 } else {
547 fmh = &skmsg->msg_buf->fmh;
548 }
549
550 skreq->fitmsg_id = skmsg->id;
551
552 scsi_req = &skmsg->msg_buf->scsi[fmh->num_protocol_cmds_coalesced];
553 memset(scsi_req, 0, sizeof(*scsi_req));
554
91f85da4 555 scsi_req->hdr.tag = skreq->id;
e2bb5548
BVA		 556 scsi_req->hdr.sg_list_dma_address =
557 cpu_to_be64(skreq->sksg_dma_address);
91f85da4 558
e2bb5548 559 if (req_op(req) == REQ_OP_FLUSH) {
91f85da4
BVA		 560 skd_prep_zerosize_flush_cdb(scsi_req, skreq);
561 SKD_ASSERT(skreq->flush_cmd == 1);
562 } else {
563 skd_prep_rw_cdb(scsi_req, data_dir, lba, count);
564 }
565
e2bb5548 566 if (req->cmd_flags & REQ_FUA)
91f85da4
BVA		 567 scsi_req->cdb[1] |= SKD_FUA_NV;
568
569 scsi_req->hdr.sg_list_len_bytes = cpu_to_be32(skreq->sg_byte_count);
570
571 /* Complete resource allocations. */
572 skreq->state = SKD_REQ_STATE_BUSY;
573
574 skmsg->length += sizeof(struct skd_scsi_request);
575 fmh->num_protocol_cmds_coalesced++;
576
91f85da4 577 dev_dbg(&skdev->pdev->dev, "req=0x%x busy=%d\n", skreq->id,
d4d0f5fc 578 skd_in_flight(skdev));
91f85da4
BVA		 579
580 /*
581 * If the FIT msg buffer is full send it.
582 */
74c74282 583 if (skd_max_req_per_msg == 1) {
91f85da4 584 skd_send_fitmsg(skdev, skmsg);
74c74282 585 } else {
c39c6c77 586 if (mqd->last ||
74c74282
BVA		 587 fmh->num_protocol_cmds_coalesced >= skd_max_req_per_msg) {
588 skd_send_fitmsg(skdev, skmsg);
589 skdev->skmsg = NULL;
590 }
591 spin_unlock_irqrestore(&skdev->lock, flags);
91f85da4 592 }
e67f86b3 593
ca33dd92 594 return BLK_STS_OK;
e67f86b3
AB		 595}
596
f2fe4459
BVA		 597static enum blk_eh_timer_return skd_timed_out(struct request *req,
598 bool reserved)
a74d5b76
BVA		 599{
600 struct skd_device *skdev = req->q->queuedata;
601
602 dev_err(&skdev->pdev->dev, "request with tag %#x timed out\n",
603 blk_mq_unique_tag(req));
604
f2fe4459 605 return BLK_EH_RESET_TIMER;
a74d5b76
BVA		 606}
607
296cb94c 608static void skd_complete_rq(struct request *req)
a74d5b76 609{
a74d5b76 610 struct skd_request_context *skreq = blk_mq_rq_to_pdu(req);
a74d5b76 611
f2fe4459 612 blk_mq_end_request(req, skreq->status);
a74d5b76
BVA		 613}
614
2a842aca 615static bool skd_preop_sg_list(struct skd_device *skdev,
38d4a1bb 616 struct skd_request_context *skreq)
e67f86b3 617{
e7278a8b 618 struct request *req = blk_mq_rq_from_pdu(skreq);
06f824c4 619 struct scatterlist *sgl = &skreq->sg[0], *sg;
e67f86b3
AB		 620 int n_sg;
621 int i;
622
623 skreq->sg_byte_count = 0;
624
b1824eef
BVA		 625 WARN_ON_ONCE(skreq->data_dir != DMA_TO_DEVICE &&
626 skreq->data_dir != DMA_FROM_DEVICE);
e67f86b3 627
06f824c4 628 n_sg = blk_rq_map_sg(skdev->queue, req, sgl);
e67f86b3 629 if (n_sg <= 0)
2a842aca 630 return false;
e67f86b3
AB		 631
632 /*
633 * Map scatterlist to PCI bus addresses.
634 * Note PCI might change the number of entries.
635 */
06f824c4 636 n_sg = pci_map_sg(skdev->pdev, sgl, n_sg, skreq->data_dir);
e67f86b3 637 if (n_sg <= 0)
2a842aca 638 return false;
e67f86b3
AB		 639
640 SKD_ASSERT(n_sg <= skdev->sgs_per_request);
641
642 skreq->n_sg = n_sg;
643
06f824c4 644 for_each_sg(sgl, sg, n_sg, i) {
e67f86b3 645 struct fit_sg_descriptor *sgd = &skreq->sksg_list[i];
06f824c4
BVA		 646 u32 cnt = sg_dma_len(sg);
647 uint64_t dma_addr = sg_dma_address(sg);
e67f86b3
AB		 648
649 sgd->control = FIT_SGD_CONTROL_NOT_LAST;
650 sgd->byte_count = cnt;
651 skreq->sg_byte_count += cnt;
652 sgd->host_side_addr = dma_addr;
653 sgd->dev_side_addr = 0;
654 }
655
656 skreq->sksg_list[n_sg - 1].next_desc_ptr = 0LL;
657 skreq->sksg_list[n_sg - 1].control = FIT_SGD_CONTROL_LAST;
658
659 if (unlikely(skdev->dbg_level > 1)) {
f98806d6
BVA		 660 dev_dbg(&skdev->pdev->dev,
661 "skreq=%x sksg_list=%p sksg_dma=%llx\n",
662 skreq->id, skreq->sksg_list, skreq->sksg_dma_address);
e67f86b3
AB		 663 for (i = 0; i < n_sg; i++) {
664 struct fit_sg_descriptor *sgd = &skreq->sksg_list[i];
f98806d6
BVA		 665
666 dev_dbg(&skdev->pdev->dev,
667 " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n",
668 i, sgd->byte_count, sgd->control,
669 sgd->host_side_addr, sgd->next_desc_ptr);
e67f86b3
AB		 670 }
671 }
672
2a842aca 673 return true;
e67f86b3
AB		 674}
675
fcd37eb3 676static void skd_postop_sg_list(struct skd_device *skdev,
38d4a1bb 677 struct skd_request_context *skreq)
e67f86b3 678{
e67f86b3
AB		 679 /*
680 * restore the next ptr for next IO request so we
681 * don't have to set it every time.
682 */
683 skreq->sksg_list[skreq->n_sg - 1].next_desc_ptr =
684 skreq->sksg_dma_address +
685 ((skreq->n_sg) * sizeof(struct fit_sg_descriptor));
b1824eef 686 pci_unmap_sg(skdev->pdev, &skreq->sg[0], skreq->n_sg, skreq->data_dir);
e67f86b3
AB		 687}
688
e67f86b3
AB		 689/*
690 *****************************************************************************
691 * TIMER
692 *****************************************************************************
693 */
694
695static void skd_timer_tick_not_online(struct skd_device *skdev);
696
ca33dd92
BVA		 697static void skd_start_queue(struct work_struct *work)
698{
699 struct skd_device *skdev = container_of(work, typeof(*skdev),
700 start_queue);
701
702 /*
703 * Although it is safe to call blk_start_queue() from interrupt
704 * context, blk_mq_start_hw_queues() must not be called from
705 * interrupt context.
706 */
707 blk_mq_start_hw_queues(skdev->queue);
708}
709
e99e88a9 710static void skd_timer_tick(struct timer_list *t)
e67f86b3 711{
e99e88a9 712 struct skd_device *skdev = from_timer(skdev, t, timer);
e67f86b3
AB		 713 unsigned long reqflags;
714 u32 state;
715
716 if (skdev->state == SKD_DRVR_STATE_FAULT)
717 /* The driver has declared fault, and we want it to
718 * stay that way until driver is reloaded.
719 */
720 return;
721
722 spin_lock_irqsave(&skdev->lock, reqflags);
723
724 state = SKD_READL(skdev, FIT_STATUS);
725 state &= FIT_SR_DRIVE_STATE_MASK;
726 if (state != skdev->drive_state)
727 skd_isr_fwstate(skdev);
728
a74d5b76 729 if (skdev->state != SKD_DRVR_STATE_ONLINE)
e67f86b3 730 skd_timer_tick_not_online(skdev);
e67f86b3 731
e67f86b3
AB		 732 mod_timer(&skdev->timer, (jiffies + HZ));
733
734 spin_unlock_irqrestore(&skdev->lock, reqflags);
735}
736
737static void skd_timer_tick_not_online(struct skd_device *skdev)
738{
739 switch (skdev->state) {
740 case SKD_DRVR_STATE_IDLE:
741 case SKD_DRVR_STATE_LOAD:
742 break;
743 case SKD_DRVR_STATE_BUSY_SANITIZE:
f98806d6
BVA		 744 dev_dbg(&skdev->pdev->dev,
745 "drive busy sanitize[%x], driver[%x]\n",
746 skdev->drive_state, skdev->state);
e67f86b3
AB		 747 /* If we've been in sanitize for 3 seconds, we figure we're not
748 * going to get anymore completions, so recover requests now
749 */
750 if (skdev->timer_countdown > 0) {
751 skdev->timer_countdown--;
752 return;
753 }
79ce12a8 754 skd_recover_requests(skdev);
e67f86b3
AB		 755 break;
756
757 case SKD_DRVR_STATE_BUSY:
758 case SKD_DRVR_STATE_BUSY_IMMINENT:
759 case SKD_DRVR_STATE_BUSY_ERASE:
f98806d6
BVA		 760 dev_dbg(&skdev->pdev->dev, "busy[%x], countdown=%d\n",
761 skdev->state, skdev->timer_countdown);
e67f86b3
AB		 762 if (skdev->timer_countdown > 0) {
763 skdev->timer_countdown--;
764 return;
765 }
f98806d6
BVA		 766 dev_dbg(&skdev->pdev->dev,
767 "busy[%x], timedout=%d, restarting device.",
768 skdev->state, skdev->timer_countdown);
e67f86b3
AB		 769 skd_restart_device(skdev);
770 break;
771
772 case SKD_DRVR_STATE_WAIT_BOOT:
773 case SKD_DRVR_STATE_STARTING:
774 if (skdev->timer_countdown > 0) {
775 skdev->timer_countdown--;
776 return;
777 }
778 /* For now, we fault the drive. Could attempt resets to
779 * revcover at some point. */
780 skdev->state = SKD_DRVR_STATE_FAULT;
781
f98806d6
BVA		 782 dev_err(&skdev->pdev->dev, "DriveFault Connect Timeout (%x)\n",
783 skdev->drive_state);
e67f86b3
AB		 784
785 /*start the queue so we can respond with error to requests */
786 /* wakeup anyone waiting for startup complete */
ca33dd92 787 schedule_work(&skdev->start_queue);
e67f86b3
AB		 788 skdev->gendisk_on = -1;
789 wake_up_interruptible(&skdev->waitq);
790 break;
791
792 case SKD_DRVR_STATE_ONLINE:
793 /* shouldn't get here. */
794 break;
795
796 case SKD_DRVR_STATE_PAUSING:
797 case SKD_DRVR_STATE_PAUSED:
798 break;
799
e67f86b3
AB		 800 case SKD_DRVR_STATE_RESTARTING:
801 if (skdev->timer_countdown > 0) {
802 skdev->timer_countdown--;
803 return;
804 }
805 /* For now, we fault the drive. Could attempt resets to
806 * revcover at some point. */
807 skdev->state = SKD_DRVR_STATE_FAULT;
f98806d6
BVA		 808 dev_err(&skdev->pdev->dev,
809 "DriveFault Reconnect Timeout (%x)\n",
810 skdev->drive_state);
e67f86b3
AB		 811
812 /*
813 * Recovering does two things:
814 * 1. completes IO with error
815 * 2. reclaims dma resources
816 * When is it safe to recover requests?
817 * - if the drive state is faulted
818 * - if the state is still soft reset after out timeout
819 * - if the drive registers are dead (state = FF)
820 * If it is "unsafe", we still need to recover, so we will
821 * disable pci bus mastering and disable our interrupts.
822 */
823
824 if ((skdev->drive_state == FIT_SR_DRIVE_SOFT_RESET) ||
825 (skdev->drive_state == FIT_SR_DRIVE_FAULT) ||
826 (skdev->drive_state == FIT_SR_DRIVE_STATE_MASK))
827 /* It never came out of soft reset. Try to
828 * recover the requests and then let them
829 * fail. This is to mitigate hung processes. */
79ce12a8 830 skd_recover_requests(skdev);
e67f86b3 831 else {
f98806d6
BVA		 832 dev_err(&skdev->pdev->dev, "Disable BusMaster (%x)\n",
833 skdev->drive_state);
e67f86b3
AB		 834 pci_disable_device(skdev->pdev);
835 skd_disable_interrupts(skdev);
79ce12a8 836 skd_recover_requests(skdev);
e67f86b3
AB		 837 }
838
839 /*start the queue so we can respond with error to requests */
840 /* wakeup anyone waiting for startup complete */
ca33dd92 841 schedule_work(&skdev->start_queue);
e67f86b3
AB		 842 skdev->gendisk_on = -1;
843 wake_up_interruptible(&skdev->waitq);
844 break;
845
846 case SKD_DRVR_STATE_RESUMING:
847 case SKD_DRVR_STATE_STOPPING:
848 case SKD_DRVR_STATE_SYNCING:
849 case SKD_DRVR_STATE_FAULT:
850 case SKD_DRVR_STATE_DISAPPEARED:
851 default:
852 break;
853 }
854}
855
856static int skd_start_timer(struct skd_device *skdev)
857{
858 int rc;
859
e99e88a9 860 timer_setup(&skdev->timer, skd_timer_tick, 0);
e67f86b3
AB		 861
862 rc = mod_timer(&skdev->timer, (jiffies + HZ));
863 if (rc)
f98806d6 864 dev_err(&skdev->pdev->dev, "failed to start timer %d\n", rc);
e67f86b3
AB		 865 return rc;
866}
867
868static void skd_kill_timer(struct skd_device *skdev)
869{
870 del_timer_sync(&skdev->timer);
871}
872
e67f86b3
AB		 873/*
874 *****************************************************************************
875 * INTERNAL REQUESTS -- generated by driver itself
876 *****************************************************************************
877 */
878
879static int skd_format_internal_skspcl(struct skd_device *skdev)
880{
881 struct skd_special_context *skspcl = &skdev->internal_skspcl;
882 struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0];
883 struct fit_msg_hdr *fmh;
884 uint64_t dma_address;
885 struct skd_scsi_request *scsi;
886
d891fe60 887 fmh = &skspcl->msg_buf->fmh;
e67f86b3
AB		 888 fmh->protocol_id = FIT_PROTOCOL_ID_SOFIT;
889 fmh->num_protocol_cmds_coalesced = 1;
890
d891fe60 891 scsi = &skspcl->msg_buf->scsi[0];
e67f86b3
AB		 892 memset(scsi, 0, sizeof(*scsi));
893 dma_address = skspcl->req.sksg_dma_address;
894 scsi->hdr.sg_list_dma_address = cpu_to_be64(dma_address);
32494df9 895 skspcl->req.n_sg = 1;
e67f86b3
AB		 896 sgd->control = FIT_SGD_CONTROL_LAST;
897 sgd->byte_count = 0;
898 sgd->host_side_addr = skspcl->db_dma_address;
899 sgd->dev_side_addr = 0;
900 sgd->next_desc_ptr = 0LL;
901
902 return 1;
903}
904
905#define WR_BUF_SIZE SKD_N_INTERNAL_BYTES
906
907static void skd_send_internal_skspcl(struct skd_device *skdev,
908 struct skd_special_context *skspcl,
909 u8 opcode)
910{
911 struct fit_sg_descriptor *sgd = &skspcl->req.sksg_list[0];
912 struct skd_scsi_request *scsi;
913 unsigned char *buf = skspcl->data_buf;
914 int i;
915
916 if (skspcl->req.state != SKD_REQ_STATE_IDLE)
917 /*
918 * A refresh is already in progress.
919 * Just wait for it to finish.
920 */
921 return;
922
e67f86b3 923 skspcl->req.state = SKD_REQ_STATE_BUSY;
e67f86b3 924
d891fe60 925 scsi = &skspcl->msg_buf->scsi[0];
e67f86b3
AB		 926 scsi->hdr.tag = skspcl->req.id;
927
928 memset(scsi->cdb, 0, sizeof(scsi->cdb));
929
930 switch (opcode) {
931 case TEST_UNIT_READY:
932 scsi->cdb[0] = TEST_UNIT_READY;
933 sgd->byte_count = 0;
934 scsi->hdr.sg_list_len_bytes = 0;
935 break;
936
937 case READ_CAPACITY:
938 scsi->cdb[0] = READ_CAPACITY;
939 sgd->byte_count = SKD_N_READ_CAP_BYTES;
940 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
941 break;
942
943 case INQUIRY:
944 scsi->cdb[0] = INQUIRY;
945 scsi->cdb[1] = 0x01; /* evpd */
946 scsi->cdb[2] = 0x80; /* serial number page */
947 scsi->cdb[4] = 0x10;
948 sgd->byte_count = 16;
949 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
950 break;
951
952 case SYNCHRONIZE_CACHE:
953 scsi->cdb[0] = SYNCHRONIZE_CACHE;
954 sgd->byte_count = 0;
955 scsi->hdr.sg_list_len_bytes = 0;
956 break;
957
958 case WRITE_BUFFER:
959 scsi->cdb[0] = WRITE_BUFFER;
960 scsi->cdb[1] = 0x02;
961 scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8;
962 scsi->cdb[8] = WR_BUF_SIZE & 0xFF;
963 sgd->byte_count = WR_BUF_SIZE;
964 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
965 /* fill incrementing byte pattern */
966 for (i = 0; i < sgd->byte_count; i++)
967 buf[i] = i & 0xFF;
968 break;
969
970 case READ_BUFFER:
971 scsi->cdb[0] = READ_BUFFER;
972 scsi->cdb[1] = 0x02;
973 scsi->cdb[7] = (WR_BUF_SIZE & 0xFF00) >> 8;
974 scsi->cdb[8] = WR_BUF_SIZE & 0xFF;
975 sgd->byte_count = WR_BUF_SIZE;
976 scsi->hdr.sg_list_len_bytes = cpu_to_be32(sgd->byte_count);
977 memset(skspcl->data_buf, 0, sgd->byte_count);
978 break;
979
980 default:
981 SKD_ASSERT("Don't know what to send");
982 return;
983
984 }
985 skd_send_special_fitmsg(skdev, skspcl);
986}
987
988static void skd_refresh_device_data(struct skd_device *skdev)
989{
990 struct skd_special_context *skspcl = &skdev->internal_skspcl;
991
992 skd_send_internal_skspcl(skdev, skspcl, TEST_UNIT_READY);
993}
994
995static int skd_chk_read_buf(struct skd_device *skdev,
996 struct skd_special_context *skspcl)
997{
998 unsigned char *buf = skspcl->data_buf;
999 int i;
1000
1001 /* check for incrementing byte pattern */
1002 for (i = 0; i < WR_BUF_SIZE; i++)
1003 if (buf[i] != (i & 0xFF))
1004 return 1;
1005
1006 return 0;
1007}
1008
1009static void skd_log_check_status(struct skd_device *skdev, u8 status, u8 key,
1010 u8 code, u8 qual, u8 fruc)
1011{
1012 /* If the check condition is of special interest, log a message */
1013 if ((status == SAM_STAT_CHECK_CONDITION) && (key == 0x02)
1014 && (code == 0x04) && (qual == 0x06)) {
f98806d6
BVA		 1015 dev_err(&skdev->pdev->dev,
1016 "*** LOST_WRITE_DATA ERROR *** key/asc/ascq/fruc %02x/%02x/%02x/%02x\n",
1017 key, code, qual, fruc);
e67f86b3
AB		 1018 }
1019}
1020
1021static void skd_complete_internal(struct skd_device *skdev,
85e34112
BVA		 1022 struct fit_completion_entry_v1 *skcomp,
1023 struct fit_comp_error_info *skerr,
e67f86b3
AB		 1024 struct skd_special_context *skspcl)
1025{
1026 u8 *buf = skspcl->data_buf;
1027 u8 status;
1028 int i;
d891fe60 1029 struct skd_scsi_request *scsi = &skspcl->msg_buf->scsi[0];
e67f86b3 1030
760b48ca
BVA		 1031 lockdep_assert_held(&skdev->lock);
1032
e67f86b3
AB		 1033 SKD_ASSERT(skspcl == &skdev->internal_skspcl);
1034
f98806d6 1035 dev_dbg(&skdev->pdev->dev, "complete internal %x\n", scsi->cdb[0]);
e67f86b3 1036
a3db102d
BVA		 1037 dma_sync_single_for_cpu(&skdev->pdev->dev,
1038 skspcl->db_dma_address,
1039 skspcl->req.sksg_list[0].byte_count,
1040 DMA_BIDIRECTIONAL);
1041
e67f86b3
AB		 1042 skspcl->req.completion = *skcomp;
1043 skspcl->req.state = SKD_REQ_STATE_IDLE;
e67f86b3
AB		 1044
1045 status = skspcl->req.completion.status;
1046
1047 skd_log_check_status(skdev, status, skerr->key, skerr->code,
1048 skerr->qual, skerr->fruc);
1049
1050 switch (scsi->cdb[0]) {
1051 case TEST_UNIT_READY:
1052 if (status == SAM_STAT_GOOD)
1053 skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER);
1054 else if ((status == SAM_STAT_CHECK_CONDITION) &&
1055 (skerr->key == MEDIUM_ERROR))
1056 skd_send_internal_skspcl(skdev, skspcl, WRITE_BUFFER);
1057 else {
1058 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1059 dev_dbg(&skdev->pdev->dev,
1060 "TUR failed, don't send anymore state 0x%x\n",
1061 skdev->state);
e67f86b3
AB		 1062 return;
1063 }
f98806d6
BVA		 1064 dev_dbg(&skdev->pdev->dev,
1065 "**** TUR failed, retry skerr\n");
fb4844b8
BVA		 1066 skd_send_internal_skspcl(skdev, skspcl,
1067 TEST_UNIT_READY);
e67f86b3
AB		 1068 }
1069 break;
1070
1071 case WRITE_BUFFER:
1072 if (status == SAM_STAT_GOOD)
1073 skd_send_internal_skspcl(skdev, skspcl, READ_BUFFER);
1074 else {
1075 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1076 dev_dbg(&skdev->pdev->dev,
1077 "write buffer failed, don't send anymore state 0x%x\n",
1078 skdev->state);
e67f86b3
AB		 1079 return;
1080 }
f98806d6
BVA		 1081 dev_dbg(&skdev->pdev->dev,
1082 "**** write buffer failed, retry skerr\n");
fb4844b8
BVA		 1083 skd_send_internal_skspcl(skdev, skspcl,
1084 TEST_UNIT_READY);
e67f86b3
AB		 1085 }
1086 break;
1087
1088 case READ_BUFFER:
1089 if (status == SAM_STAT_GOOD) {
1090 if (skd_chk_read_buf(skdev, skspcl) == 0)
1091 skd_send_internal_skspcl(skdev, skspcl,
1092 READ_CAPACITY);
1093 else {
f98806d6
BVA		 1094 dev_err(&skdev->pdev->dev,
1095 "*** W/R Buffer mismatch %d ***\n",
1096 skdev->connect_retries);
e67f86b3
AB		 1097 if (skdev->connect_retries <
1098 SKD_MAX_CONNECT_RETRIES) {
1099 skdev->connect_retries++;
1100 skd_soft_reset(skdev);
1101 } else {
f98806d6
BVA		 1102 dev_err(&skdev->pdev->dev,
1103 "W/R Buffer Connect Error\n");
e67f86b3
AB		 1104 return;
1105 }
1106 }
1107
1108 } else {
1109 if (skdev->state == SKD_DRVR_STATE_STOPPING) {
f98806d6
BVA		 1110 dev_dbg(&skdev->pdev->dev,
1111 "read buffer failed, don't send anymore state 0x%x\n",
1112 skdev->state);
e67f86b3
AB		 1113 return;
1114 }
f98806d6
BVA		 1115 dev_dbg(&skdev->pdev->dev,
1116 "**** read buffer failed, retry skerr\n");
fb4844b8
BVA		 1117 skd_send_internal_skspcl(skdev, skspcl,
1118 TEST_UNIT_READY);
e67f86b3
AB		 1119 }
1120 break;
1121
1122 case READ_CAPACITY:
1123 skdev->read_cap_is_valid = 0;
1124 if (status == SAM_STAT_GOOD) {
1125 skdev->read_cap_last_lba =
1126 (buf[0] << 24) | (buf[1] << 16) |
1127 (buf[2] << 8) | buf[3];
1128 skdev->read_cap_blocksize =
1129 (buf[4] << 24) | (buf[5] << 16) |
1130 (buf[6] << 8) | buf[7];
1131
f98806d6
BVA		 1132 dev_dbg(&skdev->pdev->dev, "last lba %d, bs %d\n",
1133 skdev->read_cap_last_lba,
1134 skdev->read_cap_blocksize);
e67f86b3
AB		 1135
1136 set_capacity(skdev->disk, skdev->read_cap_last_lba + 1);
1137
1138 skdev->read_cap_is_valid = 1;
1139
1140 skd_send_internal_skspcl(skdev, skspcl, INQUIRY);
1141 } else if ((status == SAM_STAT_CHECK_CONDITION) &&
1142 (skerr->key == MEDIUM_ERROR)) {
1143 skdev->read_cap_last_lba = ~0;
1144 set_capacity(skdev->disk, skdev->read_cap_last_lba + 1);
f98806d6 1145 dev_dbg(&skdev->pdev->dev, "**** MEDIUM ERROR caused READCAP to fail, ignore failure and continue to inquiry\n");
e67f86b3
AB		 1146 skd_send_internal_skspcl(skdev, skspcl, INQUIRY);
1147 } else {
f98806d6 1148 dev_dbg(&skdev->pdev->dev, "**** READCAP failed, retry TUR\n");
e67f86b3
AB		 1149 skd_send_internal_skspcl(skdev, skspcl,
1150 TEST_UNIT_READY);
1151 }
1152 break;
1153
1154 case INQUIRY:
1155 skdev->inquiry_is_valid = 0;
1156 if (status == SAM_STAT_GOOD) {
1157 skdev->inquiry_is_valid = 1;
1158
1159 for (i = 0; i < 12; i++)
1160 skdev->inq_serial_num[i] = buf[i + 4];
1161 skdev->inq_serial_num[12] = 0;
1162 }
1163
1164 if (skd_unquiesce_dev(skdev) < 0)
f98806d6 1165 dev_dbg(&skdev->pdev->dev, "**** failed, to ONLINE device\n");
e67f86b3
AB		 1166 /* connection is complete */
1167 skdev->connect_retries = 0;
1168 break;
1169
1170 case SYNCHRONIZE_CACHE:
1171 if (status == SAM_STAT_GOOD)
1172 skdev->sync_done = 1;
1173 else
1174 skdev->sync_done = -1;
1175 wake_up_interruptible(&skdev->waitq);
1176 break;
1177
1178 default:
1179 SKD_ASSERT("we didn't send this");
1180 }
1181}
1182
1183/*
1184 *****************************************************************************
1185 * FIT MESSAGES
1186 *****************************************************************************
1187 */
1188
1189static void skd_send_fitmsg(struct skd_device *skdev,
1190 struct skd_fitmsg_context *skmsg)
1191{
1192 u64 qcmd;
e67f86b3 1193
f98806d6 1194 dev_dbg(&skdev->pdev->dev, "dma address 0x%llx, busy=%d\n",
d4d0f5fc 1195 skmsg->mb_dma_address, skd_in_flight(skdev));
6507f436 1196 dev_dbg(&skdev->pdev->dev, "msg_buf %p\n", skmsg->msg_buf);
e67f86b3
AB		 1197
1198 qcmd = skmsg->mb_dma_address;
1199 qcmd |= FIT_QCMD_QID_NORMAL;
1200
e67f86b3
AB		 1201 if (unlikely(skdev->dbg_level > 1)) {
1202 u8 *bp = (u8 *)skmsg->msg_buf;
1203 int i;
1204 for (i = 0; i < skmsg->length; i += 8) {
f98806d6
BVA		 1205 dev_dbg(&skdev->pdev->dev, "msg[%2d] %8ph\n", i,
1206 &bp[i]);
e67f86b3
AB		 1207 if (i == 0)
1208 i = 64 - 8;
1209 }
1210 }
1211
1212 if (skmsg->length > 256)
1213 qcmd |= FIT_QCMD_MSGSIZE_512;
1214 else if (skmsg->length > 128)
1215 qcmd |= FIT_QCMD_MSGSIZE_256;
1216 else if (skmsg->length > 64)
1217 qcmd |= FIT_QCMD_MSGSIZE_128;
1218 else
1219 /*
1220 * This makes no sense because the FIT msg header is
1221 * 64 bytes. If the msg is only 64 bytes long it has
1222 * no payload.
1223 */
1224 qcmd |= FIT_QCMD_MSGSIZE_64;
1225
a3db102d
BVA		 1226 dma_sync_single_for_device(&skdev->pdev->dev, skmsg->mb_dma_address,
1227 skmsg->length, DMA_TO_DEVICE);
1228
5fbd545c
BVA		 1229 /* Make sure skd_msg_buf is written before the doorbell is triggered. */
1230 smp_wmb();
1231
e67f86b3 1232 SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND);
e67f86b3
AB		 1233}
1234
1235static void skd_send_special_fitmsg(struct skd_device *skdev,
1236 struct skd_special_context *skspcl)
1237{
1238 u64 qcmd;
1239
a3db102d
BVA		 1240 WARN_ON_ONCE(skspcl->req.n_sg != 1);
1241
e67f86b3
AB		 1242 if (unlikely(skdev->dbg_level > 1)) {
1243 u8 *bp = (u8 *)skspcl->msg_buf;
1244 int i;
1245
1246 for (i = 0; i < SKD_N_SPECIAL_FITMSG_BYTES; i += 8) {
f98806d6
BVA		 1247 dev_dbg(&skdev->pdev->dev, " spcl[%2d] %8ph\n", i,
1248 &bp[i]);
e67f86b3
AB		 1249 if (i == 0)
1250 i = 64 - 8;
1251 }
1252
f98806d6
BVA		 1253 dev_dbg(&skdev->pdev->dev,
1254 "skspcl=%p id=%04x sksg_list=%p sksg_dma=%llx\n",
1255 skspcl, skspcl->req.id, skspcl->req.sksg_list,
1256 skspcl->req.sksg_dma_address);
e67f86b3
AB		 1257 for (i = 0; i < skspcl->req.n_sg; i++) {
1258 struct fit_sg_descriptor *sgd =
1259 &skspcl->req.sksg_list[i];
1260
f98806d6
BVA		 1261 dev_dbg(&skdev->pdev->dev,
1262 " sg[%d] count=%u ctrl=0x%x addr=0x%llx next=0x%llx\n",
1263 i, sgd->byte_count, sgd->control,
1264 sgd->host_side_addr, sgd->next_desc_ptr);
e67f86b3
AB		 1265 }
1266 }
1267
1268 /*
1269 * Special FIT msgs are always 128 bytes: a 64-byte FIT hdr
1270 * and one 64-byte SSDI command.
1271 */
1272 qcmd = skspcl->mb_dma_address;
1273 qcmd |= FIT_QCMD_QID_NORMAL + FIT_QCMD_MSGSIZE_128;
1274
a3db102d
BVA		 1275 dma_sync_single_for_device(&skdev->pdev->dev, skspcl->mb_dma_address,
1276 SKD_N_SPECIAL_FITMSG_BYTES, DMA_TO_DEVICE);
1277 dma_sync_single_for_device(&skdev->pdev->dev,
1278 skspcl->req.sksg_dma_address,
1279 1 * sizeof(struct fit_sg_descriptor),
1280 DMA_TO_DEVICE);
1281 dma_sync_single_for_device(&skdev->pdev->dev,
1282 skspcl->db_dma_address,
1283 skspcl->req.sksg_list[0].byte_count,
1284 DMA_BIDIRECTIONAL);
1285
5fbd545c
BVA		 1286 /* Make sure skd_msg_buf is written before the doorbell is triggered. */
1287 smp_wmb();
1288
e67f86b3
AB		 1289 SKD_WRITEQ(skdev, qcmd, FIT_Q_COMMAND);
1290}
1291
1292/*
1293 *****************************************************************************
1294 * COMPLETION QUEUE
1295 *****************************************************************************
1296 */
1297
1298static void skd_complete_other(struct skd_device *skdev,
85e34112
BVA		 1299 struct fit_completion_entry_v1 *skcomp,
1300 struct fit_comp_error_info *skerr);
e67f86b3 1301
e67f86b3
AB		 1302struct sns_info {
1303 u8 type;
1304 u8 stat;
1305 u8 key;
1306 u8 asc;
1307 u8 ascq;
1308 u8 mask;
1309 enum skd_check_status_action action;
1310};
1311
1312static struct sns_info skd_chkstat_table[] = {
1313 /* Good */
1314 { 0x70, 0x02, RECOVERED_ERROR, 0, 0, 0x1c,
1315 SKD_CHECK_STATUS_REPORT_GOOD },
1316
1317 /* Smart alerts */
1318 { 0x70, 0x02, NO_SENSE, 0x0B, 0x00, 0x1E, /* warnings */
1319 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1320 { 0x70, 0x02, NO_SENSE, 0x5D, 0x00, 0x1E, /* thresholds */
1321 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1322 { 0x70, 0x02, RECOVERED_ERROR, 0x0B, 0x01, 0x1F, /* temperature over trigger */
1323 SKD_CHECK_STATUS_REPORT_SMART_ALERT },
1324
1325 /* Retry (with limits) */
1326 { 0x70, 0x02, 0x0B, 0, 0, 0x1C, /* This one is for DMA ERROR */
1327 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1328 { 0x70, 0x02, 0x06, 0x0B, 0x00, 0x1E, /* warnings */
1329 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1330 { 0x70, 0x02, 0x06, 0x5D, 0x00, 0x1E, /* thresholds */
1331 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1332 { 0x70, 0x02, 0x06, 0x80, 0x30, 0x1F, /* backup power */
1333 SKD_CHECK_STATUS_REQUEUE_REQUEST },
1334
1335 /* Busy (or about to be) */
1336 { 0x70, 0x02, 0x06, 0x3f, 0x01, 0x1F, /* fw changed */
1337 SKD_CHECK_STATUS_BUSY_IMMINENT },
1338};
1339
1340/*
1341 * Look up status and sense data to decide how to handle the error
1342 * from the device.
1343 * mask says which fields must match e.g., mask=0x18 means check
1344 * type and stat, ignore key, asc, ascq.
1345 */
1346
38d4a1bb
MS		 1347static enum skd_check_status_action
1348skd_check_status(struct skd_device *skdev,
85e34112 1349 u8 cmp_status, struct fit_comp_error_info *skerr)
e67f86b3 1350{
0b2e0c07 1351 int i;
e67f86b3 1352
f98806d6
BVA		 1353 dev_err(&skdev->pdev->dev, "key/asc/ascq/fruc %02x/%02x/%02x/%02x\n",
1354 skerr->key, skerr->code, skerr->qual, skerr->fruc);
e67f86b3 1355
f98806d6
BVA		 1356 dev_dbg(&skdev->pdev->dev,
1357 "stat: t=%02x stat=%02x k=%02x c=%02x q=%02x fruc=%02x\n",
1358 skerr->type, cmp_status, skerr->key, skerr->code, skerr->qual,
1359 skerr->fruc);
e67f86b3
AB		 1360
1361 /* Does the info match an entry in the good category? */
0b2e0c07 1362 for (i = 0; i < ARRAY_SIZE(skd_chkstat_table); i++) {
e67f86b3
AB		 1363 struct sns_info *sns = &skd_chkstat_table[i];
1364
1365 if (sns->mask & 0x10)
1366 if (skerr->type != sns->type)
1367 continue;
1368
1369 if (sns->mask & 0x08)
1370 if (cmp_status != sns->stat)
1371 continue;
1372
1373 if (sns->mask & 0x04)
1374 if (skerr->key != sns->key)
1375 continue;
1376
1377 if (sns->mask & 0x02)
1378 if (skerr->code != sns->asc)
1379 continue;
1380
1381 if (sns->mask & 0x01)
1382 if (skerr->qual != sns->ascq)
1383 continue;
1384
1385 if (sns->action == SKD_CHECK_STATUS_REPORT_SMART_ALERT) {
f98806d6
BVA		 1386 dev_err(&skdev->pdev->dev,
1387 "SMART Alert: sense key/asc/ascq %02x/%02x/%02x\n",
1388 skerr->key, skerr->code, skerr->qual);
e67f86b3
AB		 1389 }
1390 return sns->action;
1391 }
1392
1393 /* No other match, so nonzero status means error,
1394 * zero status means good
1395 */
1396 if (cmp_status) {
f98806d6 1397 dev_dbg(&skdev->pdev->dev, "status check: error\n");
e67f86b3
AB		 1398 return SKD_CHECK_STATUS_REPORT_ERROR;
1399 }
1400
f98806d6 1401 dev_dbg(&skdev->pdev->dev, "status check good default\n");
e67f86b3
AB		 1402 return SKD_CHECK_STATUS_REPORT_GOOD;
1403}
1404
1405static void skd_resolve_req_exception(struct skd_device *skdev,
f18c17c8
BVA		 1406 struct skd_request_context *skreq,
1407 struct request *req)
e67f86b3
AB		 1408{
1409 u8 cmp_status = skreq->completion.status;
1410
1411 switch (skd_check_status(skdev, cmp_status, &skreq->err_info)) {
1412 case SKD_CHECK_STATUS_REPORT_GOOD:
1413 case SKD_CHECK_STATUS_REPORT_SMART_ALERT:
795bc1b5
BVA		 1414 skreq->status = BLK_STS_OK;
1415 blk_mq_complete_request(req);
e67f86b3
AB		 1416 break;
1417
1418 case SKD_CHECK_STATUS_BUSY_IMMINENT:
1419 skd_log_skreq(skdev, skreq, "retry(busy)");
f18c17c8 1420 blk_requeue_request(skdev->queue, req);
f98806d6 1421 dev_info(&skdev->pdev->dev, "drive BUSY imminent\n");
e67f86b3
AB		 1422 skdev->state = SKD_DRVR_STATE_BUSY_IMMINENT;
1423 skdev->timer_countdown = SKD_TIMER_MINUTES(20);
1424 skd_quiesce_dev(skdev);
1425 break;
1426
1427 case SKD_CHECK_STATUS_REQUEUE_REQUEST:
f18c17c8 1428 if ((unsigned long) ++req->special < SKD_MAX_RETRIES) {
fcd37eb3 1429 skd_log_skreq(skdev, skreq, "retry");
f18c17c8 1430 blk_requeue_request(skdev->queue, req);
fcd37eb3 1431 break;
e67f86b3 1432 }
ce6882ba 1433 /* fall through */
e67f86b3
AB		 1434
1435 case SKD_CHECK_STATUS_REPORT_ERROR:
1436 default:
795bc1b5
BVA		 1437 skreq->status = BLK_STS_IOERR;
1438 blk_mq_complete_request(req);
e67f86b3
AB		 1439 break;
1440 }
1441}
1442
e67f86b3
AB		 1443static void skd_release_skreq(struct skd_device *skdev,
1444 struct skd_request_context *skreq)
1445{
e67f86b3
AB		 1446 /*
1447 * Reclaim the skd_request_context
1448 */
1449 skreq->state = SKD_REQ_STATE_IDLE;
f18c17c8
BVA		 1450}
1451
e67f86b3
AB		 1452static int skd_isr_completion_posted(struct skd_device *skdev,
1453 int limit, int *enqueued)
1454{
85e34112
BVA		 1455 struct fit_completion_entry_v1 *skcmp;
1456 struct fit_comp_error_info *skerr;
e67f86b3 1457 u16 req_id;
f18c17c8 1458 u32 tag;
ca33dd92 1459 u16 hwq = 0;
f18c17c8 1460 struct request *rq;
e67f86b3 1461 struct skd_request_context *skreq;
c830da8c
BVA		 1462 u16 cmp_cntxt;
1463 u8 cmp_status;
1464 u8 cmp_cycle;
1465 u32 cmp_bytes;
c0b3dda7 1466 int rc = 0;
e67f86b3 1467 int processed = 0;
e67f86b3 1468
760b48ca
BVA		 1469 lockdep_assert_held(&skdev->lock);
1470
e67f86b3
AB		 1471 for (;; ) {
1472 SKD_ASSERT(skdev->skcomp_ix < SKD_N_COMPLETION_ENTRY);
1473
1474 skcmp = &skdev->skcomp_table[skdev->skcomp_ix];
1475 cmp_cycle = skcmp->cycle;
1476 cmp_cntxt = skcmp->tag;
1477 cmp_status = skcmp->status;
1478 cmp_bytes = be32_to_cpu(skcmp->num_returned_bytes);
1479
1480 skerr = &skdev->skerr_table[skdev->skcomp_ix];
1481
f98806d6
BVA		 1482 dev_dbg(&skdev->pdev->dev,
1483 "cycle=%d ix=%d got cycle=%d cmdctxt=0x%x stat=%d busy=%d rbytes=0x%x proto=%d\n",
1484 skdev->skcomp_cycle, skdev->skcomp_ix, cmp_cycle,
d4d0f5fc 1485 cmp_cntxt, cmp_status, skd_in_flight(skdev),
6fbb2de5 1486 cmp_bytes, skdev->proto_ver);
e67f86b3
AB		 1487
1488 if (cmp_cycle != skdev->skcomp_cycle) {
f98806d6 1489 dev_dbg(&skdev->pdev->dev, "end of completions\n");
e67f86b3
AB		 1490 break;
1491 }
1492 /*
1493 * Update the completion queue head index and possibly
1494 * the completion cycle count. 8-bit wrap-around.
1495 */
1496 skdev->skcomp_ix++;
1497 if (skdev->skcomp_ix >= SKD_N_COMPLETION_ENTRY) {
1498 skdev->skcomp_ix = 0;
1499 skdev->skcomp_cycle++;
1500 }
1501
1502 /*
1503 * The command context is a unique 32-bit ID. The low order
1504 * bits help locate the request. The request is usually a
1505 * r/w request (see skd_start() above) or a special request.
1506 */
1507 req_id = cmp_cntxt;
f18c17c8 1508 tag = req_id & SKD_ID_SLOT_AND_TABLE_MASK;
e67f86b3
AB		 1509
1510 /* Is this other than a r/w request? */
f18c17c8 1511 if (tag >= skdev->num_req_context) {
e67f86b3
AB		 1512 /*
1513 * This is not a completion for a r/w request.
1514 */
ca33dd92
BVA		 1515 WARN_ON_ONCE(blk_mq_tag_to_rq(skdev->tag_set.tags[hwq],
1516 tag));
e67f86b3
AB		 1517 skd_complete_other(skdev, skcmp, skerr);
1518 continue;
1519 }
1520
ca33dd92 1521 rq = blk_mq_tag_to_rq(skdev->tag_set.tags[hwq], tag);
f18c17c8
BVA		 1522 if (WARN(!rq, "No request for tag %#x -> %#x\n", cmp_cntxt,
1523 tag))
1524 continue;
e7278a8b 1525 skreq = blk_mq_rq_to_pdu(rq);
e67f86b3
AB		 1526
1527 /*
1528 * Make sure the request ID for the slot matches.
1529 */
1530 if (skreq->id != req_id) {
49f16e2f
BVA		 1531 dev_err(&skdev->pdev->dev,
1532 "Completion mismatch comp_id=0x%04x skreq=0x%04x new=0x%04x\n",
1533 req_id, skreq->id, cmp_cntxt);
e67f86b3 1534
49f16e2f 1535 continue;
e67f86b3
AB		 1536 }
1537
1538 SKD_ASSERT(skreq->state == SKD_REQ_STATE_BUSY);
1539
e67f86b3
AB		 1540 skreq->completion = *skcmp;
1541 if (unlikely(cmp_status == SAM_STAT_CHECK_CONDITION)) {
1542 skreq->err_info = *skerr;
1543 skd_log_check_status(skdev, cmp_status, skerr->key,
1544 skerr->code, skerr->qual,
1545 skerr->fruc);
1546 }
1547 /* Release DMA resources for the request. */
1548 if (skreq->n_sg > 0)
1549 skd_postop_sg_list(skdev, skreq);
1550
f18c17c8 1551 skd_release_skreq(skdev, skreq);
e67f86b3
AB		 1552
1553 /*
f18c17c8 1554 * Capture the outcome and post it back to the native request.
e67f86b3 1555 */
795bc1b5
BVA		 1556 if (likely(cmp_status == SAM_STAT_GOOD)) {
1557 skreq->status = BLK_STS_OK;
1558 blk_mq_complete_request(rq);
1559 } else {
f18c17c8 1560 skd_resolve_req_exception(skdev, skreq, rq);
795bc1b5 1561 }
e67f86b3
AB		 1562
1563 /* skd_isr_comp_limit equal zero means no limit */
1564 if (limit) {
1565 if (++processed >= limit) {
1566 rc = 1;
1567 break;
1568 }
1569 }
1570 }
1571
6fbb2de5 1572 if (skdev->state == SKD_DRVR_STATE_PAUSING &&
d4d0f5fc 1573 skd_in_flight(skdev) == 0) {
e67f86b3
AB		 1574 skdev->state = SKD_DRVR_STATE_PAUSED;
1575 wake_up_interruptible(&skdev->waitq);
1576 }
1577
1578 return rc;
1579}
1580
1581static void skd_complete_other(struct skd_device *skdev,
85e34112
BVA		 1582 struct fit_completion_entry_v1 *skcomp,
1583 struct fit_comp_error_info *skerr)
e67f86b3
AB		 1584{
1585 u32 req_id = 0;
1586 u32 req_table;
1587 u32 req_slot;
1588 struct skd_special_context *skspcl;
1589
760b48ca
BVA		 1590 lockdep_assert_held(&skdev->lock);
1591
e67f86b3
AB		 1592 req_id = skcomp->tag;
1593 req_table = req_id & SKD_ID_TABLE_MASK;
1594 req_slot = req_id & SKD_ID_SLOT_MASK;
1595
f98806d6
BVA		 1596 dev_dbg(&skdev->pdev->dev, "table=0x%x id=0x%x slot=%d\n", req_table,
1597 req_id, req_slot);
e67f86b3
AB		 1598
1599 /*
1600 * Based on the request id, determine how to dispatch this completion.
1601 * This swich/case is finding the good cases and forwarding the
1602 * completion entry. Errors are reported below the switch.
1603 */
1604 switch (req_table) {
1605 case SKD_ID_RW_REQUEST:
1606 /*
e1d06f2d 1607 * The caller, skd_isr_completion_posted() above,
e67f86b3
AB		 1608 * handles r/w requests. The only way we get here
1609 * is if the req_slot is out of bounds.
1610 */
1611 break;
1612
e67f86b3
AB		 1613 case SKD_ID_INTERNAL:
1614 if (req_slot == 0) {
1615 skspcl = &skdev->internal_skspcl;
1616 if (skspcl->req.id == req_id &&
1617 skspcl->req.state == SKD_REQ_STATE_BUSY) {
1618 skd_complete_internal(skdev,
1619 skcomp, skerr, skspcl);
1620 return;
1621 }
1622 }
1623 break;
1624
1625 case SKD_ID_FIT_MSG:
1626 /*
1627 * These id's should never appear in a completion record.
1628 */
1629 break;
1630
1631 default:
1632 /*
1633 * These id's should never appear anywhere;
1634 */
1635 break;
1636 }
1637
1638 /*
1639 * If we get here it is a bad or stale id.
1640 */
1641}
1642
e67f86b3
AB		 1643static void skd_reset_skcomp(struct skd_device *skdev)
1644{
6f7c7675 1645 memset(skdev->skcomp_table, 0, SKD_SKCOMP_SIZE);
e67f86b3
AB		 1646
1647 skdev->skcomp_ix = 0;
1648 skdev->skcomp_cycle = 1;
1649}
1650
1651/*
1652 *****************************************************************************
1653 * INTERRUPTS
1654 *****************************************************************************
1655 */
1656static void skd_completion_worker(struct work_struct *work)
1657{
1658 struct skd_device *skdev =
1659 container_of(work, struct skd_device, completion_worker);
1660 unsigned long flags;
1661 int flush_enqueued = 0;
1662
1663 spin_lock_irqsave(&skdev->lock, flags);
1664
1665 /*
1666 * pass in limit=0, which means no limit..
1667 * process everything in compq
1668 */
1669 skd_isr_completion_posted(skdev, 0, &flush_enqueued);
ca33dd92 1670 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1671
1672 spin_unlock_irqrestore(&skdev->lock, flags);
1673}
1674
1675static void skd_isr_msg_from_dev(struct skd_device *skdev);
1676
41c9499b
AB		 1677static irqreturn_t
1678skd_isr(int irq, void *ptr)
e67f86b3 1679{
1cd3c1ab 1680 struct skd_device *skdev = ptr;
e67f86b3
AB		 1681 u32 intstat;
1682 u32 ack;
1683 int rc = 0;
1684 int deferred = 0;
1685 int flush_enqueued = 0;
1686
e67f86b3
AB		 1687 spin_lock(&skdev->lock);
1688
1689 for (;; ) {
1690 intstat = SKD_READL(skdev, FIT_INT_STATUS_HOST);
1691
1692 ack = FIT_INT_DEF_MASK;
1693 ack &= intstat;
1694
f98806d6
BVA		 1695 dev_dbg(&skdev->pdev->dev, "intstat=0x%x ack=0x%x\n", intstat,
1696 ack);
e67f86b3
AB		 1697
1698 /* As long as there is an int pending on device, keep
1699 * running loop. When none, get out, but if we've never
1700 * done any processing, call completion handler?
1701 */
1702 if (ack == 0) {
1703 /* No interrupts on device, but run the completion
1704 * processor anyway?
1705 */
1706 if (rc == 0)
1707 if (likely (skdev->state
1708 == SKD_DRVR_STATE_ONLINE))
1709 deferred = 1;
1710 break;
1711 }
1712
1713 rc = IRQ_HANDLED;
1714
1715 SKD_WRITEL(skdev, ack, FIT_INT_STATUS_HOST);
1716
1717 if (likely((skdev->state != SKD_DRVR_STATE_LOAD) &&
1718 (skdev->state != SKD_DRVR_STATE_STOPPING))) {
1719 if (intstat & FIT_ISH_COMPLETION_POSTED) {
1720 /*
1721 * If we have already deferred completion
1722 * processing, don't bother running it again
1723 */
1724 if (deferred == 0)
1725 deferred =
1726 skd_isr_completion_posted(skdev,
1727 skd_isr_comp_limit, &flush_enqueued);
1728 }
1729
1730 if (intstat & FIT_ISH_FW_STATE_CHANGE) {
1731 skd_isr_fwstate(skdev);
1732 if (skdev->state == SKD_DRVR_STATE_FAULT ||
1733 skdev->state ==
1734 SKD_DRVR_STATE_DISAPPEARED) {
1735 spin_unlock(&skdev->lock);
1736 return rc;
1737 }
1738 }
1739
1740 if (intstat & FIT_ISH_MSG_FROM_DEV)
1741 skd_isr_msg_from_dev(skdev);
1742 }
1743 }
1744
1745 if (unlikely(flush_enqueued))
ca33dd92 1746 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1747
1748 if (deferred)
1749 schedule_work(&skdev->completion_worker);
1750 else if (!flush_enqueued)
ca33dd92 1751 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1752
1753 spin_unlock(&skdev->lock);
1754
1755 return rc;
1756}
1757
e67f86b3
AB		 1758static void skd_drive_fault(struct skd_device *skdev)
1759{
1760 skdev->state = SKD_DRVR_STATE_FAULT;
f98806d6 1761 dev_err(&skdev->pdev->dev, "Drive FAULT\n");
e67f86b3
AB		 1762}
1763
1764static void skd_drive_disappeared(struct skd_device *skdev)
1765{
1766 skdev->state = SKD_DRVR_STATE_DISAPPEARED;
f98806d6 1767 dev_err(&skdev->pdev->dev, "Drive DISAPPEARED\n");
e67f86b3
AB		 1768}
1769
1770static void skd_isr_fwstate(struct skd_device *skdev)
1771{
1772 u32 sense;
1773 u32 state;
1774 u32 mtd;
1775 int prev_driver_state = skdev->state;
1776
1777 sense = SKD_READL(skdev, FIT_STATUS);
1778 state = sense & FIT_SR_DRIVE_STATE_MASK;
1779
f98806d6
BVA		 1780 dev_err(&skdev->pdev->dev, "s1120 state %s(%d)=>%s(%d)\n",
1781 skd_drive_state_to_str(skdev->drive_state), skdev->drive_state,
1782 skd_drive_state_to_str(state), state);
e67f86b3
AB		 1783
1784 skdev->drive_state = state;
1785
1786 switch (skdev->drive_state) {
1787 case FIT_SR_DRIVE_INIT:
1788 if (skdev->state == SKD_DRVR_STATE_PROTOCOL_MISMATCH) {
1789 skd_disable_interrupts(skdev);
1790 break;
1791 }
1792 if (skdev->state == SKD_DRVR_STATE_RESTARTING)
79ce12a8 1793 skd_recover_requests(skdev);
e67f86b3
AB		 1794 if (skdev->state == SKD_DRVR_STATE_WAIT_BOOT) {
1795 skdev->timer_countdown = SKD_STARTING_TIMO;
1796 skdev->state = SKD_DRVR_STATE_STARTING;
1797 skd_soft_reset(skdev);
1798 break;
1799 }
1800 mtd = FIT_MXD_CONS(FIT_MTD_FITFW_INIT, 0, 0);
1801 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1802 skdev->last_mtd = mtd;
1803 break;
1804
1805 case FIT_SR_DRIVE_ONLINE:
1806 skdev->cur_max_queue_depth = skd_max_queue_depth;
1807 if (skdev->cur_max_queue_depth > skdev->dev_max_queue_depth)
1808 skdev->cur_max_queue_depth = skdev->dev_max_queue_depth;
1809
1810 skdev->queue_low_water_mark =
1811 skdev->cur_max_queue_depth * 2 / 3 + 1;
1812 if (skdev->queue_low_water_mark < 1)
1813 skdev->queue_low_water_mark = 1;
f98806d6
BVA		 1814 dev_info(&skdev->pdev->dev,
1815 "Queue depth limit=%d dev=%d lowat=%d\n",
1816 skdev->cur_max_queue_depth,
1817 skdev->dev_max_queue_depth,
1818 skdev->queue_low_water_mark);
e67f86b3
AB		 1819
1820 skd_refresh_device_data(skdev);
1821 break;
1822
1823 case FIT_SR_DRIVE_BUSY:
1824 skdev->state = SKD_DRVR_STATE_BUSY;
1825 skdev->timer_countdown = SKD_BUSY_TIMO;
1826 skd_quiesce_dev(skdev);
1827 break;
1828 case FIT_SR_DRIVE_BUSY_SANITIZE:
1829 /* set timer for 3 seconds, we'll abort any unfinished
1830 * commands after that expires
1831 */
1832 skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE;
1833 skdev->timer_countdown = SKD_TIMER_SECONDS(3);
ca33dd92 1834 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1835 break;
1836 case FIT_SR_DRIVE_BUSY_ERASE:
1837 skdev->state = SKD_DRVR_STATE_BUSY_ERASE;
1838 skdev->timer_countdown = SKD_BUSY_TIMO;
1839 break;
1840 case FIT_SR_DRIVE_OFFLINE:
1841 skdev->state = SKD_DRVR_STATE_IDLE;
1842 break;
1843 case FIT_SR_DRIVE_SOFT_RESET:
1844 switch (skdev->state) {
1845 case SKD_DRVR_STATE_STARTING:
1846 case SKD_DRVR_STATE_RESTARTING:
1847 /* Expected by a caller of skd_soft_reset() */
1848 break;
1849 default:
1850 skdev->state = SKD_DRVR_STATE_RESTARTING;
1851 break;
1852 }
1853 break;
1854 case FIT_SR_DRIVE_FW_BOOTING:
f98806d6 1855 dev_dbg(&skdev->pdev->dev, "ISR FIT_SR_DRIVE_FW_BOOTING\n");
e67f86b3
AB		 1856 skdev->state = SKD_DRVR_STATE_WAIT_BOOT;
1857 skdev->timer_countdown = SKD_WAIT_BOOT_TIMO;
1858 break;
1859
1860 case FIT_SR_DRIVE_DEGRADED:
1861 case FIT_SR_PCIE_LINK_DOWN:
1862 case FIT_SR_DRIVE_NEED_FW_DOWNLOAD:
1863 break;
1864
1865 case FIT_SR_DRIVE_FAULT:
1866 skd_drive_fault(skdev);
79ce12a8 1867 skd_recover_requests(skdev);
ca33dd92 1868 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1869 break;
1870
1871 /* PCIe bus returned all Fs? */
1872 case 0xFF:
f98806d6
BVA		 1873 dev_info(&skdev->pdev->dev, "state=0x%x sense=0x%x\n", state,
1874 sense);
e67f86b3 1875 skd_drive_disappeared(skdev);
79ce12a8 1876 skd_recover_requests(skdev);
ca33dd92 1877 schedule_work(&skdev->start_queue);
e67f86b3
AB		 1878 break;
1879 default:
1880 /*
1881 * Uknown FW State. Wait for a state we recognize.
1882 */
1883 break;
1884 }
f98806d6
BVA		 1885 dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n",
1886 skd_skdev_state_to_str(prev_driver_state), prev_driver_state,
1887 skd_skdev_state_to_str(skdev->state), skdev->state);
e67f86b3
AB		 1888}
1889
ca33dd92 1890static void skd_recover_request(struct request *req, void *data, bool reserved)
e67f86b3 1891{
ca33dd92
BVA		 1892 struct skd_device *const skdev = data;
1893 struct skd_request_context *skreq = blk_mq_rq_to_pdu(req);
e67f86b3 1894
4e54b849
BVA		 1895 if (skreq->state != SKD_REQ_STATE_BUSY)
1896 return;
e67f86b3 1897
4e54b849 1898 skd_log_skreq(skdev, skreq, "recover");
e67f86b3 1899
4e54b849
BVA		 1900 /* Release DMA resources for the request. */
1901 if (skreq->n_sg > 0)
1902 skd_postop_sg_list(skdev, skreq);
e67f86b3 1903
4e54b849 1904 skreq->state = SKD_REQ_STATE_IDLE;
795bc1b5
BVA		 1905 skreq->status = BLK_STS_IOERR;
1906 blk_mq_complete_request(req);
4e54b849 1907}
e67f86b3 1908
4e54b849
BVA		 1909static void skd_recover_requests(struct skd_device *skdev)
1910{
ca33dd92 1911 blk_mq_tagset_busy_iter(&skdev->tag_set, skd_recover_request, skdev);
e67f86b3
AB		 1912}
1913
1914static void skd_isr_msg_from_dev(struct skd_device *skdev)
1915{
1916 u32 mfd;
1917 u32 mtd;
1918 u32 data;
1919
1920 mfd = SKD_READL(skdev, FIT_MSG_FROM_DEVICE);
1921
f98806d6
BVA		 1922 dev_dbg(&skdev->pdev->dev, "mfd=0x%x last_mtd=0x%x\n", mfd,
1923 skdev->last_mtd);
e67f86b3
AB		 1924
1925 /* ignore any mtd that is an ack for something we didn't send */
1926 if (FIT_MXD_TYPE(mfd) != FIT_MXD_TYPE(skdev->last_mtd))
1927 return;
1928
1929 switch (FIT_MXD_TYPE(mfd)) {
1930 case FIT_MTD_FITFW_INIT:
1931 skdev->proto_ver = FIT_PROTOCOL_MAJOR_VER(mfd);
1932
1933 if (skdev->proto_ver != FIT_PROTOCOL_VERSION_1) {
f98806d6
BVA		 1934 dev_err(&skdev->pdev->dev, "protocol mismatch\n");
1935 dev_err(&skdev->pdev->dev, " got=%d support=%d\n",
1936 skdev->proto_ver, FIT_PROTOCOL_VERSION_1);
1937 dev_err(&skdev->pdev->dev, " please upgrade driver\n");
e67f86b3
AB		 1938 skdev->state = SKD_DRVR_STATE_PROTOCOL_MISMATCH;
1939 skd_soft_reset(skdev);
1940 break;
1941 }
1942 mtd = FIT_MXD_CONS(FIT_MTD_GET_CMDQ_DEPTH, 0, 0);
1943 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1944 skdev->last_mtd = mtd;
1945 break;
1946
1947 case FIT_MTD_GET_CMDQ_DEPTH:
1948 skdev->dev_max_queue_depth = FIT_MXD_DATA(mfd);
1949 mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_DEPTH, 0,
1950 SKD_N_COMPLETION_ENTRY);
1951 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1952 skdev->last_mtd = mtd;
1953 break;
1954
1955 case FIT_MTD_SET_COMPQ_DEPTH:
1956 SKD_WRITEQ(skdev, skdev->cq_dma_address, FIT_MSG_TO_DEVICE_ARG);
1957 mtd = FIT_MXD_CONS(FIT_MTD_SET_COMPQ_ADDR, 0, 0);
1958 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1959 skdev->last_mtd = mtd;
1960 break;
1961
1962 case FIT_MTD_SET_COMPQ_ADDR:
1963 skd_reset_skcomp(skdev);
1964 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_HOST_ID, 0, skdev->devno);
1965 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1966 skdev->last_mtd = mtd;
1967 break;
1968
1969 case FIT_MTD_CMD_LOG_HOST_ID:
474f5da2
AB		 1970 /* hardware interface overflows in y2106 */
1971 skdev->connect_time_stamp = (u32)ktime_get_real_seconds();
e67f86b3
AB		 1972 data = skdev->connect_time_stamp & 0xFFFF;
1973 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_LO, 0, data);
1974 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1975 skdev->last_mtd = mtd;
1976 break;
1977
1978 case FIT_MTD_CMD_LOG_TIME_STAMP_LO:
1979 skdev->drive_jiffies = FIT_MXD_DATA(mfd);
1980 data = (skdev->connect_time_stamp >> 16) & 0xFFFF;
1981 mtd = FIT_MXD_CONS(FIT_MTD_CMD_LOG_TIME_STAMP_HI, 0, data);
1982 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1983 skdev->last_mtd = mtd;
1984 break;
1985
1986 case FIT_MTD_CMD_LOG_TIME_STAMP_HI:
1987 skdev->drive_jiffies |= (FIT_MXD_DATA(mfd) << 16);
1988 mtd = FIT_MXD_CONS(FIT_MTD_ARM_QUEUE, 0, 0);
1989 SKD_WRITEL(skdev, mtd, FIT_MSG_TO_DEVICE);
1990 skdev->last_mtd = mtd;
1991
f98806d6
BVA		 1992 dev_err(&skdev->pdev->dev, "Time sync driver=0x%x device=0x%x\n",
1993 skdev->connect_time_stamp, skdev->drive_jiffies);
e67f86b3
AB		 1994 break;
1995
1996 case FIT_MTD_ARM_QUEUE:
1997 skdev->last_mtd = 0;
1998 /*
1999 * State should be, or soon will be, FIT_SR_DRIVE_ONLINE.
2000 */
2001 break;
2002
2003 default:
2004 break;
2005 }
2006}
2007
2008static void skd_disable_interrupts(struct skd_device *skdev)
2009{
2010 u32 sense;
2011
2012 sense = SKD_READL(skdev, FIT_CONTROL);
2013 sense &= ~FIT_CR_ENABLE_INTERRUPTS;
2014 SKD_WRITEL(skdev, sense, FIT_CONTROL);
f98806d6 2015 dev_dbg(&skdev->pdev->dev, "sense 0x%x\n", sense);
e67f86b3
AB		 2016
2017 /* Note that the 1s is written. A 1-bit means
2018 * disable, a 0 means enable.
2019 */
2020 SKD_WRITEL(skdev, ~0, FIT_INT_MASK_HOST);
2021}
2022
2023static void skd_enable_interrupts(struct skd_device *skdev)
2024{
2025 u32 val;
2026
2027 /* unmask interrupts first */
2028 val = FIT_ISH_FW_STATE_CHANGE +
2029 FIT_ISH_COMPLETION_POSTED + FIT_ISH_MSG_FROM_DEV;
2030
2031 /* Note that the compliment of mask is written. A 1-bit means
2032 * disable, a 0 means enable. */
2033 SKD_WRITEL(skdev, ~val, FIT_INT_MASK_HOST);
f98806d6 2034 dev_dbg(&skdev->pdev->dev, "interrupt mask=0x%x\n", ~val);
e67f86b3
AB		 2035
2036 val = SKD_READL(skdev, FIT_CONTROL);
2037 val |= FIT_CR_ENABLE_INTERRUPTS;
f98806d6 2038 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
e67f86b3
AB		 2039 SKD_WRITEL(skdev, val, FIT_CONTROL);
2040}
2041
2042/*
2043 *****************************************************************************
2044 * START, STOP, RESTART, QUIESCE, UNQUIESCE
2045 *****************************************************************************
2046 */
2047
2048static void skd_soft_reset(struct skd_device *skdev)
2049{
2050 u32 val;
2051
2052 val = SKD_READL(skdev, FIT_CONTROL);
2053 val |= (FIT_CR_SOFT_RESET);
f98806d6 2054 dev_dbg(&skdev->pdev->dev, "control=0x%x\n", val);
e67f86b3
AB		 2055 SKD_WRITEL(skdev, val, FIT_CONTROL);
2056}
2057
2058static void skd_start_device(struct skd_device *skdev)
2059{
2060 unsigned long flags;
2061 u32 sense;
2062 u32 state;
2063
2064 spin_lock_irqsave(&skdev->lock, flags);
2065
2066 /* ack all ghost interrupts */
2067 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2068
2069 sense = SKD_READL(skdev, FIT_STATUS);
2070
f98806d6 2071 dev_dbg(&skdev->pdev->dev, "initial status=0x%x\n", sense);
e67f86b3
AB		 2072
2073 state = sense & FIT_SR_DRIVE_STATE_MASK;
2074 skdev->drive_state = state;
2075 skdev->last_mtd = 0;
2076
2077 skdev->state = SKD_DRVR_STATE_STARTING;
2078 skdev->timer_countdown = SKD_STARTING_TIMO;
2079
2080 skd_enable_interrupts(skdev);
2081
2082 switch (skdev->drive_state) {
2083 case FIT_SR_DRIVE_OFFLINE:
f98806d6 2084 dev_err(&skdev->pdev->dev, "Drive offline...\n");
e67f86b3
AB		 2085 break;
2086
2087 case FIT_SR_DRIVE_FW_BOOTING:
f98806d6 2088 dev_dbg(&skdev->pdev->dev, "FIT_SR_DRIVE_FW_BOOTING\n");
e67f86b3
AB		 2089 skdev->state = SKD_DRVR_STATE_WAIT_BOOT;
2090 skdev->timer_countdown = SKD_WAIT_BOOT_TIMO;
2091 break;
2092
2093 case FIT_SR_DRIVE_BUSY_SANITIZE:
f98806d6 2094 dev_info(&skdev->pdev->dev, "Start: BUSY_SANITIZE\n");
e67f86b3
AB		 2095 skdev->state = SKD_DRVR_STATE_BUSY_SANITIZE;
2096 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2097 break;
2098
2099 case FIT_SR_DRIVE_BUSY_ERASE:
f98806d6 2100 dev_info(&skdev->pdev->dev, "Start: BUSY_ERASE\n");
e67f86b3
AB		 2101 skdev->state = SKD_DRVR_STATE_BUSY_ERASE;
2102 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2103 break;
2104
2105 case FIT_SR_DRIVE_INIT:
2106 case FIT_SR_DRIVE_ONLINE:
2107 skd_soft_reset(skdev);
2108 break;
2109
2110 case FIT_SR_DRIVE_BUSY:
f98806d6 2111 dev_err(&skdev->pdev->dev, "Drive Busy...\n");
e67f86b3
AB		 2112 skdev->state = SKD_DRVR_STATE_BUSY;
2113 skdev->timer_countdown = SKD_STARTED_BUSY_TIMO;
2114 break;
2115
2116 case FIT_SR_DRIVE_SOFT_RESET:
f98806d6 2117 dev_err(&skdev->pdev->dev, "drive soft reset in prog\n");
e67f86b3
AB		 2118 break;
2119
2120 case FIT_SR_DRIVE_FAULT:
2121 /* Fault state is bad...soft reset won't do it...
2122 * Hard reset, maybe, but does it work on device?
2123 * For now, just fault so the system doesn't hang.
2124 */
2125 skd_drive_fault(skdev);
2126 /*start the queue so we can respond with error to requests */
f98806d6 2127 dev_dbg(&skdev->pdev->dev, "starting queue\n");
ca33dd92 2128 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2129 skdev->gendisk_on = -1;
2130 wake_up_interruptible(&skdev->waitq);
2131 break;
2132
2133 case 0xFF:
2134 /* Most likely the device isn't there or isn't responding
2135 * to the BAR1 addresses. */
2136 skd_drive_disappeared(skdev);
2137 /*start the queue so we can respond with error to requests */
f98806d6
BVA		 2138 dev_dbg(&skdev->pdev->dev,
2139 "starting queue to error-out reqs\n");
ca33dd92 2140 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2141 skdev->gendisk_on = -1;
2142 wake_up_interruptible(&skdev->waitq);
2143 break;
2144
2145 default:
f98806d6
BVA		 2146 dev_err(&skdev->pdev->dev, "Start: unknown state %x\n",
2147 skdev->drive_state);
e67f86b3
AB		 2148 break;
2149 }
2150
2151 state = SKD_READL(skdev, FIT_CONTROL);
f98806d6 2152 dev_dbg(&skdev->pdev->dev, "FIT Control Status=0x%x\n", state);
e67f86b3
AB		 2153
2154 state = SKD_READL(skdev, FIT_INT_STATUS_HOST);
f98806d6 2155 dev_dbg(&skdev->pdev->dev, "Intr Status=0x%x\n", state);
e67f86b3
AB		 2156
2157 state = SKD_READL(skdev, FIT_INT_MASK_HOST);
f98806d6 2158 dev_dbg(&skdev->pdev->dev, "Intr Mask=0x%x\n", state);
e67f86b3
AB		 2159
2160 state = SKD_READL(skdev, FIT_MSG_FROM_DEVICE);
f98806d6 2161 dev_dbg(&skdev->pdev->dev, "Msg from Dev=0x%x\n", state);
e67f86b3
AB		 2162
2163 state = SKD_READL(skdev, FIT_HW_VERSION);
f98806d6 2164 dev_dbg(&skdev->pdev->dev, "HW version=0x%x\n", state);
e67f86b3
AB		 2165
2166 spin_unlock_irqrestore(&skdev->lock, flags);
2167}
2168
2169static void skd_stop_device(struct skd_device *skdev)
2170{
2171 unsigned long flags;
2172 struct skd_special_context *skspcl = &skdev->internal_skspcl;
2173 u32 dev_state;
2174 int i;
2175
2176 spin_lock_irqsave(&skdev->lock, flags);
2177
2178 if (skdev->state != SKD_DRVR_STATE_ONLINE) {
f98806d6 2179 dev_err(&skdev->pdev->dev, "%s not online no sync\n", __func__);
e67f86b3
AB		 2180 goto stop_out;
2181 }
2182
2183 if (skspcl->req.state != SKD_REQ_STATE_IDLE) {
f98806d6 2184 dev_err(&skdev->pdev->dev, "%s no special\n", __func__);
e67f86b3
AB		 2185 goto stop_out;
2186 }
2187
2188 skdev->state = SKD_DRVR_STATE_SYNCING;
2189 skdev->sync_done = 0;
2190
2191 skd_send_internal_skspcl(skdev, skspcl, SYNCHRONIZE_CACHE);
2192
2193 spin_unlock_irqrestore(&skdev->lock, flags);
2194
2195 wait_event_interruptible_timeout(skdev->waitq,
2196 (skdev->sync_done), (10 * HZ));
2197
2198 spin_lock_irqsave(&skdev->lock, flags);
2199
2200 switch (skdev->sync_done) {
2201 case 0:
f98806d6 2202 dev_err(&skdev->pdev->dev, "%s no sync\n", __func__);
e67f86b3
AB		 2203 break;
2204 case 1:
f98806d6 2205 dev_err(&skdev->pdev->dev, "%s sync done\n", __func__);
e67f86b3
AB		 2206 break;
2207 default:
f98806d6 2208 dev_err(&skdev->pdev->dev, "%s sync error\n", __func__);
e67f86b3
AB		 2209 }
2210
2211stop_out:
2212 skdev->state = SKD_DRVR_STATE_STOPPING;
2213 spin_unlock_irqrestore(&skdev->lock, flags);
2214
2215 skd_kill_timer(skdev);
2216
2217 spin_lock_irqsave(&skdev->lock, flags);
2218 skd_disable_interrupts(skdev);
2219
2220 /* ensure all ints on device are cleared */
2221 /* soft reset the device to unload with a clean slate */
2222 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2223 SKD_WRITEL(skdev, FIT_CR_SOFT_RESET, FIT_CONTROL);
2224
2225 spin_unlock_irqrestore(&skdev->lock, flags);
2226
2227 /* poll every 100ms, 1 second timeout */
2228 for (i = 0; i < 10; i++) {
2229 dev_state =
2230 SKD_READL(skdev, FIT_STATUS) & FIT_SR_DRIVE_STATE_MASK;
2231 if (dev_state == FIT_SR_DRIVE_INIT)
2232 break;
2233 set_current_state(TASK_INTERRUPTIBLE);
2234 schedule_timeout(msecs_to_jiffies(100));
2235 }
2236
2237 if (dev_state != FIT_SR_DRIVE_INIT)
f98806d6
BVA		 2238 dev_err(&skdev->pdev->dev, "%s state error 0x%02x\n", __func__,
2239 dev_state);
e67f86b3
AB		 2240}
2241
2242/* assume spinlock is held */
2243static void skd_restart_device(struct skd_device *skdev)
2244{
2245 u32 state;
2246
2247 /* ack all ghost interrupts */
2248 SKD_WRITEL(skdev, FIT_INT_DEF_MASK, FIT_INT_STATUS_HOST);
2249
2250 state = SKD_READL(skdev, FIT_STATUS);
2251
f98806d6 2252 dev_dbg(&skdev->pdev->dev, "drive status=0x%x\n", state);
e67f86b3
AB		 2253
2254 state &= FIT_SR_DRIVE_STATE_MASK;
2255 skdev->drive_state = state;
2256 skdev->last_mtd = 0;
2257
2258 skdev->state = SKD_DRVR_STATE_RESTARTING;
2259 skdev->timer_countdown = SKD_RESTARTING_TIMO;
2260
2261 skd_soft_reset(skdev);
2262}
2263
2264/* assume spinlock is held */
2265static int skd_quiesce_dev(struct skd_device *skdev)
2266{
2267 int rc = 0;
2268
2269 switch (skdev->state) {
2270 case SKD_DRVR_STATE_BUSY:
2271 case SKD_DRVR_STATE_BUSY_IMMINENT:
f98806d6 2272 dev_dbg(&skdev->pdev->dev, "stopping queue\n");
ca33dd92 2273 blk_mq_stop_hw_queues(skdev->queue);
e67f86b3
AB		 2274 break;
2275 case SKD_DRVR_STATE_ONLINE:
2276 case SKD_DRVR_STATE_STOPPING:
2277 case SKD_DRVR_STATE_SYNCING:
2278 case SKD_DRVR_STATE_PAUSING:
2279 case SKD_DRVR_STATE_PAUSED:
2280 case SKD_DRVR_STATE_STARTING:
2281 case SKD_DRVR_STATE_RESTARTING:
2282 case SKD_DRVR_STATE_RESUMING:
2283 default:
2284 rc = -EINVAL;
f98806d6
BVA		 2285 dev_dbg(&skdev->pdev->dev, "state [%d] not implemented\n",
2286 skdev->state);
e67f86b3
AB		 2287 }
2288 return rc;
2289}
2290
2291/* assume spinlock is held */
2292static int skd_unquiesce_dev(struct skd_device *skdev)
2293{
2294 int prev_driver_state = skdev->state;
2295
2296 skd_log_skdev(skdev, "unquiesce");
2297 if (skdev->state == SKD_DRVR_STATE_ONLINE) {
f98806d6 2298 dev_dbg(&skdev->pdev->dev, "**** device already ONLINE\n");
e67f86b3
AB		 2299 return 0;
2300 }
2301 if (skdev->drive_state != FIT_SR_DRIVE_ONLINE) {
2302 /*
2303 * If there has been an state change to other than
2304 * ONLINE, we will rely on controller state change
2305 * to come back online and restart the queue.
2306 * The BUSY state means that driver is ready to
2307 * continue normal processing but waiting for controller
2308 * to become available.
2309 */
2310 skdev->state = SKD_DRVR_STATE_BUSY;
f98806d6 2311 dev_dbg(&skdev->pdev->dev, "drive BUSY state\n");
e67f86b3
AB		 2312 return 0;
2313 }
2314
2315 /*
2316 * Drive has just come online, driver is either in startup,
2317 * paused performing a task, or bust waiting for hardware.
2318 */
2319 switch (skdev->state) {
2320 case SKD_DRVR_STATE_PAUSED:
2321 case SKD_DRVR_STATE_BUSY:
2322 case SKD_DRVR_STATE_BUSY_IMMINENT:
2323 case SKD_DRVR_STATE_BUSY_ERASE:
2324 case SKD_DRVR_STATE_STARTING:
2325 case SKD_DRVR_STATE_RESTARTING:
2326 case SKD_DRVR_STATE_FAULT:
2327 case SKD_DRVR_STATE_IDLE:
2328 case SKD_DRVR_STATE_LOAD:
2329 skdev->state = SKD_DRVR_STATE_ONLINE;
f98806d6
BVA		 2330 dev_err(&skdev->pdev->dev, "Driver state %s(%d)=>%s(%d)\n",
2331 skd_skdev_state_to_str(prev_driver_state),
2332 prev_driver_state, skd_skdev_state_to_str(skdev->state),
2333 skdev->state);
2334 dev_dbg(&skdev->pdev->dev,
2335 "**** device ONLINE...starting block queue\n");
2336 dev_dbg(&skdev->pdev->dev, "starting queue\n");
2337 dev_info(&skdev->pdev->dev, "STEC s1120 ONLINE\n");
ca33dd92 2338 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2339 skdev->gendisk_on = 1;
2340 wake_up_interruptible(&skdev->waitq);
2341 break;
2342
2343 case SKD_DRVR_STATE_DISAPPEARED:
2344 default:
f98806d6
BVA		 2345 dev_dbg(&skdev->pdev->dev,
2346 "**** driver state %d, not implemented\n",
2347 skdev->state);
e67f86b3
AB		 2348 return -EBUSY;
2349 }
2350 return 0;
2351}
2352
2353/*
2354 *****************************************************************************
2355 * PCIe MSI/MSI-X INTERRUPT HANDLERS
2356 *****************************************************************************
2357 */
2358
2359static irqreturn_t skd_reserved_isr(int irq, void *skd_host_data)
2360{
2361 struct skd_device *skdev = skd_host_data;
2362 unsigned long flags;
2363
2364 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2365 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2366 SKD_READL(skdev, FIT_INT_STATUS_HOST));
2367 dev_err(&skdev->pdev->dev, "MSIX reserved irq %d = 0x%x\n", irq,
2368 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2369 SKD_WRITEL(skdev, FIT_INT_RESERVED_MASK, FIT_INT_STATUS_HOST);
2370 spin_unlock_irqrestore(&skdev->lock, flags);
2371 return IRQ_HANDLED;
2372}
2373
2374static irqreturn_t skd_statec_isr(int irq, void *skd_host_data)
2375{
2376 struct skd_device *skdev = skd_host_data;
2377 unsigned long flags;
2378
2379 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2380 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2381 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2382 SKD_WRITEL(skdev, FIT_ISH_FW_STATE_CHANGE, FIT_INT_STATUS_HOST);
2383 skd_isr_fwstate(skdev);
2384 spin_unlock_irqrestore(&skdev->lock, flags);
2385 return IRQ_HANDLED;
2386}
2387
2388static irqreturn_t skd_comp_q(int irq, void *skd_host_data)
2389{
2390 struct skd_device *skdev = skd_host_data;
2391 unsigned long flags;
2392 int flush_enqueued = 0;
2393 int deferred;
2394
2395 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2396 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2397 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2398 SKD_WRITEL(skdev, FIT_ISH_COMPLETION_POSTED, FIT_INT_STATUS_HOST);
2399 deferred = skd_isr_completion_posted(skdev, skd_isr_comp_limit,
2400 &flush_enqueued);
e67f86b3 2401 if (flush_enqueued)
ca33dd92 2402 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2403
2404 if (deferred)
2405 schedule_work(&skdev->completion_worker);
2406 else if (!flush_enqueued)
ca33dd92 2407 schedule_work(&skdev->start_queue);
e67f86b3
AB		 2408
2409 spin_unlock_irqrestore(&skdev->lock, flags);
2410
2411 return IRQ_HANDLED;
2412}
2413
2414static irqreturn_t skd_msg_isr(int irq, void *skd_host_data)
2415{
2416 struct skd_device *skdev = skd_host_data;
2417 unsigned long flags;
2418
2419 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2420 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2421 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2422 SKD_WRITEL(skdev, FIT_ISH_MSG_FROM_DEV, FIT_INT_STATUS_HOST);
2423 skd_isr_msg_from_dev(skdev);
2424 spin_unlock_irqrestore(&skdev->lock, flags);
2425 return IRQ_HANDLED;
2426}
2427
2428static irqreturn_t skd_qfull_isr(int irq, void *skd_host_data)
2429{
2430 struct skd_device *skdev = skd_host_data;
2431 unsigned long flags;
2432
2433 spin_lock_irqsave(&skdev->lock, flags);
f98806d6
BVA		 2434 dev_dbg(&skdev->pdev->dev, "MSIX = 0x%x\n",
2435 SKD_READL(skdev, FIT_INT_STATUS_HOST));
e67f86b3
AB		 2436 SKD_WRITEL(skdev, FIT_INT_QUEUE_FULL, FIT_INT_STATUS_HOST);
2437 spin_unlock_irqrestore(&skdev->lock, flags);
2438 return IRQ_HANDLED;
2439}
2440
2441/*
2442 *****************************************************************************
2443 * PCIe MSI/MSI-X SETUP
2444 *****************************************************************************
2445 */
2446
2447struct skd_msix_entry {
e67f86b3
AB		 2448 char isr_name[30];
2449};
2450
2451struct skd_init_msix_entry {
2452 const char *name;
2453 irq_handler_t handler;
2454};
2455
2456#define SKD_MAX_MSIX_COUNT 13
2457#define SKD_MIN_MSIX_COUNT 7
2458#define SKD_BASE_MSIX_IRQ 4
2459
2460static struct skd_init_msix_entry msix_entries[SKD_MAX_MSIX_COUNT] = {
2461 { "(DMA 0)", skd_reserved_isr },
2462 { "(DMA 1)", skd_reserved_isr },
2463 { "(DMA 2)", skd_reserved_isr },
2464 { "(DMA 3)", skd_reserved_isr },
2465 { "(State Change)", skd_statec_isr },
2466 { "(COMPL_Q)", skd_comp_q },
2467 { "(MSG)", skd_msg_isr },
2468 { "(Reserved)", skd_reserved_isr },
2469 { "(Reserved)", skd_reserved_isr },
2470 { "(Queue Full 0)", skd_qfull_isr },
2471 { "(Queue Full 1)", skd_qfull_isr },
2472 { "(Queue Full 2)", skd_qfull_isr },
2473 { "(Queue Full 3)", skd_qfull_isr },
2474};
2475
e67f86b3
AB		 2476static int skd_acquire_msix(struct skd_device *skdev)
2477{
a9df8625 2478 int i, rc;
46817769 2479 struct pci_dev *pdev = skdev->pdev;
e67f86b3 2480
180b0ae7
CH		 2481 rc = pci_alloc_irq_vectors(pdev, SKD_MAX_MSIX_COUNT, SKD_MAX_MSIX_COUNT,
2482 PCI_IRQ_MSIX);
2483 if (rc < 0) {
f98806d6 2484 dev_err(&skdev->pdev->dev, "failed to enable MSI-X %d\n", rc);
3bc8492f 2485 goto out;
e67f86b3 2486 }
46817769 2487
180b0ae7
CH		 2488 skdev->msix_entries = kcalloc(SKD_MAX_MSIX_COUNT,
2489 sizeof(struct skd_msix_entry), GFP_KERNEL);
e67f86b3
AB		 2490 if (!skdev->msix_entries) {
2491 rc = -ENOMEM;
f98806d6 2492 dev_err(&skdev->pdev->dev, "msix table allocation error\n");
3bc8492f 2493 goto out;
e67f86b3
AB		 2494 }
2495
e67f86b3 2496 /* Enable MSI-X vectors for the base queue */
180b0ae7
CH		 2497 for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) {
2498 struct skd_msix_entry *qentry = &skdev->msix_entries[i];
2499
e67f86b3
AB		 2500 snprintf(qentry->isr_name, sizeof(qentry->isr_name),
2501 "%s%d-msix %s", DRV_NAME, skdev->devno,
2502 msix_entries[i].name);
180b0ae7
CH		 2503
2504 rc = devm_request_irq(&skdev->pdev->dev,
2505 pci_irq_vector(skdev->pdev, i),
2506 msix_entries[i].handler, 0,
2507 qentry->isr_name, skdev);
e67f86b3 2508 if (rc) {
f98806d6
BVA		 2509 dev_err(&skdev->pdev->dev,
2510 "Unable to register(%d) MSI-X handler %d: %s\n",
2511 rc, i, qentry->isr_name);
e67f86b3 2512 goto msix_out;
e67f86b3
AB		 2513 }
2514 }
180b0ae7 2515
f98806d6
BVA		 2516 dev_dbg(&skdev->pdev->dev, "%d msix irq(s) enabled\n",
2517 SKD_MAX_MSIX_COUNT);
e67f86b3
AB		 2518 return 0;
2519
2520msix_out:
180b0ae7
CH		 2521 while (--i >= 0)
2522 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i), skdev);
3bc8492f 2523out:
180b0ae7
CH		 2524 kfree(skdev->msix_entries);
2525 skdev->msix_entries = NULL;
e67f86b3
AB		 2526 return rc;
2527}
2528
2529static int skd_acquire_irq(struct skd_device *skdev)
2530{
180b0ae7
CH		 2531 struct pci_dev *pdev = skdev->pdev;
2532 unsigned int irq_flag = PCI_IRQ_LEGACY;
e67f86b3 2533 int rc;
e67f86b3 2534
180b0ae7 2535 if (skd_isr_type == SKD_IRQ_MSIX) {
e67f86b3
AB		 2536 rc = skd_acquire_msix(skdev);
2537 if (!rc)
180b0ae7
CH		 2538 return 0;
2539
f98806d6
BVA		 2540 dev_err(&skdev->pdev->dev,
2541 "failed to enable MSI-X, re-trying with MSI %d\n", rc);
e67f86b3 2542 }
180b0ae7
CH		 2543
2544 snprintf(skdev->isr_name, sizeof(skdev->isr_name), "%s%d", DRV_NAME,
2545 skdev->devno);
2546
2547 if (skd_isr_type != SKD_IRQ_LEGACY)
2548 irq_flag |= PCI_IRQ_MSI;
2549 rc = pci_alloc_irq_vectors(pdev, 1, 1, irq_flag);
2550 if (rc < 0) {
f98806d6
BVA		 2551 dev_err(&skdev->pdev->dev,
2552 "failed to allocate the MSI interrupt %d\n", rc);
180b0ae7
CH		 2553 return rc;
2554 }
2555
2556 rc = devm_request_irq(&pdev->dev, pdev->irq, skd_isr,
2557 pdev->msi_enabled ? 0 : IRQF_SHARED,
2558 skdev->isr_name, skdev);
2559 if (rc) {
2560 pci_free_irq_vectors(pdev);
f98806d6
BVA		 2561 dev_err(&skdev->pdev->dev, "failed to allocate interrupt %d\n",
2562 rc);
180b0ae7
CH		 2563 return rc;
2564 }
2565
2566 return 0;
e67f86b3
AB		 2567}
2568
2569static void skd_release_irq(struct skd_device *skdev)
2570{
180b0ae7
CH		 2571 struct pci_dev *pdev = skdev->pdev;
2572
2573 if (skdev->msix_entries) {
2574 int i;
2575
2576 for (i = 0; i < SKD_MAX_MSIX_COUNT; i++) {
2577 devm_free_irq(&pdev->dev, pci_irq_vector(pdev, i),
2578 skdev);
2579 }
2580
2581 kfree(skdev->msix_entries);
2582 skdev->msix_entries = NULL;
2583 } else {
2584 devm_free_irq(&pdev->dev, pdev->irq, skdev);
e67f86b3 2585 }
180b0ae7
CH		 2586
2587 pci_free_irq_vectors(pdev);
e67f86b3
AB		 2588}
2589
2590/*
2591 *****************************************************************************
2592 * CONSTRUCT
2593 *****************************************************************************
2594 */
2595
a3db102d
BVA		 2596static void *skd_alloc_dma(struct skd_device *skdev, struct kmem_cache *s,
2597 dma_addr_t *dma_handle, gfp_t gfp,
2598 enum dma_data_direction dir)
2599{
2600 struct device *dev = &skdev->pdev->dev;
2601 void *buf;
2602
2603 buf = kmem_cache_alloc(s, gfp);
2604 if (!buf)
2605 return NULL;
2606 *dma_handle = dma_map_single(dev, buf, s->size, dir);
2607 if (dma_mapping_error(dev, *dma_handle)) {
09aa97c7 2608 kmem_cache_free(s, buf);
a3db102d
BVA		 2609 buf = NULL;
2610 }
2611 return buf;
2612}
2613
2614static void skd_free_dma(struct skd_device *skdev, struct kmem_cache *s,
2615 void *vaddr, dma_addr_t dma_handle,
2616 enum dma_data_direction dir)
2617{
2618 if (!vaddr)
2619 return;
2620
2621 dma_unmap_single(&skdev->pdev->dev, dma_handle, s->size, dir);
2622 kmem_cache_free(s, vaddr);
2623}
2624
e67f86b3
AB		 2625static int skd_cons_skcomp(struct skd_device *skdev)
2626{
2627 int rc = 0;
2628 struct fit_completion_entry_v1 *skcomp;
e67f86b3 2629
f98806d6 2630 dev_dbg(&skdev->pdev->dev,
6f7c7675
BVA		 2631 "comp pci_alloc, total bytes %zd entries %d\n",
2632 SKD_SKCOMP_SIZE, SKD_N_COMPLETION_ENTRY);
e67f86b3 2633
6f7c7675 2634 skcomp = pci_zalloc_consistent(skdev->pdev, SKD_SKCOMP_SIZE,
a5bbf616 2635 &skdev->cq_dma_address);
e67f86b3
AB		 2636
2637 if (skcomp == NULL) {
2638 rc = -ENOMEM;
2639 goto err_out;
2640 }
2641
e67f86b3
AB		 2642 skdev->skcomp_table = skcomp;
2643 skdev->skerr_table = (struct fit_comp_error_info *)((char *)skcomp +
2644 sizeof(*skcomp) *
2645 SKD_N_COMPLETION_ENTRY);
2646
2647err_out:
2648 return rc;
2649}
2650
2651static int skd_cons_skmsg(struct skd_device *skdev)
2652{
2653 int rc = 0;
2654 u32 i;
2655
f98806d6 2656 dev_dbg(&skdev->pdev->dev,
01433d0d 2657 "skmsg_table kcalloc, struct %lu, count %u total %lu\n",
f98806d6
BVA		 2658 sizeof(struct skd_fitmsg_context), skdev->num_fitmsg_context,
2659 sizeof(struct skd_fitmsg_context) * skdev->num_fitmsg_context);
e67f86b3 2660
01433d0d
BVA		 2661 skdev->skmsg_table = kcalloc(skdev->num_fitmsg_context,
2662 sizeof(struct skd_fitmsg_context),
2663 GFP_KERNEL);
e67f86b3
AB		 2664 if (skdev->skmsg_table == NULL) {
2665 rc = -ENOMEM;
2666 goto err_out;
2667 }
2668
2669 for (i = 0; i < skdev->num_fitmsg_context; i++) {
2670 struct skd_fitmsg_context *skmsg;
2671
2672 skmsg = &skdev->skmsg_table[i];
2673
2674 skmsg->id = i + SKD_ID_FIT_MSG;
2675
e67f86b3 2676 skmsg->msg_buf = pci_alloc_consistent(skdev->pdev,
6507f436 2677 SKD_N_FITMSG_BYTES,
e67f86b3
AB		 2678 &skmsg->mb_dma_address);
2679
2680 if (skmsg->msg_buf == NULL) {
2681 rc = -ENOMEM;
2682 goto err_out;
2683 }
2684
6507f436
BVA		 2685 WARN(((uintptr_t)skmsg->msg_buf | skmsg->mb_dma_address) &
2686 (FIT_QCMD_ALIGN - 1),
2687 "not aligned: msg_buf %p mb_dma_address %#llx\n",
2688 skmsg->msg_buf, skmsg->mb_dma_address);
e67f86b3 2689 memset(skmsg->msg_buf, 0, SKD_N_FITMSG_BYTES);
e67f86b3
AB		 2690 }
2691
e67f86b3
AB		 2692err_out:
2693 return rc;
2694}
2695
542d7b00
BZ		 2696static struct fit_sg_descriptor *skd_cons_sg_list(struct skd_device *skdev,
2697 u32 n_sg,
2698 dma_addr_t *ret_dma_addr)
2699{
2700 struct fit_sg_descriptor *sg_list;
542d7b00 2701
a3db102d
BVA		 2702 sg_list = skd_alloc_dma(skdev, skdev->sglist_cache, ret_dma_addr,
2703 GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE);
542d7b00
BZ		 2704
2705 if (sg_list != NULL) {
2706 uint64_t dma_address = *ret_dma_addr;
2707 u32 i;
2708
542d7b00
BZ		 2709 for (i = 0; i < n_sg - 1; i++) {
2710 uint64_t ndp_off;
2711 ndp_off = (i + 1) * sizeof(struct fit_sg_descriptor);
2712
2713 sg_list[i].next_desc_ptr = dma_address + ndp_off;
2714 }
2715 sg_list[i].next_desc_ptr = 0LL;
2716 }
2717
2718 return sg_list;
2719}
2720
5d003240 2721static void skd_free_sg_list(struct skd_device *skdev,
a3db102d 2722 struct fit_sg_descriptor *sg_list,
5d003240
BVA		 2723 dma_addr_t dma_addr)
2724{
5d003240
BVA		 2725 if (WARN_ON_ONCE(!sg_list))
2726 return;
2727
a3db102d
BVA		 2728 skd_free_dma(skdev, skdev->sglist_cache, sg_list, dma_addr,
2729 DMA_TO_DEVICE);
5d003240
BVA		 2730}
2731
ca33dd92
BVA		 2732static int skd_init_request(struct blk_mq_tag_set *set, struct request *rq,
2733 unsigned int hctx_idx, unsigned int numa_node)
e67f86b3 2734{
ca33dd92 2735 struct skd_device *skdev = set->driver_data;
e7278a8b 2736 struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq);
e67f86b3 2737
e7278a8b
BVA		 2738 skreq->state = SKD_REQ_STATE_IDLE;
2739 skreq->sg = (void *)(skreq + 1);
2740 sg_init_table(skreq->sg, skd_sgs_per_request);
2741 skreq->sksg_list = skd_cons_sg_list(skdev, skd_sgs_per_request,
2742 &skreq->sksg_dma_address);
e67f86b3 2743
e7278a8b
BVA		 2744 return skreq->sksg_list ? 0 : -ENOMEM;
2745}
e67f86b3 2746
ca33dd92
BVA		 2747static void skd_exit_request(struct blk_mq_tag_set *set, struct request *rq,
2748 unsigned int hctx_idx)
e7278a8b 2749{
ca33dd92 2750 struct skd_device *skdev = set->driver_data;
e7278a8b 2751 struct skd_request_context *skreq = blk_mq_rq_to_pdu(rq);
e67f86b3 2752
a3db102d 2753 skd_free_sg_list(skdev, skreq->sksg_list, skreq->sksg_dma_address);
e67f86b3
AB		 2754}
2755
e67f86b3
AB		 2756static int skd_cons_sksb(struct skd_device *skdev)
2757{
2758 int rc = 0;
2759 struct skd_special_context *skspcl;
e67f86b3
AB		 2760
2761 skspcl = &skdev->internal_skspcl;
2762
2763 skspcl->req.id = 0 + SKD_ID_INTERNAL;
2764 skspcl->req.state = SKD_REQ_STATE_IDLE;
2765
a3db102d
BVA		 2766 skspcl->data_buf = skd_alloc_dma(skdev, skdev->databuf_cache,
2767 &skspcl->db_dma_address,
2768 GFP_DMA | __GFP_ZERO,
2769 DMA_BIDIRECTIONAL);
e67f86b3
AB		 2770 if (skspcl->data_buf == NULL) {
2771 rc = -ENOMEM;
2772 goto err_out;
2773 }
2774
a3db102d
BVA		 2775 skspcl->msg_buf = skd_alloc_dma(skdev, skdev->msgbuf_cache,
2776 &skspcl->mb_dma_address,
2777 GFP_DMA | __GFP_ZERO, DMA_TO_DEVICE);
e67f86b3
AB		 2778 if (skspcl->msg_buf == NULL) {
2779 rc = -ENOMEM;
2780 goto err_out;
2781 }
2782
e67f86b3
AB		 2783 skspcl->req.sksg_list = skd_cons_sg_list(skdev, 1,
2784 &skspcl->req.sksg_dma_address);
2785 if (skspcl->req.sksg_list == NULL) {
2786 rc = -ENOMEM;
2787 goto err_out;
2788 }
2789
2790 if (!skd_format_internal_skspcl(skdev)) {
2791 rc = -EINVAL;
2792 goto err_out;
2793 }
2794
2795err_out:
2796 return rc;
2797}
2798
ca33dd92
BVA		 2799static const struct blk_mq_ops skd_mq_ops = {
2800 .queue_rq = skd_mq_queue_rq,
296cb94c 2801 .complete = skd_complete_rq,
f2fe4459 2802 .timeout = skd_timed_out,
ca33dd92
BVA		 2803 .init_request = skd_init_request,
2804 .exit_request = skd_exit_request,
2805};
2806
e67f86b3
AB		 2807static int skd_cons_disk(struct skd_device *skdev)
2808{
2809 int rc = 0;
2810 struct gendisk *disk;
2811 struct request_queue *q;
2812 unsigned long flags;
2813
2814 disk = alloc_disk(SKD_MINORS_PER_DEVICE);
2815 if (!disk) {
2816 rc = -ENOMEM;
2817 goto err_out;
2818 }
2819
2820 skdev->disk = disk;
2821 sprintf(disk->disk_name, DRV_NAME "%u", skdev->devno);
2822
2823 disk->major = skdev->major;
2824 disk->first_minor = skdev->devno * SKD_MINORS_PER_DEVICE;
2825 disk->fops = &skd_blockdev_ops;
2826 disk->private_data = skdev;
2827
ca33dd92
BVA		 2828 memset(&skdev->tag_set, 0, sizeof(skdev->tag_set));
2829 skdev->tag_set.ops = &skd_mq_ops;
2830 skdev->tag_set.nr_hw_queues = 1;
2831 skdev->tag_set.queue_depth = skd_max_queue_depth;
2832 skdev->tag_set.cmd_size = sizeof(struct skd_request_context) +
2833 skdev->sgs_per_request * sizeof(struct scatterlist);
2834 skdev->tag_set.numa_node = NUMA_NO_NODE;
2835 skdev->tag_set.flags = BLK_MQ_F_SHOULD_MERGE |
2836 BLK_MQ_F_SG_MERGE |
2837 BLK_ALLOC_POLICY_TO_MQ_FLAG(BLK_TAG_ALLOC_FIFO);
2838 skdev->tag_set.driver_data = skdev;
92d499d4
DC		 2839 rc = blk_mq_alloc_tag_set(&skdev->tag_set);
2840 if (rc)
2841 goto err_out;
2842 q = blk_mq_init_queue(&skdev->tag_set);
2843 if (IS_ERR(q)) {
2844 blk_mq_free_tag_set(&skdev->tag_set);
2845 rc = PTR_ERR(q);
e67f86b3
AB		 2846 goto err_out;
2847 }
e7278a8b 2848 q->queuedata = skdev;
e67f86b3
AB		 2849
2850 skdev->queue = q;
2851 disk->queue = q;
e67f86b3 2852
6975f732 2853 blk_queue_write_cache(q, true, true);
e67f86b3
AB		 2854 blk_queue_max_segments(q, skdev->sgs_per_request);
2855 blk_queue_max_hw_sectors(q, SKD_N_MAX_SECTORS);
2856
a5c5b392 2857 /* set optimal I/O size to 8KB */
e67f86b3
AB		 2858 blk_queue_io_opt(q, 8192);
2859
e67f86b3 2860 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, q);
b277da0a 2861 queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, q);
e67f86b3 2862
a74d5b76 2863 blk_queue_rq_timeout(q, 8 * HZ);
a74d5b76 2864
e67f86b3 2865 spin_lock_irqsave(&skdev->lock, flags);
f98806d6 2866 dev_dbg(&skdev->pdev->dev, "stopping queue\n");
ca33dd92 2867 blk_mq_stop_hw_queues(skdev->queue);
e67f86b3
AB		 2868 spin_unlock_irqrestore(&skdev->lock, flags);
2869
2870err_out:
2871 return rc;
2872}
2873
542d7b00
BZ		 2874#define SKD_N_DEV_TABLE 16u
2875static u32 skd_next_devno;
e67f86b3 2876
542d7b00 2877static struct skd_device *skd_construct(struct pci_dev *pdev)
e67f86b3 2878{
542d7b00
BZ		 2879 struct skd_device *skdev;
2880 int blk_major = skd_major;
a3db102d 2881 size_t size;
542d7b00 2882 int rc;
e67f86b3 2883
542d7b00 2884 skdev = kzalloc(sizeof(*skdev), GFP_KERNEL);
e67f86b3 2885
542d7b00 2886 if (!skdev) {
f98806d6 2887 dev_err(&pdev->dev, "memory alloc failure\n");
542d7b00
BZ		 2888 return NULL;
2889 }
e67f86b3 2890
542d7b00
BZ		 2891 skdev->state = SKD_DRVR_STATE_LOAD;
2892 skdev->pdev = pdev;
2893 skdev->devno = skd_next_devno++;
2894 skdev->major = blk_major;
542d7b00 2895 skdev->dev_max_queue_depth = 0;
e67f86b3 2896
542d7b00
BZ		 2897 skdev->num_req_context = skd_max_queue_depth;
2898 skdev->num_fitmsg_context = skd_max_queue_depth;
542d7b00
BZ		 2899 skdev->cur_max_queue_depth = 1;
2900 skdev->queue_low_water_mark = 1;
2901 skdev->proto_ver = 99;
2902 skdev->sgs_per_request = skd_sgs_per_request;
2903 skdev->dbg_level = skd_dbg_level;
e67f86b3 2904
542d7b00
BZ		 2905 spin_lock_init(&skdev->lock);
2906
ca33dd92 2907 INIT_WORK(&skdev->start_queue, skd_start_queue);
542d7b00 2908 INIT_WORK(&skdev->completion_worker, skd_completion_worker);
e67f86b3 2909
a3db102d
BVA		 2910 size = max(SKD_N_FITMSG_BYTES, SKD_N_SPECIAL_FITMSG_BYTES);
2911 skdev->msgbuf_cache = kmem_cache_create("skd-msgbuf", size, 0,
2912 SLAB_HWCACHE_ALIGN, NULL);
2913 if (!skdev->msgbuf_cache)
2914 goto err_out;
2915 WARN_ONCE(kmem_cache_size(skdev->msgbuf_cache) < size,
2916 "skd-msgbuf: %d < %zd\n",
2917 kmem_cache_size(skdev->msgbuf_cache), size);
2918 size = skd_sgs_per_request * sizeof(struct fit_sg_descriptor);
2919 skdev->sglist_cache = kmem_cache_create("skd-sglist", size, 0,
2920 SLAB_HWCACHE_ALIGN, NULL);
2921 if (!skdev->sglist_cache)
2922 goto err_out;
2923 WARN_ONCE(kmem_cache_size(skdev->sglist_cache) < size,
2924 "skd-sglist: %d < %zd\n",
2925 kmem_cache_size(skdev->sglist_cache), size);
2926 size = SKD_N_INTERNAL_BYTES;
2927 skdev->databuf_cache = kmem_cache_create("skd-databuf", size, 0,
2928 SLAB_HWCACHE_ALIGN, NULL);
2929 if (!skdev->databuf_cache)
2930 goto err_out;
2931 WARN_ONCE(kmem_cache_size(skdev->databuf_cache) < size,
2932 "skd-databuf: %d < %zd\n",
2933 kmem_cache_size(skdev->databuf_cache), size);
2934
f98806d6 2935 dev_dbg(&skdev->pdev->dev, "skcomp\n");
542d7b00
BZ		 2936 rc = skd_cons_skcomp(skdev);
2937 if (rc < 0)
2938 goto err_out;
e67f86b3 2939
f98806d6 2940 dev_dbg(&skdev->pdev->dev, "skmsg\n");
542d7b00
BZ		 2941 rc = skd_cons_skmsg(skdev);
2942 if (rc < 0)
2943 goto err_out;
2944
f98806d6 2945 dev_dbg(&skdev->pdev->dev, "sksb\n");
542d7b00
BZ		 2946 rc = skd_cons_sksb(skdev);
2947 if (rc < 0)
2948 goto err_out;
2949
f98806d6 2950 dev_dbg(&skdev->pdev->dev, "disk\n");
542d7b00
BZ		 2951 rc = skd_cons_disk(skdev);
2952 if (rc < 0)
2953 goto err_out;
2954
f98806d6 2955 dev_dbg(&skdev->pdev->dev, "VICTORY\n");
542d7b00
BZ		 2956 return skdev;
2957
2958err_out:
f98806d6 2959 dev_dbg(&skdev->pdev->dev, "construct failed\n");
542d7b00
BZ		 2960 skd_destruct(skdev);
2961 return NULL;
e67f86b3
AB		 2962}
2963
542d7b00
BZ		 2964/*
2965 *****************************************************************************
2966 * DESTRUCT (FREE)
2967 *****************************************************************************
2968 */
2969
e67f86b3
AB		 2970static void skd_free_skcomp(struct skd_device *skdev)
2971{
7f13bdad
BVA		 2972 if (skdev->skcomp_table)
2973 pci_free_consistent(skdev->pdev, SKD_SKCOMP_SIZE,
e67f86b3 2974 skdev->skcomp_table, skdev->cq_dma_address);
e67f86b3
AB		 2975
2976 skdev->skcomp_table = NULL;
2977 skdev->cq_dma_address = 0;
2978}
2979
2980static void skd_free_skmsg(struct skd_device *skdev)
2981{
2982 u32 i;
2983
2984 if (skdev->skmsg_table == NULL)
2985 return;
2986
2987 for (i = 0; i < skdev->num_fitmsg_context; i++) {
2988 struct skd_fitmsg_context *skmsg;
2989
2990 skmsg = &skdev->skmsg_table[i];
2991
2992 if (skmsg->msg_buf != NULL) {
e67f86b3
AB		 2993 pci_free_consistent(skdev->pdev, SKD_N_FITMSG_BYTES,
2994 skmsg->msg_buf,
2995 skmsg->mb_dma_address);
2996 }
2997 skmsg->msg_buf = NULL;
2998 skmsg->mb_dma_address = 0;
2999 }
3000
3001 kfree(skdev->skmsg_table);
3002 skdev->skmsg_table = NULL;
3003}
3004
e67f86b3
AB		 3005static void skd_free_sksb(struct skd_device *skdev)
3006{
a3db102d 3007 struct skd_special_context *skspcl = &skdev->internal_skspcl;
e67f86b3 3008
a3db102d
BVA		 3009 skd_free_dma(skdev, skdev->databuf_cache, skspcl->data_buf,
3010 skspcl->db_dma_address, DMA_BIDIRECTIONAL);
e67f86b3
AB		 3011
3012 skspcl->data_buf = NULL;
3013 skspcl->db_dma_address = 0;
3014
a3db102d
BVA		 3015 skd_free_dma(skdev, skdev->msgbuf_cache, skspcl->msg_buf,
3016 skspcl->mb_dma_address, DMA_TO_DEVICE);
e67f86b3
AB		 3017
3018 skspcl->msg_buf = NULL;
3019 skspcl->mb_dma_address = 0;
3020
a3db102d 3021 skd_free_sg_list(skdev, skspcl->req.sksg_list,
e67f86b3
AB		 3022 skspcl->req.sksg_dma_address);
3023
3024 skspcl->req.sksg_list = NULL;
3025 skspcl->req.sksg_dma_address = 0;
3026}
3027
e67f86b3
AB		 3028static void skd_free_disk(struct skd_device *skdev)
3029{
3030 struct gendisk *disk = skdev->disk;
3031
7277cc67
BVA		 3032 if (disk && (disk->flags & GENHD_FL_UP))
3033 del_gendisk(disk);
3034
3035 if (skdev->queue) {
3036 blk_cleanup_queue(skdev->queue);
3037 skdev->queue = NULL;
4633504c
BVA		 3038 if (disk)
3039 disk->queue = NULL;
e67f86b3 3040 }
7277cc67 3041
ca33dd92
BVA		 3042 if (skdev->tag_set.tags)
3043 blk_mq_free_tag_set(&skdev->tag_set);
3044
7277cc67 3045 put_disk(disk);
e67f86b3
AB		 3046 skdev->disk = NULL;
3047}
3048
542d7b00
BZ		 3049static void skd_destruct(struct skd_device *skdev)
3050{
3051 if (skdev == NULL)
3052 return;
3053
ca33dd92
BVA		 3054 cancel_work_sync(&skdev->start_queue);
3055
f98806d6 3056 dev_dbg(&skdev->pdev->dev, "disk\n");
542d7b00
BZ		 3057 skd_free_disk(skdev);
3058
f98806d6 3059 dev_dbg(&skdev->pdev->dev, "sksb\n");
542d7b00
BZ		 3060 skd_free_sksb(skdev);
3061
f98806d6 3062 dev_dbg(&skdev->pdev->dev, "skmsg\n");
542d7b00 3063 skd_free_skmsg(skdev);
e67f86b3 3064
f98806d6 3065 dev_dbg(&skdev->pdev->dev, "skcomp\n");
542d7b00
BZ		 3066 skd_free_skcomp(skdev);
3067
a3db102d
BVA		 3068 kmem_cache_destroy(skdev->databuf_cache);
3069 kmem_cache_destroy(skdev->sglist_cache);
3070 kmem_cache_destroy(skdev->msgbuf_cache);
3071
f98806d6 3072 dev_dbg(&skdev->pdev->dev, "skdev\n");
542d7b00
BZ		 3073 kfree(skdev);
3074}
e67f86b3
AB		 3075
3076/*
3077 *****************************************************************************
3078 * BLOCK DEVICE (BDEV) GLUE
3079 *****************************************************************************
3080 */
3081
3082static int skd_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
3083{
3084 struct skd_device *skdev;
3085 u64 capacity;
3086
3087 skdev = bdev->bd_disk->private_data;
3088
f98806d6
BVA		 3089 dev_dbg(&skdev->pdev->dev, "%s: CMD[%s] getgeo device\n",
3090 bdev->bd_disk->disk_name, current->comm);
e67f86b3
AB		 3091
3092 if (skdev->read_cap_is_valid) {
3093 capacity = get_capacity(skdev->disk);
3094 geo->heads = 64;
3095 geo->sectors = 255;
3096 geo->cylinders = (capacity) / (255 * 64);
3097
3098 return 0;
3099 }
3100 return -EIO;
3101}
3102
0d52c756 3103static int skd_bdev_attach(struct device *parent, struct skd_device *skdev)
e67f86b3 3104{
f98806d6 3105 dev_dbg(&skdev->pdev->dev, "add_disk\n");
0d52c756 3106 device_add_disk(parent, skdev->disk);
e67f86b3
AB		 3107 return 0;
3108}
3109
3110static const struct block_device_operations skd_blockdev_ops = {
3111 .owner = THIS_MODULE,
e67f86b3
AB		 3112 .getgeo = skd_bdev_getgeo,
3113};
3114
e67f86b3
AB		 3115/*
3116 *****************************************************************************
3117 * PCIe DRIVER GLUE
3118 *****************************************************************************
3119 */
3120
9baa3c34 3121static const struct pci_device_id skd_pci_tbl[] = {
e67f86b3
AB		 3122 { PCI_VENDOR_ID_STEC, PCI_DEVICE_ID_S1120,
3123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
3124 { 0 } /* terminate list */
3125};
3126
3127MODULE_DEVICE_TABLE(pci, skd_pci_tbl);
3128
3129static char *skd_pci_info(struct skd_device *skdev, char *str)
3130{
3131 int pcie_reg;
3132
3133 strcpy(str, "PCIe (");
3134 pcie_reg = pci_find_capability(skdev->pdev, PCI_CAP_ID_EXP);
3135
3136 if (pcie_reg) {
3137
3138 char lwstr[6];
3139 uint16_t pcie_lstat, lspeed, lwidth;
3140
3141 pcie_reg += 0x12;
3142 pci_read_config_word(skdev->pdev, pcie_reg, &pcie_lstat);
3143 lspeed = pcie_lstat & (0xF);
3144 lwidth = (pcie_lstat & 0x3F0) >> 4;
3145
3146 if (lspeed == 1)
3147 strcat(str, "2.5GT/s ");
3148 else if (lspeed == 2)
3149 strcat(str, "5.0GT/s ");
3150 else
3151 strcat(str, "<unknown> ");
3152 snprintf(lwstr, sizeof(lwstr), "%dX)", lwidth);
3153 strcat(str, lwstr);
3154 }
3155 return str;
3156}
3157
3158static int skd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3159{
3160 int i;
3161 int rc = 0;
3162 char pci_str[32];
3163 struct skd_device *skdev;
3164
bb9f7dd3
BVA		 3165 dev_dbg(&pdev->dev, "vendor=%04X device=%04x\n", pdev->vendor,
3166 pdev->device);
e67f86b3
AB		 3167
3168 rc = pci_enable_device(pdev);
3169 if (rc)
3170 return rc;
3171 rc = pci_request_regions(pdev, DRV_NAME);
3172 if (rc)
3173 goto err_out;
3174 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3175 if (!rc) {
3176 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
f98806d6
BVA		 3177 dev_err(&pdev->dev, "consistent DMA mask error %d\n",
3178 rc);
e67f86b3
AB		 3179 }
3180 } else {
f98806d6 3181 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
e67f86b3 3182 if (rc) {
f98806d6 3183 dev_err(&pdev->dev, "DMA mask error %d\n", rc);
e67f86b3
AB		 3184 goto err_out_regions;
3185 }
3186 }
3187
b8df6647
BZ		 3188 if (!skd_major) {
3189 rc = register_blkdev(0, DRV_NAME);
3190 if (rc < 0)
3191 goto err_out_regions;
3192 BUG_ON(!rc);
3193 skd_major = rc;
3194 }
3195
e67f86b3 3196 skdev = skd_construct(pdev);
1762b57f
WY		 3197 if (skdev == NULL) {
3198 rc = -ENOMEM;
e67f86b3 3199 goto err_out_regions;
1762b57f 3200 }
e67f86b3
AB		 3201
3202 skd_pci_info(skdev, pci_str);
f98806d6 3203 dev_info(&pdev->dev, "%s 64bit\n", pci_str);
e67f86b3
AB		 3204
3205 pci_set_master(pdev);
3206 rc = pci_enable_pcie_error_reporting(pdev);
3207 if (rc) {
f98806d6
BVA		 3208 dev_err(&pdev->dev,
3209 "bad enable of PCIe error reporting rc=%d\n", rc);
e67f86b3
AB		 3210 skdev->pcie_error_reporting_is_enabled = 0;
3211 } else
3212 skdev->pcie_error_reporting_is_enabled = 1;
3213
e67f86b3 3214 pci_set_drvdata(pdev, skdev);
ebedd16d 3215
e67f86b3
AB		 3216 for (i = 0; i < SKD_MAX_BARS; i++) {
3217 skdev->mem_phys[i] = pci_resource_start(pdev, i);
3218 skdev->mem_size[i] = (u32)pci_resource_len(pdev, i);
3219 skdev->mem_map[i] = ioremap(skdev->mem_phys[i],
3220 skdev->mem_size[i]);
3221 if (!skdev->mem_map[i]) {
f98806d6
BVA		 3222 dev_err(&pdev->dev,
3223 "Unable to map adapter memory!\n");
e67f86b3
AB		 3224 rc = -ENODEV;
3225 goto err_out_iounmap;
3226 }
f98806d6
BVA		 3227 dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n",
3228 skdev->mem_map[i], (uint64_t)skdev->mem_phys[i],
3229 skdev->mem_size[i]);
e67f86b3
AB		 3230 }
3231
3232 rc = skd_acquire_irq(skdev);
3233 if (rc) {
f98806d6 3234 dev_err(&pdev->dev, "interrupt resource error %d\n", rc);
e67f86b3
AB		 3235 goto err_out_iounmap;
3236 }
3237
3238 rc = skd_start_timer(skdev);
3239 if (rc)
3240 goto err_out_timer;
3241
3242 init_waitqueue_head(&skdev->waitq);
3243
3244 skd_start_device(skdev);
3245
3246 rc = wait_event_interruptible_timeout(skdev->waitq,
3247 (skdev->gendisk_on),
3248 (SKD_START_WAIT_SECONDS * HZ));
3249 if (skdev->gendisk_on > 0) {
3250 /* device came on-line after reset */
0d52c756 3251 skd_bdev_attach(&pdev->dev, skdev);
e67f86b3
AB		 3252 rc = 0;
3253 } else {
3254 /* we timed out, something is wrong with the device,
3255 don't add the disk structure */
f98806d6
BVA		 3256 dev_err(&pdev->dev, "error: waiting for s1120 timed out %d!\n",
3257 rc);
e67f86b3
AB		 3258 /* in case of no error; we timeout with ENXIO */
3259 if (!rc)
3260 rc = -ENXIO;
3261 goto err_out_timer;
3262 }
3263
e67f86b3
AB		 3264 return rc;
3265
3266err_out_timer:
3267 skd_stop_device(skdev);
3268 skd_release_irq(skdev);
3269
3270err_out_iounmap:
3271 for (i = 0; i < SKD_MAX_BARS; i++)
3272 if (skdev->mem_map[i])
3273 iounmap(skdev->mem_map[i]);
3274
3275 if (skdev->pcie_error_reporting_is_enabled)
3276 pci_disable_pcie_error_reporting(pdev);
3277
3278 skd_destruct(skdev);
3279
3280err_out_regions:
3281 pci_release_regions(pdev);
3282
3283err_out:
3284 pci_disable_device(pdev);
3285 pci_set_drvdata(pdev, NULL);
3286 return rc;
3287}
3288
3289static void skd_pci_remove(struct pci_dev *pdev)
3290{
3291 int i;
3292 struct skd_device *skdev;
3293
3294 skdev = pci_get_drvdata(pdev);
3295 if (!skdev) {
f98806d6 3296 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3297 return;
3298 }
3299 skd_stop_device(skdev);
3300 skd_release_irq(skdev);
3301
3302 for (i = 0; i < SKD_MAX_BARS; i++)
3303 if (skdev->mem_map[i])
4854afe3 3304 iounmap(skdev->mem_map[i]);
e67f86b3
AB		 3305
3306 if (skdev->pcie_error_reporting_is_enabled)
3307 pci_disable_pcie_error_reporting(pdev);
3308
3309 skd_destruct(skdev);
3310
3311 pci_release_regions(pdev);
3312 pci_disable_device(pdev);
3313 pci_set_drvdata(pdev, NULL);
3314
3315 return;
3316}
3317
3318static int skd_pci_suspend(struct pci_dev *pdev, pm_message_t state)
3319{
3320 int i;
3321 struct skd_device *skdev;
3322
3323 skdev = pci_get_drvdata(pdev);
3324 if (!skdev) {
f98806d6 3325 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3326 return -EIO;
3327 }
3328
3329 skd_stop_device(skdev);
3330
3331 skd_release_irq(skdev);
3332
3333 for (i = 0; i < SKD_MAX_BARS; i++)
3334 if (skdev->mem_map[i])
4854afe3 3335 iounmap(skdev->mem_map[i]);
e67f86b3
AB		 3336
3337 if (skdev->pcie_error_reporting_is_enabled)
3338 pci_disable_pcie_error_reporting(pdev);
3339
3340 pci_release_regions(pdev);
3341 pci_save_state(pdev);
3342 pci_disable_device(pdev);
3343 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3344 return 0;
3345}
3346
3347static int skd_pci_resume(struct pci_dev *pdev)
3348{
3349 int i;
3350 int rc = 0;
3351 struct skd_device *skdev;
3352
3353 skdev = pci_get_drvdata(pdev);
3354 if (!skdev) {
f98806d6 3355 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3356 return -1;
3357 }
3358
3359 pci_set_power_state(pdev, PCI_D0);
3360 pci_enable_wake(pdev, PCI_D0, 0);
3361 pci_restore_state(pdev);
3362
3363 rc = pci_enable_device(pdev);
3364 if (rc)
3365 return rc;
3366 rc = pci_request_regions(pdev, DRV_NAME);
3367 if (rc)
3368 goto err_out;
3369 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3370 if (!rc) {
3371 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
3372
f98806d6
BVA		 3373 dev_err(&pdev->dev, "consistent DMA mask error %d\n",
3374 rc);
e67f86b3
AB		 3375 }
3376 } else {
3377 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3378 if (rc) {
3379
f98806d6 3380 dev_err(&pdev->dev, "DMA mask error %d\n", rc);
e67f86b3
AB		 3381 goto err_out_regions;
3382 }
3383 }
3384
3385 pci_set_master(pdev);
3386 rc = pci_enable_pcie_error_reporting(pdev);
3387 if (rc) {
f98806d6
BVA		 3388 dev_err(&pdev->dev,
3389 "bad enable of PCIe error reporting rc=%d\n", rc);
e67f86b3
AB		 3390 skdev->pcie_error_reporting_is_enabled = 0;
3391 } else
3392 skdev->pcie_error_reporting_is_enabled = 1;
3393
3394 for (i = 0; i < SKD_MAX_BARS; i++) {
3395
3396 skdev->mem_phys[i] = pci_resource_start(pdev, i);
3397 skdev->mem_size[i] = (u32)pci_resource_len(pdev, i);
3398 skdev->mem_map[i] = ioremap(skdev->mem_phys[i],
3399 skdev->mem_size[i]);
3400 if (!skdev->mem_map[i]) {
f98806d6 3401 dev_err(&pdev->dev, "Unable to map adapter memory!\n");
e67f86b3
AB		 3402 rc = -ENODEV;
3403 goto err_out_iounmap;
3404 }
f98806d6
BVA		 3405 dev_dbg(&pdev->dev, "mem_map=%p, phyd=%016llx, size=%d\n",
3406 skdev->mem_map[i], (uint64_t)skdev->mem_phys[i],
3407 skdev->mem_size[i]);
e67f86b3
AB		 3408 }
3409 rc = skd_acquire_irq(skdev);
3410 if (rc) {
f98806d6 3411 dev_err(&pdev->dev, "interrupt resource error %d\n", rc);
e67f86b3
AB		 3412 goto err_out_iounmap;
3413 }
3414
3415 rc = skd_start_timer(skdev);
3416 if (rc)
3417 goto err_out_timer;
3418
3419 init_waitqueue_head(&skdev->waitq);
3420
3421 skd_start_device(skdev);
3422
3423 return rc;
3424
3425err_out_timer:
3426 skd_stop_device(skdev);
3427 skd_release_irq(skdev);
3428
3429err_out_iounmap:
3430 for (i = 0; i < SKD_MAX_BARS; i++)
3431 if (skdev->mem_map[i])
3432 iounmap(skdev->mem_map[i]);
3433
3434 if (skdev->pcie_error_reporting_is_enabled)
3435 pci_disable_pcie_error_reporting(pdev);
3436
3437err_out_regions:
3438 pci_release_regions(pdev);
3439
3440err_out:
3441 pci_disable_device(pdev);
3442 return rc;
3443}
3444
3445static void skd_pci_shutdown(struct pci_dev *pdev)
3446{
3447 struct skd_device *skdev;
3448
f98806d6 3449 dev_err(&pdev->dev, "%s called\n", __func__);
e67f86b3
AB		 3450
3451 skdev = pci_get_drvdata(pdev);
3452 if (!skdev) {
f98806d6 3453 dev_err(&pdev->dev, "no device data for PCI\n");
e67f86b3
AB		 3454 return;
3455 }
3456
f98806d6 3457 dev_err(&pdev->dev, "calling stop\n");
e67f86b3
AB		 3458 skd_stop_device(skdev);
3459}
3460
3461static struct pci_driver skd_driver = {
3462 .name = DRV_NAME,
3463 .id_table = skd_pci_tbl,
3464 .probe = skd_pci_probe,
3465 .remove = skd_pci_remove,
3466 .suspend = skd_pci_suspend,
3467 .resume = skd_pci_resume,
3468 .shutdown = skd_pci_shutdown,
3469};
3470
3471/*
3472 *****************************************************************************
3473 * LOGGING SUPPORT
3474 *****************************************************************************
3475 */
3476
e67f86b3
AB		 3477const char *skd_drive_state_to_str(int state)
3478{
3479 switch (state) {
3480 case FIT_SR_DRIVE_OFFLINE:
3481 return "OFFLINE";
3482 case FIT_SR_DRIVE_INIT:
3483 return "INIT";
3484 case FIT_SR_DRIVE_ONLINE:
3485 return "ONLINE";
3486 case FIT_SR_DRIVE_BUSY:
3487 return "BUSY";
3488 case FIT_SR_DRIVE_FAULT:
3489 return "FAULT";
3490 case FIT_SR_DRIVE_DEGRADED:
3491 return "DEGRADED";
3492 case FIT_SR_PCIE_LINK_DOWN:
3493 return "INK_DOWN";
3494 case FIT_SR_DRIVE_SOFT_RESET:
3495 return "SOFT_RESET";
3496 case FIT_SR_DRIVE_NEED_FW_DOWNLOAD:
3497 return "NEED_FW";
3498 case FIT_SR_DRIVE_INIT_FAULT:
3499 return "INIT_FAULT";
3500 case FIT_SR_DRIVE_BUSY_SANITIZE:
3501 return "BUSY_SANITIZE";
3502 case FIT_SR_DRIVE_BUSY_ERASE:
3503 return "BUSY_ERASE";
3504 case FIT_SR_DRIVE_FW_BOOTING:
3505 return "FW_BOOTING";
3506 default:
3507 return "???";
3508 }
3509}
3510
3511const char *skd_skdev_state_to_str(enum skd_drvr_state state)
3512{
3513 switch (state) {
3514 case SKD_DRVR_STATE_LOAD:
3515 return "LOAD";
3516 case SKD_DRVR_STATE_IDLE:
3517 return "IDLE";
3518 case SKD_DRVR_STATE_BUSY:
3519 return "BUSY";
3520 case SKD_DRVR_STATE_STARTING:
3521 return "STARTING";
3522 case SKD_DRVR_STATE_ONLINE:
3523 return "ONLINE";
3524 case SKD_DRVR_STATE_PAUSING:
3525 return "PAUSING";
3526 case SKD_DRVR_STATE_PAUSED:
3527 return "PAUSED";
e67f86b3
AB		 3528 case SKD_DRVR_STATE_RESTARTING:
3529 return "RESTARTING";
3530 case SKD_DRVR_STATE_RESUMING:
3531 return "RESUMING";
3532 case SKD_DRVR_STATE_STOPPING:
3533 return "STOPPING";
3534 case SKD_DRVR_STATE_SYNCING:
3535 return "SYNCING";
3536 case SKD_DRVR_STATE_FAULT:
3537 return "FAULT";
3538 case SKD_DRVR_STATE_DISAPPEARED:
3539 return "DISAPPEARED";
3540 case SKD_DRVR_STATE_BUSY_ERASE:
3541 return "BUSY_ERASE";
3542 case SKD_DRVR_STATE_BUSY_SANITIZE:
3543 return "BUSY_SANITIZE";
3544 case SKD_DRVR_STATE_BUSY_IMMINENT:
3545 return "BUSY_IMMINENT";
3546 case SKD_DRVR_STATE_WAIT_BOOT:
3547 return "WAIT_BOOT";
3548
3549 default:
3550 return "???";
3551 }
3552}
3553
a26ba7fa 3554static const char *skd_skreq_state_to_str(enum skd_req_state state)
e67f86b3
AB		 3555{
3556 switch (state) {
3557 case SKD_REQ_STATE_IDLE:
3558 return "IDLE";
3559 case SKD_REQ_STATE_SETUP:
3560 return "SETUP";
3561 case SKD_REQ_STATE_BUSY:
3562 return "BUSY";
3563 case SKD_REQ_STATE_COMPLETED:
3564 return "COMPLETED";
3565 case SKD_REQ_STATE_TIMEOUT:
3566 return "TIMEOUT";
e67f86b3
AB		 3567 default:
3568 return "???";
3569 }
3570}
3571
3572static void skd_log_skdev(struct skd_device *skdev, const char *event)
3573{
f98806d6
BVA		 3574 dev_dbg(&skdev->pdev->dev, "skdev=%p event='%s'\n", skdev, event);
3575 dev_dbg(&skdev->pdev->dev, " drive_state=%s(%d) driver_state=%s(%d)\n",
3576 skd_drive_state_to_str(skdev->drive_state), skdev->drive_state,
3577 skd_skdev_state_to_str(skdev->state), skdev->state);
3578 dev_dbg(&skdev->pdev->dev, " busy=%d limit=%d dev=%d lowat=%d\n",
d4d0f5fc 3579 skd_in_flight(skdev), skdev->cur_max_queue_depth,
f98806d6 3580 skdev->dev_max_queue_depth, skdev->queue_low_water_mark);
a74d5b76
BVA		 3581 dev_dbg(&skdev->pdev->dev, " cycle=%d cycle_ix=%d\n",
3582 skdev->skcomp_cycle, skdev->skcomp_ix);
e67f86b3
AB		 3583}
3584
e67f86b3
AB		 3585static void skd_log_skreq(struct skd_device *skdev,
3586 struct skd_request_context *skreq, const char *event)
3587{
e7278a8b
BVA		 3588 struct request *req = blk_mq_rq_from_pdu(skreq);
3589 u32 lba = blk_rq_pos(req);
3590 u32 count = blk_rq_sectors(req);
3591
f98806d6
BVA		 3592 dev_dbg(&skdev->pdev->dev, "skreq=%p event='%s'\n", skreq, event);
3593 dev_dbg(&skdev->pdev->dev, " state=%s(%d) id=0x%04x fitmsg=0x%04x\n",
3594 skd_skreq_state_to_str(skreq->state), skreq->state, skreq->id,
3595 skreq->fitmsg_id);
a74d5b76
BVA		 3596 dev_dbg(&skdev->pdev->dev, " sg_dir=%d n_sg=%d\n",
3597 skreq->data_dir, skreq->n_sg);
ca33dd92 3598
e7278a8b
BVA		 3599 dev_dbg(&skdev->pdev->dev,
3600 "req=%p lba=%u(0x%x) count=%u(0x%x) dir=%d\n", req, lba, lba,
3601 count, count, (int)rq_data_dir(req));
e67f86b3
AB		 3602}
3603
3604/*
3605 *****************************************************************************
3606 * MODULE GLUE
3607 *****************************************************************************
3608 */
3609
3610static int __init skd_init(void)
3611{
16a70534
BVA		 3612 BUILD_BUG_ON(sizeof(struct fit_completion_entry_v1) != 8);
3613 BUILD_BUG_ON(sizeof(struct fit_comp_error_info) != 32);
3614 BUILD_BUG_ON(sizeof(struct skd_command_header) != 16);
3615 BUILD_BUG_ON(sizeof(struct skd_scsi_request) != 32);
3616 BUILD_BUG_ON(sizeof(struct driver_inquiry_data) != 44);
d891fe60
BVA		 3617 BUILD_BUG_ON(offsetof(struct skd_msg_buf, fmh) != 0);
3618 BUILD_BUG_ON(offsetof(struct skd_msg_buf, scsi) != 64);
3619 BUILD_BUG_ON(sizeof(struct skd_msg_buf) != SKD_N_FITMSG_BYTES);
2da7b403 3620
e67f86b3
AB		 3621 switch (skd_isr_type) {
3622 case SKD_IRQ_LEGACY:
3623 case SKD_IRQ_MSI:
3624 case SKD_IRQ_MSIX:
3625 break;
3626 default:
fbed149a 3627 pr_err(PFX "skd_isr_type %d invalid, re-set to %d\n",
e67f86b3
AB		 3628 skd_isr_type, SKD_IRQ_DEFAULT);
3629 skd_isr_type = SKD_IRQ_DEFAULT;
3630 }
3631
fbed149a
BZ		 3632 if (skd_max_queue_depth < 1 ||
3633 skd_max_queue_depth > SKD_MAX_QUEUE_DEPTH) {
3634 pr_err(PFX "skd_max_queue_depth %d invalid, re-set to %d\n",
e67f86b3
AB		 3635 skd_max_queue_depth, SKD_MAX_QUEUE_DEPTH_DEFAULT);
3636 skd_max_queue_depth = SKD_MAX_QUEUE_DEPTH_DEFAULT;
3637 }
3638
2da7b403
BVA		 3639 if (skd_max_req_per_msg < 1 ||
3640 skd_max_req_per_msg > SKD_MAX_REQ_PER_MSG) {
fbed149a 3641 pr_err(PFX "skd_max_req_per_msg %d invalid, re-set to %d\n",
e67f86b3
AB		 3642 skd_max_req_per_msg, SKD_MAX_REQ_PER_MSG_DEFAULT);
3643 skd_max_req_per_msg = SKD_MAX_REQ_PER_MSG_DEFAULT;
3644 }
3645
3646 if (skd_sgs_per_request < 1 || skd_sgs_per_request > 4096) {
fbed149a 3647 pr_err(PFX "skd_sg_per_request %d invalid, re-set to %d\n",
e67f86b3
AB		 3648 skd_sgs_per_request, SKD_N_SG_PER_REQ_DEFAULT);
3649 skd_sgs_per_request = SKD_N_SG_PER_REQ_DEFAULT;
3650 }
3651
3652 if (skd_dbg_level < 0 || skd_dbg_level > 2) {
fbed149a 3653 pr_err(PFX "skd_dbg_level %d invalid, re-set to %d\n",
e67f86b3
AB		 3654 skd_dbg_level, 0);
3655 skd_dbg_level = 0;
3656 }
3657
3658 if (skd_isr_comp_limit < 0) {
fbed149a 3659 pr_err(PFX "skd_isr_comp_limit %d invalid, set to %d\n",
e67f86b3
AB		 3660 skd_isr_comp_limit, 0);
3661 skd_isr_comp_limit = 0;
3662 }
3663
b8df6647 3664 return pci_register_driver(&skd_driver);
e67f86b3
AB		 3665}
3666
3667static void __exit skd_exit(void)
3668{
e67f86b3 3669 pci_unregister_driver(&skd_driver);
b8df6647
BZ		 3670
3671 if (skd_major)
3672 unregister_blkdev(skd_major, DRV_NAME);
e67f86b3
AB		 3673}
3674
e67f86b3
AB		 3675module_init(skd_init);
3676module_exit(skd_exit);
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