[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / gvt / gvt.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 *
 * Authors:
 *    Kevin Tian <kevin.tian@intel.com>
 *    Eddie Dong <eddie.dong@intel.com>
 *
 * Contributors:
 *    Niu Bing <bing.niu@intel.com>
 *    Zhi Wang <zhi.a.wang@intel.com>
 *
 */

#ifndef _GVT_H_
#define _GVT_H_

#include "debug.h"
#include "hypercall.h"
#include "mmio.h"
#include "reg.h"
#include "interrupt.h"
#include "gtt.h"
#include "display.h"
#include "edid.h"
#include "execlist.h"
#include "scheduler.h"
#include "sched_policy.h"
#include "render.h"
#include "cmd_parser.h"

#define GVT_MAX_VGPU 8

enum {
	INTEL_GVT_HYPERVISOR_XEN = 0,
	INTEL_GVT_HYPERVISOR_KVM,
};

struct intel_gvt_host {
	bool initialized;
	int hypervisor_type;
	struct intel_gvt_mpt *mpt;
};

extern struct intel_gvt_host intel_gvt_host;

/* Describe per-platform limitations. */
struct intel_gvt_device_info {
	u32 max_support_vgpus;
	u32 cfg_space_size;
	u32 mmio_size;
	u32 mmio_bar;
	unsigned long msi_cap_offset;
	u32 gtt_start_offset;
	u32 gtt_entry_size;
	u32 gtt_entry_size_shift;
	int gmadr_bytes_in_cmd;
	u32 max_surface_size;
};

/* GM resources owned by a vGPU */
struct intel_vgpu_gm {
	u64 aperture_sz;
	u64 hidden_sz;
	void *aperture_va;
	struct drm_mm_node low_gm_node;
	struct drm_mm_node high_gm_node;
};

#define INTEL_GVT_MAX_NUM_FENCES 32

/* Fences owned by a vGPU */
struct intel_vgpu_fence {
	struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
	u32 base;
	u32 size;
};

struct intel_vgpu_mmio {
	void *vreg;
	void *sreg;
	bool disable_warn_untrack;
};

#define INTEL_GVT_MAX_BAR_NUM 4

struct intel_vgpu_pci_bar {
	u64 size;
	bool tracked;
};

struct intel_vgpu_cfg_space {
	unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
};

#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)

#define INTEL_GVT_MAX_PIPE 4

struct intel_vgpu_irq {
	bool irq_warn_once[INTEL_GVT_EVENT_MAX];
	DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
		       INTEL_GVT_EVENT_MAX);
};

struct intel_vgpu_opregion {
	void *va;
	u32 gfn[INTEL_GVT_OPREGION_PAGES];
	struct page *pages[INTEL_GVT_OPREGION_PAGES];
};

#define vgpu_opregion(vgpu) (&(vgpu->opregion))

#define INTEL_GVT_MAX_PORT 5

struct intel_vgpu_display {
	struct intel_vgpu_i2c_edid i2c_edid;
	struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
	struct intel_vgpu_sbi sbi;
};

struct vgpu_sched_ctl {
	int weight;
};

struct intel_vgpu {
	struct intel_gvt *gvt;
	int id;
	unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
	bool active;
	bool pv_notified;
	bool failsafe;
	unsigned int resetting_eng;
	void *sched_data;
	struct vgpu_sched_ctl sched_ctl;

	struct intel_vgpu_fence fence;
	struct intel_vgpu_gm gm;
	struct intel_vgpu_cfg_space cfg_space;
	struct intel_vgpu_mmio mmio;
	struct intel_vgpu_irq irq;
	struct intel_vgpu_gtt gtt;
	struct intel_vgpu_opregion opregion;
	struct intel_vgpu_display display;
	struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
	struct list_head workload_q_head[I915_NUM_ENGINES];
	struct kmem_cache *workloads;
	atomic_t running_workload_num;
	/* 1/2K for each reserve ring buffer */
	void *reserve_ring_buffer_va[I915_NUM_ENGINES];
	int reserve_ring_buffer_size[I915_NUM_ENGINES];
	DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
	struct i915_gem_context *shadow_ctx;
	DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);

#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
	struct {
		struct mdev_device *mdev;
		struct vfio_region *region;
		int num_regions;
		struct eventfd_ctx *intx_trigger;
		struct eventfd_ctx *msi_trigger;
		struct rb_root cache;
		struct mutex cache_lock;
		struct notifier_block iommu_notifier;
		struct notifier_block group_notifier;
		struct kvm *kvm;
		struct work_struct release_work;
		atomic_t released;
	} vdev;
#endif
};

struct intel_gvt_gm {
	unsigned long vgpu_allocated_low_gm_size;
	unsigned long vgpu_allocated_high_gm_size;
};

struct intel_gvt_fence {
	unsigned long vgpu_allocated_fence_num;
};

/* Special MMIO blocks. */
struct gvt_mmio_block {
	unsigned int device;
	i915_reg_t   offset;
	unsigned int size;
	gvt_mmio_func read;
	gvt_mmio_func write;
};

#define INTEL_GVT_MMIO_HASH_BITS 11

struct intel_gvt_mmio {
	u8 *mmio_attribute;
/* Register contains RO bits */
#define F_RO		(1 << 0)
/* Register contains graphics address */
#define F_GMADR		(1 << 1)
/* Mode mask registers with high 16 bits as the mask bits */
#define F_MODE_MASK	(1 << 2)
/* This reg can be accessed by GPU commands */
#define F_CMD_ACCESS	(1 << 3)
/* This reg has been accessed by a VM */
#define F_ACCESSED	(1 << 4)
/* This reg has been accessed through GPU commands */
#define F_CMD_ACCESSED	(1 << 5)
/* This reg could be accessed by unaligned address */
#define F_UNALIGN	(1 << 6)

	struct gvt_mmio_block *mmio_block;
	unsigned int num_mmio_block;

	DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
	unsigned int num_tracked_mmio;
};

struct intel_gvt_firmware {
	void *cfg_space;
	void *mmio;
	bool firmware_loaded;
};

struct intel_gvt_opregion {
	void *opregion_va;
	u32 opregion_pa;
};

#define NR_MAX_INTEL_VGPU_TYPES 20
struct intel_vgpu_type {
	char name[16];
	unsigned int avail_instance;
	unsigned int low_gm_size;
	unsigned int high_gm_size;
	unsigned int fence;
	unsigned int weight;
	enum intel_vgpu_edid resolution;
};

struct intel_gvt {
	struct mutex lock;
	struct drm_i915_private *dev_priv;
	struct idr vgpu_idr;	/* vGPU IDR pool */

	struct intel_gvt_device_info device_info;
	struct intel_gvt_gm gm;
	struct intel_gvt_fence fence;
	struct intel_gvt_mmio mmio;
	struct intel_gvt_firmware firmware;
	struct intel_gvt_irq irq;
	struct intel_gvt_gtt gtt;
	struct intel_gvt_opregion opregion;
	struct intel_gvt_workload_scheduler scheduler;
	struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
	DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
	struct intel_vgpu_type *types;
	unsigned int num_types;
	struct intel_vgpu *idle_vgpu;

	struct task_struct *service_thread;
	wait_queue_head_t service_thread_wq;
	unsigned long service_request;
};

static inline struct intel_gvt *to_gvt(struct drm_i915_private *i915)
{
	return i915->gvt;
}

enum {
	INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,

	/* Scheduling trigger by timer */
	INTEL_GVT_REQUEST_SCHED = 1,

	/* Scheduling trigger by event */
	INTEL_GVT_REQUEST_EVENT_SCHED = 2,
};

static inline void intel_gvt_request_service(struct intel_gvt *gvt,
		int service)
{
	set_bit(service, (void *)&gvt->service_request);
	wake_up(&gvt->service_thread_wq);
}

void intel_gvt_free_firmware(struct intel_gvt *gvt);
int intel_gvt_load_firmware(struct intel_gvt *gvt);

/* Aperture/GM space definitions for GVT device */
#define MB_TO_BYTES(mb) ((mb) << 20ULL)
#define BYTES_TO_MB(b) ((b) >> 20ULL)

#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
#define HOST_FENCE 4

/* Aperture/GM space definitions for GVT device */
#define gvt_aperture_sz(gvt)	  (gvt->dev_priv->ggtt.mappable_end)
#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)

#define gvt_ggtt_gm_sz(gvt)	  (gvt->dev_priv->ggtt.base.total)
#define gvt_ggtt_sz(gvt) \
	((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
#define gvt_hidden_sz(gvt)	  (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))

#define gvt_aperture_gmadr_base(gvt) (0)
#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
				     + gvt_aperture_sz(gvt) - 1)

#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
				    + gvt_aperture_sz(gvt))
#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
				   + gvt_hidden_sz(gvt) - 1)

#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)

/* Aperture/GM space definitions for vGPU */
#define vgpu_aperture_offset(vgpu)	((vgpu)->gm.low_gm_node.start)
#define vgpu_hidden_offset(vgpu)	((vgpu)->gm.high_gm_node.start)
#define vgpu_aperture_sz(vgpu)		((vgpu)->gm.aperture_sz)
#define vgpu_hidden_sz(vgpu)		((vgpu)->gm.hidden_sz)

#define vgpu_aperture_pa_base(vgpu) \
	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))

#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)

#define vgpu_aperture_pa_end(vgpu) \
	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)

#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
#define vgpu_aperture_gmadr_end(vgpu) \
	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)

#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
#define vgpu_hidden_gmadr_end(vgpu) \
	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)

#define vgpu_fence_base(vgpu) (vgpu->fence.base)
#define vgpu_fence_sz(vgpu) (vgpu->fence.size)

struct intel_vgpu_creation_params {
	__u64 handle;
	__u64 low_gm_sz;  /* in MB */
	__u64 high_gm_sz; /* in MB */
	__u64 fence_sz;
	__u64 resolution;
	__s32 primary;
	__u64 vgpu_id;

	__u32 weight;
};

int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
			      struct intel_vgpu_creation_params *param);
void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
	u32 fence, u64 value);

/* Macros for easily accessing vGPU virtual/shadow register */
#define vgpu_vreg(vgpu, reg) \
	(*(u32 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg8(vgpu, reg) \
	(*(u8 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg16(vgpu, reg) \
	(*(u16 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_vreg64(vgpu, reg) \
	(*(u64 *)(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg(vgpu, reg) \
	(*(u32 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg8(vgpu, reg) \
	(*(u8 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg16(vgpu, reg) \
	(*(u16 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
#define vgpu_sreg64(vgpu, reg) \
	(*(u64 *)(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))

#define for_each_active_vgpu(gvt, vgpu, id) \
	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
		for_each_if(vgpu->active)

static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
					    u32 offset, u32 val, bool low)
{
	u32 *pval;

	/* BAR offset should be 32 bits algiend */
	offset = rounddown(offset, 4);
	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);

	if (low) {
		/*
		 * only update bit 31 - bit 4,
		 * leave the bit 3 - bit 0 unchanged.
		 */
		*pval = (val & GENMASK(31, 4)) | (*pval & GENMASK(3, 0));
	} else {
		*pval = val;
	}
}

int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);

struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
					 struct intel_vgpu_type *type);
void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
				 unsigned int engine_mask);
void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);

/* validating GM functions */
#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
	((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
	 (gmadr <= vgpu_aperture_gmadr_end(vgpu)))

#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
	((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
	 (gmadr <= vgpu_hidden_gmadr_end(vgpu)))

#define vgpu_gmadr_is_valid(vgpu, gmadr) \
	 ((vgpu_gmadr_is_aperture(vgpu, gmadr) || \
	  (vgpu_gmadr_is_hidden(vgpu, gmadr))))

#define gvt_gmadr_is_aperture(gvt, gmadr) \
	 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
	  (gmadr <= gvt_aperture_gmadr_end(gvt)))

#define gvt_gmadr_is_hidden(gvt, gmadr) \
	  ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
	   (gmadr <= gvt_hidden_gmadr_end(gvt)))

#define gvt_gmadr_is_valid(gvt, gmadr) \
	  (gvt_gmadr_is_aperture(gvt, gmadr) || \
	    gvt_gmadr_is_hidden(gvt, gmadr))

bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu *vgpu, u64 g_addr, u64 *h_addr);
int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu *vgpu, u64 h_addr, u64 *g_addr);
int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
			     unsigned long *h_index);
int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
			     unsigned long *g_index);

void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
		bool primary);
void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);

int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
		void *p_data, unsigned int bytes);

int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
		void *p_data, unsigned int bytes);

static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
{
	/* We are 64bit bar. */
	return (*(u64 *)(vgpu->cfg_space.virtual_cfg_space + bar)) &
			PCI_BASE_ADDRESS_MEM_MASK;
}

void intel_gvt_clean_opregion(struct intel_gvt *gvt);
int intel_gvt_init_opregion(struct intel_gvt *gvt);

void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);

int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
void populate_pvinfo_page(struct intel_vgpu *vgpu);

int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);

struct intel_gvt_ops {
	int (*emulate_cfg_read)(struct intel_vgpu *, unsigned int, void *,
				unsigned int);
	int (*emulate_cfg_write)(struct intel_vgpu *, unsigned int, void *,
				unsigned int);
	int (*emulate_mmio_read)(struct intel_vgpu *, u64, void *,
				unsigned int);
	int (*emulate_mmio_write)(struct intel_vgpu *, u64, void *,
				unsigned int);
	struct intel_vgpu *(*vgpu_create)(struct intel_gvt *,
				struct intel_vgpu_type *);
	void (*vgpu_destroy)(struct intel_vgpu *);
	void (*vgpu_reset)(struct intel_vgpu *);
	void (*vgpu_activate)(struct intel_vgpu *);
	void (*vgpu_deactivate)(struct intel_vgpu *);
};


enum {
	GVT_FAILSAFE_UNSUPPORTED_GUEST,
	GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
};

static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv)
{
	intel_runtime_pm_get(dev_priv);
}

static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv)
{
	intel_runtime_pm_put(dev_priv);
}

/**
 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
 * @gvt: a GVT device
 * @offset: register offset
 *
 */
static inline void intel_gvt_mmio_set_accessed(
			struct intel_gvt *gvt, unsigned int offset)
{
	gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
}

/**
 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
 * @gvt: a GVT device
 * @offset: register offset
 *
 */
static inline bool intel_gvt_mmio_is_cmd_access(
			struct intel_gvt *gvt, unsigned int offset)
{
	return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
}

/**
 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
 * @gvt: a GVT device
 * @offset: register offset
 *
 */
static inline bool intel_gvt_mmio_is_unalign(
			struct intel_gvt *gvt, unsigned int offset)
{
	return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
}

/**
 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
 * @gvt: a GVT device
 * @offset: register offset
 *
 */
static inline void intel_gvt_mmio_set_cmd_accessed(
			struct intel_gvt *gvt, unsigned int offset)
{
	gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESSED;
}

/**
 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
 * @gvt: a GVT device
 * @offset: register offset
 *
 * Returns:
 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
 *
 */
static inline bool intel_gvt_mmio_has_mode_mask(
			struct intel_gvt *gvt, unsigned int offset)
{
	return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
}

#include "trace.h"
#include "mpt.h"

#endif
Commit	Line	Data
0ad35fed ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
12d14cc4 ZW	22	*
	23	* Authors:
	24	* Kevin Tian <kevin.tian@intel.com>
	25	* Eddie Dong <eddie.dong@intel.com>
	26	*
	27	* Contributors:
	28	* Niu Bing <bing.niu@intel.com>
	29	* Zhi Wang <zhi.a.wang@intel.com>
	30	*
0ad35fed ZW	31	*/
	32
	33	#ifndef _GVT_H_
	34	#define _GVT_H_
	35
	36	#include "debug.h"
	37	#include "hypercall.h"
12d14cc4	38	#include "mmio.h"
82d375d1	39	#include "reg.h"
c8fe6a68	40	#include "interrupt.h"
2707e444	41	#include "gtt.h"
04d348ae ZW	42	#include "display.h"
04d348ae ZW	43	#include "edid.h"
8453d674	44	#include "execlist.h"
28c4c6ca	45	#include "scheduler.h"
4b63960e	46	#include "sched_policy.h"
17865713	47	#include "render.h"
be1da707	48	#include "cmd_parser.h"
0ad35fed ZW	49
	50	#define GVT_MAX_VGPU 8
	51
	52	enum {
	53	INTEL_GVT_HYPERVISOR_XEN = 0,
	54	INTEL_GVT_HYPERVISOR_KVM,
	55	};
	56
	57	struct intel_gvt_host {
	58	bool initialized;
	59	int hypervisor_type;
	60	struct intel_gvt_mpt *mpt;
	61	};
	62
	63	extern struct intel_gvt_host intel_gvt_host;
	64
	65	/* Describe per-platform limitations. */
	66	struct intel_gvt_device_info {
	67	u32 max_support_vgpus;
579cea5f	68	u32 cfg_space_size;
c8fe6a68	69	u32 mmio_size;
579cea5f	70	u32 mmio_bar;
c8fe6a68	71	unsigned long msi_cap_offset;
2707e444 ZW	72	u32 gtt_start_offset;
	73	u32 gtt_entry_size;
	74	u32 gtt_entry_size_shift;
be1da707 ZW	75	int gmadr_bytes_in_cmd;
be1da707 ZW	76	u32 max_surface_size;
0ad35fed ZW	77	};
0ad35fed ZW	78
28a60dee ZW	79	/* GM resources owned by a vGPU */
	80	struct intel_vgpu_gm {
	81	u64 aperture_sz;
	82	u64 hidden_sz;
f090a00d	83	void *aperture_va;
28a60dee ZW	84	struct drm_mm_node low_gm_node;
	85	struct drm_mm_node high_gm_node;
	86	};
	87
	88	#define INTEL_GVT_MAX_NUM_FENCES 32
	89
	90	/* Fences owned by a vGPU */
	91	struct intel_vgpu_fence {
	92	struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
	93	u32 base;
	94	u32 size;
	95	};
	96
82d375d1 ZW	97	struct intel_vgpu_mmio {
	98	void *vreg;
	99	void *sreg;
e39c5add	100	bool disable_warn_untrack;
82d375d1 ZW	101	};
82d375d1 ZW	102
82d375d1 ZW	103	#define INTEL_GVT_MAX_BAR_NUM 4
	104
	105	struct intel_vgpu_pci_bar {
	106	u64 size;
	107	bool tracked;
	108	};
	109
	110	struct intel_vgpu_cfg_space {
02d578e5	111	unsigned char virtual_cfg_space[PCI_CFG_SPACE_EXP_SIZE];
82d375d1 ZW	112	struct intel_vgpu_pci_bar bar[INTEL_GVT_MAX_BAR_NUM];
	113	};
	114
	115	#define vgpu_cfg_space(vgpu) ((vgpu)->cfg_space.virtual_cfg_space)
	116
04d348ae ZW	117	#define INTEL_GVT_MAX_PIPE 4
04d348ae ZW	118
c8fe6a68 ZW	119	struct intel_vgpu_irq {
c8fe6a68 ZW	120	bool irq_warn_once[INTEL_GVT_EVENT_MAX];
04d348ae ZW	121	DECLARE_BITMAP(flip_done_event[INTEL_GVT_MAX_PIPE],
04d348ae ZW	122	INTEL_GVT_EVENT_MAX);
c8fe6a68 ZW	123	};
c8fe6a68 ZW	124
4d60c5fd ZW	125	struct intel_vgpu_opregion {
	126	void *va;
	127	u32 gfn[INTEL_GVT_OPREGION_PAGES];
	128	struct page *pages[INTEL_GVT_OPREGION_PAGES];
	129	};
	130
	131	#define vgpu_opregion(vgpu) (&(vgpu->opregion))
	132
04d348ae ZW	133	#define INTEL_GVT_MAX_PORT 5
	134
	135	struct intel_vgpu_display {
	136	struct intel_vgpu_i2c_edid i2c_edid;
	137	struct intel_vgpu_port ports[INTEL_GVT_MAX_PORT];
	138	struct intel_vgpu_sbi sbi;
	139	};
	140
f6504cce PG	141	struct vgpu_sched_ctl {
	142	int weight;
	143	};
	144
0ad35fed ZW	145	struct intel_vgpu {
	146	struct intel_gvt *gvt;
	147	int id;
	148	unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
82d375d1	149	bool active;
fd64be63 MH	150	bool pv_notified;
fd64be63 MH	151	bool failsafe;
6184cc8d	152	unsigned int resetting_eng;
4b63960e	153	void *sched_data;
bc90d097	154	struct vgpu_sched_ctl sched_ctl;
28a60dee ZW	155
	156	struct intel_vgpu_fence fence;
	157	struct intel_vgpu_gm gm;
82d375d1 ZW	158	struct intel_vgpu_cfg_space cfg_space;
82d375d1 ZW	159	struct intel_vgpu_mmio mmio;
c8fe6a68	160	struct intel_vgpu_irq irq;
2707e444	161	struct intel_vgpu_gtt gtt;
4d60c5fd	162	struct intel_vgpu_opregion opregion;
04d348ae	163	struct intel_vgpu_display display;
8453d674	164	struct intel_vgpu_execlist execlist[I915_NUM_ENGINES];
28c4c6ca ZW	165	struct list_head workload_q_head[I915_NUM_ENGINES];
28c4c6ca ZW	166	struct kmem_cache *workloads;
e4734057	167	atomic_t running_workload_num;
0a53bc07	168	/* 1/2K for each reserve ring buffer */
	169	void *reserve_ring_buffer_va[I915_NUM_ENGINES];
	170	int reserve_ring_buffer_size[I915_NUM_ENGINES];
17865713	171	DECLARE_BITMAP(tlb_handle_pending, I915_NUM_ENGINES);
e4734057	172	struct i915_gem_context *shadow_ctx;
9dfb8e5b	173	DECLARE_BITMAP(shadow_ctx_desc_updated, I915_NUM_ENGINES);
f30437c5 JS	174
	175	#if IS_ENABLED(CONFIG_DRM_I915_GVT_KVMGT)
	176	struct {
659643f7	177	struct mdev_device *mdev;
f30437c5 JS	178	struct vfio_region *region;
	179	int num_regions;
	180	struct eventfd_ctx *intx_trigger;
	181	struct eventfd_ctx *msi_trigger;
	182	struct rb_root cache;
	183	struct mutex cache_lock;
f30437c5	184	struct notifier_block iommu_notifier;
659643f7 JS	185	struct notifier_block group_notifier;
	186	struct kvm *kvm;
	187	struct work_struct release_work;
364fb6b7	188	atomic_t released;
f30437c5 JS	189	} vdev;
f30437c5 JS	190	#endif
28a60dee ZW	191	};
	192
	193	struct intel_gvt_gm {
	194	unsigned long vgpu_allocated_low_gm_size;
	195	unsigned long vgpu_allocated_high_gm_size;
	196	};
	197
	198	struct intel_gvt_fence {
	199	unsigned long vgpu_allocated_fence_num;
0ad35fed ZW	200	};
0ad35fed ZW	201
02b6ed44 TZ	202	/* Special MMIO blocks. */
	203	struct gvt_mmio_block {
	204	unsigned int device;
	205	i915_reg_t offset;
	206	unsigned int size;
	207	gvt_mmio_func read;
	208	gvt_mmio_func write;
	209	};
	210
178cd160	211	#define INTEL_GVT_MMIO_HASH_BITS 11
12d14cc4 ZW	212
12d14cc4 ZW	213	struct intel_gvt_mmio {
56a78de5	214	u8 *mmio_attribute;
5c6d4c67 CD	215	/* Register contains RO bits */
	216	#define F_RO (1 << 0)
	217	/* Register contains graphics address */
	218	#define F_GMADR (1 << 1)
	219	/* Mode mask registers with high 16 bits as the mask bits */
	220	#define F_MODE_MASK (1 << 2)
	221	/* This reg can be accessed by GPU commands */
	222	#define F_CMD_ACCESS (1 << 3)
	223	/* This reg has been accessed by a VM */
	224	#define F_ACCESSED (1 << 4)
	225	/* This reg has been accessed through GPU commands */
	226	#define F_CMD_ACCESSED (1 << 5)
	227	/* This reg could be accessed by unaligned address */
	228	#define F_UNALIGN (1 << 6)
	229
02b6ed44 TZ	230	struct gvt_mmio_block *mmio_block;
	231	unsigned int num_mmio_block;
	232
12d14cc4	233	DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
fbfd76c3	234	unsigned int num_tracked_mmio;
12d14cc4 ZW	235	};
12d14cc4 ZW	236
579cea5f ZW	237	struct intel_gvt_firmware {
	238	void *cfg_space;
	239	void *mmio;
	240	bool firmware_loaded;
	241	};
	242
4d60c5fd	243	struct intel_gvt_opregion {
f655e67a	244	void *opregion_va;
4d60c5fd ZW	245	u32 opregion_pa;
	246	};
	247
1f31c829 ZW	248	#define NR_MAX_INTEL_VGPU_TYPES 20
	249	struct intel_vgpu_type {
	250	char name[16];
1f31c829 ZW	251	unsigned int avail_instance;
	252	unsigned int low_gm_size;
	253	unsigned int high_gm_size;
	254	unsigned int fence;
bc90d097	255	unsigned int weight;
d1a513be	256	enum intel_vgpu_edid resolution;
1f31c829 ZW	257	};
1f31c829 ZW	258
0ad35fed ZW	259	struct intel_gvt {
0ad35fed ZW	260	struct mutex lock;
0ad35fed ZW	261	struct drm_i915_private *dev_priv;
	262	struct idr vgpu_idr; /* vGPU IDR pool */
	263
	264	struct intel_gvt_device_info device_info;
28a60dee ZW	265	struct intel_gvt_gm gm;
28a60dee ZW	266	struct intel_gvt_fence fence;
12d14cc4	267	struct intel_gvt_mmio mmio;
579cea5f	268	struct intel_gvt_firmware firmware;
c8fe6a68	269	struct intel_gvt_irq irq;
2707e444	270	struct intel_gvt_gtt gtt;
4d60c5fd	271	struct intel_gvt_opregion opregion;
28c4c6ca	272	struct intel_gvt_workload_scheduler scheduler;
3fc03069	273	struct notifier_block shadow_ctx_notifier_block[I915_NUM_ENGINES];
be1da707	274	DECLARE_HASHTABLE(cmd_table, GVT_CMD_HASH_BITS);
1f31c829 ZW	275	struct intel_vgpu_type *types;
1f31c829 ZW	276	unsigned int num_types;
afe04fbe	277	struct intel_vgpu *idle_vgpu;
04d348ae ZW	278
	279	struct task_struct *service_thread;
	280	wait_queue_head_t service_thread_wq;
	281	unsigned long service_request;
0ad35fed ZW	282	};
0ad35fed ZW	283
feddf6e8 ZW	284	static inline struct intel_gvt to_gvt(struct drm_i915_private i915)
	285	{
	286	return i915->gvt;
	287	}
	288
04d348ae ZW	289	enum {
04d348ae ZW	290	INTEL_GVT_REQUEST_EMULATE_VBLANK = 0,
c713cb2f PG	291
c713cb2f PG	292	/* Scheduling trigger by timer */
91d0101a	293	INTEL_GVT_REQUEST_SCHED = 1,
c713cb2f PG	294
	295	/* Scheduling trigger by event */
	296	INTEL_GVT_REQUEST_EVENT_SCHED = 2,
04d348ae ZW	297	};
	298
	299	static inline void intel_gvt_request_service(struct intel_gvt *gvt,
	300	int service)
	301	{
	302	set_bit(service, (void *)&gvt->service_request);
	303	wake_up(&gvt->service_thread_wq);
	304	}
	305
579cea5f ZW	306	void intel_gvt_free_firmware(struct intel_gvt *gvt);
	307	int intel_gvt_load_firmware(struct intel_gvt *gvt);
	308
1f31c829 ZW	309	/* Aperture/GM space definitions for GVT device */
	310	#define MB_TO_BYTES(mb) ((mb) << 20ULL)
	311	#define BYTES_TO_MB(b) ((b) >> 20ULL)
	312
	313	#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
	314	#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
	315	#define HOST_FENCE 4
	316
28a60dee ZW	317	/* Aperture/GM space definitions for GVT device */
28a60dee ZW	318	#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
b06f4c80	319	#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.gmadr.start)
28a60dee ZW	320
28a60dee ZW	321	#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
e39c5add ZW	322	#define gvt_ggtt_sz(gvt) \
e39c5add ZW	323	((gvt->dev_priv->ggtt.base.total >> PAGE_SHIFT) << 3)
28a60dee ZW	324	#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
	325
	326	#define gvt_aperture_gmadr_base(gvt) (0)
	327	#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
	328	+ gvt_aperture_sz(gvt) - 1)
	329
	330	#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
	331	+ gvt_aperture_sz(gvt))
	332	#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
	333	+ gvt_hidden_sz(gvt) - 1)
	334
	335	#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
	336
	337	/* Aperture/GM space definitions for vGPU */
	338	#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
	339	#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
	340	#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
	341	#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
	342
	343	#define vgpu_aperture_pa_base(vgpu) \
	344	(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
	345
	346	#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
	347
	348	#define vgpu_aperture_pa_end(vgpu) \
	349	(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
	350
	351	#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
	352	#define vgpu_aperture_gmadr_end(vgpu) \
	353	(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
	354
	355	#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
	356	#define vgpu_hidden_gmadr_end(vgpu) \
	357	(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
	358
	359	#define vgpu_fence_base(vgpu) (vgpu->fence.base)
	360	#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
	361
	362	struct intel_vgpu_creation_params {
	363	__u64 handle;
	364	__u64 low_gm_sz; /* in MB */
	365	__u64 high_gm_sz; /* in MB */
	366	__u64 fence_sz;
d1a513be	367	__u64 resolution;
28a60dee ZW	368	__s32 primary;
28a60dee ZW	369	__u64 vgpu_id;
bc90d097 PG	370
bc90d097 PG	371	__u32 weight;
28a60dee ZW	372	};
	373
	374	int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
	375	struct intel_vgpu_creation_params *param);
d22a48bf	376	void intel_vgpu_reset_resource(struct intel_vgpu *vgpu);
28a60dee ZW	377	void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
	378	void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
	379	u32 fence, u64 value);
	380
82d375d1 ZW	381	/* Macros for easily accessing vGPU virtual/shadow register */
	382	#define vgpu_vreg(vgpu, reg) \
	383	((u32 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	384	#define vgpu_vreg8(vgpu, reg) \
	385	((u8 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	386	#define vgpu_vreg16(vgpu, reg) \
	387	((u16 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	388	#define vgpu_vreg64(vgpu, reg) \
	389	((u64 )(vgpu->mmio.vreg + INTEL_GVT_MMIO_OFFSET(reg)))
	390	#define vgpu_sreg(vgpu, reg) \
	391	((u32 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	392	#define vgpu_sreg8(vgpu, reg) \
	393	((u8 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	394	#define vgpu_sreg16(vgpu, reg) \
	395	((u16 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	396	#define vgpu_sreg64(vgpu, reg) \
	397	((u64 )(vgpu->mmio.sreg + INTEL_GVT_MMIO_OFFSET(reg)))
	398
	399	#define for_each_active_vgpu(gvt, vgpu, id) \
	400	idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
	401	for_each_if(vgpu->active)
	402
	403	static inline void intel_vgpu_write_pci_bar(struct intel_vgpu *vgpu,
	404	u32 offset, u32 val, bool low)
	405	{
	406	u32 *pval;
	407
	408	/* BAR offset should be 32 bits algiend */
	409	offset = rounddown(offset, 4);
	410	pval = (u32 *)(vgpu_cfg_space(vgpu) + offset);
	411
	412	if (low) {
	413	/*
	414	* only update bit 31 - bit 4,
	415	* leave the bit 3 - bit 0 unchanged.
	416	*/
	417	pval = (val & GENMASK(31, 4)) \| (pval & GENMASK(3, 0));
550dd77e XC	418	} else {
550dd77e XC	419	*pval = val;
82d375d1 ZW	420	}
	421	}
	422
1f31c829 ZW	423	int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
1f31c829 ZW	424	void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
82d375d1	425
afe04fbe PG	426	struct intel_vgpu intel_gvt_create_idle_vgpu(struct intel_gvt gvt);
afe04fbe PG	427	void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu);
1f31c829 ZW	428	struct intel_vgpu intel_gvt_create_vgpu(struct intel_gvt gvt,
1f31c829 ZW	429	struct intel_vgpu_type *type);
82d375d1	430	void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu);
cfe65f40 CD	431	void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
cfe65f40 CD	432	unsigned int engine_mask);
9ec1e66b	433	void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu);
b79c52ae ZW	434	void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu);
b79c52ae ZW	435	void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu);
1f31c829	436
2707e444 ZW	437	/* validating GM functions */
	438	#define vgpu_gmadr_is_aperture(vgpu, gmadr) \
	439	((gmadr >= vgpu_aperture_gmadr_base(vgpu)) && \
	440	(gmadr <= vgpu_aperture_gmadr_end(vgpu)))
	441
	442	#define vgpu_gmadr_is_hidden(vgpu, gmadr) \
	443	((gmadr >= vgpu_hidden_gmadr_base(vgpu)) && \
	444	(gmadr <= vgpu_hidden_gmadr_end(vgpu)))
	445
	446	#define vgpu_gmadr_is_valid(vgpu, gmadr) \
	447	((vgpu_gmadr_is_aperture(vgpu, gmadr) \|\| \
	448	(vgpu_gmadr_is_hidden(vgpu, gmadr))))
	449
	450	#define gvt_gmadr_is_aperture(gvt, gmadr) \
	451	((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
	452	(gmadr <= gvt_aperture_gmadr_end(gvt)))
	453
	454	#define gvt_gmadr_is_hidden(gvt, gmadr) \
	455	((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
	456	(gmadr <= gvt_hidden_gmadr_end(gvt)))
	457
	458	#define gvt_gmadr_is_valid(gvt, gmadr) \
	459	(gvt_gmadr_is_aperture(gvt, gmadr) \|\| \
	460	gvt_gmadr_is_hidden(gvt, gmadr))
	461
	462	bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size);
	463	int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu vgpu, u64 g_addr, u64 h_addr);
	464	int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu vgpu, u64 h_addr, u64 g_addr);
	465	int intel_gvt_ggtt_index_g2h(struct intel_vgpu *vgpu, unsigned long g_index,
	466	unsigned long *h_index);
	467	int intel_gvt_ggtt_h2g_index(struct intel_vgpu *vgpu, unsigned long h_index,
	468	unsigned long *g_index);
4d60c5fd	469
536fc234 CD	470	void intel_vgpu_init_cfg_space(struct intel_vgpu *vgpu,
536fc234 CD	471	bool primary);
c64ff6c7 CD	472	void intel_vgpu_reset_cfg_space(struct intel_vgpu *vgpu);
c64ff6c7 CD	473
9ec1e66b	474	int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,
4d60c5fd ZW	475	void *p_data, unsigned int bytes);
4d60c5fd ZW	476
9ec1e66b	477	int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,
4d60c5fd ZW	478	void *p_data, unsigned int bytes);
4d60c5fd ZW	479
f090a00d CD	480	static inline u64 intel_vgpu_get_bar_gpa(struct intel_vgpu *vgpu, int bar)
	481	{
	482	/* We are 64bit bar. */
	483	return ((u64 )(vgpu->cfg_space.virtual_cfg_space + bar)) &
	484	PCI_BASE_ADDRESS_MEM_MASK;
	485	}
	486
4d60c5fd ZW	487	void intel_gvt_clean_opregion(struct intel_gvt *gvt);
	488	int intel_gvt_init_opregion(struct intel_gvt *gvt);
	489
	490	void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu);
	491	int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa);
	492
	493	int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci);
23736d1b	494	void populate_pvinfo_page(struct intel_vgpu *vgpu);
4d60c5fd	495
89ea20b9 PG	496	int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload);
89ea20b9 PG	497
9ec1e66b JS	498	struct intel_gvt_ops {
	499	int (emulate_cfg_read)(struct intel_vgpu , unsigned int, void *,
	500	unsigned int);
	501	int (emulate_cfg_write)(struct intel_vgpu , unsigned int, void *,
	502	unsigned int);
	503	int (emulate_mmio_read)(struct intel_vgpu , u64, void *,
	504	unsigned int);
	505	int (emulate_mmio_write)(struct intel_vgpu , u64, void *,
	506	unsigned int);
	507	struct intel_vgpu (vgpu_create)(struct intel_gvt *,
	508	struct intel_vgpu_type *);
	509	void (vgpu_destroy)(struct intel_vgpu );
	510	void (vgpu_reset)(struct intel_vgpu );
b79c52ae ZW	511	void (vgpu_activate)(struct intel_vgpu );
b79c52ae ZW	512	void (vgpu_deactivate)(struct intel_vgpu );
9ec1e66b JS	513	};
	514
	515
fd64be63 MH	516	enum {
fd64be63 MH	517	GVT_FAILSAFE_UNSUPPORTED_GUEST,
a33fc7a0	518	GVT_FAILSAFE_INSUFFICIENT_RESOURCE,
fd64be63 MH	519	};
fd64be63 MH	520
9b7bd65e CD	521	static inline void mmio_hw_access_pre(struct drm_i915_private *dev_priv)
	522	{
	523	intel_runtime_pm_get(dev_priv);
	524	}
	525
	526	static inline void mmio_hw_access_post(struct drm_i915_private *dev_priv)
	527	{
	528	intel_runtime_pm_put(dev_priv);
	529	}
	530
5c6d4c67 CD	531	/**
	532	* intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
	533	* @gvt: a GVT device
	534	* @offset: register offset
	535	*
	536	*/
	537	static inline void intel_gvt_mmio_set_accessed(
	538	struct intel_gvt *gvt, unsigned int offset)
	539	{
	540	gvt->mmio.mmio_attribute[offset >> 2] \|= F_ACCESSED;
	541	}
	542
	543	/**
	544	* intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
	545	* @gvt: a GVT device
	546	* @offset: register offset
	547	*
	548	*/
	549	static inline bool intel_gvt_mmio_is_cmd_access(
	550	struct intel_gvt *gvt, unsigned int offset)
	551	{
	552	return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
	553	}
	554
	555	/**
	556	* intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
	557	* @gvt: a GVT device
	558	* @offset: register offset
	559	*
	560	*/
	561	static inline bool intel_gvt_mmio_is_unalign(
	562	struct intel_gvt *gvt, unsigned int offset)
	563	{
	564	return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
	565	}
	566
	567	/**
	568	* intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
	569	* @gvt: a GVT device
	570	* @offset: register offset
	571	*
	572	*/
	573	static inline void intel_gvt_mmio_set_cmd_accessed(
	574	struct intel_gvt *gvt, unsigned int offset)
	575	{
	576	gvt->mmio.mmio_attribute[offset >> 2] \|= F_CMD_ACCESSED;
	577	}
	578
	579	/**
	580	* intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
	581	* @gvt: a GVT device
	582	* @offset: register offset
	583	*
	584	* Returns:
	585	* True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
	586	*
	587	*/
	588	static inline bool intel_gvt_mmio_has_mode_mask(
	589	struct intel_gvt *gvt, unsigned int offset)
	590	{
	591	return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
	592	}
	593
7fb6a7d6	594	#include "trace.h"
0ad35fed ZW	595	#include "mpt.h"
	596
	597	#endif