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Commit | Line | Data |
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76aaf220 DV |
1 | /* |
2 | * Copyright © 2010 Daniel Vetter | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
24 | ||
760285e7 DH |
25 | #include <drm/drmP.h> |
26 | #include <drm/i915_drm.h> | |
76aaf220 DV |
27 | #include "i915_drv.h" |
28 | #include "i915_trace.h" | |
29 | #include "intel_drv.h" | |
30 | ||
6670a5a5 BW |
31 | #define GEN6_PPGTT_PD_ENTRIES 512 |
32 | #define I915_PPGTT_PT_ENTRIES (PAGE_SIZE / sizeof(gen6_gtt_pte_t)) | |
33 | ||
26b1ff35 BW |
34 | /* PPGTT stuff */ |
35 | #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) | |
0d8ff15e | 36 | #define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) |
26b1ff35 BW |
37 | |
38 | #define GEN6_PDE_VALID (1 << 0) | |
39 | /* gen6+ has bit 11-4 for physical addr bit 39-32 */ | |
40 | #define GEN6_PDE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
41 | ||
42 | #define GEN6_PTE_VALID (1 << 0) | |
43 | #define GEN6_PTE_UNCACHED (1 << 1) | |
44 | #define HSW_PTE_UNCACHED (0) | |
45 | #define GEN6_PTE_CACHE_LLC (2 << 1) | |
46 | #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) | |
47 | #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) | |
0d8ff15e BW |
48 | #define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) |
49 | ||
50 | /* Cacheability Control is a 4-bit value. The low three bits are stored in * | |
51 | * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. | |
52 | */ | |
53 | #define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ | |
54 | (((bits) & 0x8) << (11 - 3))) | |
55 | #define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) | |
4d15c145 | 56 | #define HSW_WB_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0xb) |
26b1ff35 | 57 | |
80a74f7f | 58 | static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr, |
2d04befb | 59 | enum i915_cache_level level) |
54d12527 | 60 | { |
e7c2b58b | 61 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; |
54d12527 | 62 | pte |= GEN6_PTE_ADDR_ENCODE(addr); |
e7210c3c BW |
63 | |
64 | switch (level) { | |
65 | case I915_CACHE_LLC_MLC: | |
9119708c | 66 | pte |= GEN6_PTE_CACHE_LLC_MLC; |
e7210c3c BW |
67 | break; |
68 | case I915_CACHE_LLC: | |
69 | pte |= GEN6_PTE_CACHE_LLC; | |
70 | break; | |
71 | case I915_CACHE_NONE: | |
9119708c | 72 | pte |= GEN6_PTE_UNCACHED; |
e7210c3c BW |
73 | break; |
74 | default: | |
75 | BUG(); | |
76 | } | |
77 | ||
54d12527 BW |
78 | return pte; |
79 | } | |
80 | ||
93c34e70 KG |
81 | #define BYT_PTE_WRITEABLE (1 << 1) |
82 | #define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2) | |
83 | ||
80a74f7f | 84 | static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, |
93c34e70 KG |
85 | enum i915_cache_level level) |
86 | { | |
87 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
88 | pte |= GEN6_PTE_ADDR_ENCODE(addr); | |
89 | ||
90 | /* Mark the page as writeable. Other platforms don't have a | |
91 | * setting for read-only/writable, so this matches that behavior. | |
92 | */ | |
93 | pte |= BYT_PTE_WRITEABLE; | |
94 | ||
95 | if (level != I915_CACHE_NONE) | |
96 | pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; | |
97 | ||
98 | return pte; | |
99 | } | |
100 | ||
80a74f7f | 101 | static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, |
9119708c KG |
102 | enum i915_cache_level level) |
103 | { | |
104 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
0d8ff15e | 105 | pte |= HSW_PTE_ADDR_ENCODE(addr); |
9119708c KG |
106 | |
107 | if (level != I915_CACHE_NONE) | |
0d8ff15e | 108 | pte |= HSW_WB_LLC_AGE0; |
9119708c KG |
109 | |
110 | return pte; | |
111 | } | |
112 | ||
4d15c145 BW |
113 | static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr, |
114 | enum i915_cache_level level) | |
115 | { | |
116 | gen6_gtt_pte_t pte = GEN6_PTE_VALID; | |
117 | pte |= HSW_PTE_ADDR_ENCODE(addr); | |
118 | ||
119 | if (level != I915_CACHE_NONE) | |
120 | pte |= HSW_WB_ELLC_LLC_AGE0; | |
121 | ||
122 | return pte; | |
123 | } | |
124 | ||
3e302542 | 125 | static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt) |
6197349b | 126 | { |
3e302542 | 127 | struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; |
6197349b BW |
128 | gen6_gtt_pte_t __iomem *pd_addr; |
129 | uint32_t pd_entry; | |
130 | int i; | |
131 | ||
0a732870 | 132 | WARN_ON(ppgtt->pd_offset & 0x3f); |
6197349b BW |
133 | pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + |
134 | ppgtt->pd_offset / sizeof(gen6_gtt_pte_t); | |
135 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
136 | dma_addr_t pt_addr; | |
137 | ||
138 | pt_addr = ppgtt->pt_dma_addr[i]; | |
139 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
140 | pd_entry |= GEN6_PDE_VALID; | |
141 | ||
142 | writel(pd_entry, pd_addr + i); | |
143 | } | |
144 | readl(pd_addr); | |
3e302542 BW |
145 | } |
146 | ||
147 | static int gen6_ppgtt_enable(struct drm_device *dev) | |
148 | { | |
149 | drm_i915_private_t *dev_priv = dev->dev_private; | |
150 | uint32_t pd_offset; | |
151 | struct intel_ring_buffer *ring; | |
152 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
153 | int i; | |
154 | ||
155 | BUG_ON(ppgtt->pd_offset & 0x3f); | |
156 | ||
157 | gen6_write_pdes(ppgtt); | |
6197349b BW |
158 | |
159 | pd_offset = ppgtt->pd_offset; | |
160 | pd_offset /= 64; /* in cachelines, */ | |
161 | pd_offset <<= 16; | |
162 | ||
163 | if (INTEL_INFO(dev)->gen == 6) { | |
164 | uint32_t ecochk, gab_ctl, ecobits; | |
165 | ||
166 | ecobits = I915_READ(GAC_ECO_BITS); | |
3b9d7888 VS |
167 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | |
168 | ECOBITS_PPGTT_CACHE64B); | |
6197349b BW |
169 | |
170 | gab_ctl = I915_READ(GAB_CTL); | |
171 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
172 | ||
173 | ecochk = I915_READ(GAM_ECOCHK); | |
174 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
175 | ECOCHK_PPGTT_CACHE64B); | |
176 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
177 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
a6f429a5 | 178 | uint32_t ecochk, ecobits; |
a65c2fcd VS |
179 | |
180 | ecobits = I915_READ(GAC_ECO_BITS); | |
181 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
182 | ||
a6f429a5 VS |
183 | ecochk = I915_READ(GAM_ECOCHK); |
184 | if (IS_HASWELL(dev)) { | |
185 | ecochk |= ECOCHK_PPGTT_WB_HSW; | |
186 | } else { | |
187 | ecochk |= ECOCHK_PPGTT_LLC_IVB; | |
188 | ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; | |
189 | } | |
190 | I915_WRITE(GAM_ECOCHK, ecochk); | |
6197349b BW |
191 | /* GFX_MODE is per-ring on gen7+ */ |
192 | } | |
193 | ||
194 | for_each_ring(ring, dev_priv, i) { | |
195 | if (INTEL_INFO(dev)->gen >= 7) | |
196 | I915_WRITE(RING_MODE_GEN7(ring), | |
197 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); | |
198 | ||
199 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
200 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
201 | } | |
b7c36d25 | 202 | return 0; |
6197349b BW |
203 | } |
204 | ||
1d2a314c | 205 | /* PPGTT support for Sandybdrige/Gen6 and later */ |
def886c3 | 206 | static void gen6_ppgtt_clear_range(struct i915_hw_ppgtt *ppgtt, |
1d2a314c DV |
207 | unsigned first_entry, |
208 | unsigned num_entries) | |
209 | { | |
84f13560 | 210 | struct drm_i915_private *dev_priv = ppgtt->dev->dev_private; |
e7c2b58b | 211 | gen6_gtt_pte_t *pt_vaddr, scratch_pte; |
a15326a5 | 212 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
7bddb01f DV |
213 | unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
214 | unsigned last_pte, i; | |
1d2a314c | 215 | |
80a74f7f | 216 | scratch_pte = ppgtt->pte_encode(dev_priv->gtt.scratch.addr, |
2d04befb | 217 | I915_CACHE_LLC); |
1d2a314c | 218 | |
7bddb01f DV |
219 | while (num_entries) { |
220 | last_pte = first_pte + num_entries; | |
221 | if (last_pte > I915_PPGTT_PT_ENTRIES) | |
222 | last_pte = I915_PPGTT_PT_ENTRIES; | |
223 | ||
a15326a5 | 224 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
1d2a314c | 225 | |
7bddb01f DV |
226 | for (i = first_pte; i < last_pte; i++) |
227 | pt_vaddr[i] = scratch_pte; | |
1d2a314c DV |
228 | |
229 | kunmap_atomic(pt_vaddr); | |
1d2a314c | 230 | |
7bddb01f DV |
231 | num_entries -= last_pte - first_pte; |
232 | first_pte = 0; | |
a15326a5 | 233 | act_pt++; |
7bddb01f | 234 | } |
1d2a314c DV |
235 | } |
236 | ||
def886c3 DV |
237 | static void gen6_ppgtt_insert_entries(struct i915_hw_ppgtt *ppgtt, |
238 | struct sg_table *pages, | |
239 | unsigned first_entry, | |
240 | enum i915_cache_level cache_level) | |
241 | { | |
e7c2b58b | 242 | gen6_gtt_pte_t *pt_vaddr; |
a15326a5 | 243 | unsigned act_pt = first_entry / I915_PPGTT_PT_ENTRIES; |
6e995e23 ID |
244 | unsigned act_pte = first_entry % I915_PPGTT_PT_ENTRIES; |
245 | struct sg_page_iter sg_iter; | |
246 | ||
a15326a5 | 247 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); |
6e995e23 ID |
248 | for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { |
249 | dma_addr_t page_addr; | |
250 | ||
2db76d7c | 251 | page_addr = sg_page_iter_dma_address(&sg_iter); |
80a74f7f | 252 | pt_vaddr[act_pte] = ppgtt->pte_encode(page_addr, cache_level); |
6e995e23 ID |
253 | if (++act_pte == I915_PPGTT_PT_ENTRIES) { |
254 | kunmap_atomic(pt_vaddr); | |
a15326a5 DV |
255 | act_pt++; |
256 | pt_vaddr = kmap_atomic(ppgtt->pt_pages[act_pt]); | |
6e995e23 | 257 | act_pte = 0; |
def886c3 | 258 | |
def886c3 | 259 | } |
def886c3 | 260 | } |
6e995e23 | 261 | kunmap_atomic(pt_vaddr); |
def886c3 DV |
262 | } |
263 | ||
3440d265 | 264 | static void gen6_ppgtt_cleanup(struct i915_hw_ppgtt *ppgtt) |
1d2a314c | 265 | { |
3440d265 DV |
266 | int i; |
267 | ||
268 | if (ppgtt->pt_dma_addr) { | |
269 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
270 | pci_unmap_page(ppgtt->dev->pdev, | |
271 | ppgtt->pt_dma_addr[i], | |
272 | 4096, PCI_DMA_BIDIRECTIONAL); | |
273 | } | |
274 | ||
275 | kfree(ppgtt->pt_dma_addr); | |
276 | for (i = 0; i < ppgtt->num_pd_entries; i++) | |
277 | __free_page(ppgtt->pt_pages[i]); | |
278 | kfree(ppgtt->pt_pages); | |
279 | kfree(ppgtt); | |
280 | } | |
281 | ||
282 | static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt) | |
283 | { | |
284 | struct drm_device *dev = ppgtt->dev; | |
1d2a314c | 285 | struct drm_i915_private *dev_priv = dev->dev_private; |
1d2a314c | 286 | unsigned first_pd_entry_in_global_pt; |
1d2a314c DV |
287 | int i; |
288 | int ret = -ENOMEM; | |
289 | ||
290 | /* ppgtt PDEs reside in the global gtt pagetable, which has 512*1024 | |
291 | * entries. For aliasing ppgtt support we just steal them at the end for | |
292 | * now. */ | |
e1b73cba | 293 | first_pd_entry_in_global_pt = gtt_total_entries(dev_priv->gtt); |
1d2a314c | 294 | |
9119708c KG |
295 | if (IS_HASWELL(dev)) { |
296 | ppgtt->pte_encode = hsw_pte_encode; | |
297 | } else if (IS_VALLEYVIEW(dev)) { | |
93c34e70 KG |
298 | ppgtt->pte_encode = byt_pte_encode; |
299 | } else { | |
300 | ppgtt->pte_encode = gen6_pte_encode; | |
301 | } | |
6670a5a5 | 302 | ppgtt->num_pd_entries = GEN6_PPGTT_PD_ENTRIES; |
6197349b | 303 | ppgtt->enable = gen6_ppgtt_enable; |
def886c3 DV |
304 | ppgtt->clear_range = gen6_ppgtt_clear_range; |
305 | ppgtt->insert_entries = gen6_ppgtt_insert_entries; | |
3440d265 | 306 | ppgtt->cleanup = gen6_ppgtt_cleanup; |
1d2a314c DV |
307 | ppgtt->pt_pages = kzalloc(sizeof(struct page *)*ppgtt->num_pd_entries, |
308 | GFP_KERNEL); | |
309 | if (!ppgtt->pt_pages) | |
3440d265 | 310 | return -ENOMEM; |
1d2a314c DV |
311 | |
312 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
313 | ppgtt->pt_pages[i] = alloc_page(GFP_KERNEL); | |
314 | if (!ppgtt->pt_pages[i]) | |
315 | goto err_pt_alloc; | |
316 | } | |
317 | ||
8d2e6308 BW |
318 | ppgtt->pt_dma_addr = kzalloc(sizeof(dma_addr_t) *ppgtt->num_pd_entries, |
319 | GFP_KERNEL); | |
320 | if (!ppgtt->pt_dma_addr) | |
321 | goto err_pt_alloc; | |
1d2a314c | 322 | |
8d2e6308 BW |
323 | for (i = 0; i < ppgtt->num_pd_entries; i++) { |
324 | dma_addr_t pt_addr; | |
211c568b | 325 | |
8d2e6308 BW |
326 | pt_addr = pci_map_page(dev->pdev, ppgtt->pt_pages[i], 0, 4096, |
327 | PCI_DMA_BIDIRECTIONAL); | |
1d2a314c | 328 | |
8d2e6308 BW |
329 | if (pci_dma_mapping_error(dev->pdev, pt_addr)) { |
330 | ret = -EIO; | |
331 | goto err_pd_pin; | |
1d2a314c | 332 | |
211c568b | 333 | } |
8d2e6308 | 334 | ppgtt->pt_dma_addr[i] = pt_addr; |
1d2a314c | 335 | } |
1d2a314c | 336 | |
def886c3 DV |
337 | ppgtt->clear_range(ppgtt, 0, |
338 | ppgtt->num_pd_entries*I915_PPGTT_PT_ENTRIES); | |
1d2a314c | 339 | |
e7c2b58b | 340 | ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t); |
1d2a314c | 341 | |
1d2a314c DV |
342 | return 0; |
343 | ||
344 | err_pd_pin: | |
345 | if (ppgtt->pt_dma_addr) { | |
346 | for (i--; i >= 0; i--) | |
347 | pci_unmap_page(dev->pdev, ppgtt->pt_dma_addr[i], | |
348 | 4096, PCI_DMA_BIDIRECTIONAL); | |
349 | } | |
350 | err_pt_alloc: | |
351 | kfree(ppgtt->pt_dma_addr); | |
352 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
353 | if (ppgtt->pt_pages[i]) | |
354 | __free_page(ppgtt->pt_pages[i]); | |
355 | } | |
356 | kfree(ppgtt->pt_pages); | |
3440d265 DV |
357 | |
358 | return ret; | |
359 | } | |
360 | ||
361 | static int i915_gem_init_aliasing_ppgtt(struct drm_device *dev) | |
362 | { | |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
364 | struct i915_hw_ppgtt *ppgtt; | |
365 | int ret; | |
366 | ||
367 | ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); | |
368 | if (!ppgtt) | |
369 | return -ENOMEM; | |
370 | ||
371 | ppgtt->dev = dev; | |
372 | ||
3ed124b2 BW |
373 | if (INTEL_INFO(dev)->gen < 8) |
374 | ret = gen6_ppgtt_init(ppgtt); | |
375 | else | |
376 | BUG(); | |
377 | ||
3440d265 DV |
378 | if (ret) |
379 | kfree(ppgtt); | |
380 | else | |
381 | dev_priv->mm.aliasing_ppgtt = ppgtt; | |
1d2a314c DV |
382 | |
383 | return ret; | |
384 | } | |
385 | ||
386 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev) | |
387 | { | |
388 | struct drm_i915_private *dev_priv = dev->dev_private; | |
389 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1d2a314c DV |
390 | |
391 | if (!ppgtt) | |
392 | return; | |
393 | ||
3440d265 | 394 | ppgtt->cleanup(ppgtt); |
5963cf04 | 395 | dev_priv->mm.aliasing_ppgtt = NULL; |
1d2a314c DV |
396 | } |
397 | ||
7bddb01f DV |
398 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
399 | struct drm_i915_gem_object *obj, | |
400 | enum i915_cache_level cache_level) | |
401 | { | |
def886c3 | 402 | ppgtt->insert_entries(ppgtt, obj->pages, |
f343c5f6 | 403 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, |
def886c3 | 404 | cache_level); |
7bddb01f DV |
405 | } |
406 | ||
407 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
408 | struct drm_i915_gem_object *obj) | |
409 | { | |
def886c3 | 410 | ppgtt->clear_range(ppgtt, |
f343c5f6 | 411 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, |
def886c3 | 412 | obj->base.size >> PAGE_SHIFT); |
7bddb01f DV |
413 | } |
414 | ||
a81cc00c BW |
415 | extern int intel_iommu_gfx_mapped; |
416 | /* Certain Gen5 chipsets require require idling the GPU before | |
417 | * unmapping anything from the GTT when VT-d is enabled. | |
418 | */ | |
419 | static inline bool needs_idle_maps(struct drm_device *dev) | |
420 | { | |
421 | #ifdef CONFIG_INTEL_IOMMU | |
422 | /* Query intel_iommu to see if we need the workaround. Presumably that | |
423 | * was loaded first. | |
424 | */ | |
425 | if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) | |
426 | return true; | |
427 | #endif | |
428 | return false; | |
429 | } | |
430 | ||
5c042287 BW |
431 | static bool do_idling(struct drm_i915_private *dev_priv) |
432 | { | |
433 | bool ret = dev_priv->mm.interruptible; | |
434 | ||
a81cc00c | 435 | if (unlikely(dev_priv->gtt.do_idle_maps)) { |
5c042287 | 436 | dev_priv->mm.interruptible = false; |
b2da9fe5 | 437 | if (i915_gpu_idle(dev_priv->dev)) { |
5c042287 BW |
438 | DRM_ERROR("Couldn't idle GPU\n"); |
439 | /* Wait a bit, in hopes it avoids the hang */ | |
440 | udelay(10); | |
441 | } | |
442 | } | |
443 | ||
444 | return ret; | |
445 | } | |
446 | ||
447 | static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) | |
448 | { | |
a81cc00c | 449 | if (unlikely(dev_priv->gtt.do_idle_maps)) |
5c042287 BW |
450 | dev_priv->mm.interruptible = interruptible; |
451 | } | |
452 | ||
76aaf220 DV |
453 | void i915_gem_restore_gtt_mappings(struct drm_device *dev) |
454 | { | |
455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 456 | struct drm_i915_gem_object *obj; |
76aaf220 | 457 | |
bee4a186 | 458 | /* First fill our portion of the GTT with scratch pages */ |
7faf1ab2 DV |
459 | dev_priv->gtt.gtt_clear_range(dev, dev_priv->gtt.start / PAGE_SIZE, |
460 | dev_priv->gtt.total / PAGE_SIZE); | |
bee4a186 | 461 | |
35c20a60 | 462 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
a8e93126 | 463 | i915_gem_clflush_object(obj); |
74163907 | 464 | i915_gem_gtt_bind_object(obj, obj->cache_level); |
76aaf220 DV |
465 | } |
466 | ||
e76e9aeb | 467 | i915_gem_chipset_flush(dev); |
76aaf220 | 468 | } |
7c2e6fdf | 469 | |
74163907 | 470 | int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) |
7c2e6fdf | 471 | { |
9da3da66 | 472 | if (obj->has_dma_mapping) |
74163907 | 473 | return 0; |
9da3da66 CW |
474 | |
475 | if (!dma_map_sg(&obj->base.dev->pdev->dev, | |
476 | obj->pages->sgl, obj->pages->nents, | |
477 | PCI_DMA_BIDIRECTIONAL)) | |
478 | return -ENOSPC; | |
479 | ||
480 | return 0; | |
7c2e6fdf DV |
481 | } |
482 | ||
e76e9aeb BW |
483 | /* |
484 | * Binds an object into the global gtt with the specified cache level. The object | |
485 | * will be accessible to the GPU via commands whose operands reference offsets | |
486 | * within the global GTT as well as accessible by the GPU through the GMADR | |
487 | * mapped BAR (dev_priv->mm.gtt->gtt). | |
488 | */ | |
7faf1ab2 DV |
489 | static void gen6_ggtt_insert_entries(struct drm_device *dev, |
490 | struct sg_table *st, | |
491 | unsigned int first_entry, | |
492 | enum i915_cache_level level) | |
e76e9aeb | 493 | { |
e76e9aeb | 494 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7c2b58b BW |
495 | gen6_gtt_pte_t __iomem *gtt_entries = |
496 | (gen6_gtt_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; | |
6e995e23 ID |
497 | int i = 0; |
498 | struct sg_page_iter sg_iter; | |
e76e9aeb BW |
499 | dma_addr_t addr; |
500 | ||
6e995e23 | 501 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { |
2db76d7c | 502 | addr = sg_page_iter_dma_address(&sg_iter); |
80a74f7f | 503 | iowrite32(dev_priv->gtt.pte_encode(addr, level), |
2d04befb | 504 | >t_entries[i]); |
6e995e23 | 505 | i++; |
e76e9aeb BW |
506 | } |
507 | ||
e76e9aeb BW |
508 | /* XXX: This serves as a posting read to make sure that the PTE has |
509 | * actually been updated. There is some concern that even though | |
510 | * registers and PTEs are within the same BAR that they are potentially | |
511 | * of NUMA access patterns. Therefore, even with the way we assume | |
512 | * hardware should work, we must keep this posting read for paranoia. | |
513 | */ | |
514 | if (i != 0) | |
960e3e42 | 515 | WARN_ON(readl(>t_entries[i-1]) |
80a74f7f | 516 | != dev_priv->gtt.pte_encode(addr, level)); |
0f9b91c7 BW |
517 | |
518 | /* This next bit makes the above posting read even more important. We | |
519 | * want to flush the TLBs only after we're certain all the PTE updates | |
520 | * have finished. | |
521 | */ | |
522 | I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); | |
523 | POSTING_READ(GFX_FLSH_CNTL_GEN6); | |
e76e9aeb BW |
524 | } |
525 | ||
7faf1ab2 DV |
526 | static void gen6_ggtt_clear_range(struct drm_device *dev, |
527 | unsigned int first_entry, | |
528 | unsigned int num_entries) | |
529 | { | |
530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e7c2b58b BW |
531 | gen6_gtt_pte_t scratch_pte, __iomem *gtt_base = |
532 | (gen6_gtt_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; | |
a54c0c27 | 533 | const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; |
7faf1ab2 DV |
534 | int i; |
535 | ||
536 | if (WARN(num_entries > max_entries, | |
537 | "First entry = %d; Num entries = %d (max=%d)\n", | |
538 | first_entry, num_entries, max_entries)) | |
539 | num_entries = max_entries; | |
540 | ||
80a74f7f | 541 | scratch_pte = dev_priv->gtt.pte_encode(dev_priv->gtt.scratch.addr, |
2d04befb | 542 | I915_CACHE_LLC); |
7faf1ab2 DV |
543 | for (i = 0; i < num_entries; i++) |
544 | iowrite32(scratch_pte, >t_base[i]); | |
545 | readl(gtt_base); | |
546 | } | |
547 | ||
548 | ||
549 | static void i915_ggtt_insert_entries(struct drm_device *dev, | |
550 | struct sg_table *st, | |
551 | unsigned int pg_start, | |
552 | enum i915_cache_level cache_level) | |
553 | { | |
554 | unsigned int flags = (cache_level == I915_CACHE_NONE) ? | |
555 | AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; | |
556 | ||
557 | intel_gtt_insert_sg_entries(st, pg_start, flags); | |
558 | ||
559 | } | |
560 | ||
561 | static void i915_ggtt_clear_range(struct drm_device *dev, | |
562 | unsigned int first_entry, | |
563 | unsigned int num_entries) | |
564 | { | |
565 | intel_gtt_clear_range(first_entry, num_entries); | |
566 | } | |
567 | ||
568 | ||
74163907 DV |
569 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, |
570 | enum i915_cache_level cache_level) | |
d5bd1449 CW |
571 | { |
572 | struct drm_device *dev = obj->base.dev; | |
7faf1ab2 DV |
573 | struct drm_i915_private *dev_priv = dev->dev_private; |
574 | ||
575 | dev_priv->gtt.gtt_insert_entries(dev, obj->pages, | |
f343c5f6 | 576 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, |
7faf1ab2 | 577 | cache_level); |
d5bd1449 | 578 | |
74898d7e | 579 | obj->has_global_gtt_mapping = 1; |
d5bd1449 CW |
580 | } |
581 | ||
05394f39 | 582 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj) |
74163907 | 583 | { |
7faf1ab2 DV |
584 | struct drm_device *dev = obj->base.dev; |
585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
586 | ||
587 | dev_priv->gtt.gtt_clear_range(obj->base.dev, | |
f343c5f6 | 588 | i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT, |
7faf1ab2 | 589 | obj->base.size >> PAGE_SHIFT); |
74898d7e DV |
590 | |
591 | obj->has_global_gtt_mapping = 0; | |
74163907 DV |
592 | } |
593 | ||
594 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) | |
7c2e6fdf | 595 | { |
5c042287 BW |
596 | struct drm_device *dev = obj->base.dev; |
597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
598 | bool interruptible; | |
599 | ||
600 | interruptible = do_idling(dev_priv); | |
601 | ||
9da3da66 CW |
602 | if (!obj->has_dma_mapping) |
603 | dma_unmap_sg(&dev->pdev->dev, | |
604 | obj->pages->sgl, obj->pages->nents, | |
605 | PCI_DMA_BIDIRECTIONAL); | |
5c042287 BW |
606 | |
607 | undo_idling(dev_priv, interruptible); | |
7c2e6fdf | 608 | } |
644ec02b | 609 | |
42d6ab48 CW |
610 | static void i915_gtt_color_adjust(struct drm_mm_node *node, |
611 | unsigned long color, | |
612 | unsigned long *start, | |
613 | unsigned long *end) | |
614 | { | |
615 | if (node->color != color) | |
616 | *start += 4096; | |
617 | ||
618 | if (!list_empty(&node->node_list)) { | |
619 | node = list_entry(node->node_list.next, | |
620 | struct drm_mm_node, | |
621 | node_list); | |
622 | if (node->allocated && node->color != color) | |
623 | *end -= 4096; | |
624 | } | |
625 | } | |
d7e5008f BW |
626 | void i915_gem_setup_global_gtt(struct drm_device *dev, |
627 | unsigned long start, | |
628 | unsigned long mappable_end, | |
629 | unsigned long end) | |
644ec02b | 630 | { |
e78891ca BW |
631 | /* Let GEM Manage all of the aperture. |
632 | * | |
633 | * However, leave one page at the end still bound to the scratch page. | |
634 | * There are a number of places where the hardware apparently prefetches | |
635 | * past the end of the object, and we've seen multiple hangs with the | |
636 | * GPU head pointer stuck in a batchbuffer bound at the last page of the | |
637 | * aperture. One page should be enough to keep any prefetching inside | |
638 | * of the aperture. | |
639 | */ | |
644ec02b | 640 | drm_i915_private_t *dev_priv = dev->dev_private; |
ed2f3452 CW |
641 | struct drm_mm_node *entry; |
642 | struct drm_i915_gem_object *obj; | |
643 | unsigned long hole_start, hole_end; | |
644ec02b | 644 | |
35451cb6 BW |
645 | BUG_ON(mappable_end > end); |
646 | ||
ed2f3452 | 647 | /* Subtract the guard page ... */ |
d1dd20a9 | 648 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start - PAGE_SIZE); |
42d6ab48 CW |
649 | if (!HAS_LLC(dev)) |
650 | dev_priv->mm.gtt_space.color_adjust = i915_gtt_color_adjust; | |
644ec02b | 651 | |
ed2f3452 | 652 | /* Mark any preallocated objects as occupied */ |
35c20a60 | 653 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { |
b3a070cc | 654 | int ret; |
edd41a87 | 655 | DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", |
c6cfb325 BW |
656 | i915_gem_obj_ggtt_offset(obj), obj->base.size); |
657 | ||
658 | WARN_ON(i915_gem_obj_ggtt_bound(obj)); | |
338710e7 | 659 | ret = drm_mm_reserve_node(&dev_priv->mm.gtt_space, |
c6cfb325 BW |
660 | &obj->gtt_space); |
661 | if (ret) | |
b3a070cc | 662 | DRM_DEBUG_KMS("Reservation failed\n"); |
ed2f3452 CW |
663 | obj->has_global_gtt_mapping = 1; |
664 | } | |
665 | ||
5d4545ae | 666 | dev_priv->gtt.start = start; |
5d4545ae | 667 | dev_priv->gtt.total = end - start; |
644ec02b | 668 | |
ed2f3452 CW |
669 | /* Clear any non-preallocated blocks */ |
670 | drm_mm_for_each_hole(entry, &dev_priv->mm.gtt_space, | |
671 | hole_start, hole_end) { | |
672 | DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", | |
673 | hole_start, hole_end); | |
7faf1ab2 DV |
674 | dev_priv->gtt.gtt_clear_range(dev, hole_start / PAGE_SIZE, |
675 | (hole_end-hole_start) / PAGE_SIZE); | |
ed2f3452 CW |
676 | } |
677 | ||
678 | /* And finally clear the reserved guard page */ | |
7faf1ab2 | 679 | dev_priv->gtt.gtt_clear_range(dev, end / PAGE_SIZE - 1, 1); |
e76e9aeb BW |
680 | } |
681 | ||
d7e5008f BW |
682 | static bool |
683 | intel_enable_ppgtt(struct drm_device *dev) | |
684 | { | |
685 | if (i915_enable_ppgtt >= 0) | |
686 | return i915_enable_ppgtt; | |
687 | ||
688 | #ifdef CONFIG_INTEL_IOMMU | |
689 | /* Disable ppgtt on SNB if VT-d is on. */ | |
690 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
691 | return false; | |
692 | #endif | |
693 | ||
694 | return true; | |
695 | } | |
696 | ||
697 | void i915_gem_init_global_gtt(struct drm_device *dev) | |
698 | { | |
699 | struct drm_i915_private *dev_priv = dev->dev_private; | |
700 | unsigned long gtt_size, mappable_size; | |
d7e5008f | 701 | |
a54c0c27 | 702 | gtt_size = dev_priv->gtt.total; |
93d18799 | 703 | mappable_size = dev_priv->gtt.mappable_end; |
d7e5008f BW |
704 | |
705 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
e78891ca | 706 | int ret; |
3eb1c005 BW |
707 | |
708 | if (INTEL_INFO(dev)->gen <= 7) { | |
709 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
710 | * aperture accordingly when using aliasing ppgtt. */ | |
6670a5a5 | 711 | gtt_size -= GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
3eb1c005 | 712 | } |
d7e5008f BW |
713 | |
714 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); | |
715 | ||
716 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
e78891ca | 717 | if (!ret) |
d7e5008f | 718 | return; |
e78891ca BW |
719 | |
720 | DRM_ERROR("Aliased PPGTT setup failed %d\n", ret); | |
721 | drm_mm_takedown(&dev_priv->mm.gtt_space); | |
6670a5a5 | 722 | gtt_size += GEN6_PPGTT_PD_ENTRIES * PAGE_SIZE; |
d7e5008f | 723 | } |
e78891ca | 724 | i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); |
e76e9aeb BW |
725 | } |
726 | ||
727 | static int setup_scratch_page(struct drm_device *dev) | |
728 | { | |
729 | struct drm_i915_private *dev_priv = dev->dev_private; | |
730 | struct page *page; | |
731 | dma_addr_t dma_addr; | |
732 | ||
733 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); | |
734 | if (page == NULL) | |
735 | return -ENOMEM; | |
736 | get_page(page); | |
737 | set_pages_uc(page, 1); | |
738 | ||
739 | #ifdef CONFIG_INTEL_IOMMU | |
740 | dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, | |
741 | PCI_DMA_BIDIRECTIONAL); | |
742 | if (pci_dma_mapping_error(dev->pdev, dma_addr)) | |
743 | return -EINVAL; | |
744 | #else | |
745 | dma_addr = page_to_phys(page); | |
746 | #endif | |
67167240 BW |
747 | dev_priv->gtt.scratch.page = page; |
748 | dev_priv->gtt.scratch.addr = dma_addr; | |
e76e9aeb BW |
749 | |
750 | return 0; | |
751 | } | |
752 | ||
753 | static void teardown_scratch_page(struct drm_device *dev) | |
754 | { | |
755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
67167240 BW |
756 | set_pages_wb(dev_priv->gtt.scratch.page, 1); |
757 | pci_unmap_page(dev->pdev, dev_priv->gtt.scratch.addr, | |
e76e9aeb | 758 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
67167240 BW |
759 | put_page(dev_priv->gtt.scratch.page); |
760 | __free_page(dev_priv->gtt.scratch.page); | |
e76e9aeb BW |
761 | } |
762 | ||
763 | static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) | |
764 | { | |
765 | snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; | |
766 | snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; | |
767 | return snb_gmch_ctl << 20; | |
768 | } | |
769 | ||
baa09f5f | 770 | static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) |
e76e9aeb BW |
771 | { |
772 | snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; | |
773 | snb_gmch_ctl &= SNB_GMCH_GMS_MASK; | |
774 | return snb_gmch_ctl << 25; /* 32 MB units */ | |
775 | } | |
776 | ||
baa09f5f BW |
777 | static int gen6_gmch_probe(struct drm_device *dev, |
778 | size_t *gtt_total, | |
41907ddc BW |
779 | size_t *stolen, |
780 | phys_addr_t *mappable_base, | |
781 | unsigned long *mappable_end) | |
e76e9aeb BW |
782 | { |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
784 | phys_addr_t gtt_bus_addr; | |
baa09f5f | 785 | unsigned int gtt_size; |
e76e9aeb | 786 | u16 snb_gmch_ctl; |
e76e9aeb BW |
787 | int ret; |
788 | ||
41907ddc BW |
789 | *mappable_base = pci_resource_start(dev->pdev, 2); |
790 | *mappable_end = pci_resource_len(dev->pdev, 2); | |
791 | ||
baa09f5f BW |
792 | /* 64/512MB is the current min/max we actually know of, but this is just |
793 | * a coarse sanity check. | |
e76e9aeb | 794 | */ |
41907ddc | 795 | if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { |
baa09f5f BW |
796 | DRM_ERROR("Unknown GMADR size (%lx)\n", |
797 | dev_priv->gtt.mappable_end); | |
798 | return -ENXIO; | |
e76e9aeb BW |
799 | } |
800 | ||
e76e9aeb BW |
801 | if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) |
802 | pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); | |
e76e9aeb | 803 | pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); |
baa09f5f | 804 | gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); |
e76e9aeb | 805 | |
c4ae25ec | 806 | *stolen = gen6_get_stolen_size(snb_gmch_ctl); |
e7c2b58b | 807 | *gtt_total = (gtt_size / sizeof(gen6_gtt_pte_t)) << PAGE_SHIFT; |
e76e9aeb | 808 | |
a93e4161 BW |
809 | /* For Modern GENs the PTEs and register space are split in the BAR */ |
810 | gtt_bus_addr = pci_resource_start(dev->pdev, 0) + | |
811 | (pci_resource_len(dev->pdev, 0) / 2); | |
812 | ||
baa09f5f | 813 | dev_priv->gtt.gsm = ioremap_wc(gtt_bus_addr, gtt_size); |
5d4545ae | 814 | if (!dev_priv->gtt.gsm) { |
e76e9aeb | 815 | DRM_ERROR("Failed to map the gtt page table\n"); |
baa09f5f | 816 | return -ENOMEM; |
e76e9aeb BW |
817 | } |
818 | ||
baa09f5f BW |
819 | ret = setup_scratch_page(dev); |
820 | if (ret) | |
821 | DRM_ERROR("Scratch setup failed\n"); | |
e76e9aeb | 822 | |
7faf1ab2 DV |
823 | dev_priv->gtt.gtt_clear_range = gen6_ggtt_clear_range; |
824 | dev_priv->gtt.gtt_insert_entries = gen6_ggtt_insert_entries; | |
825 | ||
e76e9aeb BW |
826 | return ret; |
827 | } | |
828 | ||
d93c6233 | 829 | static void gen6_gmch_remove(struct drm_device *dev) |
e76e9aeb BW |
830 | { |
831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5d4545ae | 832 | iounmap(dev_priv->gtt.gsm); |
baa09f5f | 833 | teardown_scratch_page(dev_priv->dev); |
644ec02b | 834 | } |
baa09f5f BW |
835 | |
836 | static int i915_gmch_probe(struct drm_device *dev, | |
837 | size_t *gtt_total, | |
41907ddc BW |
838 | size_t *stolen, |
839 | phys_addr_t *mappable_base, | |
840 | unsigned long *mappable_end) | |
baa09f5f BW |
841 | { |
842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
843 | int ret; | |
844 | ||
baa09f5f BW |
845 | ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); |
846 | if (!ret) { | |
847 | DRM_ERROR("failed to set up gmch\n"); | |
848 | return -EIO; | |
849 | } | |
850 | ||
41907ddc | 851 | intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); |
baa09f5f BW |
852 | |
853 | dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); | |
854 | dev_priv->gtt.gtt_clear_range = i915_ggtt_clear_range; | |
855 | dev_priv->gtt.gtt_insert_entries = i915_ggtt_insert_entries; | |
856 | ||
857 | return 0; | |
858 | } | |
859 | ||
860 | static void i915_gmch_remove(struct drm_device *dev) | |
861 | { | |
862 | intel_gmch_remove(); | |
863 | } | |
864 | ||
865 | int i915_gem_gtt_init(struct drm_device *dev) | |
866 | { | |
867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
868 | struct i915_gtt *gtt = &dev_priv->gtt; | |
baa09f5f BW |
869 | int ret; |
870 | ||
baa09f5f | 871 | if (INTEL_INFO(dev)->gen <= 5) { |
b2f21b4d BW |
872 | gtt->gtt_probe = i915_gmch_probe; |
873 | gtt->gtt_remove = i915_gmch_remove; | |
baa09f5f | 874 | } else { |
b2f21b4d BW |
875 | gtt->gtt_probe = gen6_gmch_probe; |
876 | gtt->gtt_remove = gen6_gmch_remove; | |
4d15c145 BW |
877 | if (IS_HASWELL(dev) && dev_priv->ellc_size) |
878 | gtt->pte_encode = iris_pte_encode; | |
879 | else if (IS_HASWELL(dev)) | |
b2f21b4d BW |
880 | gtt->pte_encode = hsw_pte_encode; |
881 | else if (IS_VALLEYVIEW(dev)) | |
882 | gtt->pte_encode = byt_pte_encode; | |
883 | else | |
884 | gtt->pte_encode = gen6_pte_encode; | |
baa09f5f BW |
885 | } |
886 | ||
b2f21b4d BW |
887 | ret = gtt->gtt_probe(dev, >t->total, >t->stolen_size, |
888 | >t->mappable_base, >t->mappable_end); | |
a54c0c27 | 889 | if (ret) |
baa09f5f | 890 | return ret; |
baa09f5f | 891 | |
baa09f5f | 892 | /* GMADR is the PCI mmio aperture into the global GTT. */ |
b2f21b4d BW |
893 | DRM_INFO("Memory usable by graphics device = %zdM\n", gtt->total >> 20); |
894 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); | |
895 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | |
baa09f5f BW |
896 | |
897 | return 0; | |
898 | } |