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drm/i915: fix typo in function name
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179
JB		 938
939 reg = PIPECONF(pipe);
940 val = I915_READ(reg);
63d7bbe9
JB		 941 cur_state = !!(val & PIPECONF_ENABLE);
942 WARN(cur_state != state,
943 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 944 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 945}
946
947static void assert_plane_enabled(struct drm_i915_private *dev_priv,
948 enum plane plane)
949{
950 int reg;
951 u32 val;
952
953 reg = DSPCNTR(plane);
954 val = I915_READ(reg);
955 WARN(!(val & DISPLAY_PLANE_ENABLE),
956 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 957 plane_name(plane));
b24e7179
JB		 958}
959
960static void assert_planes_disabled(struct drm_i915_private *dev_priv,
961 enum pipe pipe)
962{
963 int reg, i;
964 u32 val;
965 int cur_pipe;
966
19ec1358
JB		 967 /* Planes are fixed to pipes on ILK+ */
968 if (HAS_PCH_SPLIT(dev_priv->dev))
969 return;
970
b24e7179
JB		 971 /* Need to check both planes against the pipe */
972 for (i = 0; i < 2; i++) {
973 reg = DSPCNTR(i);
974 val = I915_READ(reg);
975 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
976 DISPPLANE_SEL_PIPE_SHIFT;
977 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 978 "plane %c assertion failure, should be off on pipe %c but is still active\n",
979 plane_name(i), pipe_name(pipe));
b24e7179
JB		 980 }
981}
982
92f2584a
JB		 983static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
984{
985 u32 val;
986 bool enabled;
987
988 val = I915_READ(PCH_DREF_CONTROL);
989 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
990 DREF_SUPERSPREAD_SOURCE_MASK));
991 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
992}
993
994static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
995 enum pipe pipe)
996{
997 int reg;
998 u32 val;
999 bool enabled;
1000
1001 reg = TRANSCONF(pipe);
1002 val = I915_READ(reg);
1003 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1004 WARN(enabled,
1005 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1006 pipe_name(pipe));
92f2584a
JB		 1007}
1008
4e634389
KP		 1009static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1011{
1012 if ((val & DP_PORT_EN) == 0)
1013 return false;
1014
1015 if (HAS_PCH_CPT(dev_priv->dev)) {
1016 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1017 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1018 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1019 return false;
1020 } else {
1021 if ((val & DP_PIPE_MASK) != (pipe << 30))
1022 return false;
1023 }
1024 return true;
1025}
1026
1519b995
KP		 1027static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1028 enum pipe pipe, u32 val)
1029{
1030 if ((val & PORT_ENABLE) == 0)
1031 return false;
1032
1033 if (HAS_PCH_CPT(dev_priv->dev)) {
1034 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1035 return false;
1036 } else {
1037 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1038 return false;
1039 }
1040 return true;
1041}
1042
1043static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1044 enum pipe pipe, u32 val)
1045{
1046 if ((val & LVDS_PORT_EN) == 0)
1047 return false;
1048
1049 if (HAS_PCH_CPT(dev_priv->dev)) {
1050 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1051 return false;
1052 } else {
1053 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1054 return false;
1055 }
1056 return true;
1057}
1058
1059static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1060 enum pipe pipe, u32 val)
1061{
1062 if ((val & ADPA_DAC_ENABLE) == 0)
1063 return false;
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
291906f1 1074static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1075 enum pipe pipe, int reg, u32 port_sel)
291906f1 1076{
47a05eca 1077 u32 val = I915_READ(reg);
4e634389 1078 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1079 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1080 reg, pipe_name(pipe));
291906f1
JB		 1081}
1082
1083static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, int reg)
1085{
47a05eca 1086 u32 val = I915_READ(reg);
1519b995 1087 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1088 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1089 reg, pipe_name(pipe));
291906f1
JB		 1090}
1091
1092static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1093 enum pipe pipe)
1094{
1095 int reg;
1096 u32 val;
291906f1 1097
f0575e92
KP		 1098 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1099 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1100 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1101
1102 reg = PCH_ADPA;
1103 val = I915_READ(reg);
1519b995 1104 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1105 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1106 pipe_name(pipe));
291906f1
JB		 1107
1108 reg = PCH_LVDS;
1109 val = I915_READ(reg);
1519b995 1110 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1111 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1112 pipe_name(pipe));
291906f1
JB		 1113
1114 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1115 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1116 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1117}
1118
63d7bbe9
JB		 1119/**
1120 * intel_enable_pll - enable a PLL
1121 * @dev_priv: i915 private structure
1122 * @pipe: pipe PLL to enable
1123 *
1124 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1125 * make sure the PLL reg is writable first though, since the panel write
1126 * protect mechanism may be enabled.
1127 *
1128 * Note! This is for pre-ILK only.
1129 */
1130static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1131{
1132 int reg;
1133 u32 val;
1134
1135 /* No really, not for ILK+ */
1136 BUG_ON(dev_priv->info->gen >= 5);
1137
1138 /* PLL is protected by panel, make sure we can write it */
1139 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1140 assert_panel_unlocked(dev_priv, pipe);
1141
1142 reg = DPLL(pipe);
1143 val = I915_READ(reg);
1144 val |= DPLL_VCO_ENABLE;
1145
1146 /* We do this three times for luck */
1147 I915_WRITE(reg, val);
1148 POSTING_READ(reg);
1149 udelay(150); /* wait for warmup */
1150 I915_WRITE(reg, val);
1151 POSTING_READ(reg);
1152 udelay(150); /* wait for warmup */
1153 I915_WRITE(reg, val);
1154 POSTING_READ(reg);
1155 udelay(150); /* wait for warmup */
1156}
1157
1158/**
1159 * intel_disable_pll - disable a PLL
1160 * @dev_priv: i915 private structure
1161 * @pipe: pipe PLL to disable
1162 *
1163 * Disable the PLL for @pipe, making sure the pipe is off first.
1164 *
1165 * Note! This is for pre-ILK only.
1166 */
1167static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1168{
1169 int reg;
1170 u32 val;
1171
1172 /* Don't disable pipe A or pipe A PLLs if needed */
1173 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1174 return;
1175
1176 /* Make sure the pipe isn't still relying on us */
1177 assert_pipe_disabled(dev_priv, pipe);
1178
1179 reg = DPLL(pipe);
1180 val = I915_READ(reg);
1181 val &= ~DPLL_VCO_ENABLE;
1182 I915_WRITE(reg, val);
1183 POSTING_READ(reg);
1184}
1185
92f2584a
JB		 1186/**
1187 * intel_enable_pch_pll - enable PCH PLL
1188 * @dev_priv: i915 private structure
1189 * @pipe: pipe PLL to enable
1190 *
1191 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1192 * drives the transcoder clock.
1193 */
1194static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1195 enum pipe pipe)
1196{
1197 int reg;
1198 u32 val;
1199
4c609cb8
JB		 1200 if (pipe > 1)
1201 return;
1202
92f2584a
JB		 1203 /* PCH only available on ILK+ */
1204 BUG_ON(dev_priv->info->gen < 5);
1205
1206 /* PCH refclock must be enabled first */
1207 assert_pch_refclk_enabled(dev_priv);
1208
1209 reg = PCH_DPLL(pipe);
1210 val = I915_READ(reg);
1211 val |= DPLL_VCO_ENABLE;
1212 I915_WRITE(reg, val);
1213 POSTING_READ(reg);
1214 udelay(200);
1215}
1216
1217static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe)
1219{
1220 int reg;
7a419866
JB		 1221 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1222 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1223
4c609cb8
JB		 1224 if (pipe > 1)
1225 return;
1226
92f2584a
JB		 1227 /* PCH only available on ILK+ */
1228 BUG_ON(dev_priv->info->gen < 5);
1229
1230 /* Make sure transcoder isn't still depending on us */
1231 assert_transcoder_disabled(dev_priv, pipe);
1232
7a419866
JB		 1233 if (pipe == 0)
1234 pll_sel |= TRANSC_DPLLA_SEL;
1235 else if (pipe == 1)
1236 pll_sel |= TRANSC_DPLLB_SEL;
1237
1238
1239 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1240 return;
1241
92f2584a
JB		 1242 reg = PCH_DPLL(pipe);
1243 val = I915_READ(reg);
1244 val &= ~DPLL_VCO_ENABLE;
1245 I915_WRITE(reg, val);
1246 POSTING_READ(reg);
1247 udelay(200);
1248}
1249
040484af
JB		 1250static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252{
1253 int reg;
1254 u32 val;
1255
1256 /* PCH only available on ILK+ */
1257 BUG_ON(dev_priv->info->gen < 5);
1258
1259 /* Make sure PCH DPLL is enabled */
1260 assert_pch_pll_enabled(dev_priv, pipe);
1261
1262 /* FDI must be feeding us bits for PCH ports */
1263 assert_fdi_tx_enabled(dev_priv, pipe);
1264 assert_fdi_rx_enabled(dev_priv, pipe);
1265
1266 reg = TRANSCONF(pipe);
1267 val = I915_READ(reg);
e9bcff5c
JB		 1268
1269 if (HAS_PCH_IBX(dev_priv->dev)) {
1270 /*
1271 * make the BPC in transcoder be consistent with
1272 * that in pipeconf reg.
1273 */
1274 val &= ~PIPE_BPC_MASK;
1275 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1276 }
040484af
JB		 1277 I915_WRITE(reg, val | TRANS_ENABLE);
1278 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1279 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1280}
1281
1282static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
1287
1288 /* FDI relies on the transcoder */
1289 assert_fdi_tx_disabled(dev_priv, pipe);
1290 assert_fdi_rx_disabled(dev_priv, pipe);
1291
291906f1
JB		 1292 /* Ports must be off as well */
1293 assert_pch_ports_disabled(dev_priv, pipe);
1294
040484af
JB		 1295 reg = TRANSCONF(pipe);
1296 val = I915_READ(reg);
1297 val &= ~TRANS_ENABLE;
1298 I915_WRITE(reg, val);
1299 /* wait for PCH transcoder off, transcoder state */
1300 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1301 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1302}
1303
b24e7179 1304/**
309cfea8 1305 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe to enable
040484af 1308 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1309 *
1310 * Enable @pipe, making sure that various hardware specific requirements
1311 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1312 *
1313 * @pipe should be %PIPE_A or %PIPE_B.
1314 *
1315 * Will wait until the pipe is actually running (i.e. first vblank) before
1316 * returning.
1317 */
040484af
JB		 1318static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1319 bool pch_port)
b24e7179
JB		 1320{
1321 int reg;
1322 u32 val;
1323
1324 /*
1325 * A pipe without a PLL won't actually be able to drive bits from
1326 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1327 * need the check.
1328 */
1329 if (!HAS_PCH_SPLIT(dev_priv->dev))
1330 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1331 else {
1332 if (pch_port) {
1333 /* if driving the PCH, we need FDI enabled */
1334 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1335 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1336 }
1337 /* FIXME: assert CPU port conditions for SNB+ */
1338 }
b24e7179
JB		 1339
1340 reg = PIPECONF(pipe);
1341 val = I915_READ(reg);
00d70b15
CW		 1342 if (val & PIPECONF_ENABLE)
1343 return;
1344
1345 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1346 intel_wait_for_vblank(dev_priv->dev, pipe);
1347}
1348
1349/**
309cfea8 1350 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1351 * @dev_priv: i915 private structure
1352 * @pipe: pipe to disable
1353 *
1354 * Disable @pipe, making sure that various hardware specific requirements
1355 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1356 *
1357 * @pipe should be %PIPE_A or %PIPE_B.
1358 *
1359 * Will wait until the pipe has shut down before returning.
1360 */
1361static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1362 enum pipe pipe)
1363{
1364 int reg;
1365 u32 val;
1366
1367 /*
1368 * Make sure planes won't keep trying to pump pixels to us,
1369 * or we might hang the display.
1370 */
1371 assert_planes_disabled(dev_priv, pipe);
1372
1373 /* Don't disable pipe A or pipe A PLLs if needed */
1374 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1375 return;
1376
1377 reg = PIPECONF(pipe);
1378 val = I915_READ(reg);
00d70b15
CW		 1379 if ((val & PIPECONF_ENABLE) == 0)
1380 return;
1381
1382 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1383 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1384}
1385
d74362c9
KP		 1386/*
1387 * Plane regs are double buffered, going from enabled->disabled needs a
1388 * trigger in order to latch. The display address reg provides this.
1389 */
1390static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1391 enum plane plane)
1392{
1393 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1394 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1395}
1396
b24e7179
JB		 1397/**
1398 * intel_enable_plane - enable a display plane on a given pipe
1399 * @dev_priv: i915 private structure
1400 * @plane: plane to enable
1401 * @pipe: pipe being fed
1402 *
1403 * Enable @plane on @pipe, making sure that @pipe is running first.
1404 */
1405static void intel_enable_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane, enum pipe pipe)
1407{
1408 int reg;
1409 u32 val;
1410
1411 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1412 assert_pipe_enabled(dev_priv, pipe);
1413
1414 reg = DSPCNTR(plane);
1415 val = I915_READ(reg);
00d70b15
CW		 1416 if (val & DISPLAY_PLANE_ENABLE)
1417 return;
1418
1419 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1420 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1421 intel_wait_for_vblank(dev_priv->dev, pipe);
1422}
1423
b24e7179
JB		 1424/**
1425 * intel_disable_plane - disable a display plane
1426 * @dev_priv: i915 private structure
1427 * @plane: plane to disable
1428 * @pipe: pipe consuming the data
1429 *
1430 * Disable @plane; should be an independent operation.
1431 */
1432static void intel_disable_plane(struct drm_i915_private *dev_priv,
1433 enum plane plane, enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
1437
1438 reg = DSPCNTR(plane);
1439 val = I915_READ(reg);
00d70b15
CW		 1440 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1441 return;
1442
1443 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1444 intel_flush_display_plane(dev_priv, plane);
1445 intel_wait_for_vblank(dev_priv->dev, pipe);
1446}
1447
47a05eca 1448static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1449 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1450{
1451 u32 val = I915_READ(reg);
4e634389 1452 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1453 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1454 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1455 }
47a05eca
JB		 1456}
1457
1458static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1459 enum pipe pipe, int reg)
1460{
1461 u32 val = I915_READ(reg);
1519b995 1462 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1463 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1464 reg, pipe);
47a05eca 1465 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1466 }
47a05eca
JB		 1467}
1468
1469/* Disable any ports connected to this transcoder */
1470static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1471 enum pipe pipe)
1472{
1473 u32 reg, val;
1474
1475 val = I915_READ(PCH_PP_CONTROL);
1476 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1477
f0575e92
KP		 1478 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1479 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1480 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1481
1482 reg = PCH_ADPA;
1483 val = I915_READ(reg);
1519b995 1484 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1485 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1486
1487 reg = PCH_LVDS;
1488 val = I915_READ(reg);
1519b995
KP		 1489 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1490 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1491 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1492 POSTING_READ(reg);
1493 udelay(100);
1494 }
1495
1496 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1497 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1498 disable_pch_hdmi(dev_priv, pipe, HDMID);
1499}
1500
43a9539f
CW		 1501static void i8xx_disable_fbc(struct drm_device *dev)
1502{
1503 struct drm_i915_private *dev_priv = dev->dev_private;
1504 u32 fbc_ctl;
1505
1506 /* Disable compression */
1507 fbc_ctl = I915_READ(FBC_CONTROL);
1508 if ((fbc_ctl & FBC_CTL_EN) == 0)
1509 return;
1510
1511 fbc_ctl &= ~FBC_CTL_EN;
1512 I915_WRITE(FBC_CONTROL, fbc_ctl);
1513
1514 /* Wait for compressing bit to clear */
1515 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1516 DRM_DEBUG_KMS("FBC idle timed out\n");
1517 return;
1518 }
1519
1520 DRM_DEBUG_KMS("disabled FBC\n");
1521}
1522
80824003
JB		 1523static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1524{
1525 struct drm_device *dev = crtc->dev;
1526 struct drm_i915_private *dev_priv = dev->dev_private;
1527 struct drm_framebuffer *fb = crtc->fb;
1528 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1529 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1531 int cfb_pitch;
80824003
JB		 1532 int plane, i;
1533 u32 fbc_ctl, fbc_ctl2;
1534
016b9b61 1535 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1536 if (fb->pitches[0] < cfb_pitch)
1537 cfb_pitch = fb->pitches[0];
80824003
JB		 1538
1539 /* FBC_CTL wants 64B units */
016b9b61
CW		 1540 cfb_pitch = (cfb_pitch / 64) - 1;
1541 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1542
1543 /* Clear old tags */
1544 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1545 I915_WRITE(FBC_TAG + (i * 4), 0);
1546
1547 /* Set it up... */
de568510
CW		 1548 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1549 fbc_ctl2 |= plane;
80824003
JB		 1550 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1551 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1552
1553 /* enable it... */
1554 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1555 if (IS_I945GM(dev))
49677901 1556 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1557 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1558 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1559 fbc_ctl |= obj->fence_reg;
80824003
JB		 1560 I915_WRITE(FBC_CONTROL, fbc_ctl);
1561
016b9b61
CW		 1562 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1563 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1564}
1565
ee5382ae 1566static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1567{
80824003
JB		 1568 struct drm_i915_private *dev_priv = dev->dev_private;
1569
1570 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1571}
1572
74dff282
JB		 1573static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1574{
1575 struct drm_device *dev = crtc->dev;
1576 struct drm_i915_private *dev_priv = dev->dev_private;
1577 struct drm_framebuffer *fb = crtc->fb;
1578 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1579 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1581 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1582 unsigned long stall_watermark = 200;
1583 u32 dpfc_ctl;
1584
74dff282 1585 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1586 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1587 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1588
74dff282
JB		 1589 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1590 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1591 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1592 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1593
1594 /* enable it... */
1595 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1596
28c97730 1597 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1598}
1599
43a9539f 1600static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1601{
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 dpfc_ctl;
1604
1605 /* Disable compression */
1606 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1607 if (dpfc_ctl & DPFC_CTL_EN) {
1608 dpfc_ctl &= ~DPFC_CTL_EN;
1609 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1610
bed4a673
CW		 1611 DRM_DEBUG_KMS("disabled FBC\n");
1612 }
74dff282
JB		 1613}
1614
ee5382ae 1615static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1616{
74dff282
JB		 1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1620}
1621
4efe0708
JB		 1622static void sandybridge_blit_fbc_update(struct drm_device *dev)
1623{
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 u32 blt_ecoskpd;
1626
1627 /* Make sure blitter notifies FBC of writes */
fcca7926 1628 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1629 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1630 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1631 GEN6_BLITTER_LOCK_SHIFT;
1632 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1633 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1634 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1635 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1636 GEN6_BLITTER_LOCK_SHIFT);
1637 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1638 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1639 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1640}
1641
b52eb4dc
ZY		 1642static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1643{
1644 struct drm_device *dev = crtc->dev;
1645 struct drm_i915_private *dev_priv = dev->dev_private;
1646 struct drm_framebuffer *fb = crtc->fb;
1647 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1648 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1650 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1651 unsigned long stall_watermark = 200;
1652 u32 dpfc_ctl;
1653
bed4a673 1654 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1655 dpfc_ctl &= DPFC_RESERVED;
1656 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1657 /* Set persistent mode for front-buffer rendering, ala X. */
1658 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1659 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1660 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1661
b52eb4dc
ZY		 1662 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1663 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1664 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1665 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1666 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1667 /* enable it... */
bed4a673 1668 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1669
9c04f015
YL		 1670 if (IS_GEN6(dev)) {
1671 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1672 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1673 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1674 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1675 }
1676
b52eb4dc
ZY		 1677 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1678}
1679
43a9539f 1680static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683 u32 dpfc_ctl;
1684
1685 /* Disable compression */
1686 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1687 if (dpfc_ctl & DPFC_CTL_EN) {
1688 dpfc_ctl &= ~DPFC_CTL_EN;
1689 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1690
bed4a673
CW		 1691 DRM_DEBUG_KMS("disabled FBC\n");
1692 }
b52eb4dc
ZY		 1693}
1694
1695static bool ironlake_fbc_enabled(struct drm_device *dev)
1696{
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698
1699 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1700}
1701
ee5382ae
AJ		 1702bool intel_fbc_enabled(struct drm_device *dev)
1703{
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706 if (!dev_priv->display.fbc_enabled)
1707 return false;
1708
1709 return dev_priv->display.fbc_enabled(dev);
1710}
1711
1630fe75
CW		 1712static void intel_fbc_work_fn(struct work_struct *__work)
1713{
1714 struct intel_fbc_work *work =
1715 container_of(to_delayed_work(__work),
1716 struct intel_fbc_work, work);
1717 struct drm_device *dev = work->crtc->dev;
1718 struct drm_i915_private *dev_priv = dev->dev_private;
1719
1720 mutex_lock(&dev->struct_mutex);
1721 if (work == dev_priv->fbc_work) {
1722 /* Double check that we haven't switched fb without cancelling
1723 * the prior work.
1724 */
016b9b61 1725 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1726 dev_priv->display.enable_fbc(work->crtc,
1727 work->interval);
1728
016b9b61
CW		 1729 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1730 dev_priv->cfb_fb = work->crtc->fb->base.id;
1731 dev_priv->cfb_y = work->crtc->y;
1732 }
1733
1630fe75
CW		 1734 dev_priv->fbc_work = NULL;
1735 }
1736 mutex_unlock(&dev->struct_mutex);
1737
1738 kfree(work);
1739}
1740
1741static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1742{
1743 if (dev_priv->fbc_work == NULL)
1744 return;
1745
1746 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1747
1748 /* Synchronisation is provided by struct_mutex and checking of
1749 * dev_priv->fbc_work, so we can perform the cancellation
1750 * entirely asynchronously.
1751 */
1752 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1753 /* tasklet was killed before being run, clean up */
1754 kfree(dev_priv->fbc_work);
1755
1756 /* Mark the work as no longer wanted so that if it does
1757 * wake-up (because the work was already running and waiting
1758 * for our mutex), it will discover that is no longer
1759 * necessary to run.
1760 */
1761 dev_priv->fbc_work = NULL;
1762}
1763
43a9539f 1764static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1765{
1630fe75
CW		 1766 struct intel_fbc_work *work;
1767 struct drm_device *dev = crtc->dev;
1768 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1769
1770 if (!dev_priv->display.enable_fbc)
1771 return;
1772
1630fe75
CW		 1773 intel_cancel_fbc_work(dev_priv);
1774
1775 work = kzalloc(sizeof *work, GFP_KERNEL);
1776 if (work == NULL) {
1777 dev_priv->display.enable_fbc(crtc, interval);
1778 return;
1779 }
1780
1781 work->crtc = crtc;
1782 work->fb = crtc->fb;
1783 work->interval = interval;
1784 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1785
1786 dev_priv->fbc_work = work;
1787
1788 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1789
1790 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1791 * display to settle before starting the compression. Note that
1792 * this delay also serves a second purpose: it allows for a
1793 * vblank to pass after disabling the FBC before we attempt
1794 * to modify the control registers.
1630fe75
CW		 1795 *
1796 * A more complicated solution would involve tracking vblanks
1797 * following the termination of the page-flipping sequence
1798 * and indeed performing the enable as a co-routine and not
1799 * waiting synchronously upon the vblank.
1800 */
1801 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1802}
1803
1804void intel_disable_fbc(struct drm_device *dev)
1805{
1806 struct drm_i915_private *dev_priv = dev->dev_private;
1807
1630fe75
CW		 1808 intel_cancel_fbc_work(dev_priv);
1809
ee5382ae
AJ		 1810 if (!dev_priv->display.disable_fbc)
1811 return;
1812
1813 dev_priv->display.disable_fbc(dev);
016b9b61 1814 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1815}
1816
80824003
JB		 1817/**
1818 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1819 * @dev: the drm_device
80824003
JB		 1820 *
1821 * Set up the framebuffer compression hardware at mode set time. We
1822 * enable it if possible:
1823 * - plane A only (on pre-965)
1824 * - no pixel mulitply/line duplication
1825 * - no alpha buffer discard
1826 * - no dual wide
1827 * - framebuffer <= 2048 in width, 1536 in height
1828 *
1829 * We can't assume that any compression will take place (worst case),
1830 * so the compressed buffer has to be the same size as the uncompressed
1831 * one. It also must reside (along with the line length buffer) in
1832 * stolen memory.
1833 *
1834 * We need to enable/disable FBC on a global basis.
1835 */
bed4a673 1836static void intel_update_fbc(struct drm_device *dev)
80824003 1837{
80824003 1838 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1839 struct drm_crtc *crtc = NULL, *tmp_crtc;
1840 struct intel_crtc *intel_crtc;
1841 struct drm_framebuffer *fb;
80824003 1842 struct intel_framebuffer *intel_fb;
05394f39 1843 struct drm_i915_gem_object *obj;
cd0de039 1844 int enable_fbc;
9c928d16
JB		 1845
1846 DRM_DEBUG_KMS("\n");
80824003
JB		 1847
1848 if (!i915_powersave)
1849 return;
1850
ee5382ae 1851 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1852 return;
1853
80824003
JB		 1854 /*
1855 * If FBC is already on, we just have to verify that we can
1856 * keep it that way...
1857 * Need to disable if:
9c928d16 1858 * - more than one pipe is active
80824003
JB		 1859 * - changing FBC params (stride, fence, mode)
1860 * - new fb is too large to fit in compressed buffer
1861 * - going to an unsupported config (interlace, pixel multiply, etc.)
1862 */
9c928d16 1863 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1864 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1865 if (crtc) {
1866 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1867 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1868 goto out_disable;
1869 }
1870 crtc = tmp_crtc;
1871 }
9c928d16 1872 }
bed4a673
CW		 1873
1874 if (!crtc || crtc->fb == NULL) {
1875 DRM_DEBUG_KMS("no output, disabling\n");
1876 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1877 goto out_disable;
1878 }
bed4a673
CW		 1879
1880 intel_crtc = to_intel_crtc(crtc);
1881 fb = crtc->fb;
1882 intel_fb = to_intel_framebuffer(fb);
05394f39 1883 obj = intel_fb->obj;
bed4a673 1884
cd0de039
KP		 1885 enable_fbc = i915_enable_fbc;
1886 if (enable_fbc < 0) {
1887 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1888 enable_fbc = 1;
1889 if (INTEL_INFO(dev)->gen <= 5)
1890 enable_fbc = 0;
1891 }
1892 if (!enable_fbc) {
1893 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1894 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1895 goto out_disable;
1896 }
05394f39 1897 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1898 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1899 "compression\n");
b5e50c3f 1900 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1901 goto out_disable;
1902 }
bed4a673
CW		 1903 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1904 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1905 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1906 "disabling\n");
b5e50c3f 1907 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1908 goto out_disable;
1909 }
bed4a673
CW		 1910 if ((crtc->mode.hdisplay > 2048) ||
1911 (crtc->mode.vdisplay > 1536)) {
28c97730 1912 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1913 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1914 goto out_disable;
1915 }
bed4a673 1916 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1917 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1918 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1919 goto out_disable;
1920 }
de568510
CW		 1921
1922 /* The use of a CPU fence is mandatory in order to detect writes
1923 * by the CPU to the scanout and trigger updates to the FBC.
1924 */
1925 if (obj->tiling_mode != I915_TILING_X ||
1926 obj->fence_reg == I915_FENCE_REG_NONE) {
1927 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1928 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1929 goto out_disable;
1930 }
1931
c924b934
JW		 1932 /* If the kernel debugger is active, always disable compression */
1933 if (in_dbg_master())
1934 goto out_disable;
1935
016b9b61
CW		 1936 /* If the scanout has not changed, don't modify the FBC settings.
1937 * Note that we make the fundamental assumption that the fb->obj
1938 * cannot be unpinned (and have its GTT offset and fence revoked)
1939 * without first being decoupled from the scanout and FBC disabled.
1940 */
1941 if (dev_priv->cfb_plane == intel_crtc->plane &&
1942 dev_priv->cfb_fb == fb->base.id &&
1943 dev_priv->cfb_y == crtc->y)
1944 return;
1945
1946 if (intel_fbc_enabled(dev)) {
1947 /* We update FBC along two paths, after changing fb/crtc
1948 * configuration (modeswitching) and after page-flipping
1949 * finishes. For the latter, we know that not only did
1950 * we disable the FBC at the start of the page-flip
1951 * sequence, but also more than one vblank has passed.
1952 *
1953 * For the former case of modeswitching, it is possible
1954 * to switch between two FBC valid configurations
1955 * instantaneously so we do need to disable the FBC
1956 * before we can modify its control registers. We also
1957 * have to wait for the next vblank for that to take
1958 * effect. However, since we delay enabling FBC we can
1959 * assume that a vblank has passed since disabling and
1960 * that we can safely alter the registers in the deferred
1961 * callback.
1962 *
1963 * In the scenario that we go from a valid to invalid
1964 * and then back to valid FBC configuration we have
1965 * no strict enforcement that a vblank occurred since
1966 * disabling the FBC. However, along all current pipe
1967 * disabling paths we do need to wait for a vblank at
1968 * some point. And we wait before enabling FBC anyway.
1969 */
1970 DRM_DEBUG_KMS("disabling active FBC for update\n");
1971 intel_disable_fbc(dev);
1972 }
1973
bed4a673 1974 intel_enable_fbc(crtc, 500);
80824003
JB		 1975 return;
1976
1977out_disable:
80824003 1978 /* Multiple disables should be harmless */
a939406f
CW		 1979 if (intel_fbc_enabled(dev)) {
1980 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1981 intel_disable_fbc(dev);
a939406f 1982 }
80824003
JB		 1983}
1984
127bd2ac 1985int
48b956c5 1986intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1987 struct drm_i915_gem_object *obj,
919926ae 1988 struct intel_ring_buffer *pipelined)
6b95a207 1989{
ce453d81 1990 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1991 u32 alignment;
1992 int ret;
1993
05394f39 1994 switch (obj->tiling_mode) {
6b95a207 1995 case I915_TILING_NONE:
534843da
CW		 1996 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1997 alignment = 128 * 1024;
a6c45cf0 1998 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1999 alignment = 4 * 1024;
2000 else
2001 alignment = 64 * 1024;
6b95a207
KH		 2002 break;
2003 case I915_TILING_X:
2004 /* pin() will align the object as required by fence */
2005 alignment = 0;
2006 break;
2007 case I915_TILING_Y:
2008 /* FIXME: Is this true? */
2009 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2010 return -EINVAL;
2011 default:
2012 BUG();
2013 }
2014
ce453d81 2015 dev_priv->mm.interruptible = false;
2da3b9b9 2016 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2017 if (ret)
ce453d81 2018 goto err_interruptible;
6b95a207
KH		 2019
2020 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2021 * fence, whereas 965+ only requires a fence if using
2022 * framebuffer compression. For simplicity, we always install
2023 * a fence as the cost is not that onerous.
2024 */
05394f39 2025 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2026 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2027 if (ret)
2028 goto err_unpin;
6b95a207
KH		 2029 }
2030
ce453d81 2031 dev_priv->mm.interruptible = true;
6b95a207 2032 return 0;
48b956c5
CW		 2033
2034err_unpin:
2035 i915_gem_object_unpin(obj);
ce453d81
CW		 2036err_interruptible:
2037 dev_priv->mm.interruptible = true;
48b956c5 2038 return ret;
6b95a207
KH		 2039}
2040
17638cd6
JB		 2041static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2042 int x, int y)
81255565
JB		 2043{
2044 struct drm_device *dev = crtc->dev;
2045 struct drm_i915_private *dev_priv = dev->dev_private;
2046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2047 struct intel_framebuffer *intel_fb;
05394f39 2048 struct drm_i915_gem_object *obj;
81255565
JB		 2049 int plane = intel_crtc->plane;
2050 unsigned long Start, Offset;
81255565 2051 u32 dspcntr;
5eddb70b 2052 u32 reg;
81255565
JB		 2053
2054 switch (plane) {
2055 case 0:
2056 case 1:
2057 break;
2058 default:
2059 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2060 return -EINVAL;
2061 }
2062
2063 intel_fb = to_intel_framebuffer(fb);
2064 obj = intel_fb->obj;
81255565 2065
5eddb70b
CW		 2066 reg = DSPCNTR(plane);
2067 dspcntr = I915_READ(reg);
81255565
JB		 2068 /* Mask out pixel format bits in case we change it */
2069 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2070 switch (fb->bits_per_pixel) {
2071 case 8:
2072 dspcntr |= DISPPLANE_8BPP;
2073 break;
2074 case 16:
2075 if (fb->depth == 15)
2076 dspcntr |= DISPPLANE_15_16BPP;
2077 else
2078 dspcntr |= DISPPLANE_16BPP;
2079 break;
2080 case 24:
2081 case 32:
2082 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2083 break;
2084 default:
17638cd6 2085 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2086 return -EINVAL;
2087 }
a6c45cf0 2088 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2089 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2090 dspcntr |= DISPPLANE_TILED;
2091 else
2092 dspcntr &= ~DISPPLANE_TILED;
2093 }
2094
5eddb70b 2095 I915_WRITE(reg, dspcntr);
81255565 2096
05394f39 2097 Start = obj->gtt_offset;
01f2c773 2098 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2099
4e6cfefc 2100 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2101 Start, Offset, x, y, fb->pitches[0]);
2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2104 I915_WRITE(DSPSURF(plane), Start);
2105 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2106 I915_WRITE(DSPADDR(plane), Offset);
2107 } else
2108 I915_WRITE(DSPADDR(plane), Start + Offset);
2109 POSTING_READ(reg);
81255565 2110
17638cd6
JB		 2111 return 0;
2112}
2113
2114static int ironlake_update_plane(struct drm_crtc *crtc,
2115 struct drm_framebuffer *fb, int x, int y)
2116{
2117 struct drm_device *dev = crtc->dev;
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2120 struct intel_framebuffer *intel_fb;
2121 struct drm_i915_gem_object *obj;
2122 int plane = intel_crtc->plane;
2123 unsigned long Start, Offset;
2124 u32 dspcntr;
2125 u32 reg;
2126
2127 switch (plane) {
2128 case 0:
2129 case 1:
27f8227b 2130 case 2:
17638cd6
JB		 2131 break;
2132 default:
2133 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2134 return -EINVAL;
2135 }
2136
2137 intel_fb = to_intel_framebuffer(fb);
2138 obj = intel_fb->obj;
2139
2140 reg = DSPCNTR(plane);
2141 dspcntr = I915_READ(reg);
2142 /* Mask out pixel format bits in case we change it */
2143 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2144 switch (fb->bits_per_pixel) {
2145 case 8:
2146 dspcntr |= DISPPLANE_8BPP;
2147 break;
2148 case 16:
2149 if (fb->depth != 16)
2150 return -EINVAL;
2151
2152 dspcntr |= DISPPLANE_16BPP;
2153 break;
2154 case 24:
2155 case 32:
2156 if (fb->depth == 24)
2157 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2158 else if (fb->depth == 30)
2159 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2160 else
2161 return -EINVAL;
2162 break;
2163 default:
2164 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2165 return -EINVAL;
2166 }
2167
2168 if (obj->tiling_mode != I915_TILING_NONE)
2169 dspcntr |= DISPPLANE_TILED;
2170 else
2171 dspcntr &= ~DISPPLANE_TILED;
2172
2173 /* must disable */
2174 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2175
2176 I915_WRITE(reg, dspcntr);
2177
2178 Start = obj->gtt_offset;
01f2c773 2179 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2180
2181 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2182 Start, Offset, x, y, fb->pitches[0]);
2183 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2184 I915_WRITE(DSPSURF(plane), Start);
2185 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2186 I915_WRITE(DSPADDR(plane), Offset);
2187 POSTING_READ(reg);
2188
2189 return 0;
2190}
2191
2192/* Assume fb object is pinned & idle & fenced and just update base pointers */
2193static int
2194intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2195 int x, int y, enum mode_set_atomic state)
2196{
2197 struct drm_device *dev = crtc->dev;
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 int ret;
2200
2201 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2202 if (ret)
2203 return ret;
2204
bed4a673 2205 intel_update_fbc(dev);
3dec0095 2206 intel_increase_pllclock(crtc);
81255565
JB		 2207
2208 return 0;
2209}
2210
5c3b82e2 2211static int
3c4fdcfb
KH		 2212intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2213 struct drm_framebuffer *old_fb)
79e53945
JB		 2214{
2215 struct drm_device *dev = crtc->dev;
79e53945
JB		 2216 struct drm_i915_master_private *master_priv;
2217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2218 int ret;
79e53945
JB		 2219
2220 /* no fb bound */
2221 if (!crtc->fb) {
a5071c2f 2222 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2223 return 0;
2224 }
2225
265db958 2226 switch (intel_crtc->plane) {
5c3b82e2
CW		 2227 case 0:
2228 case 1:
2229 break;
27f8227b
JB		 2230 case 2:
2231 if (IS_IVYBRIDGE(dev))
2232 break;
2233 /* fall through otherwise */
5c3b82e2 2234 default:
a5071c2f 2235 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2236 return -EINVAL;
79e53945
JB		 2237 }
2238
5c3b82e2 2239 mutex_lock(&dev->struct_mutex);
265db958
CW		 2240 ret = intel_pin_and_fence_fb_obj(dev,
2241 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2242 NULL);
5c3b82e2
CW		 2243 if (ret != 0) {
2244 mutex_unlock(&dev->struct_mutex);
a5071c2f 2245 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2246 return ret;
2247 }
79e53945 2248
265db958 2249 if (old_fb) {
e6c3a2a6 2250 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2251 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2252
e6c3a2a6 2253 wait_event(dev_priv->pending_flip_queue,
01eec727 2254 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2255 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2256
2257 /* Big Hammer, we also need to ensure that any pending
2258 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2259 * current scanout is retired before unpinning the old
2260 * framebuffer.
01eec727
CW		 2261 *
2262 * This should only fail upon a hung GPU, in which case we
2263 * can safely continue.
85345517 2264 */
a8198eea 2265 ret = i915_gem_object_finish_gpu(obj);
01eec727 2266 (void) ret;
265db958
CW		 2267 }
2268
21c74a8e
JW		 2269 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2270 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2271 if (ret) {
265db958 2272 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2273 mutex_unlock(&dev->struct_mutex);
a5071c2f 2274 DRM_ERROR("failed to update base address\n");
4e6cfefc 2275 return ret;
79e53945 2276 }
3c4fdcfb 2277
b7f1de28
CW		 2278 if (old_fb) {
2279 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2280 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2281 }
652c393a 2282
5c3b82e2 2283 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2284
2285 if (!dev->primary->master)
5c3b82e2 2286 return 0;
79e53945
JB		 2287
2288 master_priv = dev->primary->master->driver_priv;
2289 if (!master_priv->sarea_priv)
5c3b82e2 2290 return 0;
79e53945 2291
265db958 2292 if (intel_crtc->pipe) {
79e53945
JB		 2293 master_priv->sarea_priv->pipeB_x = x;
2294 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2295 } else {
2296 master_priv->sarea_priv->pipeA_x = x;
2297 master_priv->sarea_priv->pipeA_y = y;
79e53945 2298 }
5c3b82e2
CW		 2299
2300 return 0;
79e53945
JB		 2301}
2302
5eddb70b 2303static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2304{
2305 struct drm_device *dev = crtc->dev;
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 u32 dpa_ctl;
2308
28c97730 2309 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2310 dpa_ctl = I915_READ(DP_A);
2311 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2312
2313 if (clock < 200000) {
2314 u32 temp;
2315 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2316 /* workaround for 160Mhz:
2317 1) program 0x4600c bits 15:0 = 0x8124
2318 2) program 0x46010 bit 0 = 1
2319 3) program 0x46034 bit 24 = 1
2320 4) program 0x64000 bit 14 = 1
2321 */
2322 temp = I915_READ(0x4600c);
2323 temp &= 0xffff0000;
2324 I915_WRITE(0x4600c, temp | 0x8124);
2325
2326 temp = I915_READ(0x46010);
2327 I915_WRITE(0x46010, temp | 1);
2328
2329 temp = I915_READ(0x46034);
2330 I915_WRITE(0x46034, temp | (1 << 24));
2331 } else {
2332 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2333 }
2334 I915_WRITE(DP_A, dpa_ctl);
2335
5eddb70b 2336 POSTING_READ(DP_A);
32f9d658
ZW		 2337 udelay(500);
2338}
2339
5e84e1a4
ZW		 2340static void intel_fdi_normal_train(struct drm_crtc *crtc)
2341{
2342 struct drm_device *dev = crtc->dev;
2343 struct drm_i915_private *dev_priv = dev->dev_private;
2344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2345 int pipe = intel_crtc->pipe;
2346 u32 reg, temp;
2347
2348 /* enable normal train */
2349 reg = FDI_TX_CTL(pipe);
2350 temp = I915_READ(reg);
61e499bf 2351 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2352 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2353 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2354 } else {
2355 temp &= ~FDI_LINK_TRAIN_NONE;
2356 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2357 }
5e84e1a4
ZW		 2358 I915_WRITE(reg, temp);
2359
2360 reg = FDI_RX_CTL(pipe);
2361 temp = I915_READ(reg);
2362 if (HAS_PCH_CPT(dev)) {
2363 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2364 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2365 } else {
2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_NONE;
2368 }
2369 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2370
2371 /* wait one idle pattern time */
2372 POSTING_READ(reg);
2373 udelay(1000);
357555c0
JB		 2374
2375 /* IVB wants error correction enabled */
2376 if (IS_IVYBRIDGE(dev))
2377 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2378 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2379}
2380
291427f5
JB		 2381static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2382{
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 u32 flags = I915_READ(SOUTH_CHICKEN1);
2385
2386 flags |= FDI_PHASE_SYNC_OVR(pipe);
2387 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2388 flags |= FDI_PHASE_SYNC_EN(pipe);
2389 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2390 POSTING_READ(SOUTH_CHICKEN1);
2391}
2392
8db9d77b
ZW		 2393/* The FDI link training functions for ILK/Ibexpeak. */
2394static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2395{
2396 struct drm_device *dev = crtc->dev;
2397 struct drm_i915_private *dev_priv = dev->dev_private;
2398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2399 int pipe = intel_crtc->pipe;
0fc932b8 2400 int plane = intel_crtc->plane;
5eddb70b 2401 u32 reg, temp, tries;
8db9d77b 2402
0fc932b8
JB		 2403 /* FDI needs bits from pipe & plane first */
2404 assert_pipe_enabled(dev_priv, pipe);
2405 assert_plane_enabled(dev_priv, plane);
2406
e1a44743
AJ		 2407 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2408 for train result */
5eddb70b
CW		 2409 reg = FDI_RX_IMR(pipe);
2410 temp = I915_READ(reg);
e1a44743
AJ		 2411 temp &= ~FDI_RX_SYMBOL_LOCK;
2412 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2413 I915_WRITE(reg, temp);
2414 I915_READ(reg);
e1a44743
AJ		 2415 udelay(150);
2416
8db9d77b 2417 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
77ffb597
AJ		 2420 temp &= ~(7 << 19);
2421 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2424 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2425
5eddb70b
CW		 2426 reg = FDI_RX_CTL(pipe);
2427 temp = I915_READ(reg);
8db9d77b
ZW		 2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2430 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2431
2432 POSTING_READ(reg);
8db9d77b
ZW		 2433 udelay(150);
2434
5b2adf89 2435 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2436 if (HAS_PCH_IBX(dev)) {
2437 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2439 FDI_RX_PHASE_SYNC_POINTER_EN);
2440 }
5b2adf89 2441
5eddb70b 2442 reg = FDI_RX_IIR(pipe);
e1a44743 2443 for (tries = 0; tries < 5; tries++) {
5eddb70b 2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2450 break;
2451 }
8db9d77b 2452 }
e1a44743 2453 if (tries == 5)
5eddb70b 2454 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2455
2456 /* Train 2 */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2461 I915_WRITE(reg, temp);
8db9d77b 2462
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
8db9d77b
ZW		 2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2467 I915_WRITE(reg, temp);
8db9d77b 2468
5eddb70b
CW		 2469 POSTING_READ(reg);
2470 udelay(150);
8db9d77b 2471
5eddb70b 2472 reg = FDI_RX_IIR(pipe);
e1a44743 2473 for (tries = 0; tries < 5; tries++) {
5eddb70b 2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2480 break;
2481 }
8db9d77b 2482 }
e1a44743 2483 if (tries == 5)
5eddb70b 2484 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2485
2486 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2487
8db9d77b
ZW		 2488}
2489
0206e353 2490static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495};
2496
2497/* The FDI link training functions for SNB/Cougarpoint. */
2498static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
5eddb70b 2504 u32 reg, temp, i;
8db9d77b 2505
e1a44743
AJ		 2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 for train result */
5eddb70b
CW		 2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
e1a44743
AJ		 2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597
AJ		 2520 temp &= ~(7 << 19);
2521 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 /* SNB-B */
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2528
5eddb70b
CW		 2529 reg = FDI_RX_CTL(pipe);
2530 temp = I915_READ(reg);
8db9d77b
ZW		 2531 if (HAS_PCH_CPT(dev)) {
2532 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2533 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2534 } else {
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 }
5eddb70b
CW		 2538 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2539
2540 POSTING_READ(reg);
8db9d77b
ZW		 2541 udelay(150);
2542
291427f5
JB		 2543 if (HAS_PCH_CPT(dev))
2544 cpt_phase_pointer_enable(dev, pipe);
2545
0206e353 2546 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
8db9d77b
ZW		 2554 udelay(500);
2555
5eddb70b
CW		 2556 reg = FDI_RX_IIR(pipe);
2557 temp = I915_READ(reg);
8db9d77b
ZW		 2558 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2559
2560 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563 break;
2564 }
2565 }
2566 if (i == 4)
5eddb70b 2567 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2568
2569 /* Train 2 */
5eddb70b
CW		 2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
8db9d77b
ZW		 2572 temp &= ~FDI_LINK_TRAIN_NONE;
2573 temp |= FDI_LINK_TRAIN_PATTERN_2;
2574 if (IS_GEN6(dev)) {
2575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576 /* SNB-B */
2577 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2578 }
5eddb70b 2579 I915_WRITE(reg, temp);
8db9d77b 2580
5eddb70b
CW		 2581 reg = FDI_RX_CTL(pipe);
2582 temp = I915_READ(reg);
8db9d77b
ZW		 2583 if (HAS_PCH_CPT(dev)) {
2584 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2586 } else {
2587 temp &= ~FDI_LINK_TRAIN_NONE;
2588 temp |= FDI_LINK_TRAIN_PATTERN_2;
2589 }
5eddb70b
CW		 2590 I915_WRITE(reg, temp);
2591
2592 POSTING_READ(reg);
8db9d77b
ZW		 2593 udelay(150);
2594
0206e353 2595 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2596 reg = FDI_TX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2600 I915_WRITE(reg, temp);
2601
2602 POSTING_READ(reg);
8db9d77b
ZW		 2603 udelay(500);
2604
5eddb70b
CW		 2605 reg = FDI_RX_IIR(pipe);
2606 temp = I915_READ(reg);
8db9d77b
ZW		 2607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2608
2609 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2610 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2611 DRM_DEBUG_KMS("FDI train 2 done.\n");
2612 break;
2613 }
2614 }
2615 if (i == 4)
5eddb70b 2616 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2617
2618 DRM_DEBUG_KMS("FDI train done.\n");
2619}
2620
357555c0
JB		 2621/* Manual link training for Ivy Bridge A0 parts */
2622static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2623{
2624 struct drm_device *dev = crtc->dev;
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2627 int pipe = intel_crtc->pipe;
2628 u32 reg, temp, i;
2629
2630 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2631 for train result */
2632 reg = FDI_RX_IMR(pipe);
2633 temp = I915_READ(reg);
2634 temp &= ~FDI_RX_SYMBOL_LOCK;
2635 temp &= ~FDI_RX_BIT_LOCK;
2636 I915_WRITE(reg, temp);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 /* enable CPU FDI TX and PCH FDI RX */
2642 reg = FDI_TX_CTL(pipe);
2643 temp = I915_READ(reg);
2644 temp &= ~(7 << 19);
2645 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2646 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2647 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2650 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2651 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2652
2653 reg = FDI_RX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~FDI_LINK_TRAIN_AUTO;
2656 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2657 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2658 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2659 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
291427f5
JB		 2664 if (HAS_PCH_CPT(dev))
2665 cpt_phase_pointer_enable(dev, pipe);
2666
0206e353 2667 for (i = 0; i < 4; i++) {
357555c0
JB		 2668 reg = FDI_TX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2671 temp |= snb_b_fdi_train_param[i];
2672 I915_WRITE(reg, temp);
2673
2674 POSTING_READ(reg);
2675 udelay(500);
2676
2677 reg = FDI_RX_IIR(pipe);
2678 temp = I915_READ(reg);
2679 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2680
2681 if (temp & FDI_RX_BIT_LOCK ||
2682 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2683 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2684 DRM_DEBUG_KMS("FDI train 1 done.\n");
2685 break;
2686 }
2687 }
2688 if (i == 4)
2689 DRM_ERROR("FDI train 1 fail!\n");
2690
2691 /* Train 2 */
2692 reg = FDI_TX_CTL(pipe);
2693 temp = I915_READ(reg);
2694 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2695 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2697 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2698 I915_WRITE(reg, temp);
2699
2700 reg = FDI_RX_CTL(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2703 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2704 I915_WRITE(reg, temp);
2705
2706 POSTING_READ(reg);
2707 udelay(150);
2708
0206e353 2709 for (i = 0; i < 4; i++) {
357555c0
JB		 2710 reg = FDI_TX_CTL(pipe);
2711 temp = I915_READ(reg);
2712 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2713 temp |= snb_b_fdi_train_param[i];
2714 I915_WRITE(reg, temp);
2715
2716 POSTING_READ(reg);
2717 udelay(500);
2718
2719 reg = FDI_RX_IIR(pipe);
2720 temp = I915_READ(reg);
2721 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2722
2723 if (temp & FDI_RX_SYMBOL_LOCK) {
2724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2725 DRM_DEBUG_KMS("FDI train 2 done.\n");
2726 break;
2727 }
2728 }
2729 if (i == 4)
2730 DRM_ERROR("FDI train 2 fail!\n");
2731
2732 DRM_DEBUG_KMS("FDI train done.\n");
2733}
2734
2735static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2736{
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
5eddb70b 2741 u32 reg, temp;
79e53945 2742
c64e311e 2743 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2744 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2745 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2746
c98e9dcf 2747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2748 reg = FDI_RX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2751 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2752 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2754
2755 POSTING_READ(reg);
c98e9dcf
JB		 2756 udelay(200);
2757
2758 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2759 temp = I915_READ(reg);
2760 I915_WRITE(reg, temp | FDI_PCDCLK);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
2765 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2766 reg = FDI_TX_CTL(pipe);
2767 temp = I915_READ(reg);
c98e9dcf 2768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2770
2771 POSTING_READ(reg);
c98e9dcf 2772 udelay(100);
6be4a607 2773 }
0e23b99d
JB		 2774}
2775
291427f5
JB		 2776static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2777{
2778 struct drm_i915_private *dev_priv = dev->dev_private;
2779 u32 flags = I915_READ(SOUTH_CHICKEN1);
2780
2781 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2782 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2783 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2784 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2785 POSTING_READ(SOUTH_CHICKEN1);
2786}
0fc932b8
JB		 2787static void ironlake_fdi_disable(struct drm_crtc *crtc)
2788{
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2792 int pipe = intel_crtc->pipe;
2793 u32 reg, temp;
2794
2795 /* disable CPU FDI tx and PCH FDI rx */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2799 POSTING_READ(reg);
2800
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~(0x7 << 16);
2804 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2805 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2806
2807 POSTING_READ(reg);
2808 udelay(100);
2809
2810 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2811 if (HAS_PCH_IBX(dev)) {
2812 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2813 I915_WRITE(FDI_RX_CHICKEN(pipe),
2814 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2815 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2816 } else if (HAS_PCH_CPT(dev)) {
2817 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2818 }
0fc932b8
JB		 2819
2820 /* still set train pattern 1 */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 temp &= ~FDI_LINK_TRAIN_NONE;
2824 temp |= FDI_LINK_TRAIN_PATTERN_1;
2825 I915_WRITE(reg, temp);
2826
2827 reg = FDI_RX_CTL(pipe);
2828 temp = I915_READ(reg);
2829 if (HAS_PCH_CPT(dev)) {
2830 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2831 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2832 } else {
2833 temp &= ~FDI_LINK_TRAIN_NONE;
2834 temp |= FDI_LINK_TRAIN_PATTERN_1;
2835 }
2836 /* BPC in FDI rx is consistent with that in PIPECONF */
2837 temp &= ~(0x07 << 16);
2838 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2839 I915_WRITE(reg, temp);
2840
2841 POSTING_READ(reg);
2842 udelay(100);
2843}
2844
6b383a7f
CW		 2845/*
2846 * When we disable a pipe, we need to clear any pending scanline wait events
2847 * to avoid hanging the ring, which we assume we are waiting on.
2848 */
2849static void intel_clear_scanline_wait(struct drm_device *dev)
2850{
2851 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2852 struct intel_ring_buffer *ring;
6b383a7f
CW		 2853 u32 tmp;
2854
2855 if (IS_GEN2(dev))
2856 /* Can't break the hang on i8xx */
2857 return;
2858
1ec14ad3 2859 ring = LP_RING(dev_priv);
8168bd48
CW		 2860 tmp = I915_READ_CTL(ring);
2861 if (tmp & RING_WAIT)
2862 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2863}
2864
e6c3a2a6
CW		 2865static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2866{
05394f39 2867 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2868 struct drm_i915_private *dev_priv;
2869
2870 if (crtc->fb == NULL)
2871 return;
2872
05394f39 2873 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2874 dev_priv = crtc->dev->dev_private;
2875 wait_event(dev_priv->pending_flip_queue,
05394f39 2876 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2877}
2878
040484af
JB		 2879static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2880{
2881 struct drm_device *dev = crtc->dev;
2882 struct drm_mode_config *mode_config = &dev->mode_config;
2883 struct intel_encoder *encoder;
2884
2885 /*
2886 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2887 * must be driven by its own crtc; no sharing is possible.
2888 */
2889 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2890 if (encoder->base.crtc != crtc)
2891 continue;
2892
2893 switch (encoder->type) {
2894 case INTEL_OUTPUT_EDP:
2895 if (!intel_encoder_is_pch_edp(&encoder->base))
2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902}
2903
f67a559d
JB		 2904/*
2905 * Enable PCH resources required for PCH ports:
2906 * - PCH PLLs
2907 * - FDI training & RX/TX
2908 * - update transcoder timings
2909 * - DP transcoding bits
2910 * - transcoder
2911 */
2912static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2913{
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2917 int pipe = intel_crtc->pipe;
4b645f14 2918 u32 reg, temp, transc_sel;
2c07245f 2919
c98e9dcf 2920 /* For PCH output, training FDI link */
674cf967 2921 dev_priv->display.fdi_link_train(crtc);
2c07245f 2922
92f2584a 2923 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2924
c98e9dcf 2925 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2926 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2927 TRANSC_DPLLB_SEL;
2928
c98e9dcf
JB		 2929 /* Be sure PCH DPLL SEL is set */
2930 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2931 if (pipe == 0) {
2932 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2933 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2934 } else if (pipe == 1) {
2935 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2936 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2937 } else if (pipe == 2) {
2938 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2939 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2940 }
c98e9dcf 2941 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2942 }
5eddb70b 2943
d9b6cb56
JB		 2944 /* set transcoder timing, panel must allow it */
2945 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2946 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2947 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2948 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2949
5eddb70b
CW		 2950 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2951 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2952 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2953
5e84e1a4
ZW		 2954 intel_fdi_normal_train(crtc);
2955
c98e9dcf
JB		 2956 /* For PCH DP, enable TRANS_DP_CTL */
2957 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2958 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2959 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2960 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2961 reg = TRANS_DP_CTL(pipe);
2962 temp = I915_READ(reg);
2963 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2964 TRANS_DP_SYNC_MASK |
2965 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2966 temp |= (TRANS_DP_OUTPUT_ENABLE |
2967 TRANS_DP_ENH_FRAMING);
9325c9f0 2968 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2969
2970 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2971 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2972 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2973 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2974
2975 switch (intel_trans_dp_port_sel(crtc)) {
2976 case PCH_DP_B:
5eddb70b 2977 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2978 break;
2979 case PCH_DP_C:
5eddb70b 2980 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2981 break;
2982 case PCH_DP_D:
5eddb70b 2983 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2984 break;
2985 default:
2986 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2987 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2988 break;
32f9d658 2989 }
2c07245f 2990
5eddb70b 2991 I915_WRITE(reg, temp);
6be4a607 2992 }
b52eb4dc 2993
040484af 2994 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2995}
2996
d4270e57
JB		 2997void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2998{
2999 struct drm_i915_private *dev_priv = dev->dev_private;
3000 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3001 u32 temp;
3002
3003 temp = I915_READ(dslreg);
3004 udelay(500);
3005 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3006 /* Without this, mode sets may fail silently on FDI */
3007 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3008 udelay(250);
3009 I915_WRITE(tc2reg, 0);
3010 if (wait_for(I915_READ(dslreg) != temp, 5))
3011 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3012 }
3013}
3014
f67a559d
JB		 3015static void ironlake_crtc_enable(struct drm_crtc *crtc)
3016{
3017 struct drm_device *dev = crtc->dev;
3018 struct drm_i915_private *dev_priv = dev->dev_private;
3019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3020 int pipe = intel_crtc->pipe;
3021 int plane = intel_crtc->plane;
3022 u32 temp;
3023 bool is_pch_port;
3024
3025 if (intel_crtc->active)
3026 return;
3027
3028 intel_crtc->active = true;
3029 intel_update_watermarks(dev);
3030
3031 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3032 temp = I915_READ(PCH_LVDS);
3033 if ((temp & LVDS_PORT_EN) == 0)
3034 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3035 }
3036
3037 is_pch_port = intel_crtc_driving_pch(crtc);
3038
3039 if (is_pch_port)
357555c0 3040 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3041 else
3042 ironlake_fdi_disable(crtc);
3043
3044 /* Enable panel fitting for LVDS */
3045 if (dev_priv->pch_pf_size &&
3046 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3047 /* Force use of hard-coded filter coefficients
3048 * as some pre-programmed values are broken,
3049 * e.g. x201.
3050 */
9db4a9c7
JB		 3051 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3052 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3053 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3054 }
3055
9c54c0dd
JB		 3056 /*
3057 * On ILK+ LUT must be loaded before the pipe is running but with
3058 * clocks enabled
3059 */
3060 intel_crtc_load_lut(crtc);
3061
f67a559d
JB		 3062 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3063 intel_enable_plane(dev_priv, plane, pipe);
3064
3065 if (is_pch_port)
3066 ironlake_pch_enable(crtc);
c98e9dcf 3067
d1ebd816 3068 mutex_lock(&dev->struct_mutex);
bed4a673 3069 intel_update_fbc(dev);
d1ebd816
BW		 3070 mutex_unlock(&dev->struct_mutex);
3071
6b383a7f 3072 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3073}
3074
3075static void ironlake_crtc_disable(struct drm_crtc *crtc)
3076{
3077 struct drm_device *dev = crtc->dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3080 int pipe = intel_crtc->pipe;
3081 int plane = intel_crtc->plane;
5eddb70b 3082 u32 reg, temp;
b52eb4dc 3083
f7abfe8b
CW		 3084 if (!intel_crtc->active)
3085 return;
3086
e6c3a2a6 3087 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3088 drm_vblank_off(dev, pipe);
6b383a7f 3089 intel_crtc_update_cursor(crtc, false);
5eddb70b 3090
b24e7179 3091 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3092
973d04f9
CW		 3093 if (dev_priv->cfb_plane == plane)
3094 intel_disable_fbc(dev);
2c07245f 3095
b24e7179 3096 intel_disable_pipe(dev_priv, pipe);
32f9d658 3097
6be4a607 3098 /* Disable PF */
9db4a9c7
JB		 3099 I915_WRITE(PF_CTL(pipe), 0);
3100 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3101
0fc932b8 3102 ironlake_fdi_disable(crtc);
2c07245f 3103
47a05eca
JB		 3104 /* This is a horrible layering violation; we should be doing this in
3105 * the connector/encoder ->prepare instead, but we don't always have
3106 * enough information there about the config to know whether it will
3107 * actually be necessary or just cause undesired flicker.
3108 */
3109 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3110
040484af 3111 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3112
6be4a607
JB		 3113 if (HAS_PCH_CPT(dev)) {
3114 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3115 reg = TRANS_DP_CTL(pipe);
3116 temp = I915_READ(reg);
3117 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3118 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3119 I915_WRITE(reg, temp);
6be4a607
JB		 3120
3121 /* disable DPLL_SEL */
3122 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3123 switch (pipe) {
3124 case 0:
d64311ab 3125 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3126 break;
3127 case 1:
6be4a607 3128 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3129 break;
3130 case 2:
4b645f14 3131 /* C shares PLL A or B */
d64311ab 3132 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3133 break;
3134 default:
3135 BUG(); /* wtf */
3136 }
6be4a607 3137 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3138 }
e3421a18 3139
6be4a607 3140 /* disable PCH DPLL */
4b645f14
JB		 3141 if (!intel_crtc->no_pll)
3142 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3143
6be4a607 3144 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3145 reg = FDI_RX_CTL(pipe);
3146 temp = I915_READ(reg);
3147 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3148
6be4a607 3149 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3150 reg = FDI_TX_CTL(pipe);
3151 temp = I915_READ(reg);
3152 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3153
3154 POSTING_READ(reg);
6be4a607 3155 udelay(100);
8db9d77b 3156
5eddb70b
CW		 3157 reg = FDI_RX_CTL(pipe);
3158 temp = I915_READ(reg);
3159 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3160
6be4a607 3161 /* Wait for the clocks to turn off. */
5eddb70b 3162 POSTING_READ(reg);
6be4a607 3163 udelay(100);
6b383a7f 3164
f7abfe8b 3165 intel_crtc->active = false;
6b383a7f 3166 intel_update_watermarks(dev);
d1ebd816
BW		 3167
3168 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3169 intel_update_fbc(dev);
3170 intel_clear_scanline_wait(dev);
d1ebd816 3171 mutex_unlock(&dev->struct_mutex);
6be4a607 3172}
1b3c7a47 3173
6be4a607
JB		 3174static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3175{
3176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177 int pipe = intel_crtc->pipe;
3178 int plane = intel_crtc->plane;
8db9d77b 3179
6be4a607
JB		 3180 /* XXX: When our outputs are all unaware of DPMS modes other than off
3181 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3182 */
3183 switch (mode) {
3184 case DRM_MODE_DPMS_ON:
3185 case DRM_MODE_DPMS_STANDBY:
3186 case DRM_MODE_DPMS_SUSPEND:
3187 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3188 ironlake_crtc_enable(crtc);
3189 break;
1b3c7a47 3190
6be4a607
JB		 3191 case DRM_MODE_DPMS_OFF:
3192 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3193 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3194 break;
3195 }
3196}
3197
02e792fb
DV		 3198static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3199{
02e792fb 3200 if (!enable && intel_crtc->overlay) {
23f09ce3 3201 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3202 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3203
23f09ce3 3204 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3205 dev_priv->mm.interruptible = false;
3206 (void) intel_overlay_switch_off(intel_crtc->overlay);
3207 dev_priv->mm.interruptible = true;
23f09ce3 3208 mutex_unlock(&dev->struct_mutex);
02e792fb 3209 }
02e792fb 3210
5dcdbcb0
CW		 3211 /* Let userspace switch the overlay on again. In most cases userspace
3212 * has to recompute where to put it anyway.
3213 */
02e792fb
DV		 3214}
3215
0b8765c6 3216static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3217{
3218 struct drm_device *dev = crtc->dev;
79e53945
JB		 3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221 int pipe = intel_crtc->pipe;
80824003 3222 int plane = intel_crtc->plane;
79e53945 3223
f7abfe8b
CW		 3224 if (intel_crtc->active)
3225 return;
3226
3227 intel_crtc->active = true;
6b383a7f
CW		 3228 intel_update_watermarks(dev);
3229
63d7bbe9 3230 intel_enable_pll(dev_priv, pipe);
040484af 3231 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3232 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3233
0b8765c6 3234 intel_crtc_load_lut(crtc);
bed4a673 3235 intel_update_fbc(dev);
79e53945 3236
0b8765c6
JB		 3237 /* Give the overlay scaler a chance to enable if it's on this pipe */
3238 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3239 intel_crtc_update_cursor(crtc, true);
0b8765c6 3240}
79e53945 3241
0b8765c6
JB		 3242static void i9xx_crtc_disable(struct drm_crtc *crtc)
3243{
3244 struct drm_device *dev = crtc->dev;
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3247 int pipe = intel_crtc->pipe;
3248 int plane = intel_crtc->plane;
b690e96c 3249
f7abfe8b
CW		 3250 if (!intel_crtc->active)
3251 return;
3252
0b8765c6 3253 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3254 intel_crtc_wait_for_pending_flips(crtc);
3255 drm_vblank_off(dev, pipe);
0b8765c6 3256 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3257 intel_crtc_update_cursor(crtc, false);
0b8765c6 3258
973d04f9
CW		 3259 if (dev_priv->cfb_plane == plane)
3260 intel_disable_fbc(dev);
79e53945 3261
b24e7179 3262 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3263 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3264 intel_disable_pll(dev_priv, pipe);
0b8765c6 3265
f7abfe8b 3266 intel_crtc->active = false;
6b383a7f
CW		 3267 intel_update_fbc(dev);
3268 intel_update_watermarks(dev);
3269 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3270}
3271
3272static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3273{
3274 /* XXX: When our outputs are all unaware of DPMS modes other than off
3275 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3276 */
3277 switch (mode) {
3278 case DRM_MODE_DPMS_ON:
3279 case DRM_MODE_DPMS_STANDBY:
3280 case DRM_MODE_DPMS_SUSPEND:
3281 i9xx_crtc_enable(crtc);
3282 break;
3283 case DRM_MODE_DPMS_OFF:
3284 i9xx_crtc_disable(crtc);
79e53945
JB		 3285 break;
3286 }
2c07245f
ZW		 3287}
3288
3289/**
3290 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3291 */
3292static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3293{
3294 struct drm_device *dev = crtc->dev;
e70236a8 3295 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3296 struct drm_i915_master_private *master_priv;
3297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3298 int pipe = intel_crtc->pipe;
3299 bool enabled;
3300
032d2a0d
CW		 3301 if (intel_crtc->dpms_mode == mode)
3302 return;
3303
65655d4a 3304 intel_crtc->dpms_mode = mode;
debcaddc 3305
e70236a8 3306 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3307
3308 if (!dev->primary->master)
3309 return;
3310
3311 master_priv = dev->primary->master->driver_priv;
3312 if (!master_priv->sarea_priv)
3313 return;
3314
3315 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3316
3317 switch (pipe) {
3318 case 0:
3319 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3320 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3321 break;
3322 case 1:
3323 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3324 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3325 break;
3326 default:
9db4a9c7 3327 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3328 break;
3329 }
79e53945
JB		 3330}
3331
cdd59983
CW		 3332static void intel_crtc_disable(struct drm_crtc *crtc)
3333{
3334 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3335 struct drm_device *dev = crtc->dev;
3336
3337 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3338
3339 if (crtc->fb) {
3340 mutex_lock(&dev->struct_mutex);
3341 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3342 mutex_unlock(&dev->struct_mutex);
3343 }
3344}
3345
7e7d76c3
JB		 3346/* Prepare for a mode set.
3347 *
3348 * Note we could be a lot smarter here. We need to figure out which outputs
3349 * will be enabled, which disabled (in short, how the config will changes)
3350 * and perform the minimum necessary steps to accomplish that, e.g. updating
3351 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3352 * panel fitting is in the proper state, etc.
3353 */
3354static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3355{
7e7d76c3 3356 i9xx_crtc_disable(crtc);
79e53945
JB		 3357}
3358
7e7d76c3 3359static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3360{
7e7d76c3 3361 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3362}
3363
3364static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3365{
7e7d76c3 3366 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3367}
3368
3369static void ironlake_crtc_commit(struct drm_crtc *crtc)
3370{
7e7d76c3 3371 ironlake_crtc_enable(crtc);
79e53945
JB		 3372}
3373
0206e353 3374void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3375{
3376 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3377 /* lvds has its own version of prepare see intel_lvds_prepare */
3378 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3379}
3380
0206e353 3381void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3382{
3383 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3384 struct drm_device *dev = encoder->dev;
3385 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3386 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3387
79e53945
JB		 3388 /* lvds has its own version of commit see intel_lvds_commit */
3389 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3390
3391 if (HAS_PCH_CPT(dev))
3392 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3393}
3394
ea5b213a
CW		 3395void intel_encoder_destroy(struct drm_encoder *encoder)
3396{
4ef69c7a 3397 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3398
ea5b213a
CW		 3399 drm_encoder_cleanup(encoder);
3400 kfree(intel_encoder);
3401}
3402
79e53945
JB		 3403static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3404 struct drm_display_mode *mode,
3405 struct drm_display_mode *adjusted_mode)
3406{
2c07245f 3407 struct drm_device *dev = crtc->dev;
89749350 3408
bad720ff 3409 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3410 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3411 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3412 return false;
2c07245f 3413 }
89749350
CW		 3414
3415 /* XXX some encoders set the crtcinfo, others don't.
3416 * Obviously we need some form of conflict resolution here...
3417 */
3418 if (adjusted_mode->crtc_htotal == 0)
3419 drm_mode_set_crtcinfo(adjusted_mode, 0);
3420
79e53945
JB		 3421 return true;
3422}
3423
e70236a8
JB		 3424static int i945_get_display_clock_speed(struct drm_device *dev)
3425{
3426 return 400000;
3427}
79e53945 3428
e70236a8 3429static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3430{
e70236a8
JB		 3431 return 333000;
3432}
79e53945 3433
e70236a8
JB		 3434static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3435{
3436 return 200000;
3437}
79e53945 3438
e70236a8
JB		 3439static int i915gm_get_display_clock_speed(struct drm_device *dev)
3440{
3441 u16 gcfgc = 0;
79e53945 3442
e70236a8
JB		 3443 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3444
3445 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3446 return 133000;
3447 else {
3448 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3449 case GC_DISPLAY_CLOCK_333_MHZ:
3450 return 333000;
3451 default:
3452 case GC_DISPLAY_CLOCK_190_200_MHZ:
3453 return 190000;
79e53945 3454 }
e70236a8
JB		 3455 }
3456}
3457
3458static int i865_get_display_clock_speed(struct drm_device *dev)
3459{
3460 return 266000;
3461}
3462
3463static int i855_get_display_clock_speed(struct drm_device *dev)
3464{
3465 u16 hpllcc = 0;
3466 /* Assume that the hardware is in the high speed state. This
3467 * should be the default.
3468 */
3469 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3470 case GC_CLOCK_133_200:
3471 case GC_CLOCK_100_200:
3472 return 200000;
3473 case GC_CLOCK_166_250:
3474 return 250000;
3475 case GC_CLOCK_100_133:
79e53945 3476 return 133000;
e70236a8 3477 }
79e53945 3478
e70236a8
JB		 3479 /* Shouldn't happen */
3480 return 0;
3481}
79e53945 3482
e70236a8
JB		 3483static int i830_get_display_clock_speed(struct drm_device *dev)
3484{
3485 return 133000;
79e53945
JB		 3486}
3487
2c07245f
ZW		 3488struct fdi_m_n {
3489 u32 tu;
3490 u32 gmch_m;
3491 u32 gmch_n;
3492 u32 link_m;
3493 u32 link_n;
3494};
3495
3496static void
3497fdi_reduce_ratio(u32 *num, u32 *den)
3498{
3499 while (*num > 0xffffff || *den > 0xffffff) {
3500 *num >>= 1;
3501 *den >>= 1;
3502 }
3503}
3504
2c07245f 3505static void
f2b115e6
AJ		 3506ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3507 int link_clock, struct fdi_m_n *m_n)
2c07245f 3508{
2c07245f
ZW		 3509 m_n->tu = 64; /* default size */
3510
22ed1113
CW		 3511 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3512 m_n->gmch_m = bits_per_pixel * pixel_clock;
3513 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3514 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3515
22ed1113
CW		 3516 m_n->link_m = pixel_clock;
3517 m_n->link_n = link_clock;
2c07245f
ZW		 3518 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3519}
3520
3521
7662c8bd
SL		 3522struct intel_watermark_params {
3523 unsigned long fifo_size;
3524 unsigned long max_wm;
3525 unsigned long default_wm;
3526 unsigned long guard_size;
3527 unsigned long cacheline_size;
3528};
3529
f2b115e6 3530/* Pineview has different values for various configs */
d210246a 3531static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3532 PINEVIEW_DISPLAY_FIFO,
3533 PINEVIEW_MAX_WM,
3534 PINEVIEW_DFT_WM,
3535 PINEVIEW_GUARD_WM,
3536 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3537};
d210246a 3538static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3539 PINEVIEW_DISPLAY_FIFO,
3540 PINEVIEW_MAX_WM,
3541 PINEVIEW_DFT_HPLLOFF_WM,
3542 PINEVIEW_GUARD_WM,
3543 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3544};
d210246a 3545static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3546 PINEVIEW_CURSOR_FIFO,
3547 PINEVIEW_CURSOR_MAX_WM,
3548 PINEVIEW_CURSOR_DFT_WM,
3549 PINEVIEW_CURSOR_GUARD_WM,
3550 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3551};
d210246a 3552static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3553 PINEVIEW_CURSOR_FIFO,
3554 PINEVIEW_CURSOR_MAX_WM,
3555 PINEVIEW_CURSOR_DFT_WM,
3556 PINEVIEW_CURSOR_GUARD_WM,
3557 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3558};
d210246a 3559static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3560 G4X_FIFO_SIZE,
3561 G4X_MAX_WM,
3562 G4X_MAX_WM,
3563 2,
3564 G4X_FIFO_LINE_SIZE,
3565};
d210246a 3566static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3567 I965_CURSOR_FIFO,
3568 I965_CURSOR_MAX_WM,
3569 I965_CURSOR_DFT_WM,
3570 2,
3571 G4X_FIFO_LINE_SIZE,
3572};
d210246a 3573static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3574 I965_CURSOR_FIFO,
3575 I965_CURSOR_MAX_WM,
3576 I965_CURSOR_DFT_WM,
3577 2,
3578 I915_FIFO_LINE_SIZE,
3579};
d210246a 3580static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3581 I945_FIFO_SIZE,
7662c8bd
SL		 3582 I915_MAX_WM,
3583 1,
dff33cfc
JB		 3584 2,
3585 I915_FIFO_LINE_SIZE
7662c8bd 3586};
d210246a 3587static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3588 I915_FIFO_SIZE,
7662c8bd
SL		 3589 I915_MAX_WM,
3590 1,
dff33cfc 3591 2,
7662c8bd
SL		 3592 I915_FIFO_LINE_SIZE
3593};
d210246a 3594static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3595 I855GM_FIFO_SIZE,
3596 I915_MAX_WM,
3597 1,
dff33cfc 3598 2,
7662c8bd
SL		 3599 I830_FIFO_LINE_SIZE
3600};
d210246a 3601static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3602 I830_FIFO_SIZE,
3603 I915_MAX_WM,
3604 1,
dff33cfc 3605 2,
7662c8bd
SL		 3606 I830_FIFO_LINE_SIZE
3607};
3608
d210246a 3609static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3610 ILK_DISPLAY_FIFO,
3611 ILK_DISPLAY_MAXWM,
3612 ILK_DISPLAY_DFTWM,
3613 2,
3614 ILK_FIFO_LINE_SIZE
3615};
d210246a 3616static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3617 ILK_CURSOR_FIFO,
3618 ILK_CURSOR_MAXWM,
3619 ILK_CURSOR_DFTWM,
3620 2,
3621 ILK_FIFO_LINE_SIZE
3622};
d210246a 3623static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3624 ILK_DISPLAY_SR_FIFO,
3625 ILK_DISPLAY_MAX_SRWM,
3626 ILK_DISPLAY_DFT_SRWM,
3627 2,
3628 ILK_FIFO_LINE_SIZE
3629};
d210246a 3630static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3631 ILK_CURSOR_SR_FIFO,
3632 ILK_CURSOR_MAX_SRWM,
3633 ILK_CURSOR_DFT_SRWM,
3634 2,
3635 ILK_FIFO_LINE_SIZE
3636};
3637
d210246a 3638static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3639 SNB_DISPLAY_FIFO,
3640 SNB_DISPLAY_MAXWM,
3641 SNB_DISPLAY_DFTWM,
3642 2,
3643 SNB_FIFO_LINE_SIZE
3644};
d210246a 3645static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3646 SNB_CURSOR_FIFO,
3647 SNB_CURSOR_MAXWM,
3648 SNB_CURSOR_DFTWM,
3649 2,
3650 SNB_FIFO_LINE_SIZE
3651};
d210246a 3652static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3653 SNB_DISPLAY_SR_FIFO,
3654 SNB_DISPLAY_MAX_SRWM,
3655 SNB_DISPLAY_DFT_SRWM,
3656 2,
3657 SNB_FIFO_LINE_SIZE
3658};
d210246a 3659static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3660 SNB_CURSOR_SR_FIFO,
3661 SNB_CURSOR_MAX_SRWM,
3662 SNB_CURSOR_DFT_SRWM,
3663 2,
3664 SNB_FIFO_LINE_SIZE
3665};
3666
3667
dff33cfc
JB		 3668/**
3669 * intel_calculate_wm - calculate watermark level
3670 * @clock_in_khz: pixel clock
3671 * @wm: chip FIFO params
3672 * @pixel_size: display pixel size
3673 * @latency_ns: memory latency for the platform
3674 *
3675 * Calculate the watermark level (the level at which the display plane will
3676 * start fetching from memory again). Each chip has a different display
3677 * FIFO size and allocation, so the caller needs to figure that out and pass
3678 * in the correct intel_watermark_params structure.
3679 *
3680 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3681 * on the pixel size. When it reaches the watermark level, it'll start
3682 * fetching FIFO line sized based chunks from memory until the FIFO fills
3683 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3684 * will occur, and a display engine hang could result.
3685 */
7662c8bd 3686static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3687 const struct intel_watermark_params *wm,
3688 int fifo_size,
7662c8bd
SL		 3689 int pixel_size,
3690 unsigned long latency_ns)
3691{
390c4dd4 3692 long entries_required, wm_size;
dff33cfc 3693
d660467c
JB		 3694 /*
3695 * Note: we need to make sure we don't overflow for various clock &
3696 * latency values.
3697 * clocks go from a few thousand to several hundred thousand.
3698 * latency is usually a few thousand
3699 */
3700 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3701 1000;
8de9b311 3702 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3703
bbb0aef5 3704 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3705
d210246a 3706 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3707
bbb0aef5 3708 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3709
390c4dd4
JB		 3710 /* Don't promote wm_size to unsigned... */
3711 if (wm_size > (long)wm->max_wm)
7662c8bd 3712 wm_size = wm->max_wm;
c3add4b6 3713 if (wm_size <= 0)
7662c8bd
SL		 3714 wm_size = wm->default_wm;
3715 return wm_size;
3716}
3717
3718struct cxsr_latency {
3719 int is_desktop;
95534263 3720 int is_ddr3;
7662c8bd
SL		 3721 unsigned long fsb_freq;
3722 unsigned long mem_freq;
3723 unsigned long display_sr;
3724 unsigned long display_hpll_disable;
3725 unsigned long cursor_sr;
3726 unsigned long cursor_hpll_disable;
3727};
3728
403c89ff 3729static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3730 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3731 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3732 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3733 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3734 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3735
3736 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3737 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3738 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3739 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3740 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3741
3742 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3743 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3744 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3745 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3746 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3747
3748 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3749 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3750 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3751 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3752 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3753
3754 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3755 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3756 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3757 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3758 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3759
3760 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3761 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3762 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3763 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3764 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3765};
3766
403c89ff
CW		 3767static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3768 int is_ddr3,
3769 int fsb,
3770 int mem)
7662c8bd 3771{
403c89ff 3772 const struct cxsr_latency *latency;
7662c8bd 3773 int i;
7662c8bd
SL		 3774
3775 if (fsb == 0 || mem == 0)
3776 return NULL;
3777
3778 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3779 latency = &cxsr_latency_table[i];
3780 if (is_desktop == latency->is_desktop &&
95534263 3781 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3782 fsb == latency->fsb_freq && mem == latency->mem_freq)
3783 return latency;
7662c8bd 3784 }
decbbcda 3785
28c97730 3786 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3787
3788 return NULL;
7662c8bd
SL		 3789}
3790
f2b115e6 3791static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3792{
3793 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3794
3795 /* deactivate cxsr */
3e33d94d 3796 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3797}
3798
bcc24fb4
JB		 3799/*
3800 * Latency for FIFO fetches is dependent on several factors:
3801 * - memory configuration (speed, channels)
3802 * - chipset
3803 * - current MCH state
3804 * It can be fairly high in some situations, so here we assume a fairly
3805 * pessimal value. It's a tradeoff between extra memory fetches (if we
3806 * set this value too high, the FIFO will fetch frequently to stay full)
3807 * and power consumption (set it too low to save power and we might see
3808 * FIFO underruns and display "flicker").
3809 *
3810 * A value of 5us seems to be a good balance; safe for very low end
3811 * platforms but not overly aggressive on lower latency configs.
3812 */
69e302a9 3813static const int latency_ns = 5000;
7662c8bd 3814
e70236a8 3815static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3816{
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 uint32_t dsparb = I915_READ(DSPARB);
3819 int size;
3820
8de9b311
CW		 3821 size = dsparb & 0x7f;
3822 if (plane)
3823 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3824
28c97730 3825 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3826 plane ? "B" : "A", size);
dff33cfc
JB		 3827
3828 return size;
3829}
7662c8bd 3830
e70236a8
JB		 3831static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3832{
3833 struct drm_i915_private *dev_priv = dev->dev_private;
3834 uint32_t dsparb = I915_READ(DSPARB);
3835 int size;
3836
8de9b311
CW		 3837 size = dsparb & 0x1ff;
3838 if (plane)
3839 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3840 size >>= 1; /* Convert to cachelines */
dff33cfc 3841
28c97730 3842 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3843 plane ? "B" : "A", size);
dff33cfc
JB		 3844
3845 return size;
3846}
7662c8bd 3847
e70236a8
JB		 3848static int i845_get_fifo_size(struct drm_device *dev, int plane)
3849{
3850 struct drm_i915_private *dev_priv = dev->dev_private;
3851 uint32_t dsparb = I915_READ(DSPARB);
3852 int size;
3853
3854 size = dsparb & 0x7f;
3855 size >>= 2; /* Convert to cachelines */
3856
28c97730 3857 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3858 plane ? "B" : "A",
3859 size);
e70236a8
JB		 3860
3861 return size;
3862}
3863
3864static int i830_get_fifo_size(struct drm_device *dev, int plane)
3865{
3866 struct drm_i915_private *dev_priv = dev->dev_private;
3867 uint32_t dsparb = I915_READ(DSPARB);
3868 int size;
3869
3870 size = dsparb & 0x7f;
3871 size >>= 1; /* Convert to cachelines */
3872
28c97730 3873 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3874 plane ? "B" : "A", size);
e70236a8
JB		 3875
3876 return size;
3877}
3878
d210246a
CW		 3879static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3880{
3881 struct drm_crtc *crtc, *enabled = NULL;
3882
3883 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3884 if (crtc->enabled && crtc->fb) {
3885 if (enabled)
3886 return NULL;
3887 enabled = crtc;
3888 }
3889 }
3890
3891 return enabled;
3892}
3893
3894static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3895{
3896 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3897 struct drm_crtc *crtc;
403c89ff 3898 const struct cxsr_latency *latency;
d4294342
ZY		 3899 u32 reg;
3900 unsigned long wm;
d4294342 3901
403c89ff 3902 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3903 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3904 if (!latency) {
3905 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3906 pineview_disable_cxsr(dev);
3907 return;
3908 }
3909
d210246a
CW		 3910 crtc = single_enabled_crtc(dev);
3911 if (crtc) {
3912 int clock = crtc->mode.clock;
3913 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3914
3915 /* Display SR */
d210246a
CW		 3916 wm = intel_calculate_wm(clock, &pineview_display_wm,
3917 pineview_display_wm.fifo_size,
d4294342
ZY		 3918 pixel_size, latency->display_sr);
3919 reg = I915_READ(DSPFW1);
3920 reg &= ~DSPFW_SR_MASK;
3921 reg |= wm << DSPFW_SR_SHIFT;
3922 I915_WRITE(DSPFW1, reg);
3923 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3924
3925 /* cursor SR */
d210246a
CW		 3926 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3927 pineview_display_wm.fifo_size,
d4294342
ZY		 3928 pixel_size, latency->cursor_sr);
3929 reg = I915_READ(DSPFW3);
3930 reg &= ~DSPFW_CURSOR_SR_MASK;
3931 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3932 I915_WRITE(DSPFW3, reg);
3933
3934 /* Display HPLL off SR */
d210246a
CW		 3935 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3936 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3937 pixel_size, latency->display_hpll_disable);
3938 reg = I915_READ(DSPFW3);
3939 reg &= ~DSPFW_HPLL_SR_MASK;
3940 reg |= wm & DSPFW_HPLL_SR_MASK;
3941 I915_WRITE(DSPFW3, reg);
3942
3943 /* cursor HPLL off SR */
d210246a
CW		 3944 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3945 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3946 pixel_size, latency->cursor_hpll_disable);
3947 reg = I915_READ(DSPFW3);
3948 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3949 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3950 I915_WRITE(DSPFW3, reg);
3951 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3952
3953 /* activate cxsr */
3e33d94d
CW		 3954 I915_WRITE(DSPFW3,
3955 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3956 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3957 } else {
3958 pineview_disable_cxsr(dev);
3959 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3960 }
3961}
3962
417ae147
CW		 3963static bool g4x_compute_wm0(struct drm_device *dev,
3964 int plane,
3965 const struct intel_watermark_params *display,
3966 int display_latency_ns,
3967 const struct intel_watermark_params *cursor,
3968 int cursor_latency_ns,
3969 int *plane_wm,
3970 int *cursor_wm)
3971{
3972 struct drm_crtc *crtc;
3973 int htotal, hdisplay, clock, pixel_size;
3974 int line_time_us, line_count;
3975 int entries, tlb_miss;
3976
3977 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3978 if (crtc->fb == NULL || !crtc->enabled) {
3979 *cursor_wm = cursor->guard_size;
3980 *plane_wm = display->guard_size;
417ae147 3981 return false;
5c72d064 3982 }
417ae147
CW		 3983
3984 htotal = crtc->mode.htotal;
3985 hdisplay = crtc->mode.hdisplay;
3986 clock = crtc->mode.clock;
3987 pixel_size = crtc->fb->bits_per_pixel / 8;
3988
3989 /* Use the small buffer method to calculate plane watermark */
3990 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3991 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3992 if (tlb_miss > 0)
3993 entries += tlb_miss;
3994 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3995 *plane_wm = entries + display->guard_size;
3996 if (*plane_wm > (int)display->max_wm)
3997 *plane_wm = display->max_wm;
3998
3999 /* Use the large buffer method to calculate cursor watermark */
4000 line_time_us = ((htotal * 1000) / clock);
4001 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4002 entries = line_count * 64 * pixel_size;
4003 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4004 if (tlb_miss > 0)
4005 entries += tlb_miss;
4006 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4007 *cursor_wm = entries + cursor->guard_size;
4008 if (*cursor_wm > (int)cursor->max_wm)
4009 *cursor_wm = (int)cursor->max_wm;
4010
4011 return true;
4012}
4013
4014/*
4015 * Check the wm result.
4016 *
4017 * If any calculated watermark values is larger than the maximum value that
4018 * can be programmed into the associated watermark register, that watermark
4019 * must be disabled.
4020 */
4021static bool g4x_check_srwm(struct drm_device *dev,
4022 int display_wm, int cursor_wm,
4023 const struct intel_watermark_params *display,
4024 const struct intel_watermark_params *cursor)
652c393a 4025{
417ae147
CW		 4026 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4027 display_wm, cursor_wm);
652c393a 4028
417ae147 4029 if (display_wm > display->max_wm) {
bbb0aef5 4030 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4031 display_wm, display->max_wm);
4032 return false;
4033 }
0e442c60 4034
417ae147 4035 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4036 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4037 cursor_wm, cursor->max_wm);
4038 return false;
4039 }
0e442c60 4040
417ae147
CW		 4041 if (!(display_wm || cursor_wm)) {
4042 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4043 return false;
4044 }
0e442c60 4045
417ae147
CW		 4046 return true;
4047}
0e442c60 4048
417ae147 4049static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4050 int plane,
4051 int latency_ns,
417ae147
CW		 4052 const struct intel_watermark_params *display,
4053 const struct intel_watermark_params *cursor,
4054 int *display_wm, int *cursor_wm)
4055{
d210246a
CW		 4056 struct drm_crtc *crtc;
4057 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4058 unsigned long line_time_us;
4059 int line_count, line_size;
4060 int small, large;
4061 int entries;
0e442c60 4062
417ae147
CW		 4063 if (!latency_ns) {
4064 *display_wm = *cursor_wm = 0;
4065 return false;
4066 }
0e442c60 4067
d210246a
CW		 4068 crtc = intel_get_crtc_for_plane(dev, plane);
4069 hdisplay = crtc->mode.hdisplay;
4070 htotal = crtc->mode.htotal;
4071 clock = crtc->mode.clock;
4072 pixel_size = crtc->fb->bits_per_pixel / 8;
4073
417ae147
CW		 4074 line_time_us = (htotal * 1000) / clock;
4075 line_count = (latency_ns / line_time_us + 1000) / 1000;
4076 line_size = hdisplay * pixel_size;
0e442c60 4077
417ae147
CW		 4078 /* Use the minimum of the small and large buffer method for primary */
4079 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4080 large = line_count * line_size;
0e442c60 4081
417ae147
CW		 4082 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4083 *display_wm = entries + display->guard_size;
4fe5e611 4084
417ae147
CW		 4085 /* calculate the self-refresh watermark for display cursor */
4086 entries = line_count * pixel_size * 64;
4087 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4088 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4089
417ae147
CW		 4090 return g4x_check_srwm(dev,
4091 *display_wm, *cursor_wm,
4092 display, cursor);
4093}
4fe5e611 4094
7ccb4a53 4095#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4096
4097static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4098{
4099 static const int sr_latency_ns = 12000;
4100 struct drm_i915_private *dev_priv = dev->dev_private;
4101 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4102 int plane_sr, cursor_sr;
4103 unsigned int enabled = 0;
417ae147
CW		 4104
4105 if (g4x_compute_wm0(dev, 0,
4106 &g4x_wm_info, latency_ns,
4107 &g4x_cursor_wm_info, latency_ns,
4108 &planea_wm, &cursora_wm))
d210246a 4109 enabled |= 1;
417ae147
CW		 4110
4111 if (g4x_compute_wm0(dev, 1,
4112 &g4x_wm_info, latency_ns,
4113 &g4x_cursor_wm_info, latency_ns,
4114 &planeb_wm, &cursorb_wm))
d210246a 4115 enabled |= 2;
417ae147
CW		 4116
4117 plane_sr = cursor_sr = 0;
d210246a
CW		 4118 if (single_plane_enabled(enabled) &&
4119 g4x_compute_srwm(dev, ffs(enabled) - 1,
4120 sr_latency_ns,
417ae147
CW		 4121 &g4x_wm_info,
4122 &g4x_cursor_wm_info,
4123 &plane_sr, &cursor_sr))
0e442c60 4124 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4125 else
4126 I915_WRITE(FW_BLC_SELF,
4127 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4128
308977ac
CW		 4129 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4130 planea_wm, cursora_wm,
4131 planeb_wm, cursorb_wm,
4132 plane_sr, cursor_sr);
0e442c60 4133
417ae147
CW		 4134 I915_WRITE(DSPFW1,
4135 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4136 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4137 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4138 planea_wm);
4139 I915_WRITE(DSPFW2,
4140 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4141 (cursora_wm << DSPFW_CURSORA_SHIFT));
4142 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4143 I915_WRITE(DSPFW3,
4144 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4145 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4146}
4147
d210246a 4148static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4149{
4150 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4151 struct drm_crtc *crtc;
4152 int srwm = 1;
4fe5e611 4153 int cursor_sr = 16;
1dc7546d
JB		 4154
4155 /* Calc sr entries for one plane configs */
d210246a
CW		 4156 crtc = single_enabled_crtc(dev);
4157 if (crtc) {
1dc7546d 4158 /* self-refresh has much higher latency */
69e302a9 4159 static const int sr_latency_ns = 12000;
d210246a
CW		 4160 int clock = crtc->mode.clock;
4161 int htotal = crtc->mode.htotal;
4162 int hdisplay = crtc->mode.hdisplay;
4163 int pixel_size = crtc->fb->bits_per_pixel / 8;
4164 unsigned long line_time_us;
4165 int entries;
1dc7546d 4166
d210246a 4167 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4168
4169 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4170 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4171 pixel_size * hdisplay;
4172 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4173 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4174 if (srwm < 0)
4175 srwm = 1;
1b07e04e 4176 srwm &= 0x1ff;
308977ac
CW		 4177 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4178 entries, srwm);
4fe5e611 4179
d210246a 4180 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4181 pixel_size * 64;
d210246a 4182 entries = DIV_ROUND_UP(entries,
8de9b311 4183 i965_cursor_wm_info.cacheline_size);
4fe5e611 4184 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4185 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4186
4187 if (cursor_sr > i965_cursor_wm_info.max_wm)
4188 cursor_sr = i965_cursor_wm_info.max_wm;
4189
4190 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4191 "cursor %d\n", srwm, cursor_sr);
4192
a6c45cf0 4193 if (IS_CRESTLINE(dev))
adcdbc66 4194 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4195 } else {
4196 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4197 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4198 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4199 & ~FW_BLC_SELF_EN);
1dc7546d 4200 }
7662c8bd 4201
1dc7546d
JB		 4202 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4203 srwm);
7662c8bd
SL		 4204
4205 /* 965 has limitations... */
417ae147
CW		 4206 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4207 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4208 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4209 /* update cursor SR watermark */
4210 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4211}
4212
d210246a 4213static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4214{
4215 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4216 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4217 uint32_t fwater_lo;
4218 uint32_t fwater_hi;
d210246a
CW		 4219 int cwm, srwm = 1;
4220 int fifo_size;
dff33cfc 4221 int planea_wm, planeb_wm;
d210246a 4222 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4223
72557b4f 4224 if (IS_I945GM(dev))
d210246a 4225 wm_info = &i945_wm_info;
a6c45cf0 4226 else if (!IS_GEN2(dev))
d210246a 4227 wm_info = &i915_wm_info;
7662c8bd 4228 else
d210246a
CW		 4229 wm_info = &i855_wm_info;
4230
4231 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4232 crtc = intel_get_crtc_for_plane(dev, 0);
4233 if (crtc->enabled && crtc->fb) {
4234 planea_wm = intel_calculate_wm(crtc->mode.clock,
4235 wm_info, fifo_size,
4236 crtc->fb->bits_per_pixel / 8,
4237 latency_ns);
4238 enabled = crtc;
4239 } else
4240 planea_wm = fifo_size - wm_info->guard_size;
4241
4242 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4243 crtc = intel_get_crtc_for_plane(dev, 1);
4244 if (crtc->enabled && crtc->fb) {
4245 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4246 wm_info, fifo_size,
4247 crtc->fb->bits_per_pixel / 8,
4248 latency_ns);
4249 if (enabled == NULL)
4250 enabled = crtc;
4251 else
4252 enabled = NULL;
4253 } else
4254 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4255
28c97730 4256 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4257
4258 /*
4259 * Overlay gets an aggressive default since video jitter is bad.
4260 */
4261 cwm = 2;
4262
18b2190c
AL		 4263 /* Play safe and disable self-refresh before adjusting watermarks. */
4264 if (IS_I945G(dev) || IS_I945GM(dev))
4265 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4266 else if (IS_I915GM(dev))
4267 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4268
dff33cfc 4269 /* Calc sr entries for one plane configs */
d210246a 4270 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4271 /* self-refresh has much higher latency */
69e302a9 4272 static const int sr_latency_ns = 6000;
d210246a
CW		 4273 int clock = enabled->mode.clock;
4274 int htotal = enabled->mode.htotal;
4275 int hdisplay = enabled->mode.hdisplay;
4276 int pixel_size = enabled->fb->bits_per_pixel / 8;
4277 unsigned long line_time_us;
4278 int entries;
dff33cfc 4279
d210246a 4280 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4281
4282 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4283 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4284 pixel_size * hdisplay;
4285 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4286 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4287 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4288 if (srwm < 0)
4289 srwm = 1;
ee980b80
LP		 4290
4291 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4292 I915_WRITE(FW_BLC_SELF,
4293 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4294 else if (IS_I915GM(dev))
ee980b80 4295 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4296 }
4297
28c97730 4298 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4299 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4300
dff33cfc
JB		 4301 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4302 fwater_hi = (cwm & 0x1f);
4303
4304 /* Set request length to 8 cachelines per fetch */
4305 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4306 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4307
4308 I915_WRITE(FW_BLC, fwater_lo);
4309 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4310
d210246a
CW		 4311 if (HAS_FW_BLC(dev)) {
4312 if (enabled) {
4313 if (IS_I945G(dev) || IS_I945GM(dev))
4314 I915_WRITE(FW_BLC_SELF,
4315 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4316 else if (IS_I915GM(dev))
4317 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4318 DRM_DEBUG_KMS("memory self refresh enabled\n");
4319 } else
4320 DRM_DEBUG_KMS("memory self refresh disabled\n");
4321 }
7662c8bd
SL		 4322}
4323
d210246a 4324static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4325{
4326 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4327 struct drm_crtc *crtc;
4328 uint32_t fwater_lo;
dff33cfc 4329 int planea_wm;
7662c8bd 4330
d210246a
CW		 4331 crtc = single_enabled_crtc(dev);
4332 if (crtc == NULL)
4333 return;
7662c8bd 4334
d210246a
CW		 4335 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4336 dev_priv->display.get_fifo_size(dev, 0),
4337 crtc->fb->bits_per_pixel / 8,
4338 latency_ns);
4339 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4340 fwater_lo |= (3<<8) | planea_wm;
4341
28c97730 4342 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4343
4344 I915_WRITE(FW_BLC, fwater_lo);
4345}
4346
7f8a8569 4347#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4348#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4349
1398261a
YL		 4350/*
4351 * Check the wm result.
4352 *
4353 * If any calculated watermark values is larger than the maximum value that
4354 * can be programmed into the associated watermark register, that watermark
4355 * must be disabled.
1398261a 4356 */
b79d4990
JB		 4357static bool ironlake_check_srwm(struct drm_device *dev, int level,
4358 int fbc_wm, int display_wm, int cursor_wm,
4359 const struct intel_watermark_params *display,
4360 const struct intel_watermark_params *cursor)
1398261a
YL		 4361{
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363
4364 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4365 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4366
4367 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4368 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4369 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4370
4371 /* fbc has it's own way to disable FBC WM */
4372 I915_WRITE(DISP_ARB_CTL,
4373 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4374 return false;
4375 }
4376
b79d4990 4377 if (display_wm > display->max_wm) {
1398261a 4378 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4379 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4380 return false;
4381 }
4382
b79d4990 4383 if (cursor_wm > cursor->max_wm) {
1398261a 4384 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4385 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4386 return false;
4387 }
4388
4389 if (!(fbc_wm || display_wm || cursor_wm)) {
4390 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4391 return false;
4392 }
4393
4394 return true;
4395}
4396
4397/*
4398 * Compute watermark values of WM[1-3],
4399 */
d210246a
CW		 4400static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4401 int latency_ns,
b79d4990
JB		 4402 const struct intel_watermark_params *display,
4403 const struct intel_watermark_params *cursor,
4404 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4405{
d210246a 4406 struct drm_crtc *crtc;
1398261a 4407 unsigned long line_time_us;
d210246a 4408 int hdisplay, htotal, pixel_size, clock;
b79d4990 4409 int line_count, line_size;
1398261a
YL		 4410 int small, large;
4411 int entries;
1398261a
YL		 4412
4413 if (!latency_ns) {
4414 *fbc_wm = *display_wm = *cursor_wm = 0;
4415 return false;
4416 }
4417
d210246a
CW		 4418 crtc = intel_get_crtc_for_plane(dev, plane);
4419 hdisplay = crtc->mode.hdisplay;
4420 htotal = crtc->mode.htotal;
4421 clock = crtc->mode.clock;
4422 pixel_size = crtc->fb->bits_per_pixel / 8;
4423
1398261a
YL		 4424 line_time_us = (htotal * 1000) / clock;
4425 line_count = (latency_ns / line_time_us + 1000) / 1000;
4426 line_size = hdisplay * pixel_size;
4427
4428 /* Use the minimum of the small and large buffer method for primary */
4429 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4430 large = line_count * line_size;
4431
b79d4990
JB		 4432 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4433 *display_wm = entries + display->guard_size;
1398261a
YL		 4434
4435 /*
b79d4990 4436 * Spec says:
1398261a
YL		 4437 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4438 */
4439 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4440
4441 /* calculate the self-refresh watermark for display cursor */
4442 entries = line_count * pixel_size * 64;
b79d4990
JB		 4443 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4444 *cursor_wm = entries + cursor->guard_size;
1398261a 4445
b79d4990
JB		 4446 return ironlake_check_srwm(dev, level,
4447 *fbc_wm, *display_wm, *cursor_wm,
4448 display, cursor);
4449}
4450
d210246a 4451static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4452{
4453 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4454 int fbc_wm, plane_wm, cursor_wm;
4455 unsigned int enabled;
b79d4990
JB		 4456
4457 enabled = 0;
9f405100
CW		 4458 if (g4x_compute_wm0(dev, 0,
4459 &ironlake_display_wm_info,
4460 ILK_LP0_PLANE_LATENCY,
4461 &ironlake_cursor_wm_info,
4462 ILK_LP0_CURSOR_LATENCY,
4463 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4464 I915_WRITE(WM0_PIPEA_ILK,
4465 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4467 " plane %d, " "cursor: %d\n",
4468 plane_wm, cursor_wm);
d210246a 4469 enabled |= 1;
b79d4990
JB		 4470 }
4471
9f405100
CW		 4472 if (g4x_compute_wm0(dev, 1,
4473 &ironlake_display_wm_info,
4474 ILK_LP0_PLANE_LATENCY,
4475 &ironlake_cursor_wm_info,
4476 ILK_LP0_CURSOR_LATENCY,
4477 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4478 I915_WRITE(WM0_PIPEB_ILK,
4479 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4480 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4481 " plane %d, cursor: %d\n",
4482 plane_wm, cursor_wm);
d210246a 4483 enabled |= 2;
b79d4990
JB		 4484 }
4485
4486 /*
4487 * Calculate and update the self-refresh watermark only when one
4488 * display plane is used.
4489 */
4490 I915_WRITE(WM3_LP_ILK, 0);
4491 I915_WRITE(WM2_LP_ILK, 0);
4492 I915_WRITE(WM1_LP_ILK, 0);
4493
d210246a 4494 if (!single_plane_enabled(enabled))
b79d4990 4495 return;
d210246a 4496 enabled = ffs(enabled) - 1;
b79d4990
JB		 4497
4498 /* WM1 */
d210246a
CW		 4499 if (!ironlake_compute_srwm(dev, 1, enabled,
4500 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4501 &ironlake_display_srwm_info,
4502 &ironlake_cursor_srwm_info,
4503 &fbc_wm, &plane_wm, &cursor_wm))
4504 return;
4505
4506 I915_WRITE(WM1_LP_ILK,
4507 WM1_LP_SR_EN |
4508 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4509 (fbc_wm << WM1_LP_FBC_SHIFT) |
4510 (plane_wm << WM1_LP_SR_SHIFT) |
4511 cursor_wm);
4512
4513 /* WM2 */
d210246a
CW		 4514 if (!ironlake_compute_srwm(dev, 2, enabled,
4515 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4516 &ironlake_display_srwm_info,
4517 &ironlake_cursor_srwm_info,
4518 &fbc_wm, &plane_wm, &cursor_wm))
4519 return;
4520
4521 I915_WRITE(WM2_LP_ILK,
4522 WM2_LP_EN |
4523 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4524 (fbc_wm << WM1_LP_FBC_SHIFT) |
4525 (plane_wm << WM1_LP_SR_SHIFT) |
4526 cursor_wm);
4527
4528 /*
4529 * WM3 is unsupported on ILK, probably because we don't have latency
4530 * data for that power state
4531 */
1398261a
YL		 4532}
4533
b840d907 4534void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4535{
4536 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4537 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4538 int fbc_wm, plane_wm, cursor_wm;
4539 unsigned int enabled;
1398261a
YL		 4540
4541 enabled = 0;
9f405100
CW		 4542 if (g4x_compute_wm0(dev, 0,
4543 &sandybridge_display_wm_info, latency,
4544 &sandybridge_cursor_wm_info, latency,
4545 &plane_wm, &cursor_wm)) {
1398261a
YL		 4546 I915_WRITE(WM0_PIPEA_ILK,
4547 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4548 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4549 " plane %d, " "cursor: %d\n",
4550 plane_wm, cursor_wm);
d210246a 4551 enabled |= 1;
1398261a
YL		 4552 }
4553
9f405100
CW		 4554 if (g4x_compute_wm0(dev, 1,
4555 &sandybridge_display_wm_info, latency,
4556 &sandybridge_cursor_wm_info, latency,
4557 &plane_wm, &cursor_wm)) {
1398261a
YL		 4558 I915_WRITE(WM0_PIPEB_ILK,
4559 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4561 " plane %d, cursor: %d\n",
4562 plane_wm, cursor_wm);
d210246a 4563 enabled |= 2;
1398261a
YL		 4564 }
4565
d6c892df
JB		 4566 /* IVB has 3 pipes */
4567 if (IS_IVYBRIDGE(dev) &&
4568 g4x_compute_wm0(dev, 2,
4569 &sandybridge_display_wm_info, latency,
4570 &sandybridge_cursor_wm_info, latency,
4571 &plane_wm, &cursor_wm)) {
4572 I915_WRITE(WM0_PIPEC_IVB,
4573 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4574 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4575 " plane %d, cursor: %d\n",
4576 plane_wm, cursor_wm);
4577 enabled |= 3;
4578 }
4579
1398261a
YL		 4580 /*
4581 * Calculate and update the self-refresh watermark only when one
4582 * display plane is used.
4583 *
4584 * SNB support 3 levels of watermark.
4585 *
4586 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4587 * and disabled in the descending order
4588 *
4589 */
4590 I915_WRITE(WM3_LP_ILK, 0);
4591 I915_WRITE(WM2_LP_ILK, 0);
4592 I915_WRITE(WM1_LP_ILK, 0);
4593
b840d907
JB		 4594 if (!single_plane_enabled(enabled) ||
4595 dev_priv->sprite_scaling_enabled)
1398261a 4596 return;
d210246a 4597 enabled = ffs(enabled) - 1;
1398261a
YL		 4598
4599 /* WM1 */
d210246a
CW		 4600 if (!ironlake_compute_srwm(dev, 1, enabled,
4601 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4602 &sandybridge_display_srwm_info,
4603 &sandybridge_cursor_srwm_info,
4604 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4605 return;
4606
4607 I915_WRITE(WM1_LP_ILK,
4608 WM1_LP_SR_EN |
4609 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4610 (fbc_wm << WM1_LP_FBC_SHIFT) |
4611 (plane_wm << WM1_LP_SR_SHIFT) |
4612 cursor_wm);
4613
4614 /* WM2 */
d210246a
CW		 4615 if (!ironlake_compute_srwm(dev, 2, enabled,
4616 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4617 &sandybridge_display_srwm_info,
4618 &sandybridge_cursor_srwm_info,
4619 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4620 return;
4621
4622 I915_WRITE(WM2_LP_ILK,
4623 WM2_LP_EN |
4624 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4625 (fbc_wm << WM1_LP_FBC_SHIFT) |
4626 (plane_wm << WM1_LP_SR_SHIFT) |
4627 cursor_wm);
4628
4629 /* WM3 */
d210246a
CW		 4630 if (!ironlake_compute_srwm(dev, 3, enabled,
4631 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4632 &sandybridge_display_srwm_info,
4633 &sandybridge_cursor_srwm_info,
4634 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4635 return;
4636
4637 I915_WRITE(WM3_LP_ILK,
4638 WM3_LP_EN |
4639 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4640 (fbc_wm << WM1_LP_FBC_SHIFT) |
4641 (plane_wm << WM1_LP_SR_SHIFT) |
4642 cursor_wm);
4643}
4644
b840d907
JB		 4645static bool
4646sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4647 uint32_t sprite_width, int pixel_size,
4648 const struct intel_watermark_params *display,
4649 int display_latency_ns, int *sprite_wm)
4650{
4651 struct drm_crtc *crtc;
4652 int clock;
4653 int entries, tlb_miss;
4654
4655 crtc = intel_get_crtc_for_plane(dev, plane);
4656 if (crtc->fb == NULL || !crtc->enabled) {
4657 *sprite_wm = display->guard_size;
4658 return false;
4659 }
4660
4661 clock = crtc->mode.clock;
4662
4663 /* Use the small buffer method to calculate the sprite watermark */
4664 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4665 tlb_miss = display->fifo_size*display->cacheline_size -
4666 sprite_width * 8;
4667 if (tlb_miss > 0)
4668 entries += tlb_miss;
4669 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4670 *sprite_wm = entries + display->guard_size;
4671 if (*sprite_wm > (int)display->max_wm)
4672 *sprite_wm = display->max_wm;
4673
4674 return true;
4675}
4676
4677static bool
4678sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4679 uint32_t sprite_width, int pixel_size,
4680 const struct intel_watermark_params *display,
4681 int latency_ns, int *sprite_wm)
4682{
4683 struct drm_crtc *crtc;
4684 unsigned long line_time_us;
4685 int clock;
4686 int line_count, line_size;
4687 int small, large;
4688 int entries;
4689
4690 if (!latency_ns) {
4691 *sprite_wm = 0;
4692 return false;
4693 }
4694
4695 crtc = intel_get_crtc_for_plane(dev, plane);
4696 clock = crtc->mode.clock;
4697
4698 line_time_us = (sprite_width * 1000) / clock;
4699 line_count = (latency_ns / line_time_us + 1000) / 1000;
4700 line_size = sprite_width * pixel_size;
4701
4702 /* Use the minimum of the small and large buffer method for primary */
4703 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4704 large = line_count * line_size;
4705
4706 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4707 *sprite_wm = entries + display->guard_size;
4708
4709 return *sprite_wm > 0x3ff ? false : true;
4710}
4711
4712static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4713 uint32_t sprite_width, int pixel_size)
4714{
4715 struct drm_i915_private *dev_priv = dev->dev_private;
4716 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4717 int sprite_wm, reg;
4718 int ret;
4719
4720 switch (pipe) {
4721 case 0:
4722 reg = WM0_PIPEA_ILK;
4723 break;
4724 case 1:
4725 reg = WM0_PIPEB_ILK;
4726 break;
4727 case 2:
4728 reg = WM0_PIPEC_IVB;
4729 break;
4730 default:
4731 return; /* bad pipe */
4732 }
4733
4734 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4735 &sandybridge_display_wm_info,
4736 latency, &sprite_wm);
4737 if (!ret) {
4738 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4739 pipe);
4740 return;
4741 }
4742
4743 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4744 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4745
4746
4747 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4748 pixel_size,
4749 &sandybridge_display_srwm_info,
4750 SNB_READ_WM1_LATENCY() * 500,
4751 &sprite_wm);
4752 if (!ret) {
4753 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4754 pipe);
4755 return;
4756 }
4757 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4758
4759 /* Only IVB has two more LP watermarks for sprite */
4760 if (!IS_IVYBRIDGE(dev))
4761 return;
4762
4763 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4764 pixel_size,
4765 &sandybridge_display_srwm_info,
4766 SNB_READ_WM2_LATENCY() * 500,
4767 &sprite_wm);
4768 if (!ret) {
4769 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4770 pipe);
4771 return;
4772 }
4773 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4774
4775 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4776 pixel_size,
4777 &sandybridge_display_srwm_info,
4778 SNB_READ_WM3_LATENCY() * 500,
4779 &sprite_wm);
4780 if (!ret) {
4781 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4782 pipe);
4783 return;
4784 }
4785 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4786}
4787
7662c8bd
SL		 4788/**
4789 * intel_update_watermarks - update FIFO watermark values based on current modes
4790 *
4791 * Calculate watermark values for the various WM regs based on current mode
4792 * and plane configuration.
4793 *
4794 * There are several cases to deal with here:
4795 * - normal (i.e. non-self-refresh)
4796 * - self-refresh (SR) mode
4797 * - lines are large relative to FIFO size (buffer can hold up to 2)
4798 * - lines are small relative to FIFO size (buffer can hold more than 2
4799 * lines), so need to account for TLB latency
4800 *
4801 * The normal calculation is:
4802 * watermark = dotclock * bytes per pixel * latency
4803 * where latency is platform & configuration dependent (we assume pessimal
4804 * values here).
4805 *
4806 * The SR calculation is:
4807 * watermark = (trunc(latency/line time)+1) * surface width *
4808 * bytes per pixel
4809 * where
4810 * line time = htotal / dotclock
fa143215 4811 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4812 * and latency is assumed to be high, as above.
4813 *
4814 * The final value programmed to the register should always be rounded up,
4815 * and include an extra 2 entries to account for clock crossings.
4816 *
4817 * We don't use the sprite, so we can ignore that. And on Crestline we have
4818 * to set the non-SR watermarks to 8.
5eddb70b 4819 */
7662c8bd
SL		 4820static void intel_update_watermarks(struct drm_device *dev)
4821{
e70236a8 4822 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4823
d210246a
CW		 4824 if (dev_priv->display.update_wm)
4825 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4826}
4827
b840d907
JB		 4828void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4829 uint32_t sprite_width, int pixel_size)
4830{
4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832
4833 if (dev_priv->display.update_sprite_wm)
4834 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4835 pixel_size);
4836}
4837
a7615030
CW		 4838static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4839{
72bbe58c
KP		 4840 if (i915_panel_use_ssc >= 0)
4841 return i915_panel_use_ssc != 0;
4842 return dev_priv->lvds_use_ssc
435793df 4843 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4844}
4845
5a354204
JB		 4846/**
4847 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4848 * @crtc: CRTC structure
3b5c78a3 4849 * @mode: requested mode
5a354204
JB		 4850 *
4851 * A pipe may be connected to one or more outputs. Based on the depth of the
4852 * attached framebuffer, choose a good color depth to use on the pipe.
4853 *
4854 * If possible, match the pipe depth to the fb depth. In some cases, this
4855 * isn't ideal, because the connected output supports a lesser or restricted
4856 * set of depths. Resolve that here:
4857 * LVDS typically supports only 6bpc, so clamp down in that case
4858 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4859 * Displays may support a restricted set as well, check EDID and clamp as
4860 * appropriate.
3b5c78a3 4861 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4862 *
4863 * RETURNS:
4864 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4865 * true if they don't match).
4866 */
4867static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4868 unsigned int *pipe_bpp,
4869 struct drm_display_mode *mode)
5a354204
JB		 4870{
4871 struct drm_device *dev = crtc->dev;
4872 struct drm_i915_private *dev_priv = dev->dev_private;
4873 struct drm_encoder *encoder;
4874 struct drm_connector *connector;
4875 unsigned int display_bpc = UINT_MAX, bpc;
4876
4877 /* Walk the encoders & connectors on this crtc, get min bpc */
4878 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4879 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4880
4881 if (encoder->crtc != crtc)
4882 continue;
4883
4884 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4885 unsigned int lvds_bpc;
4886
4887 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4888 LVDS_A3_POWER_UP)
4889 lvds_bpc = 8;
4890 else
4891 lvds_bpc = 6;
4892
4893 if (lvds_bpc < display_bpc) {
82820490 4894 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4895 display_bpc = lvds_bpc;
4896 }
4897 continue;
4898 }
4899
4900 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4901 /* Use VBT settings if we have an eDP panel */
4902 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4903
4904 if (edp_bpc < display_bpc) {
82820490 4905 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4906 display_bpc = edp_bpc;
4907 }
4908 continue;
4909 }
4910
4911 /* Not one of the known troublemakers, check the EDID */
4912 list_for_each_entry(connector, &dev->mode_config.connector_list,
4913 head) {
4914 if (connector->encoder != encoder)
4915 continue;
4916
62ac41a6
JB		 4917 /* Don't use an invalid EDID bpc value */
4918 if (connector->display_info.bpc &&
4919 connector->display_info.bpc < display_bpc) {
82820490 4920 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4921 display_bpc = connector->display_info.bpc;
4922 }
4923 }
4924
4925 /*
4926 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4927 * through, clamp it down. (Note: >12bpc will be caught below.)
4928 */
4929 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4930 if (display_bpc > 8 && display_bpc < 12) {
82820490 4931 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4932 display_bpc = 12;
4933 } else {
82820490 4934 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4935 display_bpc = 8;
4936 }
4937 }
4938 }
4939
3b5c78a3
AJ		 4940 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4941 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4942 display_bpc = 6;
4943 }
4944
5a354204
JB		 4945 /*
4946 * We could just drive the pipe at the highest bpc all the time and
4947 * enable dithering as needed, but that costs bandwidth. So choose
4948 * the minimum value that expresses the full color range of the fb but
4949 * also stays within the max display bpc discovered above.
4950 */
4951
4952 switch (crtc->fb->depth) {
4953 case 8:
4954 bpc = 8; /* since we go through a colormap */
4955 break;
4956 case 15:
4957 case 16:
4958 bpc = 6; /* min is 18bpp */
4959 break;
4960 case 24:
578393cd 4961 bpc = 8;
5a354204
JB		 4962 break;
4963 case 30:
578393cd 4964 bpc = 10;
5a354204
JB		 4965 break;
4966 case 48:
578393cd 4967 bpc = 12;
5a354204
JB		 4968 break;
4969 default:
4970 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4971 bpc = min((unsigned int)8, display_bpc);
4972 break;
4973 }
4974
578393cd
KP		 4975 display_bpc = min(display_bpc, bpc);
4976
82820490
AJ		 4977 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4978 bpc, display_bpc);
5a354204 4979
578393cd 4980 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4981
4982 return display_bpc != bpc;
4983}
4984
c65d77d8
JB		 4985static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4986{
4987 struct drm_device *dev = crtc->dev;
4988 struct drm_i915_private *dev_priv = dev->dev_private;
4989 int refclk;
4990
4991 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4992 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4993 refclk = dev_priv->lvds_ssc_freq * 1000;
4994 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4995 refclk / 1000);
4996 } else if (!IS_GEN2(dev)) {
4997 refclk = 96000;
4998 } else {
4999 refclk = 48000;
5000 }
5001
5002 return refclk;
5003}
5004
5005static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5006 intel_clock_t *clock)
5007{
5008 /* SDVO TV has fixed PLL values depend on its clock range,
5009 this mirrors vbios setting. */
5010 if (adjusted_mode->clock >= 100000
5011 && adjusted_mode->clock < 140500) {
5012 clock->p1 = 2;
5013 clock->p2 = 10;
5014 clock->n = 3;
5015 clock->m1 = 16;
5016 clock->m2 = 8;
5017 } else if (adjusted_mode->clock >= 140500
5018 && adjusted_mode->clock <= 200000) {
5019 clock->p1 = 1;
5020 clock->p2 = 10;
5021 clock->n = 6;
5022 clock->m1 = 12;
5023 clock->m2 = 8;
5024 }
5025}
5026
a7516a05
JB		 5027static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5028 intel_clock_t *clock,
5029 intel_clock_t *reduced_clock)
5030{
5031 struct drm_device *dev = crtc->dev;
5032 struct drm_i915_private *dev_priv = dev->dev_private;
5033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5034 int pipe = intel_crtc->pipe;
5035 u32 fp, fp2 = 0;
5036
5037 if (IS_PINEVIEW(dev)) {
5038 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5039 if (reduced_clock)
5040 fp2 = (1 << reduced_clock->n) << 16 |
5041 reduced_clock->m1 << 8 | reduced_clock->m2;
5042 } else {
5043 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5044 if (reduced_clock)
5045 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5046 reduced_clock->m2;
5047 }
5048
5049 I915_WRITE(FP0(pipe), fp);
5050
5051 intel_crtc->lowfreq_avail = false;
5052 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5053 reduced_clock && i915_powersave) {
5054 I915_WRITE(FP1(pipe), fp2);
5055 intel_crtc->lowfreq_avail = true;
5056 } else {
5057 I915_WRITE(FP1(pipe), fp);
5058 }
5059}
5060
f564048e
EA		 5061static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5062 struct drm_display_mode *mode,
5063 struct drm_display_mode *adjusted_mode,
5064 int x, int y,
5065 struct drm_framebuffer *old_fb)
79e53945
JB		 5066{
5067 struct drm_device *dev = crtc->dev;
5068 struct drm_i915_private *dev_priv = dev->dev_private;
5069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5070 int pipe = intel_crtc->pipe;
80824003 5071 int plane = intel_crtc->plane;
c751ce4f 5072 int refclk, num_connectors = 0;
652c393a 5073 intel_clock_t clock, reduced_clock;
a7516a05 5074 u32 dpll, dspcntr, pipeconf;
652c393a 5075 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5076 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5077 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5078 struct intel_encoder *encoder;
d4906093 5079 const intel_limit_t *limit;
5c3b82e2 5080 int ret;
fae14981 5081 u32 temp;
aa9b500d 5082 u32 lvds_sync = 0;
79e53945 5083
5eddb70b
CW		 5084 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5085 if (encoder->base.crtc != crtc)
79e53945
JB		 5086 continue;
5087
5eddb70b 5088 switch (encoder->type) {
79e53945
JB		 5089 case INTEL_OUTPUT_LVDS:
5090 is_lvds = true;
5091 break;
5092 case INTEL_OUTPUT_SDVO:
7d57382e 5093 case INTEL_OUTPUT_HDMI:
79e53945 5094 is_sdvo = true;
5eddb70b 5095 if (encoder->needs_tv_clock)
e2f0ba97 5096 is_tv = true;
79e53945
JB		 5097 break;
5098 case INTEL_OUTPUT_DVO:
5099 is_dvo = true;
5100 break;
5101 case INTEL_OUTPUT_TVOUT:
5102 is_tv = true;
5103 break;
5104 case INTEL_OUTPUT_ANALOG:
5105 is_crt = true;
5106 break;
a4fc5ed6
KP		 5107 case INTEL_OUTPUT_DISPLAYPORT:
5108 is_dp = true;
5109 break;
79e53945 5110 }
43565a06 5111
c751ce4f 5112 num_connectors++;
79e53945
JB		 5113 }
5114
c65d77d8 5115 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5116
d4906093
ML		 5117 /*
5118 * Returns a set of divisors for the desired target clock with the given
5119 * refclk, or FALSE. The returned values represent the clock equation:
5120 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5121 */
1b894b59 5122 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5123 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5124 &clock);
79e53945
JB		 5125 if (!ok) {
5126 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5127 return -EINVAL;
79e53945
JB		 5128 }
5129
cda4b7d3 5130 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5131 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5132
ddc9003c 5133 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5134 /*
5135 * Ensure we match the reduced clock's P to the target clock.
5136 * If the clocks don't match, we can't switch the display clock
5137 * by using the FP0/FP1. In such case we will disable the LVDS
5138 * downclock feature.
5139 */
ddc9003c 5140 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5141 dev_priv->lvds_downclock,
5142 refclk,
cec2f356 5143 &clock,
5eddb70b 5144 &reduced_clock);
652c393a 5145 }
c65d77d8
JB		 5146
5147 if (is_sdvo && is_tv)
5148 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5149
a7516a05
JB		 5150 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5151 &reduced_clock : NULL);
79e53945 5152
929c77fb 5153 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5154
a6c45cf0 5155 if (!IS_GEN2(dev)) {
79e53945
JB		 5156 if (is_lvds)
5157 dpll |= DPLLB_MODE_LVDS;
5158 else
5159 dpll |= DPLLB_MODE_DAC_SERIAL;
5160 if (is_sdvo) {
6c9547ff
CW		 5161 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5162 if (pixel_multiplier > 1) {
5163 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5164 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5165 }
79e53945 5166 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5167 }
929c77fb 5168 if (is_dp)
a4fc5ed6 5169 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5170
5171 /* compute bitmask from p1 value */
f2b115e6
AJ		 5172 if (IS_PINEVIEW(dev))
5173 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5174 else {
2177832f 5175 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5176 if (IS_G4X(dev) && has_reduced_clock)
5177 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5178 }
79e53945
JB		 5179 switch (clock.p2) {
5180 case 5:
5181 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5182 break;
5183 case 7:
5184 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5185 break;
5186 case 10:
5187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5188 break;
5189 case 14:
5190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5191 break;
5192 }
929c77fb 5193 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5194 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5195 } else {
5196 if (is_lvds) {
5197 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5198 } else {
5199 if (clock.p1 == 2)
5200 dpll |= PLL_P1_DIVIDE_BY_TWO;
5201 else
5202 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5203 if (clock.p2 == 4)
5204 dpll |= PLL_P2_DIVIDE_BY_4;
5205 }
5206 }
5207
43565a06
KH		 5208 if (is_sdvo && is_tv)
5209 dpll |= PLL_REF_INPUT_TVCLKINBC;
5210 else if (is_tv)
79e53945 5211 /* XXX: just matching BIOS for now */
43565a06 5212 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5213 dpll |= 3;
a7615030 5214 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5215 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5216 else
5217 dpll |= PLL_REF_INPUT_DREFCLK;
5218
5219 /* setup pipeconf */
5eddb70b 5220 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5221
5222 /* Set up the display plane register */
5223 dspcntr = DISPPLANE_GAMMA_ENABLE;
5224
f2b115e6 5225 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 5226 enable color space conversion */
929c77fb
EA		 5227 if (pipe == 0)
5228 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5229 else
5230 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5231
a6c45cf0 5232 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5233 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5234 * core speed.
5235 *
5236 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5237 * pipe == 0 check?
5238 */
e70236a8
JB		 5239 if (mode->clock >
5240 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5241 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5242 else
5eddb70b 5243 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5244 }
5245
3b5c78a3
AJ		 5246 /* default to 8bpc */
5247 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5248 if (is_dp) {
5249 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5250 pipeconf |= PIPECONF_BPP_6 |
5251 PIPECONF_DITHER_EN |
5252 PIPECONF_DITHER_TYPE_SP;
5253 }
5254 }
5255
929c77fb 5256 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5257
28c97730 5258 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5259 drm_mode_debug_printmodeline(mode);
5260
fae14981 5261 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5262
fae14981 5263 POSTING_READ(DPLL(pipe));
c713bb08 5264 udelay(150);
8db9d77b 5265
79e53945
JB		 5266 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5267 * This is an exception to the general rule that mode_set doesn't turn
5268 * things on.
5269 */
5270 if (is_lvds) {
fae14981 5271 temp = I915_READ(LVDS);
5eddb70b 5272 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5273 if (pipe == 1) {
929c77fb 5274 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5275 } else {
929c77fb 5276 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5277 }
a3e17eb8 5278 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5279 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5280 /* Set the B0-B3 data pairs corresponding to whether we're going to
5281 * set the DPLLs for dual-channel mode or not.
5282 */
5283 if (clock.p2 == 7)
5eddb70b 5284 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5285 else
5eddb70b 5286 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5287
5288 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5289 * appropriately here, but we need to look more thoroughly into how
5290 * panels behave in the two modes.
5291 */
929c77fb
EA		 5292 /* set the dithering flag on LVDS as needed */
5293 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5294 if (dev_priv->lvds_dither)
5eddb70b 5295 temp |= LVDS_ENABLE_DITHER;
434ed097 5296 else
5eddb70b 5297 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5298 }
aa9b500d
BF		 5299 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5300 lvds_sync |= LVDS_HSYNC_POLARITY;
5301 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5302 lvds_sync |= LVDS_VSYNC_POLARITY;
5303 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5304 != lvds_sync) {
5305 char flags[2] = "-+";
5306 DRM_INFO("Changing LVDS panel from "
5307 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5308 flags[!(temp & LVDS_HSYNC_POLARITY)],
5309 flags[!(temp & LVDS_VSYNC_POLARITY)],
5310 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5311 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5312 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5313 temp |= lvds_sync;
5314 }
fae14981 5315 I915_WRITE(LVDS, temp);
79e53945 5316 }
434ed097 5317
929c77fb 5318 if (is_dp) {
a4fc5ed6 5319 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5320 }
5321
fae14981 5322 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5323
c713bb08 5324 /* Wait for the clocks to stabilize. */
fae14981 5325 POSTING_READ(DPLL(pipe));
c713bb08 5326 udelay(150);
32f9d658 5327
c713bb08
EA		 5328 if (INTEL_INFO(dev)->gen >= 4) {
5329 temp = 0;
5330 if (is_sdvo) {
5331 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5332 if (temp > 1)
5333 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5334 else
5335 temp = 0;
32f9d658 5336 }
c713bb08
EA		 5337 I915_WRITE(DPLL_MD(pipe), temp);
5338 } else {
5339 /* The pixel multiplier can only be updated once the
5340 * DPLL is enabled and the clocks are stable.
5341 *
5342 * So write it again.
5343 */
fae14981 5344 I915_WRITE(DPLL(pipe), dpll);
79e53945 5345 }
79e53945 5346
a7516a05
JB		 5347 if (HAS_PIPE_CXSR(dev)) {
5348 if (intel_crtc->lowfreq_avail) {
28c97730 5349 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5350 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5351 } else {
28c97730 5352 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5353 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5354 }
5355 }
5356
734b4157
KH		 5357 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5358 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5359 /* the chip adds 2 halflines automatically */
5360 adjusted_mode->crtc_vdisplay -= 1;
5361 adjusted_mode->crtc_vtotal -= 1;
5362 adjusted_mode->crtc_vblank_start -= 1;
5363 adjusted_mode->crtc_vblank_end -= 1;
5364 adjusted_mode->crtc_vsync_end -= 1;
5365 adjusted_mode->crtc_vsync_start -= 1;
5366 } else
59df7b17 5367 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
734b4157 5368
5eddb70b
CW		 5369 I915_WRITE(HTOTAL(pipe),
5370 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5371 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5372 I915_WRITE(HBLANK(pipe),
5373 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5374 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5375 I915_WRITE(HSYNC(pipe),
5376 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5377 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5378
5379 I915_WRITE(VTOTAL(pipe),
5380 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5381 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5382 I915_WRITE(VBLANK(pipe),
5383 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5384 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5385 I915_WRITE(VSYNC(pipe),
5386 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5387 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5388
5389 /* pipesrc and dspsize control the size that is scaled from,
5390 * which should always be the user's requested size.
79e53945 5391 */
929c77fb
EA		 5392 I915_WRITE(DSPSIZE(plane),
5393 ((mode->vdisplay - 1) << 16) |
5394 (mode->hdisplay - 1));
5395 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5396 I915_WRITE(PIPESRC(pipe),
5397 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5398
f564048e
EA		 5399 I915_WRITE(PIPECONF(pipe), pipeconf);
5400 POSTING_READ(PIPECONF(pipe));
929c77fb 5401 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5402
5403 intel_wait_for_vblank(dev, pipe);
5404
f564048e
EA		 5405 I915_WRITE(DSPCNTR(plane), dspcntr);
5406 POSTING_READ(DSPCNTR(plane));
284d9529 5407 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5408
5409 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5410
5411 intel_update_watermarks(dev);
5412
f564048e
EA		 5413 return ret;
5414}
5415
9fb526db
KP		 5416/*
5417 * Initialize reference clocks when the driver loads
5418 */
5419void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5420{
5421 struct drm_i915_private *dev_priv = dev->dev_private;
5422 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5423 struct intel_encoder *encoder;
13d83a67
JB		 5424 u32 temp;
5425 bool has_lvds = false;
199e5d79
KP		 5426 bool has_cpu_edp = false;
5427 bool has_pch_edp = false;
5428 bool has_panel = false;
99eb6a01
KP		 5429 bool has_ck505 = false;
5430 bool can_ssc = false;
13d83a67
JB		 5431
5432 /* We need to take the global config into account */
199e5d79
KP		 5433 list_for_each_entry(encoder, &mode_config->encoder_list,
5434 base.head) {
5435 switch (encoder->type) {
5436 case INTEL_OUTPUT_LVDS:
5437 has_panel = true;
5438 has_lvds = true;
5439 break;
5440 case INTEL_OUTPUT_EDP:
5441 has_panel = true;
5442 if (intel_encoder_is_pch_edp(&encoder->base))
5443 has_pch_edp = true;
5444 else
5445 has_cpu_edp = true;
5446 break;
13d83a67
JB		 5447 }
5448 }
5449
99eb6a01
KP		 5450 if (HAS_PCH_IBX(dev)) {
5451 has_ck505 = dev_priv->display_clock_mode;
5452 can_ssc = has_ck505;
5453 } else {
5454 has_ck505 = false;
5455 can_ssc = true;
5456 }
5457
5458 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5459 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5460 has_ck505);
13d83a67
JB		 5461
5462 /* Ironlake: try to setup display ref clock before DPLL
5463 * enabling. This is only under driver's control after
5464 * PCH B stepping, previous chipset stepping should be
5465 * ignoring this setting.
5466 */
5467 temp = I915_READ(PCH_DREF_CONTROL);
5468 /* Always enable nonspread source */
5469 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5470
99eb6a01
KP		 5471 if (has_ck505)
5472 temp |= DREF_NONSPREAD_CK505_ENABLE;
5473 else
5474 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5475
199e5d79
KP		 5476 if (has_panel) {
5477 temp &= ~DREF_SSC_SOURCE_MASK;
5478 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5479
199e5d79 5480 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5481 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5482 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5483 temp |= DREF_SSC1_ENABLE;
13d83a67 5484 }
199e5d79
KP		 5485
5486 /* Get SSC going before enabling the outputs */
5487 I915_WRITE(PCH_DREF_CONTROL, temp);
5488 POSTING_READ(PCH_DREF_CONTROL);
5489 udelay(200);
5490
13d83a67
JB		 5491 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5492
5493 /* Enable CPU source on CPU attached eDP */
199e5d79 5494 if (has_cpu_edp) {
99eb6a01 5495 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5496 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5497 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5498 }
13d83a67
JB		 5499 else
5500 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5501 } else
5502 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5503
5504 I915_WRITE(PCH_DREF_CONTROL, temp);
5505 POSTING_READ(PCH_DREF_CONTROL);
5506 udelay(200);
5507 } else {
5508 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5509
5510 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5511
5512 /* Turn off CPU output */
5513 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5514
5515 I915_WRITE(PCH_DREF_CONTROL, temp);
5516 POSTING_READ(PCH_DREF_CONTROL);
5517 udelay(200);
5518
5519 /* Turn off the SSC source */
5520 temp &= ~DREF_SSC_SOURCE_MASK;
5521 temp |= DREF_SSC_SOURCE_DISABLE;
5522
5523 /* Turn off SSC1 */
5524 temp &= ~ DREF_SSC1_ENABLE;
5525
13d83a67
JB		 5526 I915_WRITE(PCH_DREF_CONTROL, temp);
5527 POSTING_READ(PCH_DREF_CONTROL);
5528 udelay(200);
5529 }
5530}
5531
d9d444cb
JB		 5532static int ironlake_get_refclk(struct drm_crtc *crtc)
5533{
5534 struct drm_device *dev = crtc->dev;
5535 struct drm_i915_private *dev_priv = dev->dev_private;
5536 struct intel_encoder *encoder;
5537 struct drm_mode_config *mode_config = &dev->mode_config;
5538 struct intel_encoder *edp_encoder = NULL;
5539 int num_connectors = 0;
5540 bool is_lvds = false;
5541
5542 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5543 if (encoder->base.crtc != crtc)
5544 continue;
5545
5546 switch (encoder->type) {
5547 case INTEL_OUTPUT_LVDS:
5548 is_lvds = true;
5549 break;
5550 case INTEL_OUTPUT_EDP:
5551 edp_encoder = encoder;
5552 break;
5553 }
5554 num_connectors++;
5555 }
5556
5557 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5558 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5559 dev_priv->lvds_ssc_freq);
5560 return dev_priv->lvds_ssc_freq * 1000;
5561 }
5562
5563 return 120000;
5564}
5565
f564048e
EA		 5566static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5567 struct drm_display_mode *mode,
5568 struct drm_display_mode *adjusted_mode,
5569 int x, int y,
5570 struct drm_framebuffer *old_fb)
79e53945
JB		 5571{
5572 struct drm_device *dev = crtc->dev;
5573 struct drm_i915_private *dev_priv = dev->dev_private;
5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575 int pipe = intel_crtc->pipe;
80824003 5576 int plane = intel_crtc->plane;
c751ce4f 5577 int refclk, num_connectors = 0;
652c393a 5578 intel_clock_t clock, reduced_clock;
5eddb70b 5579 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5580 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5581 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5582 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5583 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5584 struct intel_encoder *encoder;
d4906093 5585 const intel_limit_t *limit;
5c3b82e2 5586 int ret;
2c07245f 5587 struct fdi_m_n m_n = {0};
fae14981 5588 u32 temp;
aa9b500d 5589 u32 lvds_sync = 0;
5a354204
JB		 5590 int target_clock, pixel_multiplier, lane, link_bw, factor;
5591 unsigned int pipe_bpp;
5592 bool dither;
79e53945 5593
5eddb70b
CW		 5594 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5595 if (encoder->base.crtc != crtc)
79e53945
JB		 5596 continue;
5597
5eddb70b 5598 switch (encoder->type) {
79e53945
JB		 5599 case INTEL_OUTPUT_LVDS:
5600 is_lvds = true;
5601 break;
5602 case INTEL_OUTPUT_SDVO:
7d57382e 5603 case INTEL_OUTPUT_HDMI:
79e53945 5604 is_sdvo = true;
5eddb70b 5605 if (encoder->needs_tv_clock)
e2f0ba97 5606 is_tv = true;
79e53945 5607 break;
79e53945
JB		 5608 case INTEL_OUTPUT_TVOUT:
5609 is_tv = true;
5610 break;
5611 case INTEL_OUTPUT_ANALOG:
5612 is_crt = true;
5613 break;
a4fc5ed6
KP		 5614 case INTEL_OUTPUT_DISPLAYPORT:
5615 is_dp = true;
5616 break;
32f9d658 5617 case INTEL_OUTPUT_EDP:
5eddb70b 5618 has_edp_encoder = encoder;
32f9d658 5619 break;
79e53945 5620 }
43565a06 5621
c751ce4f 5622 num_connectors++;
79e53945
JB		 5623 }
5624
d9d444cb 5625 refclk = ironlake_get_refclk(crtc);
79e53945 5626
d4906093
ML		 5627 /*
5628 * Returns a set of divisors for the desired target clock with the given
5629 * refclk, or FALSE. The returned values represent the clock equation:
5630 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5631 */
1b894b59 5632 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5633 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5634 &clock);
79e53945
JB		 5635 if (!ok) {
5636 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5637 return -EINVAL;
79e53945
JB		 5638 }
5639
cda4b7d3 5640 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5641 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5642
ddc9003c 5643 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5644 /*
5645 * Ensure we match the reduced clock's P to the target clock.
5646 * If the clocks don't match, we can't switch the display clock
5647 * by using the FP0/FP1. In such case we will disable the LVDS
5648 * downclock feature.
5649 */
ddc9003c 5650 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5651 dev_priv->lvds_downclock,
5652 refclk,
cec2f356 5653 &clock,
5eddb70b 5654 &reduced_clock);
652c393a 5655 }
7026d4ac
ZW		 5656 /* SDVO TV has fixed PLL values depend on its clock range,
5657 this mirrors vbios setting. */
5658 if (is_sdvo && is_tv) {
5659 if (adjusted_mode->clock >= 100000
5eddb70b 5660 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5661 clock.p1 = 2;
5662 clock.p2 = 10;
5663 clock.n = 3;
5664 clock.m1 = 16;
5665 clock.m2 = 8;
5666 } else if (adjusted_mode->clock >= 140500
5eddb70b 5667 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5668 clock.p1 = 1;
5669 clock.p2 = 10;
5670 clock.n = 6;
5671 clock.m1 = 12;
5672 clock.m2 = 8;
5673 }
5674 }
5675
2c07245f 5676 /* FDI link */
8febb297
EA		 5677 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5678 lane = 0;
5679 /* CPU eDP doesn't require FDI link, so just set DP M/N
5680 according to current link config */
5681 if (has_edp_encoder &&
5682 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5683 target_clock = mode->clock;
5684 intel_edp_link_config(has_edp_encoder,
5685 &lane, &link_bw);
5686 } else {
5687 /* [e]DP over FDI requires target mode clock
5688 instead of link clock */
5689 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5690 target_clock = mode->clock;
8febb297
EA		 5691 else
5692 target_clock = adjusted_mode->clock;
5693
5694 /* FDI is a binary signal running at ~2.7GHz, encoding
5695 * each output octet as 10 bits. The actual frequency
5696 * is stored as a divider into a 100MHz clock, and the
5697 * mode pixel clock is stored in units of 1KHz.
5698 * Hence the bw of each lane in terms of the mode signal
5699 * is:
5700 */
5701 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5702 }
58a27471 5703
8febb297
EA		 5704 /* determine panel color depth */
5705 temp = I915_READ(PIPECONF(pipe));
5706 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5707 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5708 switch (pipe_bpp) {
5709 case 18:
5710 temp |= PIPE_6BPC;
8febb297 5711 break;
5a354204
JB		 5712 case 24:
5713 temp |= PIPE_8BPC;
8febb297 5714 break;
5a354204
JB		 5715 case 30:
5716 temp |= PIPE_10BPC;
8febb297 5717 break;
5a354204
JB		 5718 case 36:
5719 temp |= PIPE_12BPC;
8febb297
EA		 5720 break;
5721 default:
62ac41a6
JB		 5722 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5723 pipe_bpp);
5a354204
JB		 5724 temp |= PIPE_8BPC;
5725 pipe_bpp = 24;
5726 break;
8febb297 5727 }
77ffb597 5728
5a354204
JB		 5729 intel_crtc->bpp = pipe_bpp;
5730 I915_WRITE(PIPECONF(pipe), temp);
5731
8febb297
EA		 5732 if (!lane) {
5733 /*
5734 * Account for spread spectrum to avoid
5735 * oversubscribing the link. Max center spread
5736 * is 2.5%; use 5% for safety's sake.
5737 */
5a354204 5738 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5739 lane = bps / (link_bw * 8) + 1;
5eb08b69 5740 }
2c07245f 5741
8febb297
EA		 5742 intel_crtc->fdi_lanes = lane;
5743
5744 if (pixel_multiplier > 1)
5745 link_bw *= pixel_multiplier;
5a354204
JB		 5746 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5747 &m_n);
8febb297 5748
a07d6787
EA		 5749 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5750 if (has_reduced_clock)
5751 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5752 reduced_clock.m2;
79e53945 5753
c1858123 5754 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5755 factor = 21;
5756 if (is_lvds) {
5757 if ((intel_panel_use_ssc(dev_priv) &&
5758 dev_priv->lvds_ssc_freq == 100) ||
5759 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5760 factor = 25;
5761 } else if (is_sdvo && is_tv)
5762 factor = 20;
c1858123 5763
cb0e0931 5764 if (clock.m < factor * clock.n)
8febb297 5765 fp |= FP_CB_TUNE;
2c07245f 5766
5eddb70b 5767 dpll = 0;
2c07245f 5768
a07d6787
EA		 5769 if (is_lvds)
5770 dpll |= DPLLB_MODE_LVDS;
5771 else
5772 dpll |= DPLLB_MODE_DAC_SERIAL;
5773 if (is_sdvo) {
5774 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5775 if (pixel_multiplier > 1) {
5776 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5777 }
a07d6787
EA		 5778 dpll |= DPLL_DVO_HIGH_SPEED;
5779 }
5780 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5781 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5782
a07d6787
EA		 5783 /* compute bitmask from p1 value */
5784 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5785 /* also FPA1 */
5786 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5787
5788 switch (clock.p2) {
5789 case 5:
5790 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5791 break;
5792 case 7:
5793 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5794 break;
5795 case 10:
5796 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5797 break;
5798 case 14:
5799 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5800 break;
79e53945
JB		 5801 }
5802
43565a06
KH		 5803 if (is_sdvo && is_tv)
5804 dpll |= PLL_REF_INPUT_TVCLKINBC;
5805 else if (is_tv)
79e53945 5806 /* XXX: just matching BIOS for now */
43565a06 5807 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5808 dpll |= 3;
a7615030 5809 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5810 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5811 else
5812 dpll |= PLL_REF_INPUT_DREFCLK;
5813
5814 /* setup pipeconf */
5eddb70b 5815 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5816
5817 /* Set up the display plane register */
5818 dspcntr = DISPPLANE_GAMMA_ENABLE;
5819
f7cb34d4 5820 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5821 drm_mode_debug_printmodeline(mode);
5822
5c5313c8 5823 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5824 if (!intel_crtc->no_pll) {
5825 if (!has_edp_encoder ||
5826 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5827 I915_WRITE(PCH_FP0(pipe), fp);
5828 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5829
5830 POSTING_READ(PCH_DPLL(pipe));
5831 udelay(150);
5832 }
5833 } else {
5834 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5835 fp == I915_READ(PCH_FP0(0))) {
5836 intel_crtc->use_pll_a = true;
5837 DRM_DEBUG_KMS("using pipe a dpll\n");
5838 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5839 fp == I915_READ(PCH_FP0(1))) {
5840 intel_crtc->use_pll_a = false;
5841 DRM_DEBUG_KMS("using pipe b dpll\n");
5842 } else {
5843 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5844 return -EINVAL;
5845 }
79e53945
JB		 5846 }
5847
5848 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5849 * This is an exception to the general rule that mode_set doesn't turn
5850 * things on.
5851 */
5852 if (is_lvds) {
fae14981 5853 temp = I915_READ(PCH_LVDS);
5eddb70b 5854 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4b645f14
JB		 5855 if (HAS_PCH_CPT(dev))
5856 temp |= PORT_TRANS_SEL_CPT(pipe);
5857 else if (pipe == 1)
5858 temp |= LVDS_PIPEB_SELECT;
5859 else
5860 temp &= ~LVDS_PIPEB_SELECT;
5861
a3e17eb8 5862 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5863 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5864 /* Set the B0-B3 data pairs corresponding to whether we're going to
5865 * set the DPLLs for dual-channel mode or not.
5866 */
5867 if (clock.p2 == 7)
5eddb70b 5868 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5869 else
5eddb70b 5870 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5871
5872 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5873 * appropriately here, but we need to look more thoroughly into how
5874 * panels behave in the two modes.
5875 */
aa9b500d
BF		 5876 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5877 lvds_sync |= LVDS_HSYNC_POLARITY;
5878 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5879 lvds_sync |= LVDS_VSYNC_POLARITY;
5880 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5881 != lvds_sync) {
5882 char flags[2] = "-+";
5883 DRM_INFO("Changing LVDS panel from "
5884 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5885 flags[!(temp & LVDS_HSYNC_POLARITY)],
5886 flags[!(temp & LVDS_VSYNC_POLARITY)],
5887 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5888 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5889 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5890 temp |= lvds_sync;
5891 }
fae14981 5892 I915_WRITE(PCH_LVDS, temp);
79e53945 5893 }
434ed097 5894
8febb297
EA		 5895 pipeconf &= ~PIPECONF_DITHER_EN;
5896 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5897 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5898 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5899 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5900 }
5c5313c8 5901 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5902 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5903 } else {
8db9d77b 5904 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5905 I915_WRITE(TRANSDATA_M1(pipe), 0);
5906 I915_WRITE(TRANSDATA_N1(pipe), 0);
5907 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5908 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5909 }
79e53945 5910
4b645f14
JB		 5911 if (!intel_crtc->no_pll &&
5912 (!has_edp_encoder ||
5913 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5914 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5915
32f9d658 5916 /* Wait for the clocks to stabilize. */
fae14981 5917 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5918 udelay(150);
5919
8febb297
EA		 5920 /* The pixel multiplier can only be updated once the
5921 * DPLL is enabled and the clocks are stable.
5922 *
5923 * So write it again.
5924 */
fae14981 5925 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5926 }
79e53945 5927
5eddb70b 5928 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5929 if (!intel_crtc->no_pll) {
5930 if (is_lvds && has_reduced_clock && i915_powersave) {
5931 I915_WRITE(PCH_FP1(pipe), fp2);
5932 intel_crtc->lowfreq_avail = true;
5933 if (HAS_PIPE_CXSR(dev)) {
5934 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5935 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5936 }
5937 } else {
5938 I915_WRITE(PCH_FP1(pipe), fp);
5939 if (HAS_PIPE_CXSR(dev)) {
5940 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5941 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5942 }
652c393a
JB		 5943 }
5944 }
5945
734b4157
KH		 5946 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5947 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5948 /* the chip adds 2 halflines automatically */
5949 adjusted_mode->crtc_vdisplay -= 1;
5950 adjusted_mode->crtc_vtotal -= 1;
5951 adjusted_mode->crtc_vblank_start -= 1;
5952 adjusted_mode->crtc_vblank_end -= 1;
5953 adjusted_mode->crtc_vsync_end -= 1;
5954 adjusted_mode->crtc_vsync_start -= 1;
5955 } else
5956 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5957
5eddb70b
CW		 5958 I915_WRITE(HTOTAL(pipe),
5959 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5960 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5961 I915_WRITE(HBLANK(pipe),
5962 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5963 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5964 I915_WRITE(HSYNC(pipe),
5965 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5966 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5967
5968 I915_WRITE(VTOTAL(pipe),
5969 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5970 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5971 I915_WRITE(VBLANK(pipe),
5972 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5973 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5974 I915_WRITE(VSYNC(pipe),
5975 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5976 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5977
8febb297
EA		 5978 /* pipesrc controls the size that is scaled from, which should
5979 * always be the user's requested size.
79e53945 5980 */
5eddb70b
CW		 5981 I915_WRITE(PIPESRC(pipe),
5982 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5983
8febb297
EA		 5984 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5985 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5986 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5987 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5988
8febb297
EA		 5989 if (has_edp_encoder &&
5990 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5991 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5992 }
5993
5eddb70b
CW		 5994 I915_WRITE(PIPECONF(pipe), pipeconf);
5995 POSTING_READ(PIPECONF(pipe));
79e53945 5996
9d0498a2 5997 intel_wait_for_vblank(dev, pipe);
79e53945 5998
f00a3ddf 5999 if (IS_GEN5(dev)) {
553bd149
ZW		 6000 /* enable address swizzle for tiling buffer */
6001 temp = I915_READ(DISP_ARB_CTL);
6002 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6003 }
6004
5eddb70b 6005 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6006 POSTING_READ(DSPCNTR(plane));
79e53945 6007
5c3b82e2 6008 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6009
6010 intel_update_watermarks(dev);
6011
1f803ee5 6012 return ret;
79e53945
JB		 6013}
6014
f564048e
EA		 6015static int intel_crtc_mode_set(struct drm_crtc *crtc,
6016 struct drm_display_mode *mode,
6017 struct drm_display_mode *adjusted_mode,
6018 int x, int y,
6019 struct drm_framebuffer *old_fb)
6020{
6021 struct drm_device *dev = crtc->dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6024 int pipe = intel_crtc->pipe;
f564048e
EA		 6025 int ret;
6026
0b701d27 6027 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6028
f564048e
EA		 6029 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6030 x, y, old_fb);
79e53945 6031 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6032
d8e70a25
JB		 6033 if (ret)
6034 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6035 else
6036 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6037
1f803ee5 6038 return ret;
79e53945
JB		 6039}
6040
3a9627f4
WF		 6041static bool intel_eld_uptodate(struct drm_connector *connector,
6042 int reg_eldv, uint32_t bits_eldv,
6043 int reg_elda, uint32_t bits_elda,
6044 int reg_edid)
6045{
6046 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6047 uint8_t *eld = connector->eld;
6048 uint32_t i;
6049
6050 i = I915_READ(reg_eldv);
6051 i &= bits_eldv;
6052
6053 if (!eld[0])
6054 return !i;
6055
6056 if (!i)
6057 return false;
6058
6059 i = I915_READ(reg_elda);
6060 i &= ~bits_elda;
6061 I915_WRITE(reg_elda, i);
6062
6063 for (i = 0; i < eld[2]; i++)
6064 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6065 return false;
6066
6067 return true;
6068}
6069
e0dac65e
WF		 6070static void g4x_write_eld(struct drm_connector *connector,
6071 struct drm_crtc *crtc)
6072{
6073 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6074 uint8_t *eld = connector->eld;
6075 uint32_t eldv;
6076 uint32_t len;
6077 uint32_t i;
6078
6079 i = I915_READ(G4X_AUD_VID_DID);
6080
6081 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6082 eldv = G4X_ELDV_DEVCL_DEVBLC;
6083 else
6084 eldv = G4X_ELDV_DEVCTG;
6085
3a9627f4
WF		 6086 if (intel_eld_uptodate(connector,
6087 G4X_AUD_CNTL_ST, eldv,
6088 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6089 G4X_HDMIW_HDMIEDID))
6090 return;
6091
e0dac65e
WF		 6092 i = I915_READ(G4X_AUD_CNTL_ST);
6093 i &= ~(eldv | G4X_ELD_ADDR);
6094 len = (i >> 9) & 0x1f; /* ELD buffer size */
6095 I915_WRITE(G4X_AUD_CNTL_ST, i);
6096
6097 if (!eld[0])
6098 return;
6099
6100 len = min_t(uint8_t, eld[2], len);
6101 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6102 for (i = 0; i < len; i++)
6103 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6104
6105 i = I915_READ(G4X_AUD_CNTL_ST);
6106 i |= eldv;
6107 I915_WRITE(G4X_AUD_CNTL_ST, i);
6108}
6109
6110static void ironlake_write_eld(struct drm_connector *connector,
6111 struct drm_crtc *crtc)
6112{
6113 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6114 uint8_t *eld = connector->eld;
6115 uint32_t eldv;
6116 uint32_t i;
6117 int len;
6118 int hdmiw_hdmiedid;
6119 int aud_cntl_st;
6120 int aud_cntrl_st2;
6121
b3f33cbf 6122 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6
WF		 6123 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6124 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6125 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6126 } else {
1202b4c6
WF		 6127 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6128 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6129 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6130 }
6131
6132 i = to_intel_crtc(crtc)->pipe;
6133 hdmiw_hdmiedid += i * 0x100;
6134 aud_cntl_st += i * 0x100;
6135
6136 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6137
6138 i = I915_READ(aud_cntl_st);
6139 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6140 if (!i) {
6141 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6142 /* operate blindly on all ports */
1202b4c6
WF		 6143 eldv = IBX_ELD_VALIDB;
6144 eldv |= IBX_ELD_VALIDB << 4;
6145 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6146 } else {
6147 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6148 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6149 }
6150
3a9627f4
WF		 6151 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6152 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6153 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
e0dac65e
WF		 6154 }
6155
3a9627f4
WF		 6156 if (intel_eld_uptodate(connector,
6157 aud_cntrl_st2, eldv,
6158 aud_cntl_st, IBX_ELD_ADDRESS,
6159 hdmiw_hdmiedid))
6160 return;
6161
e0dac65e
WF		 6162 i = I915_READ(aud_cntrl_st2);
6163 i &= ~eldv;
6164 I915_WRITE(aud_cntrl_st2, i);
6165
6166 if (!eld[0])
6167 return;
6168
e0dac65e 6169 i = I915_READ(aud_cntl_st);
1202b4c6 6170 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6171 I915_WRITE(aud_cntl_st, i);
6172
6173 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6174 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6175 for (i = 0; i < len; i++)
6176 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6177
6178 i = I915_READ(aud_cntrl_st2);
6179 i |= eldv;
6180 I915_WRITE(aud_cntrl_st2, i);
6181}
6182
6183void intel_write_eld(struct drm_encoder *encoder,
6184 struct drm_display_mode *mode)
6185{
6186 struct drm_crtc *crtc = encoder->crtc;
6187 struct drm_connector *connector;
6188 struct drm_device *dev = encoder->dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190
6191 connector = drm_select_eld(encoder, mode);
6192 if (!connector)
6193 return;
6194
6195 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6196 connector->base.id,
6197 drm_get_connector_name(connector),
6198 connector->encoder->base.id,
6199 drm_get_encoder_name(connector->encoder));
6200
6201 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6202
6203 if (dev_priv->display.write_eld)
6204 dev_priv->display.write_eld(connector, crtc);
6205}
6206
79e53945
JB		 6207/** Loads the palette/gamma unit for the CRTC with the prepared values */
6208void intel_crtc_load_lut(struct drm_crtc *crtc)
6209{
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = dev->dev_private;
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6213 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6214 int i;
6215
6216 /* The clocks have to be on to load the palette. */
6217 if (!crtc->enabled)
6218 return;
6219
f2b115e6 6220 /* use legacy palette for Ironlake */
bad720ff 6221 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6222 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6223
79e53945
JB		 6224 for (i = 0; i < 256; i++) {
6225 I915_WRITE(palreg + 4 * i,
6226 (intel_crtc->lut_r[i] << 16) |
6227 (intel_crtc->lut_g[i] << 8) |
6228 intel_crtc->lut_b[i]);
6229 }
6230}
6231
560b85bb
CW		 6232static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6233{
6234 struct drm_device *dev = crtc->dev;
6235 struct drm_i915_private *dev_priv = dev->dev_private;
6236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6237 bool visible = base != 0;
6238 u32 cntl;
6239
6240 if (intel_crtc->cursor_visible == visible)
6241 return;
6242
9db4a9c7 6243 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6244 if (visible) {
6245 /* On these chipsets we can only modify the base whilst
6246 * the cursor is disabled.
6247 */
9db4a9c7 6248 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6249
6250 cntl &= ~(CURSOR_FORMAT_MASK);
6251 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6252 cntl |= CURSOR_ENABLE |
6253 CURSOR_GAMMA_ENABLE |
6254 CURSOR_FORMAT_ARGB;
6255 } else
6256 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6257 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6258
6259 intel_crtc->cursor_visible = visible;
6260}
6261
6262static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6263{
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6267 int pipe = intel_crtc->pipe;
6268 bool visible = base != 0;
6269
6270 if (intel_crtc->cursor_visible != visible) {
548f245b 6271 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6272 if (base) {
6273 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6274 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6275 cntl |= pipe << 28; /* Connect to correct pipe */
6276 } else {
6277 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6278 cntl |= CURSOR_MODE_DISABLE;
6279 }
9db4a9c7 6280 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6281
6282 intel_crtc->cursor_visible = visible;
6283 }
6284 /* and commit changes on next vblank */
9db4a9c7 6285 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6286}
6287
65a21cd6
JB		 6288static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6289{
6290 struct drm_device *dev = crtc->dev;
6291 struct drm_i915_private *dev_priv = dev->dev_private;
6292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6293 int pipe = intel_crtc->pipe;
6294 bool visible = base != 0;
6295
6296 if (intel_crtc->cursor_visible != visible) {
6297 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6298 if (base) {
6299 cntl &= ~CURSOR_MODE;
6300 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6301 } else {
6302 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6303 cntl |= CURSOR_MODE_DISABLE;
6304 }
6305 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6306
6307 intel_crtc->cursor_visible = visible;
6308 }
6309 /* and commit changes on next vblank */
6310 I915_WRITE(CURBASE_IVB(pipe), base);
6311}
6312
cda4b7d3 6313/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6314static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6315 bool on)
cda4b7d3
CW		 6316{
6317 struct drm_device *dev = crtc->dev;
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6320 int pipe = intel_crtc->pipe;
6321 int x = intel_crtc->cursor_x;
6322 int y = intel_crtc->cursor_y;
560b85bb 6323 u32 base, pos;
cda4b7d3
CW		 6324 bool visible;
6325
6326 pos = 0;
6327
6b383a7f 6328 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6329 base = intel_crtc->cursor_addr;
6330 if (x > (int) crtc->fb->width)
6331 base = 0;
6332
6333 if (y > (int) crtc->fb->height)
6334 base = 0;
6335 } else
6336 base = 0;
6337
6338 if (x < 0) {
6339 if (x + intel_crtc->cursor_width < 0)
6340 base = 0;
6341
6342 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6343 x = -x;
6344 }
6345 pos |= x << CURSOR_X_SHIFT;
6346
6347 if (y < 0) {
6348 if (y + intel_crtc->cursor_height < 0)
6349 base = 0;
6350
6351 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6352 y = -y;
6353 }
6354 pos |= y << CURSOR_Y_SHIFT;
6355
6356 visible = base != 0;
560b85bb 6357 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6358 return;
6359
65a21cd6
JB		 6360 if (IS_IVYBRIDGE(dev)) {
6361 I915_WRITE(CURPOS_IVB(pipe), pos);
6362 ivb_update_cursor(crtc, base);
6363 } else {
6364 I915_WRITE(CURPOS(pipe), pos);
6365 if (IS_845G(dev) || IS_I865G(dev))
6366 i845_update_cursor(crtc, base);
6367 else
6368 i9xx_update_cursor(crtc, base);
6369 }
cda4b7d3
CW		 6370
6371 if (visible)
6372 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6373}
6374
79e53945 6375static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6376 struct drm_file *file,
79e53945
JB		 6377 uint32_t handle,
6378 uint32_t width, uint32_t height)
6379{
6380 struct drm_device *dev = crtc->dev;
6381 struct drm_i915_private *dev_priv = dev->dev_private;
6382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6383 struct drm_i915_gem_object *obj;
cda4b7d3 6384 uint32_t addr;
3f8bc370 6385 int ret;
79e53945 6386
28c97730 6387 DRM_DEBUG_KMS("\n");
79e53945
JB		 6388
6389 /* if we want to turn off the cursor ignore width and height */
6390 if (!handle) {
28c97730 6391 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6392 addr = 0;
05394f39 6393 obj = NULL;
5004417d 6394 mutex_lock(&dev->struct_mutex);
3f8bc370 6395 goto finish;
79e53945
JB		 6396 }
6397
6398 /* Currently we only support 64x64 cursors */
6399 if (width != 64 || height != 64) {
6400 DRM_ERROR("we currently only support 64x64 cursors\n");
6401 return -EINVAL;
6402 }
6403
05394f39 6404 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6405 if (&obj->base == NULL)
79e53945
JB		 6406 return -ENOENT;
6407
05394f39 6408 if (obj->base.size < width * height * 4) {
79e53945 6409 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6410 ret = -ENOMEM;
6411 goto fail;
79e53945
JB		 6412 }
6413
71acb5eb 6414 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6415 mutex_lock(&dev->struct_mutex);
b295d1b6 6416 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6417 if (obj->tiling_mode) {
6418 DRM_ERROR("cursor cannot be tiled\n");
6419 ret = -EINVAL;
6420 goto fail_locked;
6421 }
6422
2da3b9b9 6423 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6424 if (ret) {
6425 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6426 goto fail_locked;
e7b526bb
CW		 6427 }
6428
d9e86c0e
CW		 6429 ret = i915_gem_object_put_fence(obj);
6430 if (ret) {
2da3b9b9 6431 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6432 goto fail_unpin;
6433 }
6434
05394f39 6435 addr = obj->gtt_offset;
71acb5eb 6436 } else {
6eeefaf3 6437 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6438 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6439 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6440 align);
71acb5eb
DA		 6441 if (ret) {
6442 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6443 goto fail_locked;
71acb5eb 6444 }
05394f39 6445 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6446 }
6447
a6c45cf0 6448 if (IS_GEN2(dev))
14b60391
JB		 6449 I915_WRITE(CURSIZE, (height << 12) | width);
6450
3f8bc370 6451 finish:
3f8bc370 6452 if (intel_crtc->cursor_bo) {
b295d1b6 6453 if (dev_priv->info->cursor_needs_physical) {
05394f39 6454 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6455 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6456 } else
6457 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6458 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6459 }
80824003 6460
7f9872e0 6461 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6462
6463 intel_crtc->cursor_addr = addr;
05394f39 6464 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6465 intel_crtc->cursor_width = width;
6466 intel_crtc->cursor_height = height;
6467
6b383a7f 6468 intel_crtc_update_cursor(crtc, true);
3f8bc370 6469
79e53945 6470 return 0;
e7b526bb 6471fail_unpin:
05394f39 6472 i915_gem_object_unpin(obj);
7f9872e0 6473fail_locked:
34b8686e 6474 mutex_unlock(&dev->struct_mutex);
bc9025bd 6475fail:
05394f39 6476 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6477 return ret;
79e53945
JB		 6478}
6479
6480static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6481{
79e53945 6482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6483
cda4b7d3
CW		 6484 intel_crtc->cursor_x = x;
6485 intel_crtc->cursor_y = y;
652c393a 6486
6b383a7f 6487 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6488
6489 return 0;
6490}
6491
6492/** Sets the color ramps on behalf of RandR */
6493void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6494 u16 blue, int regno)
6495{
6496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6497
6498 intel_crtc->lut_r[regno] = red >> 8;
6499 intel_crtc->lut_g[regno] = green >> 8;
6500 intel_crtc->lut_b[regno] = blue >> 8;
6501}
6502
b8c00ac5
DA		 6503void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6504 u16 *blue, int regno)
6505{
6506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6507
6508 *red = intel_crtc->lut_r[regno] << 8;
6509 *green = intel_crtc->lut_g[regno] << 8;
6510 *blue = intel_crtc->lut_b[regno] << 8;
6511}
6512
79e53945 6513static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6514 u16 *blue, uint32_t start, uint32_t size)
79e53945 6515{
7203425a 6516 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6518
7203425a 6519 for (i = start; i < end; i++) {
79e53945
JB		 6520 intel_crtc->lut_r[i] = red[i] >> 8;
6521 intel_crtc->lut_g[i] = green[i] >> 8;
6522 intel_crtc->lut_b[i] = blue[i] >> 8;
6523 }
6524
6525 intel_crtc_load_lut(crtc);
6526}
6527
6528/**
6529 * Get a pipe with a simple mode set on it for doing load-based monitor
6530 * detection.
6531 *
6532 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6533 * its requirements. The pipe will be connected to no other encoders.
79e53945 6534 *
c751ce4f 6535 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6536 * configured for it. In the future, it could choose to temporarily disable
6537 * some outputs to free up a pipe for its use.
6538 *
6539 * \return crtc, or NULL if no pipes are available.
6540 */
6541
6542/* VESA 640x480x72Hz mode to set on the pipe */
6543static struct drm_display_mode load_detect_mode = {
6544 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6545 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6546};
6547
d2dff872
CW		 6548static struct drm_framebuffer *
6549intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6550 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6551 struct drm_i915_gem_object *obj)
6552{
6553 struct intel_framebuffer *intel_fb;
6554 int ret;
6555
6556 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6557 if (!intel_fb) {
6558 drm_gem_object_unreference_unlocked(&obj->base);
6559 return ERR_PTR(-ENOMEM);
6560 }
6561
6562 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6563 if (ret) {
6564 drm_gem_object_unreference_unlocked(&obj->base);
6565 kfree(intel_fb);
6566 return ERR_PTR(ret);
6567 }
6568
6569 return &intel_fb->base;
6570}
6571
6572static u32
6573intel_framebuffer_pitch_for_width(int width, int bpp)
6574{
6575 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6576 return ALIGN(pitch, 64);
6577}
6578
6579static u32
6580intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6581{
6582 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6583 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6584}
6585
6586static struct drm_framebuffer *
6587intel_framebuffer_create_for_mode(struct drm_device *dev,
6588 struct drm_display_mode *mode,
6589 int depth, int bpp)
6590{
6591 struct drm_i915_gem_object *obj;
308e5bcb 6592 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6593
6594 obj = i915_gem_alloc_object(dev,
6595 intel_framebuffer_size_for_mode(mode, bpp));
6596 if (obj == NULL)
6597 return ERR_PTR(-ENOMEM);
6598
6599 mode_cmd.width = mode->hdisplay;
6600 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6601 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6602 bpp);
6603 mode_cmd.pixel_format = 0;
d2dff872
CW		 6604
6605 return intel_framebuffer_create(dev, &mode_cmd, obj);
6606}
6607
6608static struct drm_framebuffer *
6609mode_fits_in_fbdev(struct drm_device *dev,
6610 struct drm_display_mode *mode)
6611{
6612 struct drm_i915_private *dev_priv = dev->dev_private;
6613 struct drm_i915_gem_object *obj;
6614 struct drm_framebuffer *fb;
6615
6616 if (dev_priv->fbdev == NULL)
6617 return NULL;
6618
6619 obj = dev_priv->fbdev->ifb.obj;
6620 if (obj == NULL)
6621 return NULL;
6622
6623 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6624 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6625 fb->bits_per_pixel))
d2dff872
CW		 6626 return NULL;
6627
01f2c773 6628 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6629 return NULL;
6630
6631 return fb;
6632}
6633
7173188d
CW		 6634bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6635 struct drm_connector *connector,
6636 struct drm_display_mode *mode,
8261b191 6637 struct intel_load_detect_pipe *old)
79e53945
JB		 6638{
6639 struct intel_crtc *intel_crtc;
6640 struct drm_crtc *possible_crtc;
4ef69c7a 6641 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6642 struct drm_crtc *crtc = NULL;
6643 struct drm_device *dev = encoder->dev;
d2dff872 6644 struct drm_framebuffer *old_fb;
79e53945
JB		 6645 int i = -1;
6646
d2dff872
CW		 6647 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6648 connector->base.id, drm_get_connector_name(connector),
6649 encoder->base.id, drm_get_encoder_name(encoder));
6650
79e53945
JB		 6651 /*
6652 * Algorithm gets a little messy:
7a5e4805 6653 *
79e53945
JB		 6654 * - if the connector already has an assigned crtc, use it (but make
6655 * sure it's on first)
7a5e4805 6656 *
79e53945
JB		 6657 * - try to find the first unused crtc that can drive this connector,
6658 * and use that if we find one
79e53945
JB		 6659 */
6660
6661 /* See if we already have a CRTC for this connector */
6662 if (encoder->crtc) {
6663 crtc = encoder->crtc;
8261b191 6664
79e53945 6665 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6666 old->dpms_mode = intel_crtc->dpms_mode;
6667 old->load_detect_temp = false;
6668
6669 /* Make sure the crtc and connector are running */
79e53945 6670 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6671 struct drm_encoder_helper_funcs *encoder_funcs;
6672 struct drm_crtc_helper_funcs *crtc_funcs;
6673
79e53945
JB		 6674 crtc_funcs = crtc->helper_private;
6675 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6676
6677 encoder_funcs = encoder->helper_private;
79e53945
JB		 6678 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6679 }
8261b191 6680
7173188d 6681 return true;
79e53945
JB		 6682 }
6683
6684 /* Find an unused one (if possible) */
6685 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6686 i++;
6687 if (!(encoder->possible_crtcs & (1 << i)))
6688 continue;
6689 if (!possible_crtc->enabled) {
6690 crtc = possible_crtc;
6691 break;
6692 }
79e53945
JB		 6693 }
6694
6695 /*
6696 * If we didn't find an unused CRTC, don't use any.
6697 */
6698 if (!crtc) {
7173188d
CW		 6699 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6700 return false;
79e53945
JB		 6701 }
6702
6703 encoder->crtc = crtc;
c1c43977 6704 connector->encoder = encoder;
79e53945
JB		 6705
6706 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6707 old->dpms_mode = intel_crtc->dpms_mode;
6708 old->load_detect_temp = true;
d2dff872 6709 old->release_fb = NULL;
79e53945 6710
6492711d
CW		 6711 if (!mode)
6712 mode = &load_detect_mode;
79e53945 6713
d2dff872
CW		 6714 old_fb = crtc->fb;
6715
6716 /* We need a framebuffer large enough to accommodate all accesses
6717 * that the plane may generate whilst we perform load detection.
6718 * We can not rely on the fbcon either being present (we get called
6719 * during its initialisation to detect all boot displays, or it may
6720 * not even exist) or that it is large enough to satisfy the
6721 * requested mode.
6722 */
6723 crtc->fb = mode_fits_in_fbdev(dev, mode);
6724 if (crtc->fb == NULL) {
6725 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6726 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6727 old->release_fb = crtc->fb;
6728 } else
6729 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6730 if (IS_ERR(crtc->fb)) {
6731 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6732 crtc->fb = old_fb;
6733 return false;
79e53945 6734 }
79e53945 6735
d2dff872 6736 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6737 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6738 if (old->release_fb)
6739 old->release_fb->funcs->destroy(old->release_fb);
6740 crtc->fb = old_fb;
6492711d 6741 return false;
79e53945 6742 }
7173188d 6743
79e53945 6744 /* let the connector get through one full cycle before testing */
9d0498a2 6745 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6746
7173188d 6747 return true;
79e53945
JB		 6748}
6749
c1c43977 6750void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6751 struct drm_connector *connector,
6752 struct intel_load_detect_pipe *old)
79e53945 6753{
4ef69c7a 6754 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6755 struct drm_device *dev = encoder->dev;
6756 struct drm_crtc *crtc = encoder->crtc;
6757 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6758 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6759
d2dff872
CW		 6760 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6761 connector->base.id, drm_get_connector_name(connector),
6762 encoder->base.id, drm_get_encoder_name(encoder));
6763
8261b191 6764 if (old->load_detect_temp) {
c1c43977 6765 connector->encoder = NULL;
79e53945 6766 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6767
6768 if (old->release_fb)
6769 old->release_fb->funcs->destroy(old->release_fb);
6770
0622a53c 6771 return;
79e53945
JB		 6772 }
6773
c751ce4f 6774 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6775 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6776 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6777 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6778 }
6779}
6780
6781/* Returns the clock of the currently programmed mode of the given pipe. */
6782static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6783{
6784 struct drm_i915_private *dev_priv = dev->dev_private;
6785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6786 int pipe = intel_crtc->pipe;
548f245b 6787 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6788 u32 fp;
6789 intel_clock_t clock;
6790
6791 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6792 fp = I915_READ(FP0(pipe));
79e53945 6793 else
39adb7a5 6794 fp = I915_READ(FP1(pipe));
79e53945
JB		 6795
6796 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6797 if (IS_PINEVIEW(dev)) {
6798 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6799 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6800 } else {
6801 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6802 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6803 }
6804
a6c45cf0 6805 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6806 if (IS_PINEVIEW(dev))
6807 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6808 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6809 else
6810 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6811 DPLL_FPA01_P1_POST_DIV_SHIFT);
6812
6813 switch (dpll & DPLL_MODE_MASK) {
6814 case DPLLB_MODE_DAC_SERIAL:
6815 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6816 5 : 10;
6817 break;
6818 case DPLLB_MODE_LVDS:
6819 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6820 7 : 14;
6821 break;
6822 default:
28c97730 6823 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6824 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6825 return 0;
6826 }
6827
6828 /* XXX: Handle the 100Mhz refclk */
2177832f 6829 intel_clock(dev, 96000, &clock);
79e53945
JB		 6830 } else {
6831 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6832
6833 if (is_lvds) {
6834 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6835 DPLL_FPA01_P1_POST_DIV_SHIFT);
6836 clock.p2 = 14;
6837
6838 if ((dpll & PLL_REF_INPUT_MASK) ==
6839 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6840 /* XXX: might not be 66MHz */
2177832f 6841 intel_clock(dev, 66000, &clock);
79e53945 6842 } else
2177832f 6843 intel_clock(dev, 48000, &clock);
79e53945
JB		 6844 } else {
6845 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6846 clock.p1 = 2;
6847 else {
6848 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6849 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6850 }
6851 if (dpll & PLL_P2_DIVIDE_BY_4)
6852 clock.p2 = 4;
6853 else
6854 clock.p2 = 2;
6855
2177832f 6856 intel_clock(dev, 48000, &clock);
79e53945
JB		 6857 }
6858 }
6859
6860 /* XXX: It would be nice to validate the clocks, but we can't reuse
6861 * i830PllIsValid() because it relies on the xf86_config connector
6862 * configuration being accurate, which it isn't necessarily.
6863 */
6864
6865 return clock.dot;
6866}
6867
6868/** Returns the currently programmed mode of the given pipe. */
6869struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6870 struct drm_crtc *crtc)
6871{
548f245b 6872 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6874 int pipe = intel_crtc->pipe;
6875 struct drm_display_mode *mode;
548f245b
JB		 6876 int htot = I915_READ(HTOTAL(pipe));
6877 int hsync = I915_READ(HSYNC(pipe));
6878 int vtot = I915_READ(VTOTAL(pipe));
6879 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6880
6881 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6882 if (!mode)
6883 return NULL;
6884
6885 mode->clock = intel_crtc_clock_get(dev, crtc);
6886 mode->hdisplay = (htot & 0xffff) + 1;
6887 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6888 mode->hsync_start = (hsync & 0xffff) + 1;
6889 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6890 mode->vdisplay = (vtot & 0xffff) + 1;
6891 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6892 mode->vsync_start = (vsync & 0xffff) + 1;
6893 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6894
6895 drm_mode_set_name(mode);
6896 drm_mode_set_crtcinfo(mode, 0);
6897
6898 return mode;
6899}
6900
652c393a
JB		 6901#define GPU_IDLE_TIMEOUT 500 /* ms */
6902
6903/* When this timer fires, we've been idle for awhile */
6904static void intel_gpu_idle_timer(unsigned long arg)
6905{
6906 struct drm_device *dev = (struct drm_device *)arg;
6907 drm_i915_private_t *dev_priv = dev->dev_private;
6908
ff7ea4c0
CW		 6909 if (!list_empty(&dev_priv->mm.active_list)) {
6910 /* Still processing requests, so just re-arm the timer. */
6911 mod_timer(&dev_priv->idle_timer, jiffies +
6912 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6913 return;
6914 }
652c393a 6915
ff7ea4c0 6916 dev_priv->busy = false;
01dfba93 6917 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6918}
6919
652c393a
JB		 6920#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6921
6922static void intel_crtc_idle_timer(unsigned long arg)
6923{
6924 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6925 struct drm_crtc *crtc = &intel_crtc->base;
6926 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6927 struct intel_framebuffer *intel_fb;
652c393a 6928
ff7ea4c0
CW		 6929 intel_fb = to_intel_framebuffer(crtc->fb);
6930 if (intel_fb && intel_fb->obj->active) {
6931 /* The framebuffer is still being accessed by the GPU. */
6932 mod_timer(&intel_crtc->idle_timer, jiffies +
6933 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6934 return;
6935 }
652c393a 6936
ff7ea4c0 6937 intel_crtc->busy = false;
01dfba93 6938 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6939}
6940
3dec0095 6941static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6942{
6943 struct drm_device *dev = crtc->dev;
6944 drm_i915_private_t *dev_priv = dev->dev_private;
6945 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6946 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6947 int dpll_reg = DPLL(pipe);
6948 int dpll;
652c393a 6949
bad720ff 6950 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6951 return;
6952
6953 if (!dev_priv->lvds_downclock_avail)
6954 return;
6955
dbdc6479 6956 dpll = I915_READ(dpll_reg);
652c393a 6957 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6958 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6959
6960 /* Unlock panel regs */
dbdc6479
JB		 6961 I915_WRITE(PP_CONTROL,
6962 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6963
6964 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6965 I915_WRITE(dpll_reg, dpll);
9d0498a2 6966 intel_wait_for_vblank(dev, pipe);
dbdc6479 6967
652c393a
JB		 6968 dpll = I915_READ(dpll_reg);
6969 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6970 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6971
6972 /* ...and lock them again */
6973 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6974 }
6975
6976 /* Schedule downclock */
3dec0095
DV		 6977 mod_timer(&intel_crtc->idle_timer, jiffies +
6978 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6979}
6980
6981static void intel_decrease_pllclock(struct drm_crtc *crtc)
6982{
6983 struct drm_device *dev = crtc->dev;
6984 drm_i915_private_t *dev_priv = dev->dev_private;
6985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6986 int pipe = intel_crtc->pipe;
9db4a9c7 6987 int dpll_reg = DPLL(pipe);
652c393a
JB		 6988 int dpll = I915_READ(dpll_reg);
6989
bad720ff 6990 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6991 return;
6992
6993 if (!dev_priv->lvds_downclock_avail)
6994 return;
6995
6996 /*
6997 * Since this is called by a timer, we should never get here in
6998 * the manual case.
6999 */
7000 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7001 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 7002
7003 /* Unlock panel regs */
4a655f04
JB		 7004 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7005 PANEL_UNLOCK_REGS);
652c393a
JB		 7006
7007 dpll |= DISPLAY_RATE_SELECT_FPA1;
7008 I915_WRITE(dpll_reg, dpll);
9d0498a2 7009 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7010 dpll = I915_READ(dpll_reg);
7011 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7012 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7013
7014 /* ...and lock them again */
7015 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7016 }
7017
7018}
7019
7020/**
7021 * intel_idle_update - adjust clocks for idleness
7022 * @work: work struct
7023 *
7024 * Either the GPU or display (or both) went idle. Check the busy status
7025 * here and adjust the CRTC and GPU clocks as necessary.
7026 */
7027static void intel_idle_update(struct work_struct *work)
7028{
7029 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7030 idle_work);
7031 struct drm_device *dev = dev_priv->dev;
7032 struct drm_crtc *crtc;
7033 struct intel_crtc *intel_crtc;
7034
7035 if (!i915_powersave)
7036 return;
7037
7038 mutex_lock(&dev->struct_mutex);
7039
7648fa99
JB		 7040 i915_update_gfx_val(dev_priv);
7041
652c393a
JB		 7042 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7043 /* Skip inactive CRTCs */
7044 if (!crtc->fb)
7045 continue;
7046
7047 intel_crtc = to_intel_crtc(crtc);
7048 if (!intel_crtc->busy)
7049 intel_decrease_pllclock(crtc);
7050 }
7051
45ac22c8 7052
652c393a
JB		 7053 mutex_unlock(&dev->struct_mutex);
7054}
7055
7056/**
7057 * intel_mark_busy - mark the GPU and possibly the display busy
7058 * @dev: drm device
7059 * @obj: object we're operating on
7060 *
7061 * Callers can use this function to indicate that the GPU is busy processing
7062 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7063 * buffer), we'll also mark the display as busy, so we know to increase its
7064 * clock frequency.
7065 */
05394f39 7066void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7067{
7068 drm_i915_private_t *dev_priv = dev->dev_private;
7069 struct drm_crtc *crtc = NULL;
7070 struct intel_framebuffer *intel_fb;
7071 struct intel_crtc *intel_crtc;
7072
5e17ee74
ZW		 7073 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7074 return;
7075
18b2190c 7076 if (!dev_priv->busy)
28cf798f 7077 dev_priv->busy = true;
18b2190c 7078 else
28cf798f
CW		 7079 mod_timer(&dev_priv->idle_timer, jiffies +
7080 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7081
7082 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7083 if (!crtc->fb)
7084 continue;
7085
7086 intel_crtc = to_intel_crtc(crtc);
7087 intel_fb = to_intel_framebuffer(crtc->fb);
7088 if (intel_fb->obj == obj) {
7089 if (!intel_crtc->busy) {
7090 /* Non-busy -> busy, upclock */
3dec0095 7091 intel_increase_pllclock(crtc);
652c393a
JB		 7092 intel_crtc->busy = true;
7093 } else {
7094 /* Busy -> busy, put off timer */
7095 mod_timer(&intel_crtc->idle_timer, jiffies +
7096 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7097 }
7098 }
7099 }
7100}
7101
79e53945
JB		 7102static void intel_crtc_destroy(struct drm_crtc *crtc)
7103{
7104 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7105 struct drm_device *dev = crtc->dev;
7106 struct intel_unpin_work *work;
7107 unsigned long flags;
7108
7109 spin_lock_irqsave(&dev->event_lock, flags);
7110 work = intel_crtc->unpin_work;
7111 intel_crtc->unpin_work = NULL;
7112 spin_unlock_irqrestore(&dev->event_lock, flags);
7113
7114 if (work) {
7115 cancel_work_sync(&work->work);
7116 kfree(work);
7117 }
79e53945
JB		 7118
7119 drm_crtc_cleanup(crtc);
67e77c5a 7120
79e53945
JB		 7121 kfree(intel_crtc);
7122}
7123
6b95a207
KH		 7124static void intel_unpin_work_fn(struct work_struct *__work)
7125{
7126 struct intel_unpin_work *work =
7127 container_of(__work, struct intel_unpin_work, work);
7128
7129 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 7130 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 7131 drm_gem_object_unreference(&work->pending_flip_obj->base);
7132 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7133
7782de3b 7134 intel_update_fbc(work->dev);
6b95a207
KH		 7135 mutex_unlock(&work->dev->struct_mutex);
7136 kfree(work);
7137}
7138
1afe3e9d 7139static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7140 struct drm_crtc *crtc)
6b95a207
KH		 7141{
7142 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7144 struct intel_unpin_work *work;
05394f39 7145 struct drm_i915_gem_object *obj;
6b95a207 7146 struct drm_pending_vblank_event *e;
49b14a5c 7147 struct timeval tnow, tvbl;
6b95a207
KH		 7148 unsigned long flags;
7149
7150 /* Ignore early vblank irqs */
7151 if (intel_crtc == NULL)
7152 return;
7153
49b14a5c
MK		 7154 do_gettimeofday(&tnow);
7155
6b95a207
KH		 7156 spin_lock_irqsave(&dev->event_lock, flags);
7157 work = intel_crtc->unpin_work;
7158 if (work == NULL || !work->pending) {
7159 spin_unlock_irqrestore(&dev->event_lock, flags);
7160 return;
7161 }
7162
7163 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7164
7165 if (work->event) {
7166 e = work->event;
49b14a5c 7167 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7168
7169 /* Called before vblank count and timestamps have
7170 * been updated for the vblank interval of flip
7171 * completion? Need to increment vblank count and
7172 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7173 * to account for this. We assume this happened if we
7174 * get called over 0.9 frame durations after the last
7175 * timestamped vblank.
7176 *
7177 * This calculation can not be used with vrefresh rates
7178 * below 5Hz (10Hz to be on the safe side) without
7179 * promoting to 64 integers.
0af7e4df 7180 */
49b14a5c
MK		 7181 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7182 9 * crtc->framedur_ns) {
0af7e4df 7183 e->event.sequence++;
49b14a5c
MK		 7184 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7185 crtc->framedur_ns);
0af7e4df
MK		 7186 }
7187
49b14a5c
MK		 7188 e->event.tv_sec = tvbl.tv_sec;
7189 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7190
6b95a207
KH		 7191 list_add_tail(&e->base.link,
7192 &e->base.file_priv->event_list);
7193 wake_up_interruptible(&e->base.file_priv->event_wait);
7194 }
7195
0af7e4df
MK		 7196 drm_vblank_put(dev, intel_crtc->pipe);
7197
6b95a207
KH		 7198 spin_unlock_irqrestore(&dev->event_lock, flags);
7199
05394f39 7200 obj = work->old_fb_obj;
d9e86c0e 7201
e59f2bac 7202 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7203 &obj->pending_flip.counter);
7204 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7205 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7206
6b95a207 7207 schedule_work(&work->work);
e5510fac
JB		 7208
7209 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7210}
7211
1afe3e9d
JB		 7212void intel_finish_page_flip(struct drm_device *dev, int pipe)
7213{
7214 drm_i915_private_t *dev_priv = dev->dev_private;
7215 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7216
49b14a5c 7217 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7218}
7219
7220void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7221{
7222 drm_i915_private_t *dev_priv = dev->dev_private;
7223 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7224
49b14a5c 7225 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7226}
7227
6b95a207
KH		 7228void intel_prepare_page_flip(struct drm_device *dev, int plane)
7229{
7230 drm_i915_private_t *dev_priv = dev->dev_private;
7231 struct intel_crtc *intel_crtc =
7232 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7233 unsigned long flags;
7234
7235 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7236 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7237 if ((++intel_crtc->unpin_work->pending) > 1)
7238 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7239 } else {
7240 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7241 }
6b95a207
KH		 7242 spin_unlock_irqrestore(&dev->event_lock, flags);
7243}
7244
8c9f3aaf
JB		 7245static int intel_gen2_queue_flip(struct drm_device *dev,
7246 struct drm_crtc *crtc,
7247 struct drm_framebuffer *fb,
7248 struct drm_i915_gem_object *obj)
7249{
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7252 unsigned long offset;
7253 u32 flip_mask;
7254 int ret;
7255
7256 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7257 if (ret)
7258 goto out;
7259
7260 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7261 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7262
7263 ret = BEGIN_LP_RING(6);
7264 if (ret)
7265 goto out;
7266
7267 /* Can't queue multiple flips, so wait for the previous
7268 * one to finish before executing the next.
7269 */
7270 if (intel_crtc->plane)
7271 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7272 else
7273 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7274 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7275 OUT_RING(MI_NOOP);
7276 OUT_RING(MI_DISPLAY_FLIP |
7277 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7278 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7279 OUT_RING(obj->gtt_offset + offset);
7280 OUT_RING(MI_NOOP);
7281 ADVANCE_LP_RING();
7282out:
7283 return ret;
7284}
7285
7286static int intel_gen3_queue_flip(struct drm_device *dev,
7287 struct drm_crtc *crtc,
7288 struct drm_framebuffer *fb,
7289 struct drm_i915_gem_object *obj)
7290{
7291 struct drm_i915_private *dev_priv = dev->dev_private;
7292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7293 unsigned long offset;
7294 u32 flip_mask;
7295 int ret;
7296
7297 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7298 if (ret)
7299 goto out;
7300
7301 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7302 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7303
7304 ret = BEGIN_LP_RING(6);
7305 if (ret)
7306 goto out;
7307
7308 if (intel_crtc->plane)
7309 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7310 else
7311 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7312 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7313 OUT_RING(MI_NOOP);
7314 OUT_RING(MI_DISPLAY_FLIP_I915 |
7315 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7316 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7317 OUT_RING(obj->gtt_offset + offset);
7318 OUT_RING(MI_NOOP);
7319
7320 ADVANCE_LP_RING();
7321out:
7322 return ret;
7323}
7324
7325static int intel_gen4_queue_flip(struct drm_device *dev,
7326 struct drm_crtc *crtc,
7327 struct drm_framebuffer *fb,
7328 struct drm_i915_gem_object *obj)
7329{
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7332 uint32_t pf, pipesrc;
7333 int ret;
7334
7335 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7336 if (ret)
7337 goto out;
7338
7339 ret = BEGIN_LP_RING(4);
7340 if (ret)
7341 goto out;
7342
7343 /* i965+ uses the linear or tiled offsets from the
7344 * Display Registers (which do not change across a page-flip)
7345 * so we need only reprogram the base address.
7346 */
7347 OUT_RING(MI_DISPLAY_FLIP |
7348 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7349 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7350 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7351
7352 /* XXX Enabling the panel-fitter across page-flip is so far
7353 * untested on non-native modes, so ignore it for now.
7354 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7355 */
7356 pf = 0;
7357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7358 OUT_RING(pf | pipesrc);
7359 ADVANCE_LP_RING();
7360out:
7361 return ret;
7362}
7363
7364static int intel_gen6_queue_flip(struct drm_device *dev,
7365 struct drm_crtc *crtc,
7366 struct drm_framebuffer *fb,
7367 struct drm_i915_gem_object *obj)
7368{
7369 struct drm_i915_private *dev_priv = dev->dev_private;
7370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7371 uint32_t pf, pipesrc;
7372 int ret;
7373
7374 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7375 if (ret)
7376 goto out;
7377
7378 ret = BEGIN_LP_RING(4);
7379 if (ret)
7380 goto out;
7381
7382 OUT_RING(MI_DISPLAY_FLIP |
7383 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7384 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7385 OUT_RING(obj->gtt_offset);
7386
7387 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7388 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7389 OUT_RING(pf | pipesrc);
7390 ADVANCE_LP_RING();
7391out:
7392 return ret;
7393}
7394
7c9017e5
JB		 7395/*
7396 * On gen7 we currently use the blit ring because (in early silicon at least)
7397 * the render ring doesn't give us interrpts for page flip completion, which
7398 * means clients will hang after the first flip is queued. Fortunately the
7399 * blit ring generates interrupts properly, so use it instead.
7400 */
7401static int intel_gen7_queue_flip(struct drm_device *dev,
7402 struct drm_crtc *crtc,
7403 struct drm_framebuffer *fb,
7404 struct drm_i915_gem_object *obj)
7405{
7406 struct drm_i915_private *dev_priv = dev->dev_private;
7407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7408 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7409 int ret;
7410
7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7412 if (ret)
7413 goto out;
7414
7415 ret = intel_ring_begin(ring, 4);
7416 if (ret)
7417 goto out;
7418
7419 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7420 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7421 intel_ring_emit(ring, (obj->gtt_offset));
7422 intel_ring_emit(ring, (MI_NOOP));
7423 intel_ring_advance(ring);
7424out:
7425 return ret;
7426}
7427
8c9f3aaf
JB		 7428static int intel_default_queue_flip(struct drm_device *dev,
7429 struct drm_crtc *crtc,
7430 struct drm_framebuffer *fb,
7431 struct drm_i915_gem_object *obj)
7432{
7433 return -ENODEV;
7434}
7435
6b95a207
KH		 7436static int intel_crtc_page_flip(struct drm_crtc *crtc,
7437 struct drm_framebuffer *fb,
7438 struct drm_pending_vblank_event *event)
7439{
7440 struct drm_device *dev = crtc->dev;
7441 struct drm_i915_private *dev_priv = dev->dev_private;
7442 struct intel_framebuffer *intel_fb;
05394f39 7443 struct drm_i915_gem_object *obj;
6b95a207
KH		 7444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7445 struct intel_unpin_work *work;
8c9f3aaf 7446 unsigned long flags;
52e68630 7447 int ret;
6b95a207
KH		 7448
7449 work = kzalloc(sizeof *work, GFP_KERNEL);
7450 if (work == NULL)
7451 return -ENOMEM;
7452
6b95a207
KH		 7453 work->event = event;
7454 work->dev = crtc->dev;
7455 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7456 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7457 INIT_WORK(&work->work, intel_unpin_work_fn);
7458
7317c75e
JB		 7459 ret = drm_vblank_get(dev, intel_crtc->pipe);
7460 if (ret)
7461 goto free_work;
7462
6b95a207
KH		 7463 /* We borrow the event spin lock for protecting unpin_work */
7464 spin_lock_irqsave(&dev->event_lock, flags);
7465 if (intel_crtc->unpin_work) {
7466 spin_unlock_irqrestore(&dev->event_lock, flags);
7467 kfree(work);
7317c75e 7468 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7469
7470 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7471 return -EBUSY;
7472 }
7473 intel_crtc->unpin_work = work;
7474 spin_unlock_irqrestore(&dev->event_lock, flags);
7475
7476 intel_fb = to_intel_framebuffer(fb);
7477 obj = intel_fb->obj;
7478
468f0b44 7479 mutex_lock(&dev->struct_mutex);
6b95a207 7480
75dfca80 7481 /* Reference the objects for the scheduled work. */
05394f39
CW		 7482 drm_gem_object_reference(&work->old_fb_obj->base);
7483 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7484
7485 crtc->fb = fb;
96b099fd 7486
e1f99ce6 7487 work->pending_flip_obj = obj;
e1f99ce6 7488
4e5359cd
SF		 7489 work->enable_stall_check = true;
7490
e1f99ce6
CW		 7491 /* Block clients from rendering to the new back buffer until
7492 * the flip occurs and the object is no longer visible.
7493 */
05394f39 7494 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7495
8c9f3aaf
JB		 7496 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7497 if (ret)
7498 goto cleanup_pending;
6b95a207 7499
7782de3b 7500 intel_disable_fbc(dev);
6b95a207
KH		 7501 mutex_unlock(&dev->struct_mutex);
7502
e5510fac
JB		 7503 trace_i915_flip_request(intel_crtc->plane, obj);
7504
6b95a207 7505 return 0;
96b099fd 7506
8c9f3aaf
JB		 7507cleanup_pending:
7508 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7509 drm_gem_object_unreference(&work->old_fb_obj->base);
7510 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7511 mutex_unlock(&dev->struct_mutex);
7512
7513 spin_lock_irqsave(&dev->event_lock, flags);
7514 intel_crtc->unpin_work = NULL;
7515 spin_unlock_irqrestore(&dev->event_lock, flags);
7516
7317c75e
JB		 7517 drm_vblank_put(dev, intel_crtc->pipe);
7518free_work:
96b099fd
CW		 7519 kfree(work);
7520
7521 return ret;
6b95a207
KH		 7522}
7523
47f1c6c9
CW		 7524static void intel_sanitize_modesetting(struct drm_device *dev,
7525 int pipe, int plane)
7526{
7527 struct drm_i915_private *dev_priv = dev->dev_private;
7528 u32 reg, val;
7529
7530 if (HAS_PCH_SPLIT(dev))
7531 return;
7532
7533 /* Who knows what state these registers were left in by the BIOS or
7534 * grub?
7535 *
7536 * If we leave the registers in a conflicting state (e.g. with the
7537 * display plane reading from the other pipe than the one we intend
7538 * to use) then when we attempt to teardown the active mode, we will
7539 * not disable the pipes and planes in the correct order -- leaving
7540 * a plane reading from a disabled pipe and possibly leading to
7541 * undefined behaviour.
7542 */
7543
7544 reg = DSPCNTR(plane);
7545 val = I915_READ(reg);
7546
7547 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7548 return;
7549 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7550 return;
7551
7552 /* This display plane is active and attached to the other CPU pipe. */
7553 pipe = !pipe;
7554
7555 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7556 intel_disable_plane(dev_priv, plane, pipe);
7557 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7558}
79e53945 7559
f6e5b160
CW		 7560static void intel_crtc_reset(struct drm_crtc *crtc)
7561{
7562 struct drm_device *dev = crtc->dev;
7563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7564
7565 /* Reset flags back to the 'unknown' status so that they
7566 * will be correctly set on the initial modeset.
7567 */
7568 intel_crtc->dpms_mode = -1;
7569
7570 /* We need to fix up any BIOS configuration that conflicts with
7571 * our expectations.
7572 */
7573 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7574}
7575
7576static struct drm_crtc_helper_funcs intel_helper_funcs = {
7577 .dpms = intel_crtc_dpms,
7578 .mode_fixup = intel_crtc_mode_fixup,
7579 .mode_set = intel_crtc_mode_set,
7580 .mode_set_base = intel_pipe_set_base,
7581 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7582 .load_lut = intel_crtc_load_lut,
7583 .disable = intel_crtc_disable,
7584};
7585
7586static const struct drm_crtc_funcs intel_crtc_funcs = {
7587 .reset = intel_crtc_reset,
7588 .cursor_set = intel_crtc_cursor_set,
7589 .cursor_move = intel_crtc_cursor_move,
7590 .gamma_set = intel_crtc_gamma_set,
7591 .set_config = drm_crtc_helper_set_config,
7592 .destroy = intel_crtc_destroy,
7593 .page_flip = intel_crtc_page_flip,
7594};
7595
b358d0a6 7596static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7597{
22fd0fab 7598 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7599 struct intel_crtc *intel_crtc;
7600 int i;
7601
7602 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7603 if (intel_crtc == NULL)
7604 return;
7605
7606 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7607
7608 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7609 for (i = 0; i < 256; i++) {
7610 intel_crtc->lut_r[i] = i;
7611 intel_crtc->lut_g[i] = i;
7612 intel_crtc->lut_b[i] = i;
7613 }
7614
80824003
JB		 7615 /* Swap pipes & planes for FBC on pre-965 */
7616 intel_crtc->pipe = pipe;
7617 intel_crtc->plane = pipe;
e2e767ab 7618 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7619 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7620 intel_crtc->plane = !pipe;
80824003
JB		 7621 }
7622
22fd0fab
JB		 7623 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7624 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7625 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7626 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7627
5d1d0cc8 7628 intel_crtc_reset(&intel_crtc->base);
04dbff52 7629 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7630 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7631
7632 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7633 if (pipe == 2 && IS_IVYBRIDGE(dev))
7634 intel_crtc->no_pll = true;
7e7d76c3
JB		 7635 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7636 intel_helper_funcs.commit = ironlake_crtc_commit;
7637 } else {
7638 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7639 intel_helper_funcs.commit = i9xx_crtc_commit;
7640 }
7641
79e53945
JB		 7642 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7643
652c393a
JB		 7644 intel_crtc->busy = false;
7645
7646 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7647 (unsigned long)intel_crtc);
79e53945
JB		 7648}
7649
08d7b3d1 7650int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7651 struct drm_file *file)
08d7b3d1
CW		 7652{
7653 drm_i915_private_t *dev_priv = dev->dev_private;
7654 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7655 struct drm_mode_object *drmmode_obj;
7656 struct intel_crtc *crtc;
08d7b3d1
CW		 7657
7658 if (!dev_priv) {
7659 DRM_ERROR("called with no initialization\n");
7660 return -EINVAL;
7661 }
7662
c05422d5
DV		 7663 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7664 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7665
c05422d5 7666 if (!drmmode_obj) {
08d7b3d1
CW		 7667 DRM_ERROR("no such CRTC id\n");
7668 return -EINVAL;
7669 }
7670
c05422d5
DV		 7671 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7672 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7673
c05422d5 7674 return 0;
08d7b3d1
CW		 7675}
7676
c5e4df33 7677static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7678{
4ef69c7a 7679 struct intel_encoder *encoder;
79e53945 7680 int index_mask = 0;
79e53945
JB		 7681 int entry = 0;
7682
4ef69c7a
CW		 7683 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7684 if (type_mask & encoder->clone_mask)
79e53945
JB		 7685 index_mask |= (1 << entry);
7686 entry++;
7687 }
4ef69c7a 7688
79e53945
JB		 7689 return index_mask;
7690}
7691
4d302442
CW		 7692static bool has_edp_a(struct drm_device *dev)
7693{
7694 struct drm_i915_private *dev_priv = dev->dev_private;
7695
7696 if (!IS_MOBILE(dev))
7697 return false;
7698
7699 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7700 return false;
7701
7702 if (IS_GEN5(dev) &&
7703 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7704 return false;
7705
7706 return true;
7707}
7708
79e53945
JB		 7709static void intel_setup_outputs(struct drm_device *dev)
7710{
725e30ad 7711 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7712 struct intel_encoder *encoder;
cb0953d7 7713 bool dpd_is_edp = false;
c5d1b51d 7714 bool has_lvds = false;
79e53945 7715
541998a1 7716 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7717 has_lvds = intel_lvds_init(dev);
7718 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7719 /* disable the panel fitter on everything but LVDS */
7720 I915_WRITE(PFIT_CONTROL, 0);
7721 }
79e53945 7722
bad720ff 7723 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7724 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7725
4d302442 7726 if (has_edp_a(dev))
32f9d658
ZW		 7727 intel_dp_init(dev, DP_A);
7728
cb0953d7
AJ		 7729 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7730 intel_dp_init(dev, PCH_DP_D);
7731 }
7732
7733 intel_crt_init(dev);
7734
7735 if (HAS_PCH_SPLIT(dev)) {
7736 int found;
7737
30ad48b7 7738 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7739 /* PCH SDVOB multiplex with HDMIB */
7740 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7741 if (!found)
7742 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7743 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7744 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7745 }
7746
7747 if (I915_READ(HDMIC) & PORT_DETECTED)
7748 intel_hdmi_init(dev, HDMIC);
7749
7750 if (I915_READ(HDMID) & PORT_DETECTED)
7751 intel_hdmi_init(dev, HDMID);
7752
5eb08b69
ZW		 7753 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7754 intel_dp_init(dev, PCH_DP_C);
7755
cb0953d7 7756 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7757 intel_dp_init(dev, PCH_DP_D);
7758
103a196f 7759 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7760 bool found = false;
7d57382e 7761
725e30ad 7762 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7763 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7764 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7765 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7766 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7767 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7768 }
27185ae1 7769
b01f2c3a
JB		 7770 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7771 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7772 intel_dp_init(dev, DP_B);
b01f2c3a 7773 }
725e30ad 7774 }
13520b05
KH		 7775
7776 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7777
b01f2c3a
JB		 7778 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7779 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7780 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7781 }
27185ae1
ML		 7782
7783 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7784
b01f2c3a
JB		 7785 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7786 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7787 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7788 }
7789 if (SUPPORTS_INTEGRATED_DP(dev)) {
7790 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7791 intel_dp_init(dev, DP_C);
b01f2c3a 7792 }
725e30ad 7793 }
27185ae1 7794
b01f2c3a
JB		 7795 if (SUPPORTS_INTEGRATED_DP(dev) &&
7796 (I915_READ(DP_D) & DP_DETECTED)) {
7797 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7798 intel_dp_init(dev, DP_D);
b01f2c3a 7799 }
bad720ff 7800 } else if (IS_GEN2(dev))
79e53945
JB		 7801 intel_dvo_init(dev);
7802
103a196f 7803 if (SUPPORTS_TV(dev))
79e53945
JB		 7804 intel_tv_init(dev);
7805
4ef69c7a
CW		 7806 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7807 encoder->base.possible_crtcs = encoder->crtc_mask;
7808 encoder->base.possible_clones =
7809 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7810 }
47356eb6 7811
2c7111db
CW		 7812 /* disable all the possible outputs/crtcs before entering KMS mode */
7813 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7814
7815 if (HAS_PCH_SPLIT(dev))
7816 ironlake_init_pch_refclk(dev);
79e53945
JB		 7817}
7818
7819static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7820{
7821 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7822
7823 drm_framebuffer_cleanup(fb);
05394f39 7824 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7825
7826 kfree(intel_fb);
7827}
7828
7829static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7830 struct drm_file *file,
79e53945
JB		 7831 unsigned int *handle)
7832{
7833 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7834 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7835
05394f39 7836 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7837}
7838
7839static const struct drm_framebuffer_funcs intel_fb_funcs = {
7840 .destroy = intel_user_framebuffer_destroy,
7841 .create_handle = intel_user_framebuffer_create_handle,
7842};
7843
38651674
DA		 7844int intel_framebuffer_init(struct drm_device *dev,
7845 struct intel_framebuffer *intel_fb,
308e5bcb 7846 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7847 struct drm_i915_gem_object *obj)
79e53945 7848{
79e53945
JB		 7849 int ret;
7850
05394f39 7851 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7852 return -EINVAL;
7853
308e5bcb 7854 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7855 return -EINVAL;
7856
308e5bcb 7857 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7858 case DRM_FORMAT_RGB332:
7859 case DRM_FORMAT_RGB565:
7860 case DRM_FORMAT_XRGB8888:
7861 case DRM_FORMAT_ARGB8888:
7862 case DRM_FORMAT_XRGB2101010:
7863 case DRM_FORMAT_ARGB2101010:
308e5bcb 7864 /* RGB formats are common across chipsets */
b5626747 7865 break;
04b3924d
VS		 7866 case DRM_FORMAT_YUYV:
7867 case DRM_FORMAT_UYVY:
7868 case DRM_FORMAT_YVYU:
7869 case DRM_FORMAT_VYUY:
57cd6508
CW		 7870 break;
7871 default:
308e5bcb 7872 DRM_ERROR("unsupported pixel format\n");
57cd6508
CW		 7873 return -EINVAL;
7874 }
7875
79e53945
JB		 7876 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7877 if (ret) {
7878 DRM_ERROR("framebuffer init failed %d\n", ret);
7879 return ret;
7880 }
7881
7882 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7883 intel_fb->obj = obj;
79e53945
JB		 7884 return 0;
7885}
7886
79e53945
JB		 7887static struct drm_framebuffer *
7888intel_user_framebuffer_create(struct drm_device *dev,
7889 struct drm_file *filp,
308e5bcb 7890 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7891{
05394f39 7892 struct drm_i915_gem_object *obj;
79e53945 7893
308e5bcb
JB		 7894 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7895 mode_cmd->handles[0]));
c8725226 7896 if (&obj->base == NULL)
cce13ff7 7897 return ERR_PTR(-ENOENT);
79e53945 7898
d2dff872 7899 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7900}
7901
79e53945 7902static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7903 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7904 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7905};
7906
05394f39 7907static struct drm_i915_gem_object *
aa40d6bb 7908intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7909{
05394f39 7910 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7911 int ret;
7912
2c34b850
BW		 7913 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7914
aa40d6bb
ZN		 7915 ctx = i915_gem_alloc_object(dev, 4096);
7916 if (!ctx) {
9ea8d059
CW		 7917 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7918 return NULL;
7919 }
7920
75e9e915 7921 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7922 if (ret) {
7923 DRM_ERROR("failed to pin power context: %d\n", ret);
7924 goto err_unref;
7925 }
7926
aa40d6bb 7927 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7928 if (ret) {
7929 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7930 goto err_unpin;
7931 }
9ea8d059 7932
aa40d6bb 7933 return ctx;
9ea8d059
CW		 7934
7935err_unpin:
aa40d6bb 7936 i915_gem_object_unpin(ctx);
9ea8d059 7937err_unref:
05394f39 7938 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7939 mutex_unlock(&dev->struct_mutex);
7940 return NULL;
7941}
7942
7648fa99
JB		 7943bool ironlake_set_drps(struct drm_device *dev, u8 val)
7944{
7945 struct drm_i915_private *dev_priv = dev->dev_private;
7946 u16 rgvswctl;
7947
7948 rgvswctl = I915_READ16(MEMSWCTL);
7949 if (rgvswctl & MEMCTL_CMD_STS) {
7950 DRM_DEBUG("gpu busy, RCS change rejected\n");
7951 return false; /* still busy with another command */
7952 }
7953
7954 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7955 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7956 I915_WRITE16(MEMSWCTL, rgvswctl);
7957 POSTING_READ16(MEMSWCTL);
7958
7959 rgvswctl |= MEMCTL_CMD_STS;
7960 I915_WRITE16(MEMSWCTL, rgvswctl);
7961
7962 return true;
7963}
7964
f97108d1
JB		 7965void ironlake_enable_drps(struct drm_device *dev)
7966{
7967 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7968 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7969 u8 fmax, fmin, fstart, vstart;
f97108d1 7970
ea056c14
JB		 7971 /* Enable temp reporting */
7972 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7973 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7974
f97108d1
JB		 7975 /* 100ms RC evaluation intervals */
7976 I915_WRITE(RCUPEI, 100000);
7977 I915_WRITE(RCDNEI, 100000);
7978
7979 /* Set max/min thresholds to 90ms and 80ms respectively */
7980 I915_WRITE(RCBMAXAVG, 90000);
7981 I915_WRITE(RCBMINAVG, 80000);
7982
7983 I915_WRITE(MEMIHYST, 1);
7984
7985 /* Set up min, max, and cur for interrupt handling */
7986 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7987 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7988 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7989 MEMMODE_FSTART_SHIFT;
7648fa99 7990
f97108d1
JB		 7991 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7992 PXVFREQ_PX_SHIFT;
7993
80dbf4b7 7994 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7995 dev_priv->fstart = fstart;
7996
80dbf4b7 7997 dev_priv->max_delay = fstart;
f97108d1
JB		 7998 dev_priv->min_delay = fmin;
7999 dev_priv->cur_delay = fstart;
8000
80dbf4b7
JB		 8001 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8002 fmax, fmin, fstart);
7648fa99 8003
f97108d1
JB		 8004 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8005
8006 /*
8007 * Interrupts will be enabled in ironlake_irq_postinstall
8008 */
8009
8010 I915_WRITE(VIDSTART, vstart);
8011 POSTING_READ(VIDSTART);
8012
8013 rgvmodectl |= MEMMODE_SWMODE_EN;
8014 I915_WRITE(MEMMODECTL, rgvmodectl);
8015
481b6af3 8016 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8017 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8018 msleep(1);
8019
7648fa99 8020 ironlake_set_drps(dev, fstart);
f97108d1 8021
7648fa99
JB		 8022 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8023 I915_READ(0x112e0);
8024 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8025 dev_priv->last_count2 = I915_READ(0x112f4);
8026 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8027}
8028
8029void ironlake_disable_drps(struct drm_device *dev)
8030{
8031 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8032 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8033
8034 /* Ack interrupts, disable EFC interrupt */
8035 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8036 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8037 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8038 I915_WRITE(DEIIR, DE_PCU_EVENT);
8039 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8040
8041 /* Go back to the starting frequency */
7648fa99 8042 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8043 msleep(1);
8044 rgvswctl |= MEMCTL_CMD_STS;
8045 I915_WRITE(MEMSWCTL, rgvswctl);
8046 msleep(1);
8047
8048}
8049
3b8d8d91
JB		 8050void gen6_set_rps(struct drm_device *dev, u8 val)
8051{
8052 struct drm_i915_private *dev_priv = dev->dev_private;
8053 u32 swreq;
8054
8055 swreq = (val & 0x3ff) << 25;
8056 I915_WRITE(GEN6_RPNSWREQ, swreq);
8057}
8058
8059void gen6_disable_rps(struct drm_device *dev)
8060{
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062
8063 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8064 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8065 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8066 /* Complete PM interrupt masking here doesn't race with the rps work
8067 * item again unmasking PM interrupts because that is using a different
8068 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8069 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8070
8071 spin_lock_irq(&dev_priv->rps_lock);
8072 dev_priv->pm_iir = 0;
8073 spin_unlock_irq(&dev_priv->rps_lock);
8074
3b8d8d91
JB		 8075 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8076}
8077
7648fa99
JB		 8078static unsigned long intel_pxfreq(u32 vidfreq)
8079{
8080 unsigned long freq;
8081 int div = (vidfreq & 0x3f0000) >> 16;
8082 int post = (vidfreq & 0x3000) >> 12;
8083 int pre = (vidfreq & 0x7);
8084
8085 if (!pre)
8086 return 0;
8087
8088 freq = ((div * 133333) / ((1<<post) * pre));
8089
8090 return freq;
8091}
8092
8093void intel_init_emon(struct drm_device *dev)
8094{
8095 struct drm_i915_private *dev_priv = dev->dev_private;
8096 u32 lcfuse;
8097 u8 pxw[16];
8098 int i;
8099
8100 /* Disable to program */
8101 I915_WRITE(ECR, 0);
8102 POSTING_READ(ECR);
8103
8104 /* Program energy weights for various events */
8105 I915_WRITE(SDEW, 0x15040d00);
8106 I915_WRITE(CSIEW0, 0x007f0000);
8107 I915_WRITE(CSIEW1, 0x1e220004);
8108 I915_WRITE(CSIEW2, 0x04000004);
8109
8110 for (i = 0; i < 5; i++)
8111 I915_WRITE(PEW + (i * 4), 0);
8112 for (i = 0; i < 3; i++)
8113 I915_WRITE(DEW + (i * 4), 0);
8114
8115 /* Program P-state weights to account for frequency power adjustment */
8116 for (i = 0; i < 16; i++) {
8117 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8118 unsigned long freq = intel_pxfreq(pxvidfreq);
8119 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8120 PXVFREQ_PX_SHIFT;
8121 unsigned long val;
8122
8123 val = vid * vid;
8124 val *= (freq / 1000);
8125 val *= 255;
8126 val /= (127*127*900);
8127 if (val > 0xff)
8128 DRM_ERROR("bad pxval: %ld\n", val);
8129 pxw[i] = val;
8130 }
8131 /* Render standby states get 0 weight */
8132 pxw[14] = 0;
8133 pxw[15] = 0;
8134
8135 for (i = 0; i < 4; i++) {
8136 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8137 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8138 I915_WRITE(PXW + (i * 4), val);
8139 }
8140
8141 /* Adjust magic regs to magic values (more experimental results) */
8142 I915_WRITE(OGW0, 0);
8143 I915_WRITE(OGW1, 0);
8144 I915_WRITE(EG0, 0x00007f00);
8145 I915_WRITE(EG1, 0x0000000e);
8146 I915_WRITE(EG2, 0x000e0000);
8147 I915_WRITE(EG3, 0x68000300);
8148 I915_WRITE(EG4, 0x42000000);
8149 I915_WRITE(EG5, 0x00140031);
8150 I915_WRITE(EG6, 0);
8151 I915_WRITE(EG7, 0);
8152
8153 for (i = 0; i < 8; i++)
8154 I915_WRITE(PXWL + (i * 4), 0);
8155
8156 /* Enable PMON + select events */
8157 I915_WRITE(ECR, 0x80000019);
8158
8159 lcfuse = I915_READ(LCFUSE02);
8160
8161 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8162}
8163
c0f372b3
KP		 8164static bool intel_enable_rc6(struct drm_device *dev)
8165{
8166 /*
8167 * Respect the kernel parameter if it is set
8168 */
8169 if (i915_enable_rc6 >= 0)
8170 return i915_enable_rc6;
8171
8172 /*
8173 * Disable RC6 on Ironlake
8174 */
8175 if (INTEL_INFO(dev)->gen == 5)
8176 return 0;
8177
8178 /*
8179 * Enable rc6 on Sandybridge if DMA remapping is disabled
8180 */
8181 if (INTEL_INFO(dev)->gen == 6) {
8182 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8183 intel_iommu_enabled ? "true" : "false",
8184 !intel_iommu_enabled ? "en" : "dis");
8185 return !intel_iommu_enabled;
8186 }
8187 DRM_DEBUG_DRIVER("RC6 enabled\n");
8188 return 1;
8189}
8190
3b8d8d91 8191void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8192{
a6044e23
JB		 8193 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8194 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8195 u32 pcu_mbox, rc6_mask = 0;
a6044e23 8196 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8197 int i;
8198
8199 /* Here begins a magic sequence of register writes to enable
8200 * auto-downclocking.
8201 *
8202 * Perhaps there might be some value in exposing these to
8203 * userspace...
8204 */
8205 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8206 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 8207 gen6_gt_force_wake_get(dev_priv);
8fd26859 8208
3b8d8d91 8209 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8210 I915_WRITE(GEN6_RC_CONTROL, 0);
8211
8212 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8213 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8214 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8215 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8216 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8217
8218 for (i = 0; i < I915_NUM_RINGS; i++)
8219 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8220
8221 I915_WRITE(GEN6_RC_SLEEP, 0);
8222 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8223 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8224 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8225 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8226
c0f372b3 8227 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8228 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8229 GEN6_RC_CTL_RC6_ENABLE;
8230
8fd26859 8231 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8232 rc6_mask |
9c3d2f7f 8233 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8234 GEN6_RC_CTL_HW_ENABLE);
8235
3b8d8d91 8236 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8237 GEN6_FREQUENCY(10) |
8238 GEN6_OFFSET(0) |
8239 GEN6_AGGRESSIVE_TURBO);
8240 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8241 GEN6_FREQUENCY(12));
8242
8243 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8244 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8245 18 << 24 |
8246 6 << 16);
ccab5c82
JB		 8247 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8248 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8249 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8250 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8251 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8252 I915_WRITE(GEN6_RP_CONTROL,
8253 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8254 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8255 GEN6_RP_MEDIA_IS_GFX |
8256 GEN6_RP_ENABLE |
ccab5c82
JB		 8257 GEN6_RP_UP_BUSY_AVG |
8258 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8259
8260 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8261 500))
8262 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8263
8264 I915_WRITE(GEN6_PCODE_DATA, 0);
8265 I915_WRITE(GEN6_PCODE_MAILBOX,
8266 GEN6_PCODE_READY |
8267 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8268 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8269 500))
8270 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8271
a6044e23
JB		 8272 min_freq = (rp_state_cap & 0xff0000) >> 16;
8273 max_freq = rp_state_cap & 0xff;
8274 cur_freq = (gt_perf_status & 0xff00) >> 8;
8275
8276 /* Check for overclock support */
8277 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8278 500))
8279 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8280 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8281 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8282 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8283 500))
8284 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8285 if (pcu_mbox & (1<<31)) { /* OC supported */
8286 max_freq = pcu_mbox & 0xff;
e281fcaa 8287 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8288 }
8289
8290 /* In units of 100MHz */
8291 dev_priv->max_delay = max_freq;
8292 dev_priv->min_delay = min_freq;
8293 dev_priv->cur_delay = cur_freq;
8294
8fd26859
CW		 8295 /* requires MSI enabled */
8296 I915_WRITE(GEN6_PMIER,
8297 GEN6_PM_MBOX_EVENT |
8298 GEN6_PM_THERMAL_EVENT |
8299 GEN6_PM_RP_DOWN_TIMEOUT |
8300 GEN6_PM_RP_UP_THRESHOLD |
8301 GEN6_PM_RP_DOWN_THRESHOLD |
8302 GEN6_PM_RP_UP_EI_EXPIRED |
8303 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8304 spin_lock_irq(&dev_priv->rps_lock);
8305 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8306 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8307 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8308 /* enable all PM interrupts */
8309 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8310
fcca7926 8311 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8312 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8313}
8314
23b2f8bb
JB		 8315void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8316{
8317 int min_freq = 15;
8318 int gpu_freq, ia_freq, max_ia_freq;
8319 int scaling_factor = 180;
8320
8321 max_ia_freq = cpufreq_quick_get_max(0);
8322 /*
8323 * Default to measured freq if none found, PCU will ensure we don't go
8324 * over
8325 */
8326 if (!max_ia_freq)
8327 max_ia_freq = tsc_khz;
8328
8329 /* Convert from kHz to MHz */
8330 max_ia_freq /= 1000;
8331
8332 mutex_lock(&dev_priv->dev->struct_mutex);
8333
8334 /*
8335 * For each potential GPU frequency, load a ring frequency we'd like
8336 * to use for memory access. We do this by specifying the IA frequency
8337 * the PCU should use as a reference to determine the ring frequency.
8338 */
8339 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8340 gpu_freq--) {
8341 int diff = dev_priv->max_delay - gpu_freq;
8342
8343 /*
8344 * For GPU frequencies less than 750MHz, just use the lowest
8345 * ring freq.
8346 */
8347 if (gpu_freq < min_freq)
8348 ia_freq = 800;
8349 else
8350 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8351 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8352
8353 I915_WRITE(GEN6_PCODE_DATA,
8354 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8355 gpu_freq);
8356 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8357 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8358 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8359 GEN6_PCODE_READY) == 0, 10)) {
8360 DRM_ERROR("pcode write of freq table timed out\n");
8361 continue;
8362 }
8363 }
8364
8365 mutex_unlock(&dev_priv->dev->struct_mutex);
8366}
8367
6067aaea
JB		 8368static void ironlake_init_clock_gating(struct drm_device *dev)
8369{
8370 struct drm_i915_private *dev_priv = dev->dev_private;
8371 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8372
8373 /* Required for FBC */
8374 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8375 DPFCRUNIT_CLOCK_GATE_DISABLE |
8376 DPFDUNIT_CLOCK_GATE_DISABLE;
8377 /* Required for CxSR */
8378 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8379
8380 I915_WRITE(PCH_3DCGDIS0,
8381 MARIUNIT_CLOCK_GATE_DISABLE |
8382 SVSMUNIT_CLOCK_GATE_DISABLE);
8383 I915_WRITE(PCH_3DCGDIS1,
8384 VFMUNIT_CLOCK_GATE_DISABLE);
8385
8386 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8387
6067aaea
JB		 8388 /*
8389 * According to the spec the following bits should be set in
8390 * order to enable memory self-refresh
8391 * The bit 22/21 of 0x42004
8392 * The bit 5 of 0x42020
8393 * The bit 15 of 0x45000
8394 */
8395 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8396 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8397 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8398 I915_WRITE(ILK_DSPCLK_GATE,
8399 (I915_READ(ILK_DSPCLK_GATE) |
8400 ILK_DPARB_CLK_GATE));
8401 I915_WRITE(DISP_ARB_CTL,
8402 (I915_READ(DISP_ARB_CTL) |
8403 DISP_FBC_WM_DIS));
8404 I915_WRITE(WM3_LP_ILK, 0);
8405 I915_WRITE(WM2_LP_ILK, 0);
8406 I915_WRITE(WM1_LP_ILK, 0);
8407
8408 /*
8409 * Based on the document from hardware guys the following bits
8410 * should be set unconditionally in order to enable FBC.
8411 * The bit 22 of 0x42000
8412 * The bit 22 of 0x42004
8413 * The bit 7,8,9 of 0x42020.
8414 */
8415 if (IS_IRONLAKE_M(dev)) {
8416 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8417 I915_READ(ILK_DISPLAY_CHICKEN1) |
8418 ILK_FBCQ_DIS);
8419 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8420 I915_READ(ILK_DISPLAY_CHICKEN2) |
8421 ILK_DPARB_GATE);
8422 I915_WRITE(ILK_DSPCLK_GATE,
8423 I915_READ(ILK_DSPCLK_GATE) |
8424 ILK_DPFC_DIS1 |
8425 ILK_DPFC_DIS2 |
8426 ILK_CLK_FBC);
8427 }
8428
8429 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8430 I915_READ(ILK_DISPLAY_CHICKEN2) |
8431 ILK_ELPIN_409_SELECT);
8432 I915_WRITE(_3D_CHICKEN2,
8433 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8434 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8435}
8436
6067aaea 8437static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8438{
8439 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8440 int pipe;
6067aaea
JB		 8441 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8442
8443 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8444
6067aaea
JB		 8445 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8446 I915_READ(ILK_DISPLAY_CHICKEN2) |
8447 ILK_ELPIN_409_SELECT);
8956c8bb 8448
6067aaea
JB		 8449 I915_WRITE(WM3_LP_ILK, 0);
8450 I915_WRITE(WM2_LP_ILK, 0);
8451 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8452
406478dc
EA		 8453 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8454 * gating disable must be set. Failure to set it results in
8455 * flickering pixels due to Z write ordering failures after
8456 * some amount of runtime in the Mesa "fire" demo, and Unigine
8457 * Sanctuary and Tropics, and apparently anything else with
8458 * alpha test or pixel discard.
9ca1d10d
EA		 8459 *
8460 * According to the spec, bit 11 (RCCUNIT) must also be set,
8461 * but we didn't debug actual testcases to find it out.
406478dc 8462 */
9ca1d10d
EA		 8463 I915_WRITE(GEN6_UCGCTL2,
8464 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8465 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8466
652c393a 8467 /*
6067aaea
JB		 8468 * According to the spec the following bits should be
8469 * set in order to enable memory self-refresh and fbc:
8470 * The bit21 and bit22 of 0x42000
8471 * The bit21 and bit22 of 0x42004
8472 * The bit5 and bit7 of 0x42020
8473 * The bit14 of 0x70180
8474 * The bit14 of 0x71180
652c393a 8475 */
6067aaea
JB		 8476 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8477 I915_READ(ILK_DISPLAY_CHICKEN1) |
8478 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8479 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8480 I915_READ(ILK_DISPLAY_CHICKEN2) |
8481 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8482 I915_WRITE(ILK_DSPCLK_GATE,
8483 I915_READ(ILK_DSPCLK_GATE) |
8484 ILK_DPARB_CLK_GATE |
8485 ILK_DPFD_CLK_GATE);
8956c8bb 8486
d74362c9 8487 for_each_pipe(pipe) {
6067aaea
JB		 8488 I915_WRITE(DSPCNTR(pipe),
8489 I915_READ(DSPCNTR(pipe)) |
8490 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8491 intel_flush_display_plane(dev_priv, pipe);
8492 }
6067aaea 8493}
8956c8bb 8494
28963a3e
JB		 8495static void ivybridge_init_clock_gating(struct drm_device *dev)
8496{
8497 struct drm_i915_private *dev_priv = dev->dev_private;
8498 int pipe;
8499 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8500
28963a3e 8501 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8502
28963a3e
JB		 8503 I915_WRITE(WM3_LP_ILK, 0);
8504 I915_WRITE(WM2_LP_ILK, 0);
8505 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8506
28963a3e 8507 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8508
116ac8d2
EA		 8509 I915_WRITE(IVB_CHICKEN3,
8510 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8511 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8512
d74362c9 8513 for_each_pipe(pipe) {
28963a3e
JB		 8514 I915_WRITE(DSPCNTR(pipe),
8515 I915_READ(DSPCNTR(pipe)) |
8516 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8517 intel_flush_display_plane(dev_priv, pipe);
8518 }
28963a3e
JB		 8519}
8520
6067aaea
JB		 8521static void g4x_init_clock_gating(struct drm_device *dev)
8522{
8523 struct drm_i915_private *dev_priv = dev->dev_private;
8524 uint32_t dspclk_gate;
8fd26859 8525
6067aaea
JB		 8526 I915_WRITE(RENCLK_GATE_D1, 0);
8527 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8528 GS_UNIT_CLOCK_GATE_DISABLE |
8529 CL_UNIT_CLOCK_GATE_DISABLE);
8530 I915_WRITE(RAMCLK_GATE_D, 0);
8531 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8532 OVRUNIT_CLOCK_GATE_DISABLE |
8533 OVCUNIT_CLOCK_GATE_DISABLE;
8534 if (IS_GM45(dev))
8535 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8536 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8537}
1398261a 8538
6067aaea
JB		 8539static void crestline_init_clock_gating(struct drm_device *dev)
8540{
8541 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8542
6067aaea
JB		 8543 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8544 I915_WRITE(RENCLK_GATE_D2, 0);
8545 I915_WRITE(DSPCLK_GATE_D, 0);
8546 I915_WRITE(RAMCLK_GATE_D, 0);
8547 I915_WRITE16(DEUC, 0);
8548}
652c393a 8549
6067aaea
JB		 8550static void broadwater_init_clock_gating(struct drm_device *dev)
8551{
8552 struct drm_i915_private *dev_priv = dev->dev_private;
8553
8554 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8555 I965_RCC_CLOCK_GATE_DISABLE |
8556 I965_RCPB_CLOCK_GATE_DISABLE |
8557 I965_ISC_CLOCK_GATE_DISABLE |
8558 I965_FBC_CLOCK_GATE_DISABLE);
8559 I915_WRITE(RENCLK_GATE_D2, 0);
8560}
8561
8562static void gen3_init_clock_gating(struct drm_device *dev)
8563{
8564 struct drm_i915_private *dev_priv = dev->dev_private;
8565 u32 dstate = I915_READ(D_STATE);
8566
8567 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8568 DSTATE_DOT_CLOCK_GATING;
8569 I915_WRITE(D_STATE, dstate);
8570}
8571
8572static void i85x_init_clock_gating(struct drm_device *dev)
8573{
8574 struct drm_i915_private *dev_priv = dev->dev_private;
8575
8576 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8577}
8578
8579static void i830_init_clock_gating(struct drm_device *dev)
8580{
8581 struct drm_i915_private *dev_priv = dev->dev_private;
8582
8583 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8584}
8585
645c62a5
JB		 8586static void ibx_init_clock_gating(struct drm_device *dev)
8587{
8588 struct drm_i915_private *dev_priv = dev->dev_private;
8589
8590 /*
8591 * On Ibex Peak and Cougar Point, we need to disable clock
8592 * gating for the panel power sequencer or it will fail to
8593 * start up when no ports are active.
8594 */
8595 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8596}
8597
8598static void cpt_init_clock_gating(struct drm_device *dev)
8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8601 int pipe;
645c62a5
JB		 8602
8603 /*
8604 * On Ibex Peak and Cougar Point, we need to disable clock
8605 * gating for the panel power sequencer or it will fail to
8606 * start up when no ports are active.
8607 */
8608 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8609 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8610 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8611 /* Without this, mode sets may fail silently on FDI */
8612 for_each_pipe(pipe)
8613 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8614}
8615
ac668088 8616static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8617{
8618 struct drm_i915_private *dev_priv = dev->dev_private;
8619
8620 if (dev_priv->renderctx) {
ac668088
CW		 8621 i915_gem_object_unpin(dev_priv->renderctx);
8622 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8623 dev_priv->renderctx = NULL;
8624 }
8625
8626 if (dev_priv->pwrctx) {
ac668088
CW		 8627 i915_gem_object_unpin(dev_priv->pwrctx);
8628 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8629 dev_priv->pwrctx = NULL;
8630 }
8631}
8632
8633static void ironlake_disable_rc6(struct drm_device *dev)
8634{
8635 struct drm_i915_private *dev_priv = dev->dev_private;
8636
8637 if (I915_READ(PWRCTXA)) {
8638 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8639 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8640 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8641 50);
0cdab21f
CW		 8642
8643 I915_WRITE(PWRCTXA, 0);
8644 POSTING_READ(PWRCTXA);
8645
ac668088
CW		 8646 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8647 POSTING_READ(RSTDBYCTL);
0cdab21f 8648 }
ac668088 8649
99507307 8650 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8651}
8652
ac668088 8653static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8654{
8655 struct drm_i915_private *dev_priv = dev->dev_private;
8656
ac668088
CW		 8657 if (dev_priv->renderctx == NULL)
8658 dev_priv->renderctx = intel_alloc_context_page(dev);
8659 if (!dev_priv->renderctx)
8660 return -ENOMEM;
8661
8662 if (dev_priv->pwrctx == NULL)
8663 dev_priv->pwrctx = intel_alloc_context_page(dev);
8664 if (!dev_priv->pwrctx) {
8665 ironlake_teardown_rc6(dev);
8666 return -ENOMEM;
8667 }
8668
8669 return 0;
d5bb081b
JB		 8670}
8671
8672void ironlake_enable_rc6(struct drm_device *dev)
8673{
8674 struct drm_i915_private *dev_priv = dev->dev_private;
8675 int ret;
8676
ac668088
CW		 8677 /* rc6 disabled by default due to repeated reports of hanging during
8678 * boot and resume.
8679 */
c0f372b3 8680 if (!intel_enable_rc6(dev))
ac668088
CW		 8681 return;
8682
2c34b850 8683 mutex_lock(&dev->struct_mutex);
ac668088 8684 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8685 if (ret) {
8686 mutex_unlock(&dev->struct_mutex);
ac668088 8687 return;
2c34b850 8688 }
ac668088 8689
d5bb081b
JB		 8690 /*
8691 * GPU can automatically power down the render unit if given a page
8692 * to save state.
8693 */
8694 ret = BEGIN_LP_RING(6);
8695 if (ret) {
ac668088 8696 ironlake_teardown_rc6(dev);
2c34b850 8697 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8698 return;
8699 }
ac668088 8700
d5bb081b
JB		 8701 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8702 OUT_RING(MI_SET_CONTEXT);
8703 OUT_RING(dev_priv->renderctx->gtt_offset |
8704 MI_MM_SPACE_GTT |
8705 MI_SAVE_EXT_STATE_EN |
8706 MI_RESTORE_EXT_STATE_EN |
8707 MI_RESTORE_INHIBIT);
8708 OUT_RING(MI_SUSPEND_FLUSH);
8709 OUT_RING(MI_NOOP);
8710 OUT_RING(MI_FLUSH);
8711 ADVANCE_LP_RING();
8712
4a246cfc
BW		 8713 /*
8714 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8715 * does an implicit flush, combined with MI_FLUSH above, it should be
8716 * safe to assume that renderctx is valid
8717 */
8718 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8719 if (ret) {
8720 DRM_ERROR("failed to enable ironlake power power savings\n");
8721 ironlake_teardown_rc6(dev);
8722 mutex_unlock(&dev->struct_mutex);
8723 return;
8724 }
8725
d5bb081b
JB		 8726 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8727 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8728 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8729}
8730
645c62a5
JB		 8731void intel_init_clock_gating(struct drm_device *dev)
8732{
8733 struct drm_i915_private *dev_priv = dev->dev_private;
8734
8735 dev_priv->display.init_clock_gating(dev);
8736
8737 if (dev_priv->display.init_pch_clock_gating)
8738 dev_priv->display.init_pch_clock_gating(dev);
8739}
ac668088 8740
e70236a8
JB		 8741/* Set up chip specific display functions */
8742static void intel_init_display(struct drm_device *dev)
8743{
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745
8746 /* We always want a DPMS function */
f564048e 8747 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8748 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8749 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8750 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8751 } else {
e70236a8 8752 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8753 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8754 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8755 }
e70236a8 8756
ee5382ae 8757 if (I915_HAS_FBC(dev)) {
9c04f015 8758 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8759 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8760 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8761 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8762 } else if (IS_GM45(dev)) {
74dff282
JB		 8763 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8764 dev_priv->display.enable_fbc = g4x_enable_fbc;
8765 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8766 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8767 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8768 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8769 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8770 }
74dff282 8771 /* 855GM needs testing */
e70236a8
JB		 8772 }
8773
8774 /* Returns the core display clock speed */
0206e353 8775 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8776 dev_priv->display.get_display_clock_speed =
8777 i945_get_display_clock_speed;
8778 else if (IS_I915G(dev))
8779 dev_priv->display.get_display_clock_speed =
8780 i915_get_display_clock_speed;
f2b115e6 8781 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8782 dev_priv->display.get_display_clock_speed =
8783 i9xx_misc_get_display_clock_speed;
8784 else if (IS_I915GM(dev))
8785 dev_priv->display.get_display_clock_speed =
8786 i915gm_get_display_clock_speed;
8787 else if (IS_I865G(dev))
8788 dev_priv->display.get_display_clock_speed =
8789 i865_get_display_clock_speed;
f0f8a9ce 8790 else if (IS_I85X(dev))
e70236a8
JB		 8791 dev_priv->display.get_display_clock_speed =
8792 i855_get_display_clock_speed;
8793 else /* 852, 830 */
8794 dev_priv->display.get_display_clock_speed =
8795 i830_get_display_clock_speed;
8796
8797 /* For FIFO watermark updates */
7f8a8569 8798 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8799 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8800 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8801
8802 /* IVB configs may use multi-threaded forcewake */
8803 if (IS_IVYBRIDGE(dev)) {
8804 u32 ecobus;
8805
c7dffff7
KP		 8806 /* A small trick here - if the bios hasn't configured MT forcewake,
8807 * and if the device is in RC6, then force_wake_mt_get will not wake
8808 * the device and the ECOBUS read will return zero. Which will be
8809 * (correctly) interpreted by the test below as MT forcewake being
8810 * disabled.
8811 */
8d715f00
KP		 8812 mutex_lock(&dev->struct_mutex);
8813 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8814 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8815 __gen6_gt_force_wake_mt_put(dev_priv);
8816 mutex_unlock(&dev->struct_mutex);
8817
8818 if (ecobus & FORCEWAKE_MT_ENABLE) {
8819 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8820 dev_priv->display.force_wake_get =
8821 __gen6_gt_force_wake_mt_get;
8822 dev_priv->display.force_wake_put =
8823 __gen6_gt_force_wake_mt_put;
8824 }
8825 }
8826
645c62a5
JB		 8827 if (HAS_PCH_IBX(dev))
8828 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8829 else if (HAS_PCH_CPT(dev))
8830 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8831
f00a3ddf 8832 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8833 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8834 dev_priv->display.update_wm = ironlake_update_wm;
8835 else {
8836 DRM_DEBUG_KMS("Failed to get proper latency. "
8837 "Disable CxSR\n");
8838 dev_priv->display.update_wm = NULL;
1398261a 8839 }
674cf967 8840 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8841 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8842 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8843 } else if (IS_GEN6(dev)) {
8844 if (SNB_READ_WM0_LATENCY()) {
8845 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8846 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8847 } else {
8848 DRM_DEBUG_KMS("Failed to read display plane latency. "
8849 "Disable CxSR\n");
8850 dev_priv->display.update_wm = NULL;
7f8a8569 8851 }
674cf967 8852 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8853 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8854 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8855 } else if (IS_IVYBRIDGE(dev)) {
8856 /* FIXME: detect B0+ stepping and use auto training */
8857 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8858 if (SNB_READ_WM0_LATENCY()) {
8859 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8860 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8861 } else {
8862 DRM_DEBUG_KMS("Failed to read display plane latency. "
8863 "Disable CxSR\n");
8864 dev_priv->display.update_wm = NULL;
8865 }
28963a3e 8866 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8867 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8868 } else
8869 dev_priv->display.update_wm = NULL;
8870 } else if (IS_PINEVIEW(dev)) {
d4294342 8871 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8872 dev_priv->is_ddr3,
d4294342
ZY		 8873 dev_priv->fsb_freq,
8874 dev_priv->mem_freq)) {
8875 DRM_INFO("failed to find known CxSR latency "
95534263 8876 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8877 "disabling CxSR\n",
0206e353 8878 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8879 dev_priv->fsb_freq, dev_priv->mem_freq);
8880 /* Disable CxSR and never update its watermark again */
8881 pineview_disable_cxsr(dev);
8882 dev_priv->display.update_wm = NULL;
8883 } else
8884 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8885 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8886 } else if (IS_G4X(dev)) {
e0dac65e 8887 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8888 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8889 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8890 } else if (IS_GEN4(dev)) {
e70236a8 8891 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8892 if (IS_CRESTLINE(dev))
8893 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8894 else if (IS_BROADWATER(dev))
8895 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8896 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8897 dev_priv->display.update_wm = i9xx_update_wm;
8898 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8899 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8900 } else if (IS_I865G(dev)) {
8901 dev_priv->display.update_wm = i830_update_wm;
8902 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8903 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8904 } else if (IS_I85X(dev)) {
8905 dev_priv->display.update_wm = i9xx_update_wm;
8906 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8907 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8908 } else {
8f4695ed 8909 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8910 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8911 if (IS_845G(dev))
e70236a8
JB		 8912 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8913 else
8914 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8915 }
8c9f3aaf
JB		 8916
8917 /* Default just returns -ENODEV to indicate unsupported */
8918 dev_priv->display.queue_flip = intel_default_queue_flip;
8919
8920 switch (INTEL_INFO(dev)->gen) {
8921 case 2:
8922 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8923 break;
8924
8925 case 3:
8926 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8927 break;
8928
8929 case 4:
8930 case 5:
8931 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8932 break;
8933
8934 case 6:
8935 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8936 break;
7c9017e5
JB		 8937 case 7:
8938 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8939 break;
8c9f3aaf 8940 }
e70236a8
JB		 8941}
8942
b690e96c
JB		 8943/*
8944 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8945 * resume, or other times. This quirk makes sure that's the case for
8946 * affected systems.
8947 */
0206e353 8948static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8949{
8950 struct drm_i915_private *dev_priv = dev->dev_private;
8951
8952 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8953 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8954}
8955
435793df
KP		 8956/*
8957 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8958 */
8959static void quirk_ssc_force_disable(struct drm_device *dev)
8960{
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8963}
8964
b690e96c
JB		 8965struct intel_quirk {
8966 int device;
8967 int subsystem_vendor;
8968 int subsystem_device;
8969 void (*hook)(struct drm_device *dev);
8970};
8971
8972struct intel_quirk intel_quirks[] = {
8973 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8974 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8975 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8976 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8977
8978 /* Thinkpad R31 needs pipe A force quirk */
8979 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8980 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8981 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8982
8983 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8984 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8985 /* ThinkPad X40 needs pipe A force quirk */
8986
8987 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8988 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8989
8990 /* 855 & before need to leave pipe A & dpll A up */
8991 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8992 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8993
8994 /* Lenovo U160 cannot use SSC on LVDS */
8995 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8996
8997 /* Sony Vaio Y cannot use SSC on LVDS */
8998 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8999};
9000
9001static void intel_init_quirks(struct drm_device *dev)
9002{
9003 struct pci_dev *d = dev->pdev;
9004 int i;
9005
9006 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9007 struct intel_quirk *q = &intel_quirks[i];
9008
9009 if (d->device == q->device &&
9010 (d->subsystem_vendor == q->subsystem_vendor ||
9011 q->subsystem_vendor == PCI_ANY_ID) &&
9012 (d->subsystem_device == q->subsystem_device ||
9013 q->subsystem_device == PCI_ANY_ID))
9014 q->hook(dev);
9015 }
9016}
9017
9cce37f4
JB		 9018/* Disable the VGA plane that we never use */
9019static void i915_disable_vga(struct drm_device *dev)
9020{
9021 struct drm_i915_private *dev_priv = dev->dev_private;
9022 u8 sr1;
9023 u32 vga_reg;
9024
9025 if (HAS_PCH_SPLIT(dev))
9026 vga_reg = CPU_VGACNTRL;
9027 else
9028 vga_reg = VGACNTRL;
9029
9030 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9031 outb(1, VGA_SR_INDEX);
9032 sr1 = inb(VGA_SR_DATA);
9033 outb(sr1 | 1<<5, VGA_SR_DATA);
9034 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9035 udelay(300);
9036
9037 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9038 POSTING_READ(vga_reg);
9039}
9040
79e53945
JB		 9041void intel_modeset_init(struct drm_device *dev)
9042{
652c393a 9043 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9044 int i, ret;
79e53945
JB		 9045
9046 drm_mode_config_init(dev);
9047
9048 dev->mode_config.min_width = 0;
9049 dev->mode_config.min_height = 0;
9050
9051 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9052
b690e96c
JB		 9053 intel_init_quirks(dev);
9054
e70236a8
JB		 9055 intel_init_display(dev);
9056
a6c45cf0
CW		 9057 if (IS_GEN2(dev)) {
9058 dev->mode_config.max_width = 2048;
9059 dev->mode_config.max_height = 2048;
9060 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9061 dev->mode_config.max_width = 4096;
9062 dev->mode_config.max_height = 4096;
79e53945 9063 } else {
a6c45cf0
CW		 9064 dev->mode_config.max_width = 8192;
9065 dev->mode_config.max_height = 8192;
79e53945 9066 }
35c3047a 9067 dev->mode_config.fb_base = dev->agp->base;
79e53945 9068
28c97730 9069 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9070 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9071
a3524f1b 9072 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9073 intel_crtc_init(dev, i);
b840d907
JB		 9074 if (HAS_PCH_SPLIT(dev)) {
9075 ret = intel_plane_init(dev, i);
9076 if (ret)
9077 DRM_ERROR("plane %d init failed: %d\n",
9078 i, ret);
9079 }
79e53945
JB		 9080 }
9081
9cce37f4
JB		 9082 /* Just disable it once at startup */
9083 i915_disable_vga(dev);
79e53945 9084 intel_setup_outputs(dev);
652c393a 9085
645c62a5 9086 intel_init_clock_gating(dev);
9cce37f4 9087
7648fa99 9088 if (IS_IRONLAKE_M(dev)) {
f97108d1 9089 ironlake_enable_drps(dev);
7648fa99
JB		 9090 intel_init_emon(dev);
9091 }
f97108d1 9092
1c70c0ce 9093 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9094 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9095 gen6_update_ring_freq(dev_priv);
9096 }
3b8d8d91 9097
652c393a
JB		 9098 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9099 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9100 (unsigned long)dev);
2c7111db
CW		 9101}
9102
9103void intel_modeset_gem_init(struct drm_device *dev)
9104{
9105 if (IS_IRONLAKE_M(dev))
9106 ironlake_enable_rc6(dev);
02e792fb
DV		 9107
9108 intel_setup_overlay(dev);
79e53945
JB		 9109}
9110
9111void intel_modeset_cleanup(struct drm_device *dev)
9112{
652c393a
JB		 9113 struct drm_i915_private *dev_priv = dev->dev_private;
9114 struct drm_crtc *crtc;
9115 struct intel_crtc *intel_crtc;
9116
f87ea761 9117 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9118 mutex_lock(&dev->struct_mutex);
9119
723bfd70
JB		 9120 intel_unregister_dsm_handler();
9121
9122
652c393a
JB		 9123 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9124 /* Skip inactive CRTCs */
9125 if (!crtc->fb)
9126 continue;
9127
9128 intel_crtc = to_intel_crtc(crtc);
3dec0095 9129 intel_increase_pllclock(crtc);
652c393a
JB		 9130 }
9131
973d04f9 9132 intel_disable_fbc(dev);
e70236a8 9133
f97108d1
JB		 9134 if (IS_IRONLAKE_M(dev))
9135 ironlake_disable_drps(dev);
1c70c0ce 9136 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9137 gen6_disable_rps(dev);
f97108d1 9138
d5bb081b
JB		 9139 if (IS_IRONLAKE_M(dev))
9140 ironlake_disable_rc6(dev);
0cdab21f 9141
69341a5e
KH		 9142 mutex_unlock(&dev->struct_mutex);
9143
6c0d9350
DV		 9144 /* Disable the irq before mode object teardown, for the irq might
9145 * enqueue unpin/hotplug work. */
9146 drm_irq_uninstall(dev);
9147 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9148 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9149
1630fe75
CW		 9150 /* flush any delayed tasks or pending work */
9151 flush_scheduled_work();
9152
3dec0095
DV		 9153 /* Shut off idle work before the crtcs get freed. */
9154 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9155 intel_crtc = to_intel_crtc(crtc);
9156 del_timer_sync(&intel_crtc->idle_timer);
9157 }
9158 del_timer_sync(&dev_priv->idle_timer);
9159 cancel_work_sync(&dev_priv->idle_work);
9160
79e53945
JB		 9161 drm_mode_config_cleanup(dev);
9162}
9163
f1c79df3
ZW		 9164/*
9165 * Return which encoder is currently attached for connector.
9166 */
df0e9248 9167struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9168{
df0e9248
CW		 9169 return &intel_attached_encoder(connector)->base;
9170}
f1c79df3 9171
df0e9248
CW		 9172void intel_connector_attach_encoder(struct intel_connector *connector,
9173 struct intel_encoder *encoder)
9174{
9175 connector->encoder = encoder;
9176 drm_mode_connector_attach_encoder(&connector->base,
9177 &encoder->base);
79e53945 9178}
28d52043
DA		 9179
9180/*
9181 * set vga decode state - true == enable VGA decode
9182 */
9183int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9184{
9185 struct drm_i915_private *dev_priv = dev->dev_private;
9186 u16 gmch_ctrl;
9187
9188 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9189 if (state)
9190 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9191 else
9192 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9193 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9194 return 0;
9195}
c4a1d9e4
CW		 9196
9197#ifdef CONFIG_DEBUG_FS
9198#include <linux/seq_file.h>
9199
9200struct intel_display_error_state {
9201 struct intel_cursor_error_state {
9202 u32 control;
9203 u32 position;
9204 u32 base;
9205 u32 size;
9206 } cursor[2];
9207
9208 struct intel_pipe_error_state {
9209 u32 conf;
9210 u32 source;
9211
9212 u32 htotal;
9213 u32 hblank;
9214 u32 hsync;
9215 u32 vtotal;
9216 u32 vblank;
9217 u32 vsync;
9218 } pipe[2];
9219
9220 struct intel_plane_error_state {
9221 u32 control;
9222 u32 stride;
9223 u32 size;
9224 u32 pos;
9225 u32 addr;
9226 u32 surface;
9227 u32 tile_offset;
9228 } plane[2];
9229};
9230
9231struct intel_display_error_state *
9232intel_display_capture_error_state(struct drm_device *dev)
9233{
0206e353 9234 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9235 struct intel_display_error_state *error;
9236 int i;
9237
9238 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9239 if (error == NULL)
9240 return NULL;
9241
9242 for (i = 0; i < 2; i++) {
9243 error->cursor[i].control = I915_READ(CURCNTR(i));
9244 error->cursor[i].position = I915_READ(CURPOS(i));
9245 error->cursor[i].base = I915_READ(CURBASE(i));
9246
9247 error->plane[i].control = I915_READ(DSPCNTR(i));
9248 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9249 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9250 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9251 error->plane[i].addr = I915_READ(DSPADDR(i));
9252 if (INTEL_INFO(dev)->gen >= 4) {
9253 error->plane[i].surface = I915_READ(DSPSURF(i));
9254 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9255 }
9256
9257 error->pipe[i].conf = I915_READ(PIPECONF(i));
9258 error->pipe[i].source = I915_READ(PIPESRC(i));
9259 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9260 error->pipe[i].hblank = I915_READ(HBLANK(i));
9261 error->pipe[i].hsync = I915_READ(HSYNC(i));
9262 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9263 error->pipe[i].vblank = I915_READ(VBLANK(i));
9264 error->pipe[i].vsync = I915_READ(VSYNC(i));
9265 }
9266
9267 return error;
9268}
9269
9270void
9271intel_display_print_error_state(struct seq_file *m,
9272 struct drm_device *dev,
9273 struct intel_display_error_state *error)
9274{
9275 int i;
9276
9277 for (i = 0; i < 2; i++) {
9278 seq_printf(m, "Pipe [%d]:\n", i);
9279 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9280 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9281 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9282 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9283 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9284 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9285 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9286 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9287
9288 seq_printf(m, "Plane [%d]:\n", i);
9289 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9290 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9291 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9292 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9293 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9294 if (INTEL_INFO(dev)->gen >= 4) {
9295 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9296 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9297 }
9298
9299 seq_printf(m, "Cursor [%d]:\n", i);
9300 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9301 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9302 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9303 }
9304}
9305#endif
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