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UAPI: (Scripted) Remove redundant DRM UAPI header #inclusions from drivers/gpu/.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
8ea30864 29#include "i915_drm.h"
80824003 30#include "i915_drv.h"
79e53945 31#include "drm_crtc.h"
79e53945 32#include "drm_crtc_helper.h"
37811fcc 33#include "drm_fb_helper.h"
913d8d11 34
481b6af3 35#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 36 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
37 int ret__ = 0; \
0206e353 38 while (!(COND)) { \
913d8d11
CW		 39 if (time_after(jiffies, timeout__)) { \
40 ret__ = -ETIMEDOUT; \
41 break; \
42 } \
cc1f7194 43 if (W && drm_can_sleep()) msleep(W); \
913d8d11
CW		 44 } \
45 ret__; \
46})
47
57f350b6 48#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 49 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
50 int ret__ = 0; \
51 while (!(COND)) { \
52 if (time_after(jiffies, timeout__)) { \
53 ret__ = -ETIMEDOUT; \
54 break; \
55 } \
56 cpu_relax(); \
57 } \
58 ret__; \
57f350b6
JB		 59})
60
481b6af3
CW		 61#define wait_for(COND, MS) _wait_for(COND, MS, 1)
62#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
63
021357ac
CW		 64#define KHz(x) (1000*x)
65#define MHz(x) KHz(1000*x)
66
79e53945
JB		 67/*
68 * Display related stuff
69 */
70
71/* store information about an Ixxx DVO */
72/* The i830->i865 use multiple DVOs with multiple i2cs */
73/* the i915, i945 have a single sDVO i2c bus - which is different */
74#define MAX_OUTPUTS 6
75/* maximum connectors per crtcs in the mode set */
76#define INTELFB_CONN_LIMIT 4
77
78#define INTEL_I2C_BUS_DVO 1
79#define INTEL_I2C_BUS_SDVO 2
80
81/* these are outputs from the chip - integrated only
82 external chips are via DVO or SDVO output */
83#define INTEL_OUTPUT_UNUSED 0
84#define INTEL_OUTPUT_ANALOG 1
85#define INTEL_OUTPUT_DVO 2
86#define INTEL_OUTPUT_SDVO 3
87#define INTEL_OUTPUT_LVDS 4
88#define INTEL_OUTPUT_TVOUT 5
7d57382e 89#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 90#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 91#define INTEL_OUTPUT_EDP 8
79e53945 92
f8aed700
ML		 93/* Intel Pipe Clone Bit */
94#define INTEL_HDMIB_CLONE_BIT 1
95#define INTEL_HDMIC_CLONE_BIT 2
96#define INTEL_HDMID_CLONE_BIT 3
97#define INTEL_HDMIE_CLONE_BIT 4
98#define INTEL_HDMIF_CLONE_BIT 5
99#define INTEL_SDVO_NON_TV_CLONE_BIT 6
100#define INTEL_SDVO_TV_CLONE_BIT 7
101#define INTEL_SDVO_LVDS_CLONE_BIT 8
102#define INTEL_ANALOG_CLONE_BIT 9
103#define INTEL_TV_CLONE_BIT 10
104#define INTEL_DP_B_CLONE_BIT 11
105#define INTEL_DP_C_CLONE_BIT 12
106#define INTEL_DP_D_CLONE_BIT 13
107#define INTEL_LVDS_CLONE_BIT 14
108#define INTEL_DVO_TMDS_CLONE_BIT 15
109#define INTEL_DVO_LVDS_CLONE_BIT 16
7c8460db 110#define INTEL_EDP_CLONE_BIT 17
f8aed700 111
79e53945
JB		 112#define INTEL_DVO_CHIP_NONE 0
113#define INTEL_DVO_CHIP_LVDS 1
114#define INTEL_DVO_CHIP_TMDS 2
115#define INTEL_DVO_CHIP_TVOUT 4
116
6c9547ff
CW		 117/* drm_display_mode->private_flags */
118#define INTEL_MODE_PIXEL_MULTIPLIER_SHIFT (0x0)
119#define INTEL_MODE_PIXEL_MULTIPLIER_MASK (0xf << INTEL_MODE_PIXEL_MULTIPLIER_SHIFT)
3b5c78a3 120#define INTEL_MODE_DP_FORCE_6BPC (0x10)
f9bef081
DV		 121/* This flag must be set by the encoder's mode_fixup if it changes the crtc
122 * timings in the mode to prevent the crtc fixup from overwriting them.
123 * Currently only lvds needs that. */
124#define INTEL_MODE_CRTC_TIMINGS_SET (0x20)
6c9547ff
CW		 125
126static inline void
127intel_mode_set_pixel_multiplier(struct drm_display_mode *mode,
128 int multiplier)
129{
130 mode->clock *= multiplier;
131 mode->private_flags |= multiplier;
132}
133
134static inline int
135intel_mode_get_pixel_multiplier(const struct drm_display_mode *mode)
136{
137 return (mode->private_flags & INTEL_MODE_PIXEL_MULTIPLIER_MASK) >> INTEL_MODE_PIXEL_MULTIPLIER_SHIFT;
138}
139
79e53945
JB		 140struct intel_framebuffer {
141 struct drm_framebuffer base;
05394f39 142 struct drm_i915_gem_object *obj;
79e53945
JB		 143};
144
37811fcc
CW		 145struct intel_fbdev {
146 struct drm_fb_helper helper;
147 struct intel_framebuffer ifb;
148 struct list_head fbdev_list;
149 struct drm_display_mode *our_mode;
150};
79e53945 151
21d40d37 152struct intel_encoder {
4ef69c7a 153 struct drm_encoder base;
79e53945 154 int type;
e2f0ba97 155 bool needs_tv_clock;
21d40d37 156 void (*hot_plug)(struct intel_encoder *);
f8aed700
ML		 157 int crtc_mask;
158 int clone_mask;
79e53945
JB		 159};
160
5daa55eb
ZW		 161struct intel_connector {
162 struct drm_connector base;
df0e9248 163 struct intel_encoder *encoder;
5daa55eb
ZW		 164};
165
79e53945
JB		 166struct intel_crtc {
167 struct drm_crtc base;
80824003
JB		 168 enum pipe pipe;
169 enum plane plane;
79e53945
JB		 170 u8 lut_r[256], lut_g[256], lut_b[256];
171 int dpms_mode;
f7abfe8b 172 bool active; /* is the crtc on? independent of the dpms mode */
93314b5b 173 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a
JB		 174 bool busy; /* is scanout buffer being updated frequently? */
175 struct timer_list idle_timer;
176 bool lowfreq_avail;
02e792fb 177 struct intel_overlay *overlay;
6b95a207 178 struct intel_unpin_work *unpin_work;
77ffb597 179 int fdi_lanes;
cda4b7d3 180
e506a0c6
DV		 181 /* Display surface base address adjustement for pageflips. Note that on
182 * gen4+ this only adjusts up to a tile, offsets within a tile are
183 * handled in the hw itself (with the TILEOFF register). */
184 unsigned long dspaddr_offset;
185
05394f39 186 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 187 uint32_t cursor_addr;
188 int16_t cursor_x, cursor_y;
189 int16_t cursor_width, cursor_height;
6b383a7f 190 bool cursor_visible;
5a354204 191 unsigned int bpp;
4b645f14 192
ee7b9f93
JB		 193 /* We can share PLLs across outputs if the timings match */
194 struct intel_pch_pll *pch_pll;
79e53945
JB		 195};
196
b840d907
JB		 197struct intel_plane {
198 struct drm_plane base;
199 enum pipe pipe;
200 struct drm_i915_gem_object *obj;
201 int max_downscale;
202 u32 lut_r[1024], lut_g[1024], lut_b[1024];
203 void (*update_plane)(struct drm_plane *plane,
204 struct drm_framebuffer *fb,
205 struct drm_i915_gem_object *obj,
206 int crtc_x, int crtc_y,
207 unsigned int crtc_w, unsigned int crtc_h,
208 uint32_t x, uint32_t y,
209 uint32_t src_w, uint32_t src_h);
210 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 211 int (*update_colorkey)(struct drm_plane *plane,
212 struct drm_intel_sprite_colorkey *key);
213 void (*get_colorkey)(struct drm_plane *plane,
214 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 215};
216
b445e3b0
ED		 217struct intel_watermark_params {
218 unsigned long fifo_size;
219 unsigned long max_wm;
220 unsigned long default_wm;
221 unsigned long guard_size;
222 unsigned long cacheline_size;
223};
224
225struct cxsr_latency {
226 int is_desktop;
227 int is_ddr3;
228 unsigned long fsb_freq;
229 unsigned long mem_freq;
230 unsigned long display_sr;
231 unsigned long display_hpll_disable;
232 unsigned long cursor_sr;
233 unsigned long cursor_hpll_disable;
234};
235
79e53945 236#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 237#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 238#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 239#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 240#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 241
45187ace
JB		 242#define DIP_HEADER_SIZE 5
243
3c17fe4b
DH		 244#define DIP_TYPE_AVI 0x82
245#define DIP_VERSION_AVI 0x2
246#define DIP_LEN_AVI 13
c846b619
PZ		 247#define DIP_AVI_PR_1 0
248#define DIP_AVI_PR_2 1
3c17fe4b 249
26005210 250#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 251#define DIP_VERSION_SPD 0x1
252#define DIP_LEN_SPD 25
253#define DIP_SPD_UNKNOWN 0
254#define DIP_SPD_DSTB 0x1
255#define DIP_SPD_DVDP 0x2
256#define DIP_SPD_DVHS 0x3
257#define DIP_SPD_HDDVR 0x4
258#define DIP_SPD_DVC 0x5
259#define DIP_SPD_DSC 0x6
260#define DIP_SPD_VCD 0x7
261#define DIP_SPD_GAME 0x8
262#define DIP_SPD_PC 0x9
263#define DIP_SPD_BD 0xa
264#define DIP_SPD_SCD 0xb
265
3c17fe4b
DH		 266struct dip_infoframe {
267 uint8_t type; /* HB0 */
268 uint8_t ver; /* HB1 */
269 uint8_t len; /* HB2 - body len, not including checksum */
270 uint8_t ecc; /* Header ECC */
271 uint8_t checksum; /* PB0 */
272 union {
273 struct {
274 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
275 uint8_t Y_A_B_S;
276 /* PB2 - C 7:6, M 5:4, R 3:0 */
277 uint8_t C_M_R;
278 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
279 uint8_t ITC_EC_Q_SC;
280 /* PB4 - VIC 6:0 */
281 uint8_t VIC;
0aa534df
PZ		 282 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
283 uint8_t YQ_CN_PR;
3c17fe4b
DH		 284 /* PB6 to PB13 */
285 uint16_t top_bar_end;
286 uint16_t bottom_bar_start;
287 uint16_t left_bar_end;
288 uint16_t right_bar_start;
81014b9d 289 } __attribute__ ((packed)) avi;
c0864cb3
JB		 290 struct {
291 uint8_t vn[8];
292 uint8_t pd[16];
293 uint8_t sdi;
81014b9d 294 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 295 uint8_t payload[27];
296 } __attribute__ ((packed)) body;
297} __attribute__((packed));
298
f5bbfca3
ED		 299struct intel_hdmi {
300 struct intel_encoder base;
301 u32 sdvox_reg;
302 int ddc_bus;
303 int ddi_port;
304 uint32_t color_range;
305 bool has_hdmi_sink;
306 bool has_audio;
307 enum hdmi_force_audio force_audio;
308 void (*write_infoframe)(struct drm_encoder *encoder,
309 struct dip_infoframe *frame);
687f4d06
PZ		 310 void (*set_infoframes)(struct drm_encoder *encoder,
311 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 312};
313
f875c15a
CW		 314static inline struct drm_crtc *
315intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
316{
317 struct drm_i915_private *dev_priv = dev->dev_private;
318 return dev_priv->pipe_to_crtc_mapping[pipe];
319}
320
417ae147
CW		 321static inline struct drm_crtc *
322intel_get_crtc_for_plane(struct drm_device *dev, int plane)
323{
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 return dev_priv->plane_to_crtc_mapping[plane];
326}
327
4e5359cd
SF		 328struct intel_unpin_work {
329 struct work_struct work;
330 struct drm_device *dev;
05394f39
CW		 331 struct drm_i915_gem_object *old_fb_obj;
332 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd
SF		 333 struct drm_pending_vblank_event *event;
334 int pending;
335 bool enable_stall_check;
336};
337
1630fe75
CW		 338struct intel_fbc_work {
339 struct delayed_work work;
340 struct drm_crtc *crtc;
341 struct drm_framebuffer *fb;
342 int interval;
343};
344
4eab8136
JN		 345int intel_connector_update_modes(struct drm_connector *connector,
346 struct edid *edid);
335af9a2 347int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 348
3f43c48d 349extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 350extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
351
79e53945 352extern void intel_crt_init(struct drm_device *dev);
7d57382e 353extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
f5bbfca3 354extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
f5bbfca3 355extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 356extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
357 bool is_sdvob);
79e53945
JB		 358extern void intel_dvo_init(struct drm_device *dev);
359extern void intel_tv_init(struct drm_device *dev);
05394f39
CW		 360extern void intel_mark_busy(struct drm_device *dev,
361 struct drm_i915_gem_object *obj);
c5d1b51d 362extern bool intel_lvds_init(struct drm_device *dev);
a4fc5ed6
KP		 363extern void intel_dp_init(struct drm_device *dev, int dp_reg);
364void
365intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
366 struct drm_display_mode *adjusted_mode);
cb0953d7 367extern bool intel_dpd_is_edp(struct drm_device *dev);
0206e353 368extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 369extern int intel_edp_target_clock(struct intel_encoder *,
370 struct drm_display_mode *mode);
814948ad 371extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 372extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 373extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
374 enum plane plane);
32f9d658 375
9104183d
CW		 376void intel_sanitize_pm(struct drm_device *dev);
377
a9573556 378/* intel_panel.c */
1d8e1c75
CW		 379extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
380 struct drm_display_mode *adjusted_mode);
381extern void intel_pch_panel_fitting(struct drm_device *dev,
382 int fitting_mode,
cb1793ce 383 const struct drm_display_mode *mode,
1d8e1c75 384 struct drm_display_mode *adjusted_mode);
a9573556 385extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 386extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
aaa6fd2a 387extern int intel_panel_setup_backlight(struct drm_device *dev);
24ded204
DV		 388extern void intel_panel_enable_backlight(struct drm_device *dev,
389 enum pipe pipe);
47356eb6 390extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 391extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 392extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 393
79e53945 394extern void intel_crtc_load_lut(struct drm_crtc *crtc);
0206e353
AJ		 395extern void intel_encoder_prepare(struct drm_encoder *encoder);
396extern void intel_encoder_commit(struct drm_encoder *encoder);
ea5b213a 397extern void intel_encoder_destroy(struct drm_encoder *encoder);
79e53945 398
df0e9248
CW		 399static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
400{
401 return to_intel_connector(connector)->encoder;
402}
403
404extern void intel_connector_attach_encoder(struct intel_connector *connector,
405 struct intel_encoder *encoder);
406extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 407
408extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
409 struct drm_crtc *crtc);
08d7b3d1
CW		 410int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
411 struct drm_file *file_priv);
9d0498a2 412extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 413extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
8261b191
CW		 414
415struct intel_load_detect_pipe {
d2dff872 416 struct drm_framebuffer *release_fb;
8261b191
CW		 417 bool load_detect_temp;
418 int dpms_mode;
419};
7173188d
CW		 420extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
421 struct drm_connector *connector,
422 struct drm_display_mode *mode,
8261b191 423 struct intel_load_detect_pipe *old);
21d40d37 424extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
c1c43977 425 struct drm_connector *connector,
8261b191 426 struct intel_load_detect_pipe *old);
79e53945 427
79e53945
JB		 428extern void intelfb_restore(void);
429extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
430 u16 blue, int regno);
b8c00ac5
DA		 431extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
432 u16 *blue, int regno);
0cdab21f 433extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 434
127bd2ac 435extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 436 struct drm_i915_gem_object *obj,
919926ae 437 struct intel_ring_buffer *pipelined);
1690e1eb 438extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 439
38651674
DA		 440extern int intel_framebuffer_init(struct drm_device *dev,
441 struct intel_framebuffer *ifb,
308e5bcb 442 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 443 struct drm_i915_gem_object *obj);
38651674
DA		 444extern int intel_fbdev_init(struct drm_device *dev);
445extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 446extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 447extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
448extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 449extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 450
02e792fb
DV		 451extern void intel_setup_overlay(struct drm_device *dev);
452extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 453extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 454extern int intel_overlay_put_image(struct drm_device *dev, void *data,
455 struct drm_file *file_priv);
456extern int intel_overlay_attrs(struct drm_device *dev, void *data,
457 struct drm_file *file_priv);
4abe3520 458
eb1f8e4f 459extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 460extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 461
b840d907
JB		 462extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
463 bool state);
464#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
465#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
466
645c62a5 467extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 468extern void intel_write_eld(struct drm_encoder *encoder,
469 struct drm_display_mode *mode);
d4270e57 470extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 471extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 472extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 473extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 474
b840d907 475/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 476extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 477extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
478 uint32_t sprite_width,
479 int pixel_size);
1f8eeabf
ED		 480extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
481 struct drm_display_mode *mode);
8ea30864
JB		 482
483extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
484 struct drm_file *file_priv);
485extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
486 struct drm_file *file_priv);
487
57f350b6
JB		 488extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
489
85208be0 490/* Power-related functions, located in intel_pm.c */
1fa61106 491extern void intel_init_pm(struct drm_device *dev);
85208be0 492/* FBC */
85208be0
ED		 493extern bool intel_fbc_enabled(struct drm_device *dev);
494extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
495extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 496/* IPS */
497extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
498extern void intel_gpu_ips_teardown(void);
85208be0 499
0232e927 500extern void intel_init_power_wells(struct drm_device *dev);
8090c6b9
DV		 501extern void intel_enable_gt_powersave(struct drm_device *dev);
502extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 503extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 504extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 505
72662e10
ED		 506extern void intel_ddi_dpms(struct drm_encoder *encoder, int mode);
507extern void intel_ddi_mode_set(struct drm_encoder *encoder,
508 struct drm_display_mode *mode,
509 struct drm_display_mode *adjusted_mode);
510
79e53945 511#endif /* __INTEL_DRV_H__ */
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