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drm/i915/overlay: Workaround i830 overlay activation bug.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
8d74f656
CW		 173static struct overlay_registers *
174intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
175 int slot)
02e792fb
DV		 176{
177 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
178 struct overlay_registers *regs;
179
9bb2ff73 180 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
31578148 181 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 182 else
02e792fb 183 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
fca3ec01 184 overlay->reg_bo->gtt_offset,
8d74f656 185 slot);
02e792fb 186
9bb2ff73 187 return regs;
02e792fb
DV		 188}
189
8d74f656 190static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
9bb2ff73
CW		 191 int slot,
192 struct overlay_registers *regs)
02e792fb 193{
31578148 194 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 195 io_mapping_unmap_atomic(regs, slot);
8d74f656
CW		 196}
197
198static struct overlay_registers *
199intel_overlay_map_regs(struct intel_overlay *overlay)
200{
201 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
202 struct overlay_registers *regs;
203
9bb2ff73 204 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656 205 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 206 else
8d74f656
CW		 207 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
208 overlay->reg_bo->gtt_offset);
209
9bb2ff73 210 return regs;
8d74f656
CW		 211}
212
9bb2ff73
CW		 213static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
214 struct overlay_registers *regs)
8d74f656
CW		 215{
216 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 217 io_mapping_unmap(regs);
02e792fb
DV		 218}
219
b6c028e0 220static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
8dc5d147 221 struct drm_i915_gem_request *request,
b6c028e0
CW		 222 bool interruptible,
223 int stage)
02e792fb
DV		 224{
225 struct drm_device *dev = overlay->dev;
852835f3 226 drm_i915_private_t *dev_priv = dev->dev_private;
b6c028e0 227 int ret;
02e792fb 228
852835f3 229 overlay->last_flip_req =
8dc5d147 230 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
03f77ea5
DV		 231 if (overlay->last_flip_req == 0)
232 return -ENOMEM;
02e792fb 233
b6c028e0 234 overlay->hw_wedged = stage;
852835f3 235 ret = i915_do_wait_request(dev,
722506f0
CW		 236 overlay->last_flip_req, true,
237 &dev_priv->render_ring);
b6c028e0 238 if (ret)
03f77ea5 239 return ret;
02e792fb 240
03f77ea5
DV		 241 overlay->hw_wedged = 0;
242 overlay->last_flip_req = 0;
02e792fb
DV		 243 return 0;
244}
245
106dadac
CW		 246/* Workaround for i830 bug where pipe a must be enable to change control regs */
247static int
248i830_activate_pipe_a(struct drm_device *dev)
249{
250 drm_i915_private_t *dev_priv = dev->dev_private;
251 struct intel_crtc *crtc;
252 struct drm_crtc_helper_funcs *crtc_funcs;
253 struct drm_display_mode vesa_640x480 = {
254 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
255 752, 800, 0, 480, 489, 492, 525, 0,
256 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
257 }, *mode;
258
259 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
260 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
261 return 0;
262
263 /* most i8xx have pipe a forced on, so don't trust dpms mode */
264 if (I915_READ(PIPEACONF) & PIPEACONF_ENABLE)
265 return 0;
266
267 crtc_funcs = crtc->base.helper_private;
268 if (crtc_funcs->dpms == NULL)
269 return 0;
270
271 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
272
273 mode = drm_mode_duplicate(dev, &vesa_640x480);
274 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
275 if(!drm_crtc_helper_set_mode(&crtc->base, mode,
276 crtc->base.x, crtc->base.y,
277 crtc->base.fb))
278 return 0;
279
280 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
281 return 1;
282}
283
284static void
285i830_deactivate_pipe_a(struct drm_device *dev)
286{
287 drm_i915_private_t *dev_priv = dev->dev_private;
288 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
289 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
290
291 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
292}
293
b6c028e0
CW		 294/* overlay needs to be disable in OCMD reg */
295static int intel_overlay_on(struct intel_overlay *overlay)
296{
297 struct drm_device *dev = overlay->dev;
8dc5d147 298 struct drm_i915_gem_request *request;
106dadac
CW		 299 int pipe_a_quirk = 0;
300 int ret;
b6c028e0
CW		 301
302 BUG_ON(overlay->active);
b6c028e0
CW		 303 overlay->active = 1;
304
106dadac
CW		 305 if (IS_I830(dev)) {
306 pipe_a_quirk = i830_activate_pipe_a(dev);
307 if (pipe_a_quirk < 0)
308 return pipe_a_quirk;
309 }
310
8dc5d147 311 request = kzalloc(sizeof(*request), GFP_KERNEL);
106dadac
CW		 312 if (request == NULL) {
313 ret = -ENOMEM;
314 goto out;
315 }
8dc5d147 316
b6c028e0
CW		 317 BEGIN_LP_RING(4);
318 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
319 OUT_RING(overlay->flip_addr | OFC_UPDATE);
320 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
321 OUT_RING(MI_NOOP);
322 ADVANCE_LP_RING();
323
106dadac
CW		 324 ret = intel_overlay_do_wait_request(overlay, request, true,
325 NEEDS_WAIT_FOR_FLIP);
326out:
327 if (pipe_a_quirk)
328 i830_deactivate_pipe_a(dev);
329
330 return ret;
b6c028e0
CW		 331}
332
02e792fb 333/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 334static int intel_overlay_continue(struct intel_overlay *overlay,
335 bool load_polyphase_filter)
02e792fb
DV		 336{
337 struct drm_device *dev = overlay->dev;
338 drm_i915_private_t *dev_priv = dev->dev_private;
8dc5d147 339 struct drm_i915_gem_request *request;
02e792fb
DV		 340 u32 flip_addr = overlay->flip_addr;
341 u32 tmp;
02e792fb
DV		 342
343 BUG_ON(!overlay->active);
344
8dc5d147
CW		 345 request = kzalloc(sizeof(*request), GFP_KERNEL);
346 if (request == NULL)
347 return -ENOMEM;
348
02e792fb
DV		 349 if (load_polyphase_filter)
350 flip_addr |= OFC_UPDATE;
351
352 /* check for underruns */
353 tmp = I915_READ(DOVSTA);
354 if (tmp & (1 << 17))
355 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
356
4f8a567c 357 BEGIN_LP_RING(2);
02e792fb
DV		 358 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
359 OUT_RING(flip_addr);
5a5a0c64
DV		 360 ADVANCE_LP_RING();
361
852835f3 362 overlay->last_flip_req =
8dc5d147
CW		 363 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
364 return 0;
5a5a0c64
DV		 365}
366
02e792fb
DV		 367/* overlay needs to be disabled in OCMD reg */
368static int intel_overlay_off(struct intel_overlay *overlay)
369{
02e792fb 370 struct drm_device *dev = overlay->dev;
8dc5d147
CW		 371 u32 flip_addr = overlay->flip_addr;
372 struct drm_i915_gem_request *request;
02e792fb
DV		 373
374 BUG_ON(!overlay->active);
375
8dc5d147
CW		 376 request = kzalloc(sizeof(*request), GFP_KERNEL);
377 if (request == NULL)
378 return -ENOMEM;
379
02e792fb
DV		 380 /* According to intel docs the overlay hw may hang (when switching
381 * off) without loading the filter coeffs. It is however unclear whether
382 * this applies to the disabling of the overlay or to the switching off
383 * of the hw. Do it in both cases */
384 flip_addr |= OFC_UPDATE;
385
8dfbc340 386 BEGIN_LP_RING(6);
02e792fb 387 /* wait for overlay to go idle */
02e792fb
DV		 388 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
389 OUT_RING(flip_addr);
722506f0 390 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 391 /* turn overlay off */
722506f0 392 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 393 OUT_RING(flip_addr);
722506f0 394 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb
DV		 395 ADVANCE_LP_RING();
396
8dc5d147
CW		 397 return intel_overlay_do_wait_request(overlay, request, true,
398 SWITCH_OFF);
02e792fb
DV		 399}
400
5cd68c98
CW		 401static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
402{
403 struct drm_gem_object *obj = &overlay->old_vid_bo->base;
404
405 i915_gem_object_unpin(obj);
406 drm_gem_object_unreference(obj);
407
408 overlay->old_vid_bo = NULL;
409}
410
12ca45fe
DV		 411static void intel_overlay_off_tail(struct intel_overlay *overlay)
412{
413 struct drm_gem_object *obj;
414
415 /* never have the overlay hw on without showing a frame */
416 BUG_ON(!overlay->vid_bo);
a8089e84 417 obj = &overlay->vid_bo->base;
12ca45fe
DV		 418
419 i915_gem_object_unpin(obj);
420 drm_gem_object_unreference(obj);
421 overlay->vid_bo = NULL;
422
423 overlay->crtc->overlay = NULL;
424 overlay->crtc = NULL;
425 overlay->active = 0;
426}
427
03f77ea5
DV		 428/* recover from an interruption due to a signal
429 * We have to be careful not to repeat work forever an make forward progess. */
430int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
722506f0 431 bool interruptible)
03f77ea5
DV		 432{
433 struct drm_device *dev = overlay->dev;
852835f3 434 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5 435 int ret;
03f77ea5
DV		 436
437 if (overlay->hw_wedged == HW_WEDGED)
438 return -EIO;
439
852835f3 440 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 441 interruptible, &dev_priv->render_ring);
b6c028e0 442 if (ret)
03f77ea5
DV		 443 return ret;
444
445 switch (overlay->hw_wedged) {
722506f0 446 case RELEASE_OLD_VID:
5cd68c98 447 intel_overlay_release_old_vid_tail(overlay);
722506f0 448 break;
b6c028e0 449
8dfbc340 450 case SWITCH_OFF:
722506f0
CW		 451 intel_overlay_off_tail(overlay);
452 break;
8dfbc340 453
722506f0
CW		 454 default:
455 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
03f77ea5
DV		 456 }
457
458 overlay->hw_wedged = 0;
459 overlay->last_flip_req = 0;
460 return 0;
461}
462
5a5a0c64
DV		 463/* Wait for pending overlay flip and release old frame.
464 * Needs to be called before the overlay register are changed
8d74f656
CW		 465 * via intel_overlay_(un)map_regs
466 */
02e792fb
DV		 467static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
468{
5cd68c98
CW		 469 struct drm_device *dev = overlay->dev;
470 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 471 int ret;
02e792fb 472
5cd68c98
CW		 473 /* Only wait if there is actually an old frame to release to
474 * guarantee forward progress.
475 */
03f77ea5
DV		 476 if (!overlay->old_vid_bo)
477 return 0;
478
5cd68c98 479 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
8dc5d147
CW		 480 struct drm_i915_gem_request *request;
481
5cd68c98 482 /* synchronous slowpath */
8dc5d147
CW		 483 request = kzalloc(sizeof(*request), GFP_KERNEL);
484 if (request == NULL)
485 return -ENOMEM;
486
5cd68c98
CW		 487 BEGIN_LP_RING(2);
488 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
489 OUT_RING(MI_NOOP);
490 ADVANCE_LP_RING();
491
8dc5d147 492 ret = intel_overlay_do_wait_request(overlay, request, true,
5cd68c98
CW		 493 RELEASE_OLD_VID);
494 if (ret)
495 return ret;
496 }
02e792fb 497
5cd68c98 498 intel_overlay_release_old_vid_tail(overlay);
02e792fb
DV		 499 return 0;
500}
501
502struct put_image_params {
503 int format;
504 short dst_x;
505 short dst_y;
506 short dst_w;
507 short dst_h;
508 short src_w;
509 short src_scan_h;
510 short src_scan_w;
511 short src_h;
512 short stride_Y;
513 short stride_UV;
514 int offset_Y;
515 int offset_U;
516 int offset_V;
517};
518
519static int packed_depth_bytes(u32 format)
520{
521 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 522 case I915_OVERLAY_YUV422:
523 return 4;
524 case I915_OVERLAY_YUV411:
525 /* return 6; not implemented */
526 default:
527 return -EINVAL;
02e792fb
DV		 528 }
529}
530
531static int packed_width_bytes(u32 format, short width)
532{
533 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 534 case I915_OVERLAY_YUV422:
535 return width << 1;
536 default:
537 return -EINVAL;
02e792fb
DV		 538 }
539}
540
541static int uv_hsubsampling(u32 format)
542{
543 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 544 case I915_OVERLAY_YUV422:
545 case I915_OVERLAY_YUV420:
546 return 2;
547 case I915_OVERLAY_YUV411:
548 case I915_OVERLAY_YUV410:
549 return 4;
550 default:
551 return -EINVAL;
02e792fb
DV		 552 }
553}
554
555static int uv_vsubsampling(u32 format)
556{
557 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 558 case I915_OVERLAY_YUV420:
559 case I915_OVERLAY_YUV410:
560 return 2;
561 case I915_OVERLAY_YUV422:
562 case I915_OVERLAY_YUV411:
563 return 1;
564 default:
565 return -EINVAL;
02e792fb
DV		 566 }
567}
568
569static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
570{
571 u32 mask, shift, ret;
572 if (IS_I9XX(dev)) {
573 mask = 0x3f;
574 shift = 6;
575 } else {
576 mask = 0x1f;
577 shift = 5;
578 }
579 ret = ((offset + width + mask) >> shift) - (offset >> shift);
580 if (IS_I9XX(dev))
581 ret <<= 1;
582 ret -=1;
583 return ret << 2;
584}
585
586static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
587 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
588 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
589 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
590 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
591 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
592 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
593 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
594 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
595 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
596 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
597 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
598 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
599 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
600 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
601 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
602 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 603 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
604};
605
02e792fb
DV		 606static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
607 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
608 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
609 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
610 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
611 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
612 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
613 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
614 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 615 0x3000, 0x0800, 0x3000
616};
02e792fb
DV		 617
618static void update_polyphase_filter(struct overlay_registers *regs)
619{
620 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
621 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
622}
623
624static bool update_scaling_factors(struct intel_overlay *overlay,
625 struct overlay_registers *regs,
626 struct put_image_params *params)
627{
628 /* fixed point with a 12 bit shift */
629 u32 xscale, yscale, xscale_UV, yscale_UV;
630#define FP_SHIFT 12
631#define FRACT_MASK 0xfff
632 bool scale_changed = false;
633 int uv_hscale = uv_hsubsampling(params->format);
634 int uv_vscale = uv_vsubsampling(params->format);
635
636 if (params->dst_w > 1)
637 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
638 /(params->dst_w);
639 else
640 xscale = 1 << FP_SHIFT;
641
642 if (params->dst_h > 1)
643 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
644 /(params->dst_h);
645 else
646 yscale = 1 << FP_SHIFT;
647
648 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 649 xscale_UV = xscale/uv_hscale;
650 yscale_UV = yscale/uv_vscale;
651 /* make the Y scale to UV scale ratio an exact multiply */
652 xscale = xscale_UV * uv_hscale;
653 yscale = yscale_UV * uv_vscale;
02e792fb 654 /*} else {
722506f0
CW		 655 xscale_UV = 0;
656 yscale_UV = 0;
657 }*/
02e792fb
DV		 658
659 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
660 scale_changed = true;
661 overlay->old_xscale = xscale;
662 overlay->old_yscale = yscale;
663
722506f0
CW		 664 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
665 ((xscale >> FP_SHIFT) << 16) |
666 ((xscale & FRACT_MASK) << 3));
667
668 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
669 ((xscale_UV >> FP_SHIFT) << 16) |
670 ((xscale_UV & FRACT_MASK) << 3));
671
672 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
673 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 674
675 if (scale_changed)
676 update_polyphase_filter(regs);
677
678 return scale_changed;
679}
680
681static void update_colorkey(struct intel_overlay *overlay,
682 struct overlay_registers *regs)
683{
684 u32 key = overlay->color_key;
6ba3ddd9 685
02e792fb 686 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 687 case 8:
688 regs->DCLRKV = 0;
689 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 690 break;
691
722506f0
CW		 692 case 16:
693 if (overlay->crtc->base.fb->depth == 15) {
694 regs->DCLRKV = RGB15_TO_COLORKEY(key);
695 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
696 } else {
697 regs->DCLRKV = RGB16_TO_COLORKEY(key);
698 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
699 }
6ba3ddd9
CW		 700 break;
701
722506f0
CW		 702 case 24:
703 case 32:
704 regs->DCLRKV = key;
705 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 706 break;
02e792fb
DV		 707 }
708}
709
710static u32 overlay_cmd_reg(struct put_image_params *params)
711{
712 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
713
714 if (params->format & I915_OVERLAY_YUV_PLANAR) {
715 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 716 case I915_OVERLAY_YUV422:
717 cmd |= OCMD_YUV_422_PLANAR;
718 break;
719 case I915_OVERLAY_YUV420:
720 cmd |= OCMD_YUV_420_PLANAR;
721 break;
722 case I915_OVERLAY_YUV411:
723 case I915_OVERLAY_YUV410:
724 cmd |= OCMD_YUV_410_PLANAR;
725 break;
02e792fb
DV		 726 }
727 } else { /* YUV packed */
728 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 729 case I915_OVERLAY_YUV422:
730 cmd |= OCMD_YUV_422_PACKED;
731 break;
732 case I915_OVERLAY_YUV411:
733 cmd |= OCMD_YUV_411_PACKED;
734 break;
02e792fb
DV		 735 }
736
737 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 738 case I915_OVERLAY_NO_SWAP:
739 break;
740 case I915_OVERLAY_UV_SWAP:
741 cmd |= OCMD_UV_SWAP;
742 break;
743 case I915_OVERLAY_Y_SWAP:
744 cmd |= OCMD_Y_SWAP;
745 break;
746 case I915_OVERLAY_Y_AND_UV_SWAP:
747 cmd |= OCMD_Y_AND_UV_SWAP;
748 break;
02e792fb
DV		 749 }
750 }
751
752 return cmd;
753}
754
5fe82c5e
CW		 755static int intel_overlay_do_put_image(struct intel_overlay *overlay,
756 struct drm_gem_object *new_bo,
757 struct put_image_params *params)
02e792fb
DV		 758{
759 int ret, tmp_width;
760 struct overlay_registers *regs;
761 bool scale_changed = false;
23010e43 762 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 763 struct drm_device *dev = overlay->dev;
764
765 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
766 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
767 BUG_ON(!overlay);
768
02e792fb
DV		 769 ret = intel_overlay_release_old_vid(overlay);
770 if (ret != 0)
771 return ret;
772
773 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
774 if (ret != 0)
775 return ret;
776
777 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
778 if (ret != 0)
779 goto out_unpin;
780
781 if (!overlay->active) {
8d74f656 782 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 783 if (!regs) {
784 ret = -ENOMEM;
785 goto out_unpin;
786 }
787 regs->OCONFIG = OCONF_CC_OUT_8BIT;
788 if (IS_I965GM(overlay->dev))
789 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
790 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
791 OCONF_PIPE_A : OCONF_PIPE_B;
9bb2ff73 792 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 793
794 ret = intel_overlay_on(overlay);
795 if (ret != 0)
796 goto out_unpin;
797 }
798
8d74f656 799 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 800 if (!regs) {
801 ret = -ENOMEM;
802 goto out_unpin;
803 }
804
805 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
806 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
807
808 if (params->format & I915_OVERLAY_YUV_PACKED)
809 tmp_width = packed_width_bytes(params->format, params->src_w);
810 else
811 tmp_width = params->src_w;
812
813 regs->SWIDTH = params->src_w;
814 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 815 params->offset_Y, tmp_width);
02e792fb
DV		 816 regs->SHEIGHT = params->src_h;
817 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
818 regs->OSTRIDE = params->stride_Y;
819
820 if (params->format & I915_OVERLAY_YUV_PLANAR) {
821 int uv_hscale = uv_hsubsampling(params->format);
822 int uv_vscale = uv_vsubsampling(params->format);
823 u32 tmp_U, tmp_V;
824 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
825 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 826 params->src_w/uv_hscale);
02e792fb 827 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 828 params->src_w/uv_hscale);
02e792fb
DV		 829 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
830 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
831 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
832 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
833 regs->OSTRIDE |= params->stride_UV << 16;
834 }
835
836 scale_changed = update_scaling_factors(overlay, regs, params);
837
838 update_colorkey(overlay, regs);
839
840 regs->OCMD = overlay_cmd_reg(params);
841
9bb2ff73 842 intel_overlay_unmap_regs(overlay, regs);
02e792fb 843
8dc5d147
CW		 844 ret = intel_overlay_continue(overlay, scale_changed);
845 if (ret)
846 goto out_unpin;
02e792fb
DV		 847
848 overlay->old_vid_bo = overlay->vid_bo;
23010e43 849 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 850
851 return 0;
852
853out_unpin:
854 i915_gem_object_unpin(new_bo);
855 return ret;
856}
857
858int intel_overlay_switch_off(struct intel_overlay *overlay)
859{
860 int ret;
861 struct overlay_registers *regs;
02e792fb
DV		 862 struct drm_device *dev = overlay->dev;
863
864 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
865 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
866
9bedb974
DV		 867 if (overlay->hw_wedged) {
868 ret = intel_overlay_recover_from_interrupt(overlay, 1);
869 if (ret != 0)
870 return ret;
871 }
872
02e792fb
DV		 873 if (!overlay->active)
874 return 0;
875
02e792fb
DV		 876 ret = intel_overlay_release_old_vid(overlay);
877 if (ret != 0)
878 return ret;
879
8d74f656 880 regs = intel_overlay_map_regs(overlay);
02e792fb 881 regs->OCMD = 0;
9bb2ff73 882 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 883
884 ret = intel_overlay_off(overlay);
03f77ea5
DV		 885 if (ret != 0)
886 return ret;
887
12ca45fe 888 intel_overlay_off_tail(overlay);
02e792fb
DV		 889
890 return 0;
891}
892
893static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
894 struct intel_crtc *crtc)
895{
722506f0 896 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb
DV		 897 u32 pipeconf;
898 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
899
900 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
901 return -EINVAL;
902
903 pipeconf = I915_READ(pipeconf_reg);
904
905 /* can't use the overlay with double wide pipe */
906 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
907 return -EINVAL;
908
909 return 0;
910}
911
912static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
913{
914 struct drm_device *dev = overlay->dev;
722506f0 915 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 916 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 917 u32 ratio;
02e792fb
DV		 918
919 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 920 * line with the intel documentation for the i965
921 */
922 if (!IS_I965G(dev)) {
923 if (pfit_control & VERT_AUTO_SCALE)
924 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 925 else
446d2183
CW		 926 ratio = I915_READ(PFIT_PGM_RATIOS);
927 ratio >>= PFIT_VERT_SCALE_SHIFT;
928 } else { /* on i965 use the PGM reg to read out the autoscaler values */
929 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
02e792fb
DV		 930 }
931
932 overlay->pfit_vscale_ratio = ratio;
933}
934
935static int check_overlay_dst(struct intel_overlay *overlay,
936 struct drm_intel_overlay_put_image *rec)
937{
938 struct drm_display_mode *mode = &overlay->crtc->base.mode;
939
722506f0
CW		 940 if (rec->dst_x < mode->crtc_hdisplay &&
941 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
942 rec->dst_y < mode->crtc_vdisplay &&
943 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 944 return 0;
945 else
946 return -EINVAL;
947}
948
949static int check_overlay_scaling(struct put_image_params *rec)
950{
951 u32 tmp;
952
953 /* downscaling limit is 8.0 */
954 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
955 if (tmp > 7)
956 return -EINVAL;
957 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
958 if (tmp > 7)
959 return -EINVAL;
960
961 return 0;
962}
963
964static int check_overlay_src(struct drm_device *dev,
965 struct drm_intel_overlay_put_image *rec,
966 struct drm_gem_object *new_bo)
967{
02e792fb
DV		 968 int uv_hscale = uv_hsubsampling(rec->flags);
969 int uv_vscale = uv_vsubsampling(rec->flags);
9f7c3f44 970 u32 stride_mask, depth, tmp;
02e792fb
DV		 971
972 /* check src dimensions */
973 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 974 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 975 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 976 return -EINVAL;
977 } else {
722506f0 978 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 979 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 980 return -EINVAL;
981 }
9f7c3f44 982
02e792fb 983 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 984 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 985 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 986 return -EINVAL;
987
a1efd14a 988 /* check alignment constraints */
02e792fb 989 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 990 case I915_OVERLAY_RGB:
991 /* not implemented */
992 return -EINVAL;
9f7c3f44 993
722506f0 994 case I915_OVERLAY_YUV_PACKED:
722506f0 995 if (uv_vscale != 1)
02e792fb 996 return -EINVAL;
9f7c3f44
CW		 997
998 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 999 if (depth < 0)
1000 return depth;
9f7c3f44 1001
722506f0
CW		 1002 /* ignore UV planes */
1003 rec->stride_UV = 0;
1004 rec->offset_U = 0;
1005 rec->offset_V = 0;
1006 /* check pixel alignment */
1007 if (rec->offset_Y % depth)
1008 return -EINVAL;
1009 break;
9f7c3f44 1010
722506f0
CW		 1011 case I915_OVERLAY_YUV_PLANAR:
1012 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 1013 return -EINVAL;
722506f0
CW		 1014 /* no offset restrictions for planar formats */
1015 break;
9f7c3f44 1016
722506f0
CW		 1017 default:
1018 return -EINVAL;
02e792fb
DV		 1019 }
1020
1021 if (rec->src_width % uv_hscale)
1022 return -EINVAL;
1023
1024 /* stride checking */
a1efd14a
CW		 1025 if (IS_I830(dev) || IS_845G(dev))
1026 stride_mask = 255;
1027 else
1028 stride_mask = 63;
02e792fb
DV		 1029
1030 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1031 return -EINVAL;
1032 if (IS_I965G(dev) && rec->stride_Y < 512)
1033 return -EINVAL;
1034
1035 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 1036 4096 : 8192;
1037 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 1038 return -EINVAL;
1039
1040 /* check buffer dimensions */
1041 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1042 case I915_OVERLAY_RGB:
1043 case I915_OVERLAY_YUV_PACKED:
1044 /* always 4 Y values per depth pixels */
1045 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1046 return -EINVAL;
1047
1048 tmp = rec->stride_Y*rec->src_height;
1049 if (rec->offset_Y + tmp > new_bo->size)
1050 return -EINVAL;
1051 break;
1052
1053 case I915_OVERLAY_YUV_PLANAR:
1054 if (rec->src_width > rec->stride_Y)
1055 return -EINVAL;
1056 if (rec->src_width/uv_hscale > rec->stride_UV)
1057 return -EINVAL;
1058
9f7c3f44 1059 tmp = rec->stride_Y * rec->src_height;
722506f0
CW		 1060 if (rec->offset_Y + tmp > new_bo->size)
1061 return -EINVAL;
9f7c3f44
CW		 1062
1063 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
722506f0
CW		 1064 if (rec->offset_U + tmp > new_bo->size ||
1065 rec->offset_V + tmp > new_bo->size)
1066 return -EINVAL;
1067 break;
02e792fb
DV		 1068 }
1069
1070 return 0;
1071}
1072
1073int intel_overlay_put_image(struct drm_device *dev, void *data,
1074 struct drm_file *file_priv)
1075{
1076 struct drm_intel_overlay_put_image *put_image_rec = data;
1077 drm_i915_private_t *dev_priv = dev->dev_private;
1078 struct intel_overlay *overlay;
1079 struct drm_mode_object *drmmode_obj;
1080 struct intel_crtc *crtc;
1081 struct drm_gem_object *new_bo;
1082 struct put_image_params *params;
1083 int ret;
1084
1085 if (!dev_priv) {
1086 DRM_ERROR("called with no initialization\n");
1087 return -EINVAL;
1088 }
1089
1090 overlay = dev_priv->overlay;
1091 if (!overlay) {
1092 DRM_DEBUG("userspace bug: no overlay\n");
1093 return -ENODEV;
1094 }
1095
1096 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1097 mutex_lock(&dev->mode_config.mutex);
1098 mutex_lock(&dev->struct_mutex);
1099
1100 ret = intel_overlay_switch_off(overlay);
1101
1102 mutex_unlock(&dev->struct_mutex);
1103 mutex_unlock(&dev->mode_config.mutex);
1104
1105 return ret;
1106 }
1107
1108 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1109 if (!params)
1110 return -ENOMEM;
1111
1112 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1113 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1114 if (!drmmode_obj) {
1115 ret = -ENOENT;
1116 goto out_free;
1117 }
02e792fb
DV		 1118 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1119
1120 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1121 put_image_rec->bo_handle);
915a428e
DC		 1122 if (!new_bo) {
1123 ret = -ENOENT;
1124 goto out_free;
1125 }
02e792fb
DV		 1126
1127 mutex_lock(&dev->mode_config.mutex);
1128 mutex_lock(&dev->struct_mutex);
1129
03f77ea5
DV		 1130 if (overlay->hw_wedged) {
1131 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1132 if (ret != 0)
1133 goto out_unlock;
1134 }
1135
02e792fb
DV		 1136 if (overlay->crtc != crtc) {
1137 struct drm_display_mode *mode = &crtc->base.mode;
1138 ret = intel_overlay_switch_off(overlay);
1139 if (ret != 0)
1140 goto out_unlock;
1141
1142 ret = check_overlay_possible_on_crtc(overlay, crtc);
1143 if (ret != 0)
1144 goto out_unlock;
1145
1146 overlay->crtc = crtc;
1147 crtc->overlay = overlay;
1148
1149 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1150 /* and line to wide, i.e. one-line-mode */
1151 && mode->hdisplay > 1024) {
1152 overlay->pfit_active = 1;
1153 update_pfit_vscale_ratio(overlay);
1154 } else
1155 overlay->pfit_active = 0;
1156 }
1157
1158 ret = check_overlay_dst(overlay, put_image_rec);
1159 if (ret != 0)
1160 goto out_unlock;
1161
1162 if (overlay->pfit_active) {
1163 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1164 overlay->pfit_vscale_ratio);
02e792fb
DV		 1165 /* shifting right rounds downwards, so add 1 */
1166 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1167 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1168 } else {
1169 params->dst_y = put_image_rec->dst_y;
1170 params->dst_h = put_image_rec->dst_height;
1171 }
1172 params->dst_x = put_image_rec->dst_x;
1173 params->dst_w = put_image_rec->dst_width;
1174
1175 params->src_w = put_image_rec->src_width;
1176 params->src_h = put_image_rec->src_height;
1177 params->src_scan_w = put_image_rec->src_scan_width;
1178 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1179 if (params->src_scan_h > params->src_h ||
1180 params->src_scan_w > params->src_w) {
02e792fb
DV		 1181 ret = -EINVAL;
1182 goto out_unlock;
1183 }
1184
1185 ret = check_overlay_src(dev, put_image_rec, new_bo);
1186 if (ret != 0)
1187 goto out_unlock;
1188 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1189 params->stride_Y = put_image_rec->stride_Y;
1190 params->stride_UV = put_image_rec->stride_UV;
1191 params->offset_Y = put_image_rec->offset_Y;
1192 params->offset_U = put_image_rec->offset_U;
1193 params->offset_V = put_image_rec->offset_V;
1194
1195 /* Check scaling after src size to prevent a divide-by-zero. */
1196 ret = check_overlay_scaling(params);
1197 if (ret != 0)
1198 goto out_unlock;
1199
1200 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1201 if (ret != 0)
1202 goto out_unlock;
1203
1204 mutex_unlock(&dev->struct_mutex);
1205 mutex_unlock(&dev->mode_config.mutex);
1206
1207 kfree(params);
1208
1209 return 0;
1210
1211out_unlock:
1212 mutex_unlock(&dev->struct_mutex);
1213 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1214 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1215out_free:
02e792fb
DV		 1216 kfree(params);
1217
1218 return ret;
1219}
1220
1221static void update_reg_attrs(struct intel_overlay *overlay,
1222 struct overlay_registers *regs)
1223{
1224 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1225 regs->OCLRC1 = overlay->saturation;
1226}
1227
1228static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1229{
1230 int i;
1231
1232 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1233 return false;
1234
1235 for (i = 0; i < 3; i++) {
722506f0 1236 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1237 return false;
1238 }
1239
1240 return true;
1241}
1242
1243static bool check_gamma5_errata(u32 gamma5)
1244{
1245 int i;
1246
1247 for (i = 0; i < 3; i++) {
1248 if (((gamma5 >> i*8) & 0xff) == 0x80)
1249 return false;
1250 }
1251
1252 return true;
1253}
1254
1255static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1256{
722506f0
CW		 1257 if (!check_gamma_bounds(0, attrs->gamma0) ||
1258 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1259 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1260 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1261 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1262 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1263 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1264 return -EINVAL;
722506f0 1265
02e792fb
DV		 1266 if (!check_gamma5_errata(attrs->gamma5))
1267 return -EINVAL;
722506f0 1268
02e792fb
DV		 1269 return 0;
1270}
1271
1272int intel_overlay_attrs(struct drm_device *dev, void *data,
1273 struct drm_file *file_priv)
1274{
1275 struct drm_intel_overlay_attrs *attrs = data;
1276 drm_i915_private_t *dev_priv = dev->dev_private;
1277 struct intel_overlay *overlay;
1278 struct overlay_registers *regs;
1279 int ret;
1280
1281 if (!dev_priv) {
1282 DRM_ERROR("called with no initialization\n");
1283 return -EINVAL;
1284 }
1285
1286 overlay = dev_priv->overlay;
1287 if (!overlay) {
1288 DRM_DEBUG("userspace bug: no overlay\n");
1289 return -ENODEV;
1290 }
1291
1292 mutex_lock(&dev->mode_config.mutex);
1293 mutex_lock(&dev->struct_mutex);
1294
60fc332c 1295 ret = -EINVAL;
02e792fb 1296 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1297 attrs->color_key = overlay->color_key;
02e792fb 1298 attrs->brightness = overlay->brightness;
60fc332c 1299 attrs->contrast = overlay->contrast;
02e792fb
DV		 1300 attrs->saturation = overlay->saturation;
1301
1302 if (IS_I9XX(dev)) {
1303 attrs->gamma0 = I915_READ(OGAMC0);
1304 attrs->gamma1 = I915_READ(OGAMC1);
1305 attrs->gamma2 = I915_READ(OGAMC2);
1306 attrs->gamma3 = I915_READ(OGAMC3);
1307 attrs->gamma4 = I915_READ(OGAMC4);
1308 attrs->gamma5 = I915_READ(OGAMC5);
1309 }
02e792fb 1310 } else {
60fc332c 1311 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1312 goto out_unlock;
60fc332c 1313 if (attrs->contrast > 255)
02e792fb 1314 goto out_unlock;
60fc332c 1315 if (attrs->saturation > 1023)
02e792fb 1316 goto out_unlock;
60fc332c
CW		 1317
1318 overlay->color_key = attrs->color_key;
1319 overlay->brightness = attrs->brightness;
1320 overlay->contrast = attrs->contrast;
1321 overlay->saturation = attrs->saturation;
02e792fb 1322
8d74f656 1323 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1324 if (!regs) {
1325 ret = -ENOMEM;
1326 goto out_unlock;
1327 }
1328
1329 update_reg_attrs(overlay, regs);
1330
9bb2ff73 1331 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1332
1333 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
60fc332c 1334 if (!IS_I9XX(dev))
02e792fb 1335 goto out_unlock;
02e792fb
DV		 1336
1337 if (overlay->active) {
1338 ret = -EBUSY;
1339 goto out_unlock;
1340 }
1341
1342 ret = check_gamma(attrs);
60fc332c 1343 if (ret)
02e792fb
DV		 1344 goto out_unlock;
1345
1346 I915_WRITE(OGAMC0, attrs->gamma0);
1347 I915_WRITE(OGAMC1, attrs->gamma1);
1348 I915_WRITE(OGAMC2, attrs->gamma2);
1349 I915_WRITE(OGAMC3, attrs->gamma3);
1350 I915_WRITE(OGAMC4, attrs->gamma4);
1351 I915_WRITE(OGAMC5, attrs->gamma5);
1352 }
02e792fb
DV		 1353 }
1354
60fc332c 1355 ret = 0;
02e792fb
DV		 1356out_unlock:
1357 mutex_unlock(&dev->struct_mutex);
1358 mutex_unlock(&dev->mode_config.mutex);
1359
1360 return ret;
1361}
1362
1363void intel_setup_overlay(struct drm_device *dev)
1364{
1365 drm_i915_private_t *dev_priv = dev->dev_private;
1366 struct intel_overlay *overlay;
1367 struct drm_gem_object *reg_bo;
1368 struct overlay_registers *regs;
1369 int ret;
1370
31578148 1371 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1372 return;
1373
1374 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1375 if (!overlay)
1376 return;
1377 overlay->dev = dev;
1378
ac52bc56 1379 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1380 if (!reg_bo)
1381 goto out_free;
23010e43 1382 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1383
31578148
CW		 1384 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1385 ret = i915_gem_attach_phys_object(dev, reg_bo,
1386 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1387 PAGE_SIZE);
31578148
CW		 1388 if (ret) {
1389 DRM_ERROR("failed to attach phys overlay regs\n");
1390 goto out_free_bo;
1391 }
1392 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1393 } else {
02e792fb
DV		 1394 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1395 if (ret) {
1396 DRM_ERROR("failed to pin overlay register bo\n");
1397 goto out_free_bo;
1398 }
1399 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1400
1401 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1402 if (ret) {
1403 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1404 goto out_unpin_bo;
1405 }
02e792fb
DV		 1406 }
1407
1408 /* init all values */
1409 overlay->color_key = 0x0101fe;
1410 overlay->brightness = -19;
1411 overlay->contrast = 75;
1412 overlay->saturation = 146;
1413
8d74f656 1414 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1415 if (!regs)
1416 goto out_free_bo;
1417
1418 memset(regs, 0, sizeof(struct overlay_registers));
1419 update_polyphase_filter(regs);
02e792fb
DV		 1420 update_reg_attrs(overlay, regs);
1421
9bb2ff73 1422 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1423
1424 dev_priv->overlay = overlay;
1425 DRM_INFO("initialized overlay support\n");
1426 return;
1427
0ddc1289
CW		 1428out_unpin_bo:
1429 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1430out_free_bo:
1431 drm_gem_object_unreference(reg_bo);
1432out_free:
1433 kfree(overlay);
1434 return;
1435}
1436
1437void intel_cleanup_overlay(struct drm_device *dev)
1438{
722506f0 1439 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1440
62cf4e6f
CW		 1441 if (!dev_priv->overlay)
1442 return;
02e792fb 1443
62cf4e6f
CW		 1444 /* The bo's should be free'd by the generic code already.
1445 * Furthermore modesetting teardown happens beforehand so the
1446 * hardware should be off already */
1447 BUG_ON(dev_priv->overlay->active);
1448
1449 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1450 kfree(dev_priv->overlay);
02e792fb 1451}
6ef3d427
CW		 1452
1453struct intel_overlay_error_state {
1454 struct overlay_registers regs;
1455 unsigned long base;
1456 u32 dovsta;
1457 u32 isr;
1458};
1459
1460struct intel_overlay_error_state *
1461intel_overlay_capture_error_state(struct drm_device *dev)
1462{
1463 drm_i915_private_t *dev_priv = dev->dev_private;
1464 struct intel_overlay *overlay = dev_priv->overlay;
1465 struct intel_overlay_error_state *error;
1466 struct overlay_registers __iomem *regs;
1467
1468 if (!overlay || !overlay->active)
1469 return NULL;
1470
1471 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1472 if (error == NULL)
1473 return NULL;
1474
1475 error->dovsta = I915_READ(DOVSTA);
1476 error->isr = I915_READ(ISR);
31578148 1477 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1478 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1479 else
1480 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427 1481
8d74f656 1482 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1483 if (!regs)
1484 goto err;
1485
1486 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
9bb2ff73 1487 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0, regs);
6ef3d427
CW		 1488
1489 return error;
1490
1491err:
1492 kfree(error);
1493 return NULL;
1494}
1495
1496void
1497intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1498{
1499 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1500 error->dovsta, error->isr);
1501 seq_printf(m, " Register file at 0x%08lx:\n",
1502 error->base);
1503
1504#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1505 P(OBUF_0Y);
1506 P(OBUF_1Y);
1507 P(OBUF_0U);
1508 P(OBUF_0V);
1509 P(OBUF_1U);
1510 P(OBUF_1V);
1511 P(OSTRIDE);
1512 P(YRGB_VPH);
1513 P(UV_VPH);
1514 P(HORZ_PH);
1515 P(INIT_PHS);
1516 P(DWINPOS);
1517 P(DWINSZ);
1518 P(SWIDTH);
1519 P(SWIDTHSW);
1520 P(SHEIGHT);
1521 P(YRGBSCALE);
1522 P(UVSCALE);
1523 P(OCLRC0);
1524 P(OCLRC1);
1525 P(DCLRKV);
1526 P(DCLRKM);
1527 P(SCLRKVH);
1528 P(SCLRKVL);
1529 P(SCLRKEN);
1530 P(OCONFIG);
1531 P(OCMD);
1532 P(OSTART_0Y);
1533 P(OSTART_1Y);
1534 P(OSTART_0U);
1535 P(OSTART_0V);
1536 P(OSTART_1U);
1537 P(OSTART_1V);
1538 P(OTILEOFF_0Y);
1539 P(OTILEOFF_1Y);
1540 P(OTILEOFF_0U);
1541 P(OTILEOFF_0V);
1542 P(OTILEOFF_1U);
1543 P(OTILEOFF_1V);
1544 P(FASTHSCALE);
1545 P(UVSCALEV);
1546#undef P
1547}
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