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KVM: VMX: Use vmx to inject real-mode interrupts
[mirror_ubuntu-bionic-kernel.git] / drivers / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18#include "kvm.h"
34c16eec 19#include "x86.h"
e7d5d76c 20#include "x86_emulate.h"
85f455f7 21#include "irq.h"
6aa8b732 22#include "vmx.h"
e495606d
AK		 23#include "segment_descriptor.h"
24
6aa8b732 25#include <linux/module.h>
9d8f549d 26#include <linux/kernel.h>
6aa8b732
AK		 27#include <linux/mm.h>
28#include <linux/highmem.h>
e8edc6e0 29#include <linux/sched.h>
c7addb90 30#include <linux/moduleparam.h>
e495606d 31
6aa8b732 32#include <asm/io.h>
3b3be0d1 33#include <asm/desc.h>
6aa8b732 34
6aa8b732
AK		 35MODULE_AUTHOR("Qumranet");
36MODULE_LICENSE("GPL");
37
c7addb90
AK		 38static int bypass_guest_pf = 1;
39module_param(bypass_guest_pf, bool, 0);
40
a2fa3e9f
GH		 41struct vmcs {
42 u32 revision_id;
43 u32 abort;
44 char data[0];
45};
46
47struct vcpu_vmx {
fb3f0f51 48 struct kvm_vcpu vcpu;
a2fa3e9f 49 int launched;
29bd8a78 50 u8 fail;
a2fa3e9f
GH		 51 struct kvm_msr_entry *guest_msrs;
52 struct kvm_msr_entry *host_msrs;
53 int nmsrs;
54 int save_nmsrs;
55 int msr_offset_efer;
56#ifdef CONFIG_X86_64
57 int msr_offset_kernel_gs_base;
58#endif
59 struct vmcs *vmcs;
60 struct {
61 int loaded;
62 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 63 int gs_ldt_reload_needed;
64 int fs_reload_needed;
51c6cf66 65 int guest_efer_loaded;
d77c26fc 66 } host_state;
a2fa3e9f
GH		 67
68};
69
70static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
71{
fb3f0f51 72 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 73}
74
75880a01
AK		 75static int init_rmode_tss(struct kvm *kvm);
76
6aa8b732
AK		 77static DEFINE_PER_CPU(struct vmcs *, vmxarea);
78static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
79
fdef3ad1
HQ		 80static struct page *vmx_io_bitmap_a;
81static struct page *vmx_io_bitmap_b;
82
1c3d14fe 83static struct vmcs_config {
6aa8b732
AK		 84 int size;
85 int order;
86 u32 revision_id;
1c3d14fe
YS		 87 u32 pin_based_exec_ctrl;
88 u32 cpu_based_exec_ctrl;
f78e0e2e 89 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 90 u32 vmexit_ctrl;
91 u32 vmentry_ctrl;
92} vmcs_config;
6aa8b732
AK		 93
94#define VMX_SEGMENT_FIELD(seg) \
95 [VCPU_SREG_##seg] = { \
96 .selector = GUEST_##seg##_SELECTOR, \
97 .base = GUEST_##seg##_BASE, \
98 .limit = GUEST_##seg##_LIMIT, \
99 .ar_bytes = GUEST_##seg##_AR_BYTES, \
100 }
101
102static struct kvm_vmx_segment_field {
103 unsigned selector;
104 unsigned base;
105 unsigned limit;
106 unsigned ar_bytes;
107} kvm_vmx_segment_fields[] = {
108 VMX_SEGMENT_FIELD(CS),
109 VMX_SEGMENT_FIELD(DS),
110 VMX_SEGMENT_FIELD(ES),
111 VMX_SEGMENT_FIELD(FS),
112 VMX_SEGMENT_FIELD(GS),
113 VMX_SEGMENT_FIELD(SS),
114 VMX_SEGMENT_FIELD(TR),
115 VMX_SEGMENT_FIELD(LDTR),
116};
117
4d56c8a7
AK		 118/*
119 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
120 * away by decrementing the array size.
121 */
6aa8b732 122static const u32 vmx_msr_index[] = {
05b3e0c2 123#ifdef CONFIG_X86_64
6aa8b732
AK		 124 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
125#endif
126 MSR_EFER, MSR_K6_STAR,
127};
9d8f549d 128#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 129
a2fa3e9f
GH		 130static void load_msrs(struct kvm_msr_entry *e, int n)
131{
132 int i;
133
134 for (i = 0; i < n; ++i)
135 wrmsrl(e[i].index, e[i].data);
136}
137
138static void save_msrs(struct kvm_msr_entry *e, int n)
139{
140 int i;
141
142 for (i = 0; i < n; ++i)
143 rdmsrl(e[i].index, e[i].data);
144}
145
6aa8b732
AK		 146static inline int is_page_fault(u32 intr_info)
147{
148 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
149 INTR_INFO_VALID_MASK)) ==
150 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
151}
152
2ab455cc
AL		 153static inline int is_no_device(u32 intr_info)
154{
155 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
156 INTR_INFO_VALID_MASK)) ==
157 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
158}
159
7aa81cc0
AL		 160static inline int is_invalid_opcode(u32 intr_info)
161{
162 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
163 INTR_INFO_VALID_MASK)) ==
164 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
165}
166
6aa8b732
AK		 167static inline int is_external_interrupt(u32 intr_info)
168{
169 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
170 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171}
172
6e5d865c
YS		 173static inline int cpu_has_vmx_tpr_shadow(void)
174{
175 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
176}
177
178static inline int vm_need_tpr_shadow(struct kvm *kvm)
179{
180 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
181}
182
f78e0e2e
SY		 183static inline int cpu_has_secondary_exec_ctrls(void)
184{
185 return (vmcs_config.cpu_based_exec_ctrl &
186 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
187}
188
189static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
190{
191 return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
192}
193
194static inline int cpu_has_vmx_virtualize_apic_accesses(void)
195{
196 return (vmcs_config.cpu_based_2nd_exec_ctrl &
197 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
198}
199
200static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
201{
202 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
203 (irqchip_in_kernel(kvm)));
204}
205
8b9cf98c 206static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 207{
208 int i;
209
a2fa3e9f
GH		 210 for (i = 0; i < vmx->nmsrs; ++i)
211 if (vmx->guest_msrs[i].index == msr)
a75beee6
ED		 212 return i;
213 return -1;
214}
215
8b9cf98c 216static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 217{
218 int i;
219
8b9cf98c 220 i = __find_msr_index(vmx, msr);
a75beee6 221 if (i >= 0)
a2fa3e9f 222 return &vmx->guest_msrs[i];
8b6d44c7 223 return NULL;
7725f0ba
AK		 224}
225
6aa8b732
AK		 226static void vmcs_clear(struct vmcs *vmcs)
227{
228 u64 phys_addr = __pa(vmcs);
229 u8 error;
230
231 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
232 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
233 : "cc", "memory");
234 if (error)
235 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
236 vmcs, phys_addr);
237}
238
239static void __vcpu_clear(void *arg)
240{
8b9cf98c 241 struct vcpu_vmx *vmx = arg;
d3b2c338 242 int cpu = raw_smp_processor_id();
6aa8b732 243
8b9cf98c 244 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 245 vmcs_clear(vmx->vmcs);
246 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 247 per_cpu(current_vmcs, cpu) = NULL;
8b9cf98c 248 rdtscll(vmx->vcpu.host_tsc);
6aa8b732
AK		 249}
250
8b9cf98c 251static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 252{
eae5ecb5
AK		 253 if (vmx->vcpu.cpu == -1)
254 return;
f566e09f 255 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
8b9cf98c 256 vmx->launched = 0;
8d0be2b3
AK		 257}
258
6aa8b732
AK		 259static unsigned long vmcs_readl(unsigned long field)
260{
261 unsigned long value;
262
263 asm volatile (ASM_VMX_VMREAD_RDX_RAX
264 : "=a"(value) : "d"(field) : "cc");
265 return value;
266}
267
268static u16 vmcs_read16(unsigned long field)
269{
270 return vmcs_readl(field);
271}
272
273static u32 vmcs_read32(unsigned long field)
274{
275 return vmcs_readl(field);
276}
277
278static u64 vmcs_read64(unsigned long field)
279{
05b3e0c2 280#ifdef CONFIG_X86_64
6aa8b732
AK		 281 return vmcs_readl(field);
282#else
283 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
284#endif
285}
286
e52de1b8
AK		 287static noinline void vmwrite_error(unsigned long field, unsigned long value)
288{
289 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
290 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
291 dump_stack();
292}
293
6aa8b732
AK		 294static void vmcs_writel(unsigned long field, unsigned long value)
295{
296 u8 error;
297
298 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
d77c26fc 299 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 300 if (unlikely(error))
301 vmwrite_error(field, value);
6aa8b732
AK		 302}
303
304static void vmcs_write16(unsigned long field, u16 value)
305{
306 vmcs_writel(field, value);
307}
308
309static void vmcs_write32(unsigned long field, u32 value)
310{
311 vmcs_writel(field, value);
312}
313
314static void vmcs_write64(unsigned long field, u64 value)
315{
05b3e0c2 316#ifdef CONFIG_X86_64
6aa8b732
AK		 317 vmcs_writel(field, value);
318#else
319 vmcs_writel(field, value);
320 asm volatile ("");
321 vmcs_writel(field+1, value >> 32);
322#endif
323}
324
2ab455cc
AL		 325static void vmcs_clear_bits(unsigned long field, u32 mask)
326{
327 vmcs_writel(field, vmcs_readl(field) & ~mask);
328}
329
330static void vmcs_set_bits(unsigned long field, u32 mask)
331{
332 vmcs_writel(field, vmcs_readl(field) | mask);
333}
334
abd3f2d6
AK		 335static void update_exception_bitmap(struct kvm_vcpu *vcpu)
336{
337 u32 eb;
338
7aa81cc0 339 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
abd3f2d6
AK		 340 if (!vcpu->fpu_active)
341 eb |= 1u << NM_VECTOR;
342 if (vcpu->guest_debug.enabled)
343 eb |= 1u << 1;
344 if (vcpu->rmode.active)
345 eb = ~0;
346 vmcs_write32(EXCEPTION_BITMAP, eb);
347}
348
33ed6329
AK		 349static void reload_tss(void)
350{
351#ifndef CONFIG_X86_64
352
353 /*
354 * VT restores TR but not its size. Useless.
355 */
356 struct descriptor_table gdt;
357 struct segment_descriptor *descs;
358
359 get_gdt(&gdt);
360 descs = (void *)gdt.base;
361 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
362 load_TR_desc();
363#endif
364}
365
8b9cf98c 366static void load_transition_efer(struct vcpu_vmx *vmx)
2cc51560 367{
a2fa3e9f 368 int efer_offset = vmx->msr_offset_efer;
51c6cf66
AK		 369 u64 host_efer = vmx->host_msrs[efer_offset].data;
370 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
371 u64 ignore_bits;
372
373 if (efer_offset < 0)
374 return;
375 /*
376 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
377 * outside long mode
378 */
379 ignore_bits = EFER_NX | EFER_SCE;
380#ifdef CONFIG_X86_64
381 ignore_bits |= EFER_LMA | EFER_LME;
382 /* SCE is meaningful only in long mode on Intel */
383 if (guest_efer & EFER_LMA)
384 ignore_bits &= ~(u64)EFER_SCE;
385#endif
386 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
387 return;
2cc51560 388
51c6cf66
AK		 389 vmx->host_state.guest_efer_loaded = 1;
390 guest_efer &= ~ignore_bits;
391 guest_efer |= host_efer & ignore_bits;
392 wrmsrl(MSR_EFER, guest_efer);
8b9cf98c 393 vmx->vcpu.stat.efer_reload++;
2cc51560
ED		 394}
395
51c6cf66
AK		 396static void reload_host_efer(struct vcpu_vmx *vmx)
397{
398 if (vmx->host_state.guest_efer_loaded) {
399 vmx->host_state.guest_efer_loaded = 0;
400 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
401 }
402}
403
04d2cc77 404static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 405{
04d2cc77
AK		 406 struct vcpu_vmx *vmx = to_vmx(vcpu);
407
a2fa3e9f 408 if (vmx->host_state.loaded)
33ed6329
AK		 409 return;
410
a2fa3e9f 411 vmx->host_state.loaded = 1;
33ed6329
AK		 412 /*
413 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
414 * allow segment selectors with cpl > 0 or ti == 1.
415 */
a2fa3e9f 416 vmx->host_state.ldt_sel = read_ldt();
152d3f2f 417 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
a2fa3e9f 418 vmx->host_state.fs_sel = read_fs();
152d3f2f 419 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 420 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 421 vmx->host_state.fs_reload_needed = 0;
422 } else {
33ed6329 423 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 424 vmx->host_state.fs_reload_needed = 1;
33ed6329 425 }
a2fa3e9f
GH		 426 vmx->host_state.gs_sel = read_gs();
427 if (!(vmx->host_state.gs_sel & 7))
428 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 429 else {
430 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 431 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 432 }
433
434#ifdef CONFIG_X86_64
435 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
436 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
437#else
a2fa3e9f
GH		 438 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
439 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 440#endif
707c0874
AK		 441
442#ifdef CONFIG_X86_64
d77c26fc 443 if (is_long_mode(&vmx->vcpu))
a2fa3e9f
GH		 444 save_msrs(vmx->host_msrs +
445 vmx->msr_offset_kernel_gs_base, 1);
d77c26fc 446
707c0874 447#endif
a2fa3e9f 448 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
51c6cf66 449 load_transition_efer(vmx);
33ed6329
AK		 450}
451
8b9cf98c 452static void vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 453{
15ad7146 454 unsigned long flags;
33ed6329 455
a2fa3e9f 456 if (!vmx->host_state.loaded)
33ed6329
AK		 457 return;
458
a2fa3e9f 459 vmx->host_state.loaded = 0;
152d3f2f 460 if (vmx->host_state.fs_reload_needed)
a2fa3e9f 461 load_fs(vmx->host_state.fs_sel);
152d3f2f
LV		 462 if (vmx->host_state.gs_ldt_reload_needed) {
463 load_ldt(vmx->host_state.ldt_sel);
33ed6329
AK		 464 /*
465 * If we have to reload gs, we must take care to
466 * preserve our gs base.
467 */
15ad7146 468 local_irq_save(flags);
a2fa3e9f 469 load_gs(vmx->host_state.gs_sel);
33ed6329
AK		 470#ifdef CONFIG_X86_64
471 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
472#endif
15ad7146 473 local_irq_restore(flags);
33ed6329 474 }
152d3f2f 475 reload_tss();
a2fa3e9f
GH		 476 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
477 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
51c6cf66 478 reload_host_efer(vmx);
33ed6329
AK		 479}
480
6aa8b732
AK		 481/*
482 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
483 * vcpu mutex is already taken.
484 */
15ad7146 485static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 486{
a2fa3e9f
GH		 487 struct vcpu_vmx *vmx = to_vmx(vcpu);
488 u64 phys_addr = __pa(vmx->vmcs);
7700270e 489 u64 tsc_this, delta;
6aa8b732 490
a3d7f85f 491 if (vcpu->cpu != cpu) {
8b9cf98c 492 vcpu_clear(vmx);
a3d7f85f
ED		 493 kvm_migrate_apic_timer(vcpu);
494 }
6aa8b732 495
a2fa3e9f 496 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
6aa8b732
AK		 497 u8 error;
498
a2fa3e9f 499 per_cpu(current_vmcs, cpu) = vmx->vmcs;
6aa8b732
AK		 500 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
501 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
502 : "cc");
503 if (error)
504 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
a2fa3e9f 505 vmx->vmcs, phys_addr);
6aa8b732
AK		 506 }
507
508 if (vcpu->cpu != cpu) {
509 struct descriptor_table dt;
510 unsigned long sysenter_esp;
511
512 vcpu->cpu = cpu;
513 /*
514 * Linux uses per-cpu TSS and GDT, so set these when switching
515 * processors.
516 */
517 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
518 get_gdt(&dt);
519 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
520
521 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
522 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
7700270e
AK		 523
524 /*
525 * Make sure the time stamp counter is monotonous.
526 */
527 rdtscll(tsc_this);
528 delta = vcpu->host_tsc - tsc_this;
529 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
6aa8b732 530 }
6aa8b732
AK		 531}
532
533static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
534{
8b9cf98c 535 vmx_load_host_state(to_vmx(vcpu));
7702fd1f 536 kvm_put_guest_fpu(vcpu);
6aa8b732
AK		 537}
538
5fd86fcf
AK		 539static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
540{
541 if (vcpu->fpu_active)
542 return;
543 vcpu->fpu_active = 1;
707d92fa
RR		 544 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
545 if (vcpu->cr0 & X86_CR0_TS)
546 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 547 update_exception_bitmap(vcpu);
548}
549
550static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
551{
552 if (!vcpu->fpu_active)
553 return;
554 vcpu->fpu_active = 0;
707d92fa 555 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
5fd86fcf
AK		 556 update_exception_bitmap(vcpu);
557}
558
774c47f1
AK		 559static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
560{
8b9cf98c 561 vcpu_clear(to_vmx(vcpu));
774c47f1
AK		 562}
563
6aa8b732
AK		 564static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
565{
566 return vmcs_readl(GUEST_RFLAGS);
567}
568
569static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
570{
78f78268 571 if (vcpu->rmode.active)
053de044 572 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 573 vmcs_writel(GUEST_RFLAGS, rflags);
574}
575
576static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
577{
578 unsigned long rip;
579 u32 interruptibility;
580
581 rip = vmcs_readl(GUEST_RIP);
582 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
583 vmcs_writel(GUEST_RIP, rip);
584
585 /*
586 * We emulated an instruction, so temporary interrupt blocking
587 * should be removed, if set.
588 */
589 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
590 if (interruptibility & 3)
591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
592 interruptibility & ~3);
c1150d8c 593 vcpu->interrupt_window_open = 1;
6aa8b732
AK		 594}
595
596static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
597{
598 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
599 vmcs_readl(GUEST_RIP));
600 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
601 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
602 GP_VECTOR |
603 INTR_TYPE_EXCEPTION |
604 INTR_INFO_DELIEVER_CODE_MASK |
605 INTR_INFO_VALID_MASK);
606}
607
7aa81cc0
AL		 608static void vmx_inject_ud(struct kvm_vcpu *vcpu)
609{
610 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
611 UD_VECTOR |
612 INTR_TYPE_EXCEPTION |
613 INTR_INFO_VALID_MASK);
614}
615
a75beee6
ED		 616/*
617 * Swap MSR entry in host/guest MSR entry array.
618 */
54e11fa1 619#ifdef CONFIG_X86_64
8b9cf98c 620static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 621{
a2fa3e9f
GH		 622 struct kvm_msr_entry tmp;
623
624 tmp = vmx->guest_msrs[to];
625 vmx->guest_msrs[to] = vmx->guest_msrs[from];
626 vmx->guest_msrs[from] = tmp;
627 tmp = vmx->host_msrs[to];
628 vmx->host_msrs[to] = vmx->host_msrs[from];
629 vmx->host_msrs[from] = tmp;
a75beee6 630}
54e11fa1 631#endif
a75beee6 632
e38aea3e
AK		 633/*
634 * Set up the vmcs to automatically save and restore system
635 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
636 * mode, as fiddling with msrs is very expensive.
637 */
8b9cf98c 638static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 639{
2cc51560 640 int save_nmsrs;
e38aea3e 641
a75beee6
ED		 642 save_nmsrs = 0;
643#ifdef CONFIG_X86_64
8b9cf98c 644 if (is_long_mode(&vmx->vcpu)) {
2cc51560
ED		 645 int index;
646
8b9cf98c 647 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 648 if (index >= 0)
8b9cf98c
RR		 649 move_msr_up(vmx, index, save_nmsrs++);
650 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 651 if (index >= 0)
8b9cf98c
RR		 652 move_msr_up(vmx, index, save_nmsrs++);
653 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 654 if (index >= 0)
8b9cf98c
RR		 655 move_msr_up(vmx, index, save_nmsrs++);
656 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
a75beee6 657 if (index >= 0)
8b9cf98c 658 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 659 /*
660 * MSR_K6_STAR is only needed on long mode guests, and only
661 * if efer.sce is enabled.
662 */
8b9cf98c
RR		 663 index = __find_msr_index(vmx, MSR_K6_STAR);
664 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
665 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 666 }
667#endif
a2fa3e9f 668 vmx->save_nmsrs = save_nmsrs;
e38aea3e 669
4d56c8a7 670#ifdef CONFIG_X86_64
a2fa3e9f 671 vmx->msr_offset_kernel_gs_base =
8b9cf98c 672 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
4d56c8a7 673#endif
8b9cf98c 674 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
e38aea3e
AK		 675}
676
6aa8b732
AK		 677/*
678 * reads and returns guest's timestamp counter "register"
679 * guest_tsc = host_tsc + tsc_offset -- 21.3
680 */
681static u64 guest_read_tsc(void)
682{
683 u64 host_tsc, tsc_offset;
684
685 rdtscll(host_tsc);
686 tsc_offset = vmcs_read64(TSC_OFFSET);
687 return host_tsc + tsc_offset;
688}
689
690/*
691 * writes 'guest_tsc' into guest's timestamp counter "register"
692 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
693 */
694static void guest_write_tsc(u64 guest_tsc)
695{
696 u64 host_tsc;
697
698 rdtscll(host_tsc);
699 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
700}
701
6aa8b732
AK		 702/*
703 * Reads an msr value (of 'msr_index') into 'pdata'.
704 * Returns 0 on success, non-0 otherwise.
705 * Assumes vcpu_load() was already called.
706 */
707static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
708{
709 u64 data;
a2fa3e9f 710 struct kvm_msr_entry *msr;
6aa8b732
AK		 711
712 if (!pdata) {
713 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
714 return -EINVAL;
715 }
716
717 switch (msr_index) {
05b3e0c2 718#ifdef CONFIG_X86_64
6aa8b732
AK		 719 case MSR_FS_BASE:
720 data = vmcs_readl(GUEST_FS_BASE);
721 break;
722 case MSR_GS_BASE:
723 data = vmcs_readl(GUEST_GS_BASE);
724 break;
725 case MSR_EFER:
3bab1f5d 726 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 727#endif
728 case MSR_IA32_TIME_STAMP_COUNTER:
729 data = guest_read_tsc();
730 break;
731 case MSR_IA32_SYSENTER_CS:
732 data = vmcs_read32(GUEST_SYSENTER_CS);
733 break;
734 case MSR_IA32_SYSENTER_EIP:
f5b42c33 735 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 736 break;
737 case MSR_IA32_SYSENTER_ESP:
f5b42c33 738 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 739 break;
6aa8b732 740 default:
8b9cf98c 741 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 742 if (msr) {
743 data = msr->data;
744 break;
6aa8b732 745 }
3bab1f5d 746 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 747 }
748
749 *pdata = data;
750 return 0;
751}
752
753/*
754 * Writes msr value into into the appropriate "register".
755 * Returns 0 on success, non-0 otherwise.
756 * Assumes vcpu_load() was already called.
757 */
758static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
759{
a2fa3e9f
GH		 760 struct vcpu_vmx *vmx = to_vmx(vcpu);
761 struct kvm_msr_entry *msr;
2cc51560
ED		 762 int ret = 0;
763
6aa8b732 764 switch (msr_index) {
05b3e0c2 765#ifdef CONFIG_X86_64
3bab1f5d 766 case MSR_EFER:
2cc51560 767 ret = kvm_set_msr_common(vcpu, msr_index, data);
51c6cf66
AK		 768 if (vmx->host_state.loaded) {
769 reload_host_efer(vmx);
8b9cf98c 770 load_transition_efer(vmx);
51c6cf66 771 }
2cc51560 772 break;
6aa8b732
AK		 773 case MSR_FS_BASE:
774 vmcs_writel(GUEST_FS_BASE, data);
775 break;
776 case MSR_GS_BASE:
777 vmcs_writel(GUEST_GS_BASE, data);
778 break;
779#endif
780 case MSR_IA32_SYSENTER_CS:
781 vmcs_write32(GUEST_SYSENTER_CS, data);
782 break;
783 case MSR_IA32_SYSENTER_EIP:
f5b42c33 784 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 785 break;
786 case MSR_IA32_SYSENTER_ESP:
f5b42c33 787 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 788 break;
d27d4aca 789 case MSR_IA32_TIME_STAMP_COUNTER:
6aa8b732
AK		 790 guest_write_tsc(data);
791 break;
6aa8b732 792 default:
8b9cf98c 793 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 794 if (msr) {
795 msr->data = data;
a2fa3e9f
GH		 796 if (vmx->host_state.loaded)
797 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
3bab1f5d 798 break;
6aa8b732 799 }
2cc51560 800 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 801 }
802
2cc51560 803 return ret;
6aa8b732
AK		 804}
805
806/*
807 * Sync the rsp and rip registers into the vcpu structure. This allows
808 * registers to be accessed by indexing vcpu->regs.
809 */
810static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
811{
812 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
813 vcpu->rip = vmcs_readl(GUEST_RIP);
814}
815
816/*
817 * Syncs rsp and rip back into the vmcs. Should be called after possible
818 * modification.
819 */
820static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
821{
822 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
823 vmcs_writel(GUEST_RIP, vcpu->rip);
824}
825
826static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
827{
828 unsigned long dr7 = 0x400;
6aa8b732
AK		 829 int old_singlestep;
830
6aa8b732
AK		 831 old_singlestep = vcpu->guest_debug.singlestep;
832
833 vcpu->guest_debug.enabled = dbg->enabled;
834 if (vcpu->guest_debug.enabled) {
835 int i;
836
837 dr7 |= 0x200; /* exact */
838 for (i = 0; i < 4; ++i) {
839 if (!dbg->breakpoints[i].enabled)
840 continue;
841 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
842 dr7 |= 2 << (i*2); /* global enable */
843 dr7 |= 0 << (i*4+16); /* execution breakpoint */
844 }
845
6aa8b732 846 vcpu->guest_debug.singlestep = dbg->singlestep;
abd3f2d6 847 } else
6aa8b732 848 vcpu->guest_debug.singlestep = 0;
6aa8b732
AK		 849
850 if (old_singlestep && !vcpu->guest_debug.singlestep) {
851 unsigned long flags;
852
853 flags = vmcs_readl(GUEST_RFLAGS);
854 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
855 vmcs_writel(GUEST_RFLAGS, flags);
856 }
857
abd3f2d6 858 update_exception_bitmap(vcpu);
6aa8b732
AK		 859 vmcs_writel(GUEST_DR7, dr7);
860
861 return 0;
862}
863
2a8067f1
ED		 864static int vmx_get_irq(struct kvm_vcpu *vcpu)
865{
866 u32 idtv_info_field;
867
868 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
869 if (idtv_info_field & INTR_INFO_VALID_MASK) {
870 if (is_external_interrupt(idtv_info_field))
871 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
872 else
d77c26fc 873 printk(KERN_DEBUG "pending exception: not handled yet\n");
2a8067f1
ED		 874 }
875 return -1;
876}
877
6aa8b732
AK		 878static __init int cpu_has_kvm_support(void)
879{
880 unsigned long ecx = cpuid_ecx(1);
881 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
882}
883
884static __init int vmx_disabled_by_bios(void)
885{
886 u64 msr;
887
888 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
62b3ffb8
YS		 889 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
890 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
891 == MSR_IA32_FEATURE_CONTROL_LOCKED;
892 /* locked but not enabled */
6aa8b732
AK		 893}
894
774c47f1 895static void hardware_enable(void *garbage)
6aa8b732
AK		 896{
897 int cpu = raw_smp_processor_id();
898 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
899 u64 old;
900
901 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
62b3ffb8
YS		 902 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
903 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
904 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
905 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
6aa8b732 906 /* enable and lock */
62b3ffb8
YS		 907 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
908 MSR_IA32_FEATURE_CONTROL_LOCKED |
909 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
66aee91a 910 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
6aa8b732
AK		 911 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
912 : "memory", "cc");
913}
914
915static void hardware_disable(void *garbage)
916{
917 asm volatile (ASM_VMX_VMXOFF : : : "cc");
918}
919
1c3d14fe 920static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 921 u32 msr, u32 *result)
1c3d14fe
YS		 922{
923 u32 vmx_msr_low, vmx_msr_high;
924 u32 ctl = ctl_min | ctl_opt;
925
926 rdmsr(msr, vmx_msr_low, vmx_msr_high);
927
928 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
929 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
930
931 /* Ensure minimum (required) set of control bits are supported. */
932 if (ctl_min & ~ctl)
002c7f7c 933 return -EIO;
1c3d14fe
YS		 934
935 *result = ctl;
936 return 0;
937}
938
002c7f7c 939static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 940{
941 u32 vmx_msr_low, vmx_msr_high;
1c3d14fe
YS		 942 u32 min, opt;
943 u32 _pin_based_exec_control = 0;
944 u32 _cpu_based_exec_control = 0;
f78e0e2e 945 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 946 u32 _vmexit_control = 0;
947 u32 _vmentry_control = 0;
948
949 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
950 opt = 0;
951 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
952 &_pin_based_exec_control) < 0)
002c7f7c 953 return -EIO;
1c3d14fe
YS		 954
955 min = CPU_BASED_HLT_EXITING |
956#ifdef CONFIG_X86_64
957 CPU_BASED_CR8_LOAD_EXITING |
958 CPU_BASED_CR8_STORE_EXITING |
959#endif
960 CPU_BASED_USE_IO_BITMAPS |
961 CPU_BASED_MOV_DR_EXITING |
962 CPU_BASED_USE_TSC_OFFSETING;
f78e0e2e
SY		 963 opt = CPU_BASED_TPR_SHADOW |
964 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 965 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
966 &_cpu_based_exec_control) < 0)
002c7f7c 967 return -EIO;
6e5d865c
YS		 968#ifdef CONFIG_X86_64
969 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
970 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
971 ~CPU_BASED_CR8_STORE_EXITING;
972#endif
f78e0e2e
SY		 973 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
974 min = 0;
975 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
976 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
977 &_cpu_based_2nd_exec_control) < 0)
978 return -EIO;
979 }
980#ifndef CONFIG_X86_64
981 if (!(_cpu_based_2nd_exec_control &
982 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
983 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
984#endif
1c3d14fe
YS		 985
986 min = 0;
987#ifdef CONFIG_X86_64
988 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
989#endif
990 opt = 0;
991 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
992 &_vmexit_control) < 0)
002c7f7c 993 return -EIO;
1c3d14fe
YS		 994
995 min = opt = 0;
996 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
997 &_vmentry_control) < 0)
002c7f7c 998 return -EIO;
6aa8b732 999
c68876fd 1000 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1001
1002 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1003 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1004 return -EIO;
1c3d14fe
YS		 1005
1006#ifdef CONFIG_X86_64
1007 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1008 if (vmx_msr_high & (1u<<16))
002c7f7c 1009 return -EIO;
1c3d14fe
YS		 1010#endif
1011
1012 /* Require Write-Back (WB) memory type for VMCS accesses. */
1013 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1014 return -EIO;
1c3d14fe 1015
002c7f7c
YS		 1016 vmcs_conf->size = vmx_msr_high & 0x1fff;
1017 vmcs_conf->order = get_order(vmcs_config.size);
1018 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1019
002c7f7c
YS		 1020 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1021 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1022 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1023 vmcs_conf->vmexit_ctrl = _vmexit_control;
1024 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1025
1026 return 0;
c68876fd 1027}
6aa8b732
AK		 1028
1029static struct vmcs *alloc_vmcs_cpu(int cpu)
1030{
1031 int node = cpu_to_node(cpu);
1032 struct page *pages;
1033 struct vmcs *vmcs;
1034
1c3d14fe 1035 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1036 if (!pages)
1037 return NULL;
1038 vmcs = page_address(pages);
1c3d14fe
YS		 1039 memset(vmcs, 0, vmcs_config.size);
1040 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1041 return vmcs;
1042}
1043
1044static struct vmcs *alloc_vmcs(void)
1045{
d3b2c338 1046 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1047}
1048
1049static void free_vmcs(struct vmcs *vmcs)
1050{
1c3d14fe 1051 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1052}
1053
39959588 1054static void free_kvm_area(void)
6aa8b732
AK		 1055{
1056 int cpu;
1057
1058 for_each_online_cpu(cpu)
1059 free_vmcs(per_cpu(vmxarea, cpu));
1060}
1061
6aa8b732
AK		 1062static __init int alloc_kvm_area(void)
1063{
1064 int cpu;
1065
1066 for_each_online_cpu(cpu) {
1067 struct vmcs *vmcs;
1068
1069 vmcs = alloc_vmcs_cpu(cpu);
1070 if (!vmcs) {
1071 free_kvm_area();
1072 return -ENOMEM;
1073 }
1074
1075 per_cpu(vmxarea, cpu) = vmcs;
1076 }
1077 return 0;
1078}
1079
1080static __init int hardware_setup(void)
1081{
002c7f7c
YS		 1082 if (setup_vmcs_config(&vmcs_config) < 0)
1083 return -EIO;
6aa8b732
AK		 1084 return alloc_kvm_area();
1085}
1086
1087static __exit void hardware_unsetup(void)
1088{
1089 free_kvm_area();
1090}
1091
6aa8b732
AK		 1092static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1093{
1094 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1095
6af11b9e 1096 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1097 vmcs_write16(sf->selector, save->selector);
1098 vmcs_writel(sf->base, save->base);
1099 vmcs_write32(sf->limit, save->limit);
1100 vmcs_write32(sf->ar_bytes, save->ar);
1101 } else {
1102 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1103 << AR_DPL_SHIFT;
1104 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1105 }
1106}
1107
1108static void enter_pmode(struct kvm_vcpu *vcpu)
1109{
1110 unsigned long flags;
1111
1112 vcpu->rmode.active = 0;
1113
1114 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1115 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1116 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1117
1118 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1119 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
6aa8b732
AK		 1120 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1121 vmcs_writel(GUEST_RFLAGS, flags);
1122
66aee91a
RR		 1123 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1124 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1125
1126 update_exception_bitmap(vcpu);
1127
1128 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1129 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1130 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1131 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1132
1133 vmcs_write16(GUEST_SS_SELECTOR, 0);
1134 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1135
1136 vmcs_write16(GUEST_CS_SELECTOR,
1137 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1138 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1139}
1140
d77c26fc 1141static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1142{
cbc94022
IE		 1143 if (!kvm->tss_addr) {
1144 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1145 kvm->memslots[0].npages - 3;
1146 return base_gfn << PAGE_SHIFT;
1147 }
1148 return kvm->tss_addr;
6aa8b732
AK		 1149}
1150
1151static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1152{
1153 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1154
1155 save->selector = vmcs_read16(sf->selector);
1156 save->base = vmcs_readl(sf->base);
1157 save->limit = vmcs_read32(sf->limit);
1158 save->ar = vmcs_read32(sf->ar_bytes);
1159 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1160 vmcs_write32(sf->limit, 0xffff);
1161 vmcs_write32(sf->ar_bytes, 0xf3);
1162}
1163
1164static void enter_rmode(struct kvm_vcpu *vcpu)
1165{
1166 unsigned long flags;
1167
1168 vcpu->rmode.active = 1;
1169
1170 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1171 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1172
1173 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1174 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1175
1176 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1177 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1178
1179 flags = vmcs_readl(GUEST_RFLAGS);
053de044 1180 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
6aa8b732 1181
053de044 1182 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1183
1184 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1185 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1186 update_exception_bitmap(vcpu);
1187
1188 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1189 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1190 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1191
1192 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1193 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1194 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1195 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1196 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1197
1198 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1199 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1200 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1201 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
75880a01 1202
8668a3c4 1203 kvm_mmu_reset_context(vcpu);
75880a01 1204 init_rmode_tss(vcpu->kvm);
6aa8b732
AK		 1205}
1206
05b3e0c2 1207#ifdef CONFIG_X86_64
6aa8b732
AK		 1208
1209static void enter_lmode(struct kvm_vcpu *vcpu)
1210{
1211 u32 guest_tr_ar;
1212
1213 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1214 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1215 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1216 __FUNCTION__);
1217 vmcs_write32(GUEST_TR_AR_BYTES,
1218 (guest_tr_ar & ~AR_TYPE_MASK)
1219 | AR_TYPE_BUSY_64_TSS);
1220 }
1221
1222 vcpu->shadow_efer |= EFER_LMA;
1223
8b9cf98c 1224 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
6aa8b732
AK		 1225 vmcs_write32(VM_ENTRY_CONTROLS,
1226 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1227 | VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1228}
1229
1230static void exit_lmode(struct kvm_vcpu *vcpu)
1231{
1232 vcpu->shadow_efer &= ~EFER_LMA;
1233
1234 vmcs_write32(VM_ENTRY_CONTROLS,
1235 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1236 & ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1237}
1238
1239#endif
1240
25c4c276 1241static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1242{
399badf3
AK		 1243 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1244 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1245}
1246
6aa8b732
AK		 1247static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1248{
5fd86fcf
AK		 1249 vmx_fpu_deactivate(vcpu);
1250
707d92fa 1251 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1252 enter_pmode(vcpu);
1253
707d92fa 1254 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1255 enter_rmode(vcpu);
1256
05b3e0c2 1257#ifdef CONFIG_X86_64
6aa8b732 1258 if (vcpu->shadow_efer & EFER_LME) {
707d92fa 1259 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1260 enter_lmode(vcpu);
707d92fa 1261 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1262 exit_lmode(vcpu);
1263 }
1264#endif
1265
1266 vmcs_writel(CR0_READ_SHADOW, cr0);
1267 vmcs_writel(GUEST_CR0,
1268 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1269 vcpu->cr0 = cr0;
5fd86fcf 1270
707d92fa 1271 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
5fd86fcf 1272 vmx_fpu_activate(vcpu);
6aa8b732
AK		 1273}
1274
6aa8b732
AK		 1275static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1276{
1277 vmcs_writel(GUEST_CR3, cr3);
707d92fa 1278 if (vcpu->cr0 & X86_CR0_PE)
5fd86fcf 1279 vmx_fpu_deactivate(vcpu);
6aa8b732
AK		 1280}
1281
1282static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1283{
1284 vmcs_writel(CR4_READ_SHADOW, cr4);
1285 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1286 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1287 vcpu->cr4 = cr4;
1288}
1289
05b3e0c2 1290#ifdef CONFIG_X86_64
6aa8b732
AK		 1291
1292static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1293{
8b9cf98c
RR		 1294 struct vcpu_vmx *vmx = to_vmx(vcpu);
1295 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
6aa8b732
AK		 1296
1297 vcpu->shadow_efer = efer;
1298 if (efer & EFER_LMA) {
1299 vmcs_write32(VM_ENTRY_CONTROLS,
1300 vmcs_read32(VM_ENTRY_CONTROLS) |
1e4e6e00 1301 VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1302 msr->data = efer;
1303
1304 } else {
1305 vmcs_write32(VM_ENTRY_CONTROLS,
1306 vmcs_read32(VM_ENTRY_CONTROLS) &
1e4e6e00 1307 ~VM_ENTRY_IA32E_MODE);
6aa8b732
AK		 1308
1309 msr->data = efer & ~EFER_LME;
1310 }
8b9cf98c 1311 setup_msrs(vmx);
6aa8b732
AK		 1312}
1313
1314#endif
1315
1316static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1317{
1318 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1319
1320 return vmcs_readl(sf->base);
1321}
1322
1323static void vmx_get_segment(struct kvm_vcpu *vcpu,
1324 struct kvm_segment *var, int seg)
1325{
1326 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1327 u32 ar;
1328
1329 var->base = vmcs_readl(sf->base);
1330 var->limit = vmcs_read32(sf->limit);
1331 var->selector = vmcs_read16(sf->selector);
1332 ar = vmcs_read32(sf->ar_bytes);
1333 if (ar & AR_UNUSABLE_MASK)
1334 ar = 0;
1335 var->type = ar & 15;
1336 var->s = (ar >> 4) & 1;
1337 var->dpl = (ar >> 5) & 3;
1338 var->present = (ar >> 7) & 1;
1339 var->avl = (ar >> 12) & 1;
1340 var->l = (ar >> 13) & 1;
1341 var->db = (ar >> 14) & 1;
1342 var->g = (ar >> 15) & 1;
1343 var->unusable = (ar >> 16) & 1;
1344}
1345
653e3108 1346static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 1347{
6aa8b732
AK		 1348 u32 ar;
1349
653e3108 1350 if (var->unusable)
6aa8b732
AK		 1351 ar = 1 << 16;
1352 else {
1353 ar = var->type & 15;
1354 ar |= (var->s & 1) << 4;
1355 ar |= (var->dpl & 3) << 5;
1356 ar |= (var->present & 1) << 7;
1357 ar |= (var->avl & 1) << 12;
1358 ar |= (var->l & 1) << 13;
1359 ar |= (var->db & 1) << 14;
1360 ar |= (var->g & 1) << 15;
1361 }
f7fbf1fd
UL		 1362 if (ar == 0) /* a 0 value means unusable */
1363 ar = AR_UNUSABLE_MASK;
653e3108
AK		 1364
1365 return ar;
1366}
1367
1368static void vmx_set_segment(struct kvm_vcpu *vcpu,
1369 struct kvm_segment *var, int seg)
1370{
1371 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1372 u32 ar;
1373
1374 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1375 vcpu->rmode.tr.selector = var->selector;
1376 vcpu->rmode.tr.base = var->base;
1377 vcpu->rmode.tr.limit = var->limit;
1378 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1379 return;
1380 }
1381 vmcs_writel(sf->base, var->base);
1382 vmcs_write32(sf->limit, var->limit);
1383 vmcs_write16(sf->selector, var->selector);
1384 if (vcpu->rmode.active && var->s) {
1385 /*
1386 * Hack real-mode segments into vm86 compatibility.
1387 */
1388 if (var->base == 0xffff0000 && var->selector == 0xf000)
1389 vmcs_writel(sf->base, 0xf0000);
1390 ar = 0xf3;
1391 } else
1392 ar = vmx_segment_access_rights(var);
6aa8b732
AK		 1393 vmcs_write32(sf->ar_bytes, ar);
1394}
1395
6aa8b732
AK		 1396static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1397{
1398 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1399
1400 *db = (ar >> 14) & 1;
1401 *l = (ar >> 13) & 1;
1402}
1403
1404static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1405{
1406 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1407 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1408}
1409
1410static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1411{
1412 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1413 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1414}
1415
1416static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1417{
1418 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1419 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1420}
1421
1422static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1423{
1424 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1425 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1426}
1427
d77c26fc 1428static int init_rmode_tss(struct kvm *kvm)
6aa8b732 1429{
6aa8b732 1430 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 1431 u16 data = 0;
1432 int r;
6aa8b732 1433
195aefde
IE		 1434 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1435 if (r < 0)
1436 return 0;
1437 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1438 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1439 if (r < 0)
1440 return 0;
1441 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1442 if (r < 0)
1443 return 0;
1444 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1445 if (r < 0)
1446 return 0;
1447 data = ~0;
1448 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1449 sizeof(u8));
1450 if (r < 0)
6aa8b732 1451 return 0;
6aa8b732
AK		 1452 return 1;
1453}
1454
6aa8b732
AK		 1455static void seg_setup(int seg)
1456{
1457 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1458
1459 vmcs_write16(sf->selector, 0);
1460 vmcs_writel(sf->base, 0);
1461 vmcs_write32(sf->limit, 0xffff);
1462 vmcs_write32(sf->ar_bytes, 0x93);
1463}
1464
f78e0e2e
SY		 1465static int alloc_apic_access_page(struct kvm *kvm)
1466{
1467 struct kvm_userspace_memory_region kvm_userspace_mem;
1468 int r = 0;
1469
1470 mutex_lock(&kvm->lock);
1471 if (kvm->apic_access_page)
1472 goto out;
1473 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1474 kvm_userspace_mem.flags = 0;
1475 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1476 kvm_userspace_mem.memory_size = PAGE_SIZE;
1477 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1478 if (r)
1479 goto out;
1480 kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1481out:
1482 mutex_unlock(&kvm->lock);
1483 return r;
1484}
1485
6aa8b732
AK		 1486/*
1487 * Sets up the vmcs for emulated real mode.
1488 */
8b9cf98c 1489static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732
AK		 1490{
1491 u32 host_sysenter_cs;
1492 u32 junk;
1493 unsigned long a;
1494 struct descriptor_table dt;
1495 int i;
cd2276a7 1496 unsigned long kvm_vmx_return;
6e5d865c 1497 u32 exec_control;
6aa8b732 1498
6aa8b732 1499 /* I/O */
fdef3ad1
HQ		 1500 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1501 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
6aa8b732 1502
6aa8b732
AK		 1503 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1504
6aa8b732 1505 /* Control */
1c3d14fe
YS		 1506 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1507 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 1508
1509 exec_control = vmcs_config.cpu_based_exec_ctrl;
1510 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1511 exec_control &= ~CPU_BASED_TPR_SHADOW;
1512#ifdef CONFIG_X86_64
1513 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1514 CPU_BASED_CR8_LOAD_EXITING;
1515#endif
1516 }
f78e0e2e
SY		 1517 if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1518 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
6e5d865c 1519 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 1520
f78e0e2e
SY		 1521 if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1522 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1523 vmcs_config.cpu_based_2nd_exec_ctrl);
1524
c7addb90
AK		 1525 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1526 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 1527 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1528
1529 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1530 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1531 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1532
1533 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1534 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1535 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1536 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1537 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1538 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 1539#ifdef CONFIG_X86_64
6aa8b732
AK		 1540 rdmsrl(MSR_FS_BASE, a);
1541 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1542 rdmsrl(MSR_GS_BASE, a);
1543 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1544#else
1545 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1546 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1547#endif
1548
1549 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1550
1551 get_idt(&dt);
1552 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1553
d77c26fc 1554 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 1555 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 1556 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1557 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1558 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
6aa8b732
AK		 1559
1560 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1561 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1562 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1563 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1564 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1565 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1566
6aa8b732
AK		 1567 for (i = 0; i < NR_VMX_MSR; ++i) {
1568 u32 index = vmx_msr_index[i];
1569 u32 data_low, data_high;
1570 u64 data;
a2fa3e9f 1571 int j = vmx->nmsrs;
6aa8b732
AK		 1572
1573 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1574 continue;
432bd6cb
AK		 1575 if (wrmsr_safe(index, data_low, data_high) < 0)
1576 continue;
6aa8b732 1577 data = data_low | ((u64)data_high << 32);
a2fa3e9f
GH		 1578 vmx->host_msrs[j].index = index;
1579 vmx->host_msrs[j].reserved = 0;
1580 vmx->host_msrs[j].data = data;
1581 vmx->guest_msrs[j] = vmx->host_msrs[j];
1582 ++vmx->nmsrs;
6aa8b732 1583 }
6aa8b732 1584
1c3d14fe 1585 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 1586
1587 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 1588 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1589
e00c8cf2
AK		 1590 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1591 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1592
f78e0e2e
SY		 1593 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1594 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1595 return -ENOMEM;
1596
e00c8cf2
AK		 1597 return 0;
1598}
1599
1600static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1601{
1602 struct vcpu_vmx *vmx = to_vmx(vcpu);
1603 u64 msr;
1604 int ret;
1605
1606 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1607 ret = -ENOMEM;
1608 goto out;
1609 }
1610
1611 vmx->vcpu.rmode.active = 0;
1612
1613 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1614 set_cr8(&vmx->vcpu, 0);
1615 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1616 if (vmx->vcpu.vcpu_id == 0)
1617 msr |= MSR_IA32_APICBASE_BSP;
1618 kvm_set_apic_base(&vmx->vcpu, msr);
1619
1620 fx_init(&vmx->vcpu);
1621
1622 /*
1623 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1624 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1625 */
1626 if (vmx->vcpu.vcpu_id == 0) {
1627 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1628 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1629 } else {
1630 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1631 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1632 }
1633 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1634 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1635
1636 seg_setup(VCPU_SREG_DS);
1637 seg_setup(VCPU_SREG_ES);
1638 seg_setup(VCPU_SREG_FS);
1639 seg_setup(VCPU_SREG_GS);
1640 seg_setup(VCPU_SREG_SS);
1641
1642 vmcs_write16(GUEST_TR_SELECTOR, 0);
1643 vmcs_writel(GUEST_TR_BASE, 0);
1644 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1645 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1646
1647 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1648 vmcs_writel(GUEST_LDTR_BASE, 0);
1649 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1650 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1651
1652 vmcs_write32(GUEST_SYSENTER_CS, 0);
1653 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1654 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1655
1656 vmcs_writel(GUEST_RFLAGS, 0x02);
1657 if (vmx->vcpu.vcpu_id == 0)
1658 vmcs_writel(GUEST_RIP, 0xfff0);
1659 else
1660 vmcs_writel(GUEST_RIP, 0);
1661 vmcs_writel(GUEST_RSP, 0);
1662
1663 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1664 vmcs_writel(GUEST_DR7, 0x400);
1665
1666 vmcs_writel(GUEST_GDTR_BASE, 0);
1667 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1668
1669 vmcs_writel(GUEST_IDTR_BASE, 0);
1670 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1671
1672 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1673 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1674 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1675
1676 guest_write_tsc(0);
1677
1678 /* Special registers */
1679 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1680
1681 setup_msrs(vmx);
1682
6aa8b732
AK		 1683 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1684
f78e0e2e
SY		 1685 if (cpu_has_vmx_tpr_shadow()) {
1686 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1687 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1688 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1689 page_to_phys(vmx->vcpu.apic->regs_page));
1690 vmcs_write32(TPR_THRESHOLD, 0);
1691 }
1692
1693 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1694 vmcs_write64(APIC_ACCESS_ADDR,
1695 page_to_phys(vmx->vcpu.kvm->apic_access_page));
6aa8b732 1696
8b9cf98c 1697 vmx->vcpu.cr0 = 0x60000010;
d77c26fc 1698 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
8b9cf98c 1699 vmx_set_cr4(&vmx->vcpu, 0);
05b3e0c2 1700#ifdef CONFIG_X86_64
8b9cf98c 1701 vmx_set_efer(&vmx->vcpu, 0);
6aa8b732 1702#endif
8b9cf98c
RR		 1703 vmx_fpu_activate(&vmx->vcpu);
1704 update_exception_bitmap(&vmx->vcpu);
6aa8b732
AK		 1705
1706 return 0;
1707
6aa8b732
AK		 1708out:
1709 return ret;
1710}
1711
85f455f7
ED		 1712static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1713{
1714 if (vcpu->rmode.active) {
9c5623e3
AK		 1715 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1716 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1717 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1718 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) - 1);
85f455f7
ED		 1719 return;
1720 }
1721 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1722 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1723}
1724
6aa8b732
AK		 1725static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1726{
1727 int word_index = __ffs(vcpu->irq_summary);
1728 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1729 int irq = word_index * BITS_PER_LONG + bit_index;
1730
1731 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1732 if (!vcpu->irq_pending[word_index])
1733 clear_bit(word_index, &vcpu->irq_summary);
85f455f7 1734 vmx_inject_irq(vcpu, irq);
6aa8b732
AK		 1735}
1736
c1150d8c
DL		 1737
1738static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1739 struct kvm_run *kvm_run)
6aa8b732 1740{
c1150d8c
DL		 1741 u32 cpu_based_vm_exec_control;
1742
1743 vcpu->interrupt_window_open =
1744 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1745 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1746
1747 if (vcpu->interrupt_window_open &&
1748 vcpu->irq_summary &&
1749 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
6aa8b732 1750 /*
c1150d8c 1751 * If interrupts enabled, and not blocked by sti or mov ss. Good.
6aa8b732
AK		 1752 */
1753 kvm_do_inject_irq(vcpu);
c1150d8c
DL		 1754
1755 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1756 if (!vcpu->interrupt_window_open &&
1757 (vcpu->irq_summary || kvm_run->request_interrupt_window))
6aa8b732
AK		 1758 /*
1759 * Interrupts blocked. Wait for unblock.
1760 */
c1150d8c
DL		 1761 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1762 else
1763 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1764 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6aa8b732
AK		 1765}
1766
cbc94022
IE		 1767static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1768{
1769 int ret;
1770 struct kvm_userspace_memory_region tss_mem = {
1771 .slot = 8,
1772 .guest_phys_addr = addr,
1773 .memory_size = PAGE_SIZE * 3,
1774 .flags = 0,
1775 };
1776
1777 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1778 if (ret)
1779 return ret;
1780 kvm->tss_addr = addr;
1781 return 0;
1782}
1783
6aa8b732
AK		 1784static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1785{
1786 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1787
1788 set_debugreg(dbg->bp[0], 0);
1789 set_debugreg(dbg->bp[1], 1);
1790 set_debugreg(dbg->bp[2], 2);
1791 set_debugreg(dbg->bp[3], 3);
1792
1793 if (dbg->singlestep) {
1794 unsigned long flags;
1795
1796 flags = vmcs_readl(GUEST_RFLAGS);
1797 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1798 vmcs_writel(GUEST_RFLAGS, flags);
1799 }
1800}
1801
1802static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1803 int vec, u32 err_code)
1804{
1805 if (!vcpu->rmode.active)
1806 return 0;
1807
b3f37707
NK		 1808 /*
1809 * Instruction with address size override prefix opcode 0x67
1810 * Cause the #SS fault with 0 error code in VM86 mode.
1811 */
1812 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
3427318f 1813 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
6aa8b732
AK		 1814 return 1;
1815 return 0;
1816}
1817
1818static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1819{
1820 u32 intr_info, error_code;
1821 unsigned long cr2, rip;
1822 u32 vect_info;
1823 enum emulation_result er;
1824
1825 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1826 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1827
1828 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
d77c26fc 1829 !is_page_fault(intr_info))
6aa8b732
AK		 1830 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1831 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
6aa8b732 1832
85f455f7 1833 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
6aa8b732
AK		 1834 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1835 set_bit(irq, vcpu->irq_pending);
1836 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1837 }
1838
1b6269db
AK		 1839 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1840 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 1841
1842 if (is_no_device(intr_info)) {
5fd86fcf 1843 vmx_fpu_activate(vcpu);
2ab455cc
AL		 1844 return 1;
1845 }
1846
7aa81cc0 1847 if (is_invalid_opcode(intr_info)) {
3427318f 1848 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
7aa81cc0
AL		 1849 if (er != EMULATE_DONE)
1850 vmx_inject_ud(vcpu);
1851
1852 return 1;
1853 }
1854
6aa8b732
AK		 1855 error_code = 0;
1856 rip = vmcs_readl(GUEST_RIP);
1857 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1858 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1859 if (is_page_fault(intr_info)) {
1860 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3067714c 1861 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 1862 }
1863
1864 if (vcpu->rmode.active &&
1865 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0
AK		 1866 error_code)) {
1867 if (vcpu->halt_request) {
1868 vcpu->halt_request = 0;
1869 return kvm_emulate_halt(vcpu);
1870 }
6aa8b732 1871 return 1;
72d6e5a0 1872 }
6aa8b732 1873
d77c26fc
MD		 1874 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1875 (INTR_TYPE_EXCEPTION | 1)) {
6aa8b732
AK		 1876 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1877 return 0;
1878 }
1879 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1880 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1881 kvm_run->ex.error_code = error_code;
1882 return 0;
1883}
1884
1885static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1886 struct kvm_run *kvm_run)
1887{
1165f5fe 1888 ++vcpu->stat.irq_exits;
6aa8b732
AK		 1889 return 1;
1890}
1891
988ad74f
AK		 1892static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1893{
1894 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1895 return 0;
1896}
6aa8b732 1897
6aa8b732
AK		 1898static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1899{
bfdaab09 1900 unsigned long exit_qualification;
039576c0
AK		 1901 int size, down, in, string, rep;
1902 unsigned port;
6aa8b732 1903
1165f5fe 1904 ++vcpu->stat.io_exits;
bfdaab09 1905 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 1906 string = (exit_qualification & 16) != 0;
e70669ab
LV		 1907
1908 if (string) {
3427318f
LV		 1909 if (emulate_instruction(vcpu,
1910 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
e70669ab
LV		 1911 return 0;
1912 return 1;
1913 }
1914
1915 size = (exit_qualification & 7) + 1;
1916 in = (exit_qualification & 8) != 0;
039576c0 1917 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
039576c0
AK		 1918 rep = (exit_qualification & 32) != 0;
1919 port = exit_qualification >> 16;
e70669ab 1920
3090dd73 1921 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
6aa8b732
AK		 1922}
1923
102d8325
IM		 1924static void
1925vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1926{
1927 /*
1928 * Patch in the VMCALL instruction:
1929 */
1930 hypercall[0] = 0x0f;
1931 hypercall[1] = 0x01;
1932 hypercall[2] = 0xc1;
102d8325
IM		 1933}
1934
6aa8b732
AK		 1935static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1936{
bfdaab09 1937 unsigned long exit_qualification;
6aa8b732
AK		 1938 int cr;
1939 int reg;
1940
bfdaab09 1941 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 1942 cr = exit_qualification & 15;
1943 reg = (exit_qualification >> 8) & 15;
1944 switch ((exit_qualification >> 4) & 3) {
1945 case 0: /* mov to cr */
1946 switch (cr) {
1947 case 0:
1948 vcpu_load_rsp_rip(vcpu);
1949 set_cr0(vcpu, vcpu->regs[reg]);
1950 skip_emulated_instruction(vcpu);
1951 return 1;
1952 case 3:
1953 vcpu_load_rsp_rip(vcpu);
1954 set_cr3(vcpu, vcpu->regs[reg]);
1955 skip_emulated_instruction(vcpu);
1956 return 1;
1957 case 4:
1958 vcpu_load_rsp_rip(vcpu);
1959 set_cr4(vcpu, vcpu->regs[reg]);
1960 skip_emulated_instruction(vcpu);
1961 return 1;
1962 case 8:
1963 vcpu_load_rsp_rip(vcpu);
1964 set_cr8(vcpu, vcpu->regs[reg]);
1965 skip_emulated_instruction(vcpu);
253abdee
YS		 1966 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1967 return 0;
6aa8b732
AK		 1968 };
1969 break;
25c4c276
AL		 1970 case 2: /* clts */
1971 vcpu_load_rsp_rip(vcpu);
5fd86fcf 1972 vmx_fpu_deactivate(vcpu);
707d92fa 1973 vcpu->cr0 &= ~X86_CR0_TS;
2ab455cc 1974 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
5fd86fcf 1975 vmx_fpu_activate(vcpu);
25c4c276
AL		 1976 skip_emulated_instruction(vcpu);
1977 return 1;
6aa8b732
AK		 1978 case 1: /*mov from cr*/
1979 switch (cr) {
1980 case 3:
1981 vcpu_load_rsp_rip(vcpu);
1982 vcpu->regs[reg] = vcpu->cr3;
1983 vcpu_put_rsp_rip(vcpu);
1984 skip_emulated_instruction(vcpu);
1985 return 1;
1986 case 8:
6aa8b732 1987 vcpu_load_rsp_rip(vcpu);
7017fc3d 1988 vcpu->regs[reg] = get_cr8(vcpu);
6aa8b732
AK		 1989 vcpu_put_rsp_rip(vcpu);
1990 skip_emulated_instruction(vcpu);
1991 return 1;
1992 }
1993 break;
1994 case 3: /* lmsw */
1995 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1996
1997 skip_emulated_instruction(vcpu);
1998 return 1;
1999 default:
2000 break;
2001 }
2002 kvm_run->exit_reason = 0;
f0242478 2003 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 2004 (int)(exit_qualification >> 4) & 3, cr);
2005 return 0;
2006}
2007
2008static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2009{
bfdaab09 2010 unsigned long exit_qualification;
6aa8b732
AK		 2011 unsigned long val;
2012 int dr, reg;
2013
2014 /*
2015 * FIXME: this code assumes the host is debugging the guest.
2016 * need to deal with guest debugging itself too.
2017 */
bfdaab09 2018 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 2019 dr = exit_qualification & 7;
2020 reg = (exit_qualification >> 8) & 15;
2021 vcpu_load_rsp_rip(vcpu);
2022 if (exit_qualification & 16) {
2023 /* mov from dr */
2024 switch (dr) {
2025 case 6:
2026 val = 0xffff0ff0;
2027 break;
2028 case 7:
2029 val = 0x400;
2030 break;
2031 default:
2032 val = 0;
2033 }
2034 vcpu->regs[reg] = val;
2035 } else {
2036 /* mov to dr */
2037 }
2038 vcpu_put_rsp_rip(vcpu);
2039 skip_emulated_instruction(vcpu);
2040 return 1;
2041}
2042
2043static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2044{
06465c5a
AK		 2045 kvm_emulate_cpuid(vcpu);
2046 return 1;
6aa8b732
AK		 2047}
2048
2049static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2050{
2051 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2052 u64 data;
2053
2054 if (vmx_get_msr(vcpu, ecx, &data)) {
2055 vmx_inject_gp(vcpu, 0);
2056 return 1;
2057 }
2058
2059 /* FIXME: handling of bits 32:63 of rax, rdx */
2060 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2061 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2062 skip_emulated_instruction(vcpu);
2063 return 1;
2064}
2065
2066static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2067{
2068 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2069 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2070 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2071
2072 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2073 vmx_inject_gp(vcpu, 0);
2074 return 1;
2075 }
2076
2077 skip_emulated_instruction(vcpu);
2078 return 1;
2079}
2080
6e5d865c
YS		 2081static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2082 struct kvm_run *kvm_run)
2083{
2084 return 1;
2085}
2086
6aa8b732
AK		 2087static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2088 struct kvm_run *kvm_run)
2089{
85f455f7
ED		 2090 u32 cpu_based_vm_exec_control;
2091
2092 /* clear pending irq */
2093 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2094 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2095 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
c1150d8c
DL		 2096 /*
2097 * If the user space waits to inject interrupts, exit as soon as
2098 * possible
2099 */
2100 if (kvm_run->request_interrupt_window &&
022a9308 2101 !vcpu->irq_summary) {
c1150d8c 2102 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1165f5fe 2103 ++vcpu->stat.irq_window_exits;
c1150d8c
DL		 2104 return 0;
2105 }
6aa8b732
AK		 2106 return 1;
2107}
2108
2109static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2110{
2111 skip_emulated_instruction(vcpu);
d3bef15f 2112 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 2113}
2114
c21415e8
IM		 2115static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2116{
510043da 2117 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 2118 kvm_emulate_hypercall(vcpu);
2119 return 1;
c21415e8
IM		 2120}
2121
f78e0e2e
SY		 2122static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2123{
2124 u64 exit_qualification;
2125 enum emulation_result er;
2126 unsigned long offset;
2127
2128 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2129 offset = exit_qualification & 0xffful;
2130
2131 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2132
2133 if (er != EMULATE_DONE) {
2134 printk(KERN_ERR
2135 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2136 offset);
2137 return -ENOTSUPP;
2138 }
2139 return 1;
2140}
2141
6aa8b732
AK		 2142/*
2143 * The exit handlers return 1 if the exit was handled fully and guest execution
2144 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2145 * to be done to userspace and return 0.
2146 */
2147static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2148 struct kvm_run *kvm_run) = {
2149 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2150 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 2151 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
6aa8b732 2152 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 2153 [EXIT_REASON_CR_ACCESS] = handle_cr,
2154 [EXIT_REASON_DR_ACCESS] = handle_dr,
2155 [EXIT_REASON_CPUID] = handle_cpuid,
2156 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2157 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2158 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2159 [EXIT_REASON_HLT] = handle_halt,
c21415e8 2160 [EXIT_REASON_VMCALL] = handle_vmcall,
f78e0e2e
SY		 2161 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2162 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
6aa8b732
AK		 2163};
2164
2165static const int kvm_vmx_max_exit_handlers =
50a3485c 2166 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 2167
2168/*
2169 * The guest has exited. See if we can fix it or if we need userspace
2170 * assistance.
2171 */
2172static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2173{
2174 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2175 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
29bd8a78
AK		 2176 struct vcpu_vmx *vmx = to_vmx(vcpu);
2177
2178 if (unlikely(vmx->fail)) {
2179 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2180 kvm_run->fail_entry.hardware_entry_failure_reason
2181 = vmcs_read32(VM_INSTRUCTION_ERROR);
2182 return 0;
2183 }
6aa8b732 2184
d77c26fc
MD		 2185 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2186 exit_reason != EXIT_REASON_EXCEPTION_NMI)
6aa8b732
AK		 2187 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2188 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
6aa8b732
AK		 2189 if (exit_reason < kvm_vmx_max_exit_handlers
2190 && kvm_vmx_exit_handlers[exit_reason])
2191 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2192 else {
2193 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2194 kvm_run->hw.hardware_exit_reason = exit_reason;
2195 }
2196 return 0;
2197}
2198
d9e368d6
AK		 2199static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2200{
d9e368d6
AK		 2201}
2202
6e5d865c
YS		 2203static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2204{
2205 int max_irr, tpr;
2206
2207 if (!vm_need_tpr_shadow(vcpu->kvm))
2208 return;
2209
2210 if (!kvm_lapic_enabled(vcpu) ||
2211 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2212 vmcs_write32(TPR_THRESHOLD, 0);
2213 return;
2214 }
2215
2216 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2217 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2218}
2219
85f455f7
ED		 2220static void enable_irq_window(struct kvm_vcpu *vcpu)
2221{
2222 u32 cpu_based_vm_exec_control;
2223
2224 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2225 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2226 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2227}
2228
2229static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2230{
2231 u32 idtv_info_field, intr_info_field;
2232 int has_ext_irq, interrupt_window_open;
1b9778da 2233 int vector;
85f455f7 2234
6e5d865c
YS		 2235 update_tpr_threshold(vcpu);
2236
85f455f7
ED		 2237 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2238 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2239 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2240 if (intr_info_field & INTR_INFO_VALID_MASK) {
2241 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2242 /* TODO: fault when IDT_Vectoring */
2243 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2244 }
2245 if (has_ext_irq)
2246 enable_irq_window(vcpu);
2247 return;
2248 }
2249 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2250 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2251 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2252 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2253
2254 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2255 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2256 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2257 if (unlikely(has_ext_irq))
2258 enable_irq_window(vcpu);
2259 return;
2260 }
2261 if (!has_ext_irq)
2262 return;
2263 interrupt_window_open =
2264 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2265 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1b9778da
ED		 2266 if (interrupt_window_open) {
2267 vector = kvm_cpu_get_interrupt(vcpu);
2268 vmx_inject_irq(vcpu, vector);
2269 kvm_timer_intr_post(vcpu, vector);
2270 } else
85f455f7
ED		 2271 enable_irq_window(vcpu);
2272}
2273
04d2cc77 2274static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6aa8b732 2275{
a2fa3e9f 2276 struct vcpu_vmx *vmx = to_vmx(vcpu);
1b6269db 2277 u32 intr_info;
e6adf283
AK		 2278
2279 /*
2280 * Loading guest fpu may have cleared host cr0.ts
2281 */
2282 vmcs_writel(HOST_CR0, read_cr0());
2283
d77c26fc 2284 asm(
6aa8b732 2285 /* Store host registers */
05b3e0c2 2286#ifdef CONFIG_X86_64
c2036300 2287 "push %%rdx; push %%rbp;"
6aa8b732 2288 "push %%rcx \n\t"
6aa8b732 2289#else
ff593e5a
LV		 2290 "push %%edx; push %%ebp;"
2291 "push %%ecx \n\t"
6aa8b732 2292#endif
c2036300 2293 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
6aa8b732
AK		 2294 /* Check if vmlaunch of vmresume is needed */
2295 "cmp $0, %1 \n\t"
2296 /* Load guest registers. Don't clobber flags. */
05b3e0c2 2297#ifdef CONFIG_X86_64
6aa8b732
AK		 2298 "mov %c[cr2](%3), %%rax \n\t"
2299 "mov %%rax, %%cr2 \n\t"
2300 "mov %c[rax](%3), %%rax \n\t"
2301 "mov %c[rbx](%3), %%rbx \n\t"
2302 "mov %c[rdx](%3), %%rdx \n\t"
2303 "mov %c[rsi](%3), %%rsi \n\t"
2304 "mov %c[rdi](%3), %%rdi \n\t"
2305 "mov %c[rbp](%3), %%rbp \n\t"
2306 "mov %c[r8](%3), %%r8 \n\t"
2307 "mov %c[r9](%3), %%r9 \n\t"
2308 "mov %c[r10](%3), %%r10 \n\t"
2309 "mov %c[r11](%3), %%r11 \n\t"
2310 "mov %c[r12](%3), %%r12 \n\t"
2311 "mov %c[r13](%3), %%r13 \n\t"
2312 "mov %c[r14](%3), %%r14 \n\t"
2313 "mov %c[r15](%3), %%r15 \n\t"
2314 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2315#else
2316 "mov %c[cr2](%3), %%eax \n\t"
2317 "mov %%eax, %%cr2 \n\t"
2318 "mov %c[rax](%3), %%eax \n\t"
2319 "mov %c[rbx](%3), %%ebx \n\t"
2320 "mov %c[rdx](%3), %%edx \n\t"
2321 "mov %c[rsi](%3), %%esi \n\t"
2322 "mov %c[rdi](%3), %%edi \n\t"
2323 "mov %c[rbp](%3), %%ebp \n\t"
2324 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2325#endif
2326 /* Enter guest mode */
cd2276a7 2327 "jne .Llaunched \n\t"
6aa8b732 2328 ASM_VMX_VMLAUNCH "\n\t"
cd2276a7
AK		 2329 "jmp .Lkvm_vmx_return \n\t"
2330 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2331 ".Lkvm_vmx_return: "
6aa8b732 2332 /* Save guest registers, load host registers, keep flags */
05b3e0c2 2333#ifdef CONFIG_X86_64
96958231 2334 "xchg %3, (%%rsp) \n\t"
6aa8b732
AK		 2335 "mov %%rax, %c[rax](%3) \n\t"
2336 "mov %%rbx, %c[rbx](%3) \n\t"
96958231 2337 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
6aa8b732
AK		 2338 "mov %%rdx, %c[rdx](%3) \n\t"
2339 "mov %%rsi, %c[rsi](%3) \n\t"
2340 "mov %%rdi, %c[rdi](%3) \n\t"
2341 "mov %%rbp, %c[rbp](%3) \n\t"
2342 "mov %%r8, %c[r8](%3) \n\t"
2343 "mov %%r9, %c[r9](%3) \n\t"
2344 "mov %%r10, %c[r10](%3) \n\t"
2345 "mov %%r11, %c[r11](%3) \n\t"
2346 "mov %%r12, %c[r12](%3) \n\t"
2347 "mov %%r13, %c[r13](%3) \n\t"
2348 "mov %%r14, %c[r14](%3) \n\t"
2349 "mov %%r15, %c[r15](%3) \n\t"
2350 "mov %%cr2, %%rax \n\t"
2351 "mov %%rax, %c[cr2](%3) \n\t"
6aa8b732 2352
c2036300 2353 "pop %%rcx; pop %%rbp; pop %%rdx \n\t"
6aa8b732 2354#else
96958231 2355 "xchg %3, (%%esp) \n\t"
6aa8b732
AK		 2356 "mov %%eax, %c[rax](%3) \n\t"
2357 "mov %%ebx, %c[rbx](%3) \n\t"
96958231 2358 "pushl (%%esp); popl %c[rcx](%3) \n\t"
6aa8b732
AK		 2359 "mov %%edx, %c[rdx](%3) \n\t"
2360 "mov %%esi, %c[rsi](%3) \n\t"
2361 "mov %%edi, %c[rdi](%3) \n\t"
2362 "mov %%ebp, %c[rbp](%3) \n\t"
2363 "mov %%cr2, %%eax \n\t"
2364 "mov %%eax, %c[cr2](%3) \n\t"
6aa8b732 2365
ff593e5a 2366 "pop %%ecx; pop %%ebp; pop %%edx \n\t"
6aa8b732
AK		 2367#endif
2368 "setbe %0 \n\t"
29bd8a78 2369 : "=q" (vmx->fail)
a2fa3e9f 2370 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
6aa8b732
AK		 2371 "c"(vcpu),
2372 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2373 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2374 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2375 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2376 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2377 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2378 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
05b3e0c2 2379#ifdef CONFIG_X86_64
d77c26fc
MD		 2380 [r8]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8])),
2381 [r9]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9])),
6aa8b732
AK		 2382 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2383 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2384 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2385 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2386 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2387 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2388#endif
2389 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
c2036300
LV		 2390 : "cc", "memory"
2391#ifdef CONFIG_X86_64
2392 , "rbx", "rdi", "rsi"
2393 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
ff593e5a
LV		 2394#else
2395 , "ebx", "edi", "rsi"
c2036300
LV		 2396#endif
2397 );
6aa8b732 2398
d77c26fc
MD		 2399 vcpu->interrupt_window_open =
2400 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
6aa8b732 2401
d77c26fc 2402 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 2403 vmx->launched = 1;
1b6269db
AK		 2404
2405 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2406
2407 /* We need to handle NMIs before interrupts are enabled */
2408 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2409 asm("int $2");
6aa8b732
AK		 2410}
2411
6aa8b732
AK		 2412static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2413 unsigned long addr,
2414 u32 err_code)
2415{
2416 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2417
1165f5fe 2418 ++vcpu->stat.pf_guest;
6aa8b732
AK		 2419
2420 if (is_page_fault(vect_info)) {
2421 printk(KERN_DEBUG "inject_page_fault: "
2422 "double fault 0x%lx @ 0x%lx\n",
2423 addr, vmcs_readl(GUEST_RIP));
2424 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2425 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2426 DF_VECTOR |
2427 INTR_TYPE_EXCEPTION |
2428 INTR_INFO_DELIEVER_CODE_MASK |
2429 INTR_INFO_VALID_MASK);
2430 return;
2431 }
2432 vcpu->cr2 = addr;
2433 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2434 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2435 PF_VECTOR |
2436 INTR_TYPE_EXCEPTION |
2437 INTR_INFO_DELIEVER_CODE_MASK |
2438 INTR_INFO_VALID_MASK);
2439
2440}
2441
2442static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2443{
a2fa3e9f
GH		 2444 struct vcpu_vmx *vmx = to_vmx(vcpu);
2445
2446 if (vmx->vmcs) {
8b9cf98c 2447 on_each_cpu(__vcpu_clear, vmx, 0, 1);
a2fa3e9f
GH		 2448 free_vmcs(vmx->vmcs);
2449 vmx->vmcs = NULL;
6aa8b732
AK		 2450 }
2451}
2452
2453static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2454{
fb3f0f51
RR		 2455 struct vcpu_vmx *vmx = to_vmx(vcpu);
2456
6aa8b732 2457 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 2458 kfree(vmx->host_msrs);
2459 kfree(vmx->guest_msrs);
2460 kvm_vcpu_uninit(vcpu);
a4770347 2461 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 2462}
2463
fb3f0f51 2464static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 2465{
fb3f0f51 2466 int err;
c16f862d 2467 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 2468 int cpu;
6aa8b732 2469
a2fa3e9f 2470 if (!vmx)
fb3f0f51
RR		 2471 return ERR_PTR(-ENOMEM);
2472
2473 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2474 if (err)
2475 goto free_vcpu;
965b58a5 2476
a2fa3e9f 2477 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 2478 if (!vmx->guest_msrs) {
2479 err = -ENOMEM;
2480 goto uninit_vcpu;
2481 }
965b58a5 2482
a2fa3e9f
GH		 2483 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2484 if (!vmx->host_msrs)
fb3f0f51 2485 goto free_guest_msrs;
965b58a5 2486
a2fa3e9f
GH		 2487 vmx->vmcs = alloc_vmcs();
2488 if (!vmx->vmcs)
fb3f0f51 2489 goto free_msrs;
a2fa3e9f
GH		 2490
2491 vmcs_clear(vmx->vmcs);
2492
15ad7146
AK		 2493 cpu = get_cpu();
2494 vmx_vcpu_load(&vmx->vcpu, cpu);
8b9cf98c 2495 err = vmx_vcpu_setup(vmx);
fb3f0f51 2496 vmx_vcpu_put(&vmx->vcpu);
15ad7146 2497 put_cpu();
fb3f0f51
RR		 2498 if (err)
2499 goto free_vmcs;
2500
2501 return &vmx->vcpu;
2502
2503free_vmcs:
2504 free_vmcs(vmx->vmcs);
2505free_msrs:
2506 kfree(vmx->host_msrs);
2507free_guest_msrs:
2508 kfree(vmx->guest_msrs);
2509uninit_vcpu:
2510 kvm_vcpu_uninit(&vmx->vcpu);
2511free_vcpu:
a4770347 2512 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 2513 return ERR_PTR(err);
6aa8b732
AK		 2514}
2515
002c7f7c
YS		 2516static void __init vmx_check_processor_compat(void *rtn)
2517{
2518 struct vmcs_config vmcs_conf;
2519
2520 *(int *)rtn = 0;
2521 if (setup_vmcs_config(&vmcs_conf) < 0)
2522 *(int *)rtn = -EIO;
2523 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2524 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2525 smp_processor_id());
2526 *(int *)rtn = -EIO;
2527 }
2528}
2529
cbdd1bea 2530static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 2531 .cpu_has_kvm_support = cpu_has_kvm_support,
2532 .disabled_by_bios = vmx_disabled_by_bios,
2533 .hardware_setup = hardware_setup,
2534 .hardware_unsetup = hardware_unsetup,
002c7f7c 2535 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 2536 .hardware_enable = hardware_enable,
2537 .hardware_disable = hardware_disable,
2538
2539 .vcpu_create = vmx_create_vcpu,
2540 .vcpu_free = vmx_free_vcpu,
04d2cc77 2541 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 2542
04d2cc77 2543 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 2544 .vcpu_load = vmx_vcpu_load,
2545 .vcpu_put = vmx_vcpu_put,
774c47f1 2546 .vcpu_decache = vmx_vcpu_decache,
6aa8b732
AK		 2547
2548 .set_guest_debug = set_guest_debug,
04d2cc77 2549 .guest_debug_pre = kvm_guest_debug_pre,
6aa8b732
AK		 2550 .get_msr = vmx_get_msr,
2551 .set_msr = vmx_set_msr,
2552 .get_segment_base = vmx_get_segment_base,
2553 .get_segment = vmx_get_segment,
2554 .set_segment = vmx_set_segment,
6aa8b732 2555 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
25c4c276 2556 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 2557 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 2558 .set_cr3 = vmx_set_cr3,
2559 .set_cr4 = vmx_set_cr4,
05b3e0c2 2560#ifdef CONFIG_X86_64
6aa8b732
AK		 2561 .set_efer = vmx_set_efer,
2562#endif
2563 .get_idt = vmx_get_idt,
2564 .set_idt = vmx_set_idt,
2565 .get_gdt = vmx_get_gdt,
2566 .set_gdt = vmx_set_gdt,
2567 .cache_regs = vcpu_load_rsp_rip,
2568 .decache_regs = vcpu_put_rsp_rip,
2569 .get_rflags = vmx_get_rflags,
2570 .set_rflags = vmx_set_rflags,
2571
2572 .tlb_flush = vmx_flush_tlb,
2573 .inject_page_fault = vmx_inject_page_fault,
2574
2575 .inject_gp = vmx_inject_gp,
2576
2577 .run = vmx_vcpu_run,
04d2cc77 2578 .handle_exit = kvm_handle_exit,
6aa8b732 2579 .skip_emulated_instruction = skip_emulated_instruction,
102d8325 2580 .patch_hypercall = vmx_patch_hypercall,
2a8067f1
ED		 2581 .get_irq = vmx_get_irq,
2582 .set_irq = vmx_inject_irq,
04d2cc77
AK		 2583 .inject_pending_irq = vmx_intr_assist,
2584 .inject_pending_vectors = do_interrupt_requests,
cbc94022
IE		 2585
2586 .set_tss_addr = vmx_set_tss_addr,
6aa8b732
AK		 2587};
2588
2589static int __init vmx_init(void)
2590{
fdef3ad1
HQ		 2591 void *iova;
2592 int r;
2593
2594 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2595 if (!vmx_io_bitmap_a)
2596 return -ENOMEM;
2597
2598 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2599 if (!vmx_io_bitmap_b) {
2600 r = -ENOMEM;
2601 goto out;
2602 }
2603
2604 /*
2605 * Allow direct access to the PC debug port (it is often used for I/O
2606 * delays, but the vmexits simply slow things down).
2607 */
2608 iova = kmap(vmx_io_bitmap_a);
2609 memset(iova, 0xff, PAGE_SIZE);
2610 clear_bit(0x80, iova);
cd0536d7 2611 kunmap(vmx_io_bitmap_a);
fdef3ad1
HQ		 2612
2613 iova = kmap(vmx_io_bitmap_b);
2614 memset(iova, 0xff, PAGE_SIZE);
cd0536d7 2615 kunmap(vmx_io_bitmap_b);
fdef3ad1 2616
cbdd1bea 2617 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
fdef3ad1
HQ		 2618 if (r)
2619 goto out1;
2620
c7addb90
AK		 2621 if (bypass_guest_pf)
2622 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2623
fdef3ad1
HQ		 2624 return 0;
2625
2626out1:
2627 __free_page(vmx_io_bitmap_b);
2628out:
2629 __free_page(vmx_io_bitmap_a);
2630 return r;
6aa8b732
AK		 2631}
2632
2633static void __exit vmx_exit(void)
2634{
fdef3ad1
HQ		 2635 __free_page(vmx_io_bitmap_b);
2636 __free_page(vmx_io_bitmap_a);
2637
cbdd1bea 2638 kvm_exit_x86();
6aa8b732
AK		 2639}
2640
2641module_init(vmx_init)
2642module_exit(vmx_exit)
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