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9ea53b74 1/*
11b64d31 2 * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX)
9ea53b74
ML
3 *
4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA
11b64d31
ML
20 *
21 * Special thanks to:
22 * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore
23 * bringing to life support for transmission & learning mode.
24 *
25 * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in
26 * bringing up the support of new firmware buffer that is popular
27 * on latest notebooks
28 *
29 * ENE for partial device documentation
30 *
9ea53b74
ML
31 */
32
7de3461c
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33#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
9ea53b74
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35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pnp.h>
38#include <linux/io.h>
39#include <linux/interrupt.h>
40#include <linux/sched.h>
931e39a1 41#include <linux/slab.h>
6bda9644 42#include <media/rc-core.h>
931e39a1 43#include "ene_ir.h"
9ea53b74 44
11b64d31 45static int sample_period;
c29bc4d7 46static bool learning_mode_force;
9ea53b74 47static int debug;
11b64d31 48static bool txsim;
9ea53b74 49
11b64d31
ML
50static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
51{
52 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
53 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
54}
9ea53b74
ML
55
56/* read a hardware register */
11b64d31 57static u8 ene_read_reg(struct ene_device *dev, u16 reg)
9ea53b74
ML
58{
59 u8 retval;
11b64d31 60 ene_set_reg_addr(dev, reg);
9ea53b74 61 retval = inb(dev->hw_io + ENE_IO);
11b64d31 62 dbg_regs("reg %04x == %02x", reg, retval);
9ea53b74
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63 return retval;
64}
65
66/* write a hardware register */
11b64d31 67static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
9ea53b74 68{
11b64d31
ML
69 dbg_regs("reg %04x <- %02x", reg, value);
70 ene_set_reg_addr(dev, reg);
9ea53b74 71 outb(value, dev->hw_io + ENE_IO);
9ea53b74
ML
72}
73
11b64d31
ML
74/* Set bits in hardware register */
75static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
9ea53b74 76{
11b64d31
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77 dbg_regs("reg %04x |= %02x", reg, mask);
78 ene_set_reg_addr(dev, reg);
79 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
80}
9ea53b74 81
11b64d31
ML
82/* Clear bits in hardware register */
83static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
84{
85 dbg_regs("reg %04x &= ~%02x ", reg, mask);
86 ene_set_reg_addr(dev, reg);
87 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
88}
9ea53b74 89
11b64d31
ML
90/* A helper to set/clear a bit in register according to boolean variable */
91static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
92 bool set)
93{
94 if (set)
95 ene_set_reg_mask(dev, reg, mask);
96 else
97 ene_clear_reg_mask(dev, reg, mask);
9ea53b74
ML
98}
99
100/* detect hardware features */
101static int ene_hw_detect(struct ene_device *dev)
102{
103 u8 chip_major, chip_minor;
104 u8 hw_revision, old_ver;
11b64d31 105 u8 fw_reg2, fw_reg1;
9ea53b74 106
11b64d31
ML
107 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
108 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
109 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
110 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
9ea53b74 111
11b64d31
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112 hw_revision = ene_read_reg(dev, ENE_ECHV);
113 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
9ea53b74 114
11b64d31
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115 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
116 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
931e39a1 117
11b64d31
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118 if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD)
119 dev->rx_period_adjust =
120 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
931e39a1 121
9ea53b74 122 if (hw_revision == 0xFF) {
7de3461c
JP
123 pr_warn("device seems to be disabled\n");
124 pr_warn("send a mail to lirc-list@lists.sourceforge.net\n");
125 pr_warn("please attach output of acpidump and dmidecode\n");
9ea53b74
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126 return -ENODEV;
127 }
128
7de3461c
JP
129 pr_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x\n",
130 chip_major, chip_minor, old_ver, hw_revision);
11b64d31 131
7de3461c 132 pr_notice("PLL freq = %d\n", dev->pll_freq);
11b64d31 133
9ea53b74 134 if (chip_major == 0x33) {
7de3461c 135 pr_warn("chips 0x33xx aren't supported\n");
9ea53b74
ML
136 return -ENODEV;
137 }
138
139 if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
140 dev->hw_revision = ENE_HW_C;
7de3461c 141 pr_notice("KB3926C detected\n");
9ea53b74
ML
142 } else if (old_ver == 0x24 && hw_revision == 0xC0) {
143 dev->hw_revision = ENE_HW_B;
7de3461c 144 pr_notice("KB3926B detected\n");
9ea53b74
ML
145 } else {
146 dev->hw_revision = ENE_HW_D;
7de3461c 147 pr_notice("KB3926D or higher detected\n");
9ea53b74
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148 }
149
9ea53b74
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150 /* detect features hardware supports */
151 if (dev->hw_revision < ENE_HW_C)
152 return 0;
153
11b64d31
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154 fw_reg1 = ene_read_reg(dev, ENE_FW1);
155 fw_reg2 = ene_read_reg(dev, ENE_FW2);
9ea53b74 156
7de3461c 157 pr_notice("Firmware regs: %02x %02x\n", fw_reg1, fw_reg2);
9ea53b74 158
a06423c9
ML
159 dev->hw_use_gpio_0a = !!(fw_reg2 & ENE_FW2_GP0A);
160 dev->hw_learning_and_tx_capable = !!(fw_reg2 & ENE_FW2_LEARNING);
161 dev->hw_extra_buffer = !!(fw_reg1 & ENE_FW1_HAS_EXTRA_BUF);
162
163 if (dev->hw_learning_and_tx_capable)
164 dev->hw_fan_input = !!(fw_reg2 & ENE_FW2_FAN_INPUT);
9ea53b74 165
7de3461c 166 pr_notice("Hardware features:\n");
9ea53b74
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167
168 if (dev->hw_learning_and_tx_capable) {
7de3461c
JP
169 pr_notice("* Supports transmitting & learning mode\n");
170 pr_notice(" This feature is rare and therefore,\n");
171 pr_notice(" you are welcome to test it,\n");
172 pr_notice(" and/or contact the author via:\n");
173 pr_notice(" lirc-list@lists.sourceforge.net\n");
174 pr_notice(" or maximlevitsky@gmail.com\n");
11b64d31 175
7de3461c
JP
176 pr_notice("* Uses GPIO %s for IR raw input\n",
177 dev->hw_use_gpio_0a ? "40" : "0A");
11b64d31
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178
179 if (dev->hw_fan_input)
7de3461c 180 pr_notice("* Uses unused fan feedback input as source of demodulated IR data\n");
9ea53b74 181 }
11b64d31
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182
183 if (!dev->hw_fan_input)
7de3461c
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184 pr_notice("* Uses GPIO %s for IR demodulated input\n",
185 dev->hw_use_gpio_0a ? "0A" : "40");
11b64d31
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186
187 if (dev->hw_extra_buffer)
7de3461c 188 pr_notice("* Uses new style input buffer\n");
9ea53b74
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189 return 0;
190}
191
c29bc4d7
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192/* Read properities of hw sample buffer */
193static void ene_rx_setup_hw_buffer(struct ene_device *dev)
194{
195 u16 tmp;
196
197 ene_rx_read_hw_pointer(dev);
198 dev->r_pointer = dev->w_pointer;
199
200 if (!dev->hw_extra_buffer) {
201 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
202 return;
203 }
204
205 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
206 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
207 dev->extra_buf1_address = tmp;
208
209 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
210
211 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
212 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
213 dev->extra_buf2_address = tmp;
214
215 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
216
217 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
218
7de3461c
JP
219 pr_notice("Hardware uses 2 extended buffers:\n");
220 pr_notice(" 0x%04x - len : %d\n",
221 dev->extra_buf1_address, dev->extra_buf1_len);
222 pr_notice(" 0x%04x - len : %d\n",
223 dev->extra_buf2_address, dev->extra_buf2_len);
c29bc4d7 224
7de3461c 225 pr_notice("Total buffer len = %d\n", dev->buffer_len);
c29bc4d7
ML
226
227 if (dev->buffer_len > 64 || dev->buffer_len < 16)
228 goto error;
229
230 if (dev->extra_buf1_address > 0xFBFC ||
231 dev->extra_buf1_address < 0xEC00)
232 goto error;
233
234 if (dev->extra_buf2_address > 0xFBFC ||
235 dev->extra_buf2_address < 0xEC00)
236 goto error;
237
238 if (dev->r_pointer > dev->buffer_len)
239 goto error;
240
241 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
242 return;
243error:
7de3461c 244 pr_warn("Error validating extra buffers, device probably won't work\n");
c29bc4d7
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245 dev->hw_extra_buffer = false;
246 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
247}
248
249
250/* Restore the pointers to extra buffers - to make module reload work*/
251static void ene_rx_restore_hw_buffer(struct ene_device *dev)
252{
253 if (!dev->hw_extra_buffer)
254 return;
255
256 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
257 dev->extra_buf1_address & 0xFF);
258 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
259 dev->extra_buf1_address >> 8);
260 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
261
262 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
263 dev->extra_buf2_address & 0xFF);
264 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
265 dev->extra_buf2_address >> 8);
266 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
267 dev->extra_buf2_len);
268 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
269}
270
271/* Read hardware write pointer */
272static void ene_rx_read_hw_pointer(struct ene_device *dev)
273{
274 if (dev->hw_extra_buffer)
275 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
276 else
277 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
278 & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE;
279
280 dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x",
281 dev->w_pointer, dev->r_pointer);
282}
283
284/* Gets address of next sample from HW ring buffer */
285static int ene_rx_get_sample_reg(struct ene_device *dev)
286{
287 int r_pointer;
288
289 if (dev->r_pointer == dev->w_pointer) {
290 dbg_verbose("RB: hit end, try update w_pointer");
291 ene_rx_read_hw_pointer(dev);
292 }
293
294 if (dev->r_pointer == dev->w_pointer) {
295 dbg_verbose("RB: end of data at %d", dev->r_pointer);
296 return 0;
297 }
298
299 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
300 r_pointer = dev->r_pointer;
301
302 dev->r_pointer++;
303 if (dev->r_pointer == dev->buffer_len)
304 dev->r_pointer = 0;
305
306 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
307
308 if (r_pointer < 8) {
309 dbg_verbose("RB: read at main buffer at %d", r_pointer);
310 return ENE_FW_SAMPLE_BUFFER + r_pointer;
311 }
312
313 r_pointer -= 8;
314
315 if (r_pointer < dev->extra_buf1_len) {
316 dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer);
317 return dev->extra_buf1_address + r_pointer;
318 }
319
320 r_pointer -= dev->extra_buf1_len;
321
322 if (r_pointer < dev->extra_buf2_len) {
323 dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer);
324 return dev->extra_buf2_address + r_pointer;
325 }
326
90802ed9 327 dbg("attempt to read beyond ring buffer end");
c29bc4d7
ML
328 return 0;
329}
330
11b64d31
ML
331/* Sense current received carrier */
332void ene_rx_sense_carrier(struct ene_device *dev)
9ea53b74 333{
e1b1ddbe
ML
334 DEFINE_IR_RAW_EVENT(ev);
335
336 int carrier, duty_cycle;
11b64d31
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337 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
338 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
11b64d31
ML
339
340 if (!(period & ENE_CIRCAR_PRD_VALID))
341 return;
342
343 period &= ~ENE_CIRCAR_PRD_VALID;
344
345 if (!period)
346 return;
347
348 dbg("RX: hardware carrier period = %02x", period);
349 dbg("RX: hardware carrier pulse period = %02x", hperiod);
350
11b64d31
ML
351 carrier = 2000000 / period;
352 duty_cycle = (hperiod * 100) / period;
353 dbg("RX: sensed carrier = %d Hz, duty cycle %d%%",
e1b1ddbe
ML
354 carrier, duty_cycle);
355 if (dev->carrier_detect_enabled) {
356 ev.carrier_report = true;
357 ev.carrier = carrier;
358 ev.duty_cycle = duty_cycle;
d8b4b582 359 ir_raw_event_store(dev->rdev, &ev);
e1b1ddbe 360 }
9ea53b74
ML
361}
362
11b64d31 363/* this enables/disables the CIR RX engine */
c29bc4d7 364static void ene_rx_enable_cir_engine(struct ene_device *dev, bool enable)
9ea53b74 365{
11b64d31
ML
366 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
367 ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable);
9ea53b74
ML
368}
369
11b64d31 370/* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/
c29bc4d7 371static void ene_rx_select_input(struct ene_device *dev, bool gpio_0a)
9ea53b74 372{
11b64d31 373 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
9ea53b74
ML
374}
375
11b64d31
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376/*
377 * this enables alternative input via fan tachometer sensor and bypasses
378 * the hw CIR engine
379 */
c29bc4d7 380static void ene_rx_enable_fan_input(struct ene_device *dev, bool enable)
9ea53b74 381{
11b64d31
ML
382 if (!dev->hw_fan_input)
383 return;
9ea53b74 384
11b64d31
ML
385 if (!enable)
386 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
387 else {
388 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
389 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
390 }
9ea53b74
ML
391}
392
11b64d31
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393/* setup the receiver for RX*/
394static void ene_rx_setup(struct ene_device *dev)
9ea53b74 395{
c29bc4d7 396 bool learning_mode = dev->learning_mode_enabled ||
11b64d31
ML
397 dev->carrier_detect_enabled;
398 int sample_period_adjust = 0;
9ea53b74 399
c29bc4d7
ML
400 dbg("RX: setup receiver, learning mode = %d", learning_mode);
401
402
a06423c9
ML
403 /* This selects RLC input and clears CFG2 settings */
404 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
9ea53b74 405
11b64d31
ML
406 /* set sample period*/
407 if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD)
408 sample_period_adjust =
409 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
9ea53b74 410
11b64d31
ML
411 ene_write_reg(dev, ENE_CIRRLC_CFG,
412 (sample_period + sample_period_adjust) |
413 ENE_CIRRLC_CFG_OVERFLOW);
414 /* revB doesn't support inputs */
415 if (dev->hw_revision < ENE_HW_C)
416 goto select_timeout;
9ea53b74 417
a06423c9
ML
418 if (learning_mode) {
419
420 WARN_ON(!dev->hw_learning_and_tx_capable);
9ea53b74 421
11b64d31
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422 /* Enable the opposite of the normal input
423 That means that if GPIO40 is normally used, use GPIO0A
424 and vice versa.
425 This input will carry non demodulated
426 signal, and we will tell the hw to demodulate it itself */
c29bc4d7 427 ene_rx_select_input(dev, !dev->hw_use_gpio_0a);
11b64d31 428 dev->rx_fan_input_inuse = false;
9ea53b74 429
11b64d31
ML
430 /* Enable carrier demodulation */
431 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
9ea53b74 432
11b64d31 433 /* Enable carrier detection */
a06423c9 434 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
11b64d31
ML
435 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
436 dev->carrier_detect_enabled || debug);
9ea53b74 437 } else {
11b64d31
ML
438 if (dev->hw_fan_input)
439 dev->rx_fan_input_inuse = true;
440 else
c29bc4d7 441 ene_rx_select_input(dev, dev->hw_use_gpio_0a);
11b64d31
ML
442
443 /* Disable carrier detection & demodulation */
444 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
445 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
9ea53b74
ML
446 }
447
11b64d31 448select_timeout:
931e39a1 449 if (dev->rx_fan_input_inuse) {
5aad7242 450 dev->rdev->rx_resolution = US_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN);
931e39a1 451
11b64d31
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452 /* Fan input doesn't support timeouts, it just ends the
453 input with a maximum sample */
d8b4b582 454 dev->rdev->min_timeout = dev->rdev->max_timeout =
5aad7242 455 US_TO_NS(ENE_FW_SMPL_BUF_FAN_MSK *
11b64d31 456 ENE_FW_SAMPLE_PERIOD_FAN);
931e39a1 457 } else {
5aad7242 458 dev->rdev->rx_resolution = US_TO_NS(sample_period);
11b64d31
ML
459
460 /* Theoreticly timeout is unlimited, but we cap it
461 * because it was seen that on one device, it
462 * would stop sending spaces after around 250 msec.
463 * Besides, this is close to 2^32 anyway and timeout is u32.
464 */
5aad7242
JW
465 dev->rdev->min_timeout = US_TO_NS(127 * sample_period);
466 dev->rdev->max_timeout = US_TO_NS(200000);
931e39a1 467 }
11b64d31
ML
468
469 if (dev->hw_learning_and_tx_capable)
5aad7242 470 dev->rdev->tx_resolution = US_TO_NS(sample_period);
11b64d31 471
d8b4b582
DH
472 if (dev->rdev->timeout > dev->rdev->max_timeout)
473 dev->rdev->timeout = dev->rdev->max_timeout;
474 if (dev->rdev->timeout < dev->rdev->min_timeout)
475 dev->rdev->timeout = dev->rdev->min_timeout;
9ea53b74
ML
476}
477
478/* Enable the device for receive */
479static void ene_rx_enable(struct ene_device *dev)
480{
481 u8 reg_value;
482
11b64d31 483 /* Enable system interrupt */
9ea53b74 484 if (dev->hw_revision < ENE_HW_C) {
11b64d31
ML
485 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
486 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
9ea53b74 487 } else {
11b64d31
ML
488 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
489 reg_value |= ENE_IRQ_UNK_EN;
490 reg_value &= ~ENE_IRQ_STATUS;
491 reg_value |= (dev->irq & ENE_IRQ_MASK);
492 ene_write_reg(dev, ENE_IRQ, reg_value);
9ea53b74
ML
493 }
494
a06423c9 495 /* Enable inputs */
c29bc4d7
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496 ene_rx_enable_fan_input(dev, dev->rx_fan_input_inuse);
497 ene_rx_enable_cir_engine(dev, !dev->rx_fan_input_inuse);
9ea53b74
ML
498
499 /* ack any pending irqs - just in case */
500 ene_irq_status(dev);
501
9ea53b74 502 /* enable firmware bits */
11b64d31 503 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
931e39a1
ML
504
505 /* enter idle mode */
d8b4b582 506 ir_raw_event_set_idle(dev->rdev, true);
11b64d31 507 dev->rx_enabled = true;
9ea53b74
ML
508}
509
931e39a1 510/* Disable the device receiver */
9ea53b74
ML
511static void ene_rx_disable(struct ene_device *dev)
512{
513 /* disable inputs */
c29bc4d7
ML
514 ene_rx_enable_cir_engine(dev, false);
515 ene_rx_enable_fan_input(dev, false);
9ea53b74
ML
516
517 /* disable hardware IRQ and firmware flag */
11b64d31 518 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
9ea53b74 519
d8b4b582 520 ir_raw_event_set_idle(dev->rdev, true);
11b64d31 521 dev->rx_enabled = false;
9ea53b74
ML
522}
523
25985edc 524/* This resets the receiver. Useful to stop stream of spaces at end of
c29bc4d7
ML
525 * transmission
526 */
527static void ene_rx_reset(struct ene_device *dev)
528{
529 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
530 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
531}
532
533/* Set up the TX carrier frequency and duty cycle */
534static void ene_tx_set_carrier(struct ene_device *dev)
535{
536 u8 tx_puls_width;
537 unsigned long flags;
538
539 spin_lock_irqsave(&dev->hw_lock, flags);
540
541 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
542 ENE_CIRCFG_TX_CARR, dev->tx_period > 0);
543
544 if (!dev->tx_period)
545 goto unlock;
546
547 BUG_ON(dev->tx_duty_cycle >= 100 || dev->tx_duty_cycle <= 0);
548
549 tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
550
551 if (!tx_puls_width)
552 tx_puls_width = 1;
553
554 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
555 dbg("TX: pulse width = %d * 500 ns", tx_puls_width);
556
557 ene_write_reg(dev, ENE_CIRMOD_PRD, dev->tx_period | ENE_CIRMOD_PRD_POL);
558 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
559unlock:
560 spin_unlock_irqrestore(&dev->hw_lock, flags);
561}
562
563/* Enable/disable transmitters */
564static void ene_tx_set_transmitters(struct ene_device *dev)
565{
566 unsigned long flags;
567
568 spin_lock_irqsave(&dev->hw_lock, flags);
569 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
570 !!(dev->transmitter_mask & 0x01));
571 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
572 !!(dev->transmitter_mask & 0x02));
573 spin_unlock_irqrestore(&dev->hw_lock, flags);
574}
575
9ea53b74 576/* prepare transmission */
c29bc4d7 577static void ene_tx_enable(struct ene_device *dev)
9ea53b74 578{
11b64d31
ML
579 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
580 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
9ea53b74 581
9ea53b74
ML
582 dev->saved_conf1 = conf1;
583
11b64d31
ML
584 /* Show information about currently connected transmitter jacks */
585 if (fwreg2 & ENE_FW2_EMMITER1_CONN)
586 dbg("TX: Transmitter #1 is connected");
9ea53b74 587
11b64d31
ML
588 if (fwreg2 & ENE_FW2_EMMITER2_CONN)
589 dbg("TX: Transmitter #2 is connected");
9ea53b74 590
11b64d31 591 if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN)))
7de3461c 592 pr_warn("TX: transmitter cable isn't connected!\n");
11b64d31 593
11b64d31
ML
594 /* disable receive on revc */
595 if (dev->hw_revision == ENE_HW_C)
596 conf1 &= ~ENE_CIRCFG_RX_EN;
9ea53b74 597
11b64d31
ML
598 /* Enable TX engine */
599 conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ;
600 ene_write_reg(dev, ENE_CIRCFG, conf1);
9ea53b74
ML
601}
602
603/* end transmission */
c29bc4d7 604static void ene_tx_disable(struct ene_device *dev)
9ea53b74 605{
11b64d31 606 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
931e39a1 607 dev->tx_buffer = NULL;
9ea53b74
ML
608}
609
9ea53b74
ML
610
611/* TX one sample - must be called with dev->hw_lock*/
612static void ene_tx_sample(struct ene_device *dev)
613{
614 u8 raw_tx;
615 u32 sample;
11b64d31 616 bool pulse = dev->tx_sample_pulse;
9ea53b74 617
931e39a1 618 if (!dev->tx_buffer) {
7de3461c 619 pr_warn("TX: BUG: attempt to transmit NULL buffer\n");
9ea53b74
ML
620 return;
621 }
622
623 /* Grab next TX sample */
624 if (!dev->tx_sample) {
11b64d31
ML
625
626 if (dev->tx_pos == dev->tx_len) {
9ea53b74 627 if (!dev->tx_done) {
11b64d31
ML
628 dbg("TX: no more data to send");
629 dev->tx_done = true;
9ea53b74
ML
630 goto exit;
631 } else {
11b64d31 632 dbg("TX: last sample sent by hardware");
c29bc4d7 633 ene_tx_disable(dev);
9ea53b74
ML
634 complete(&dev->tx_complete);
635 return;
636 }
637 }
638
639 sample = dev->tx_buffer[dev->tx_pos++];
640 dev->tx_sample_pulse = !dev->tx_sample_pulse;
641
11b64d31 642 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
9ea53b74 643
9ea53b74 644 if (!dev->tx_sample)
11b64d31 645 dev->tx_sample = 1;
9ea53b74
ML
646 }
647
11b64d31 648 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
9ea53b74
ML
649 dev->tx_sample -= raw_tx;
650
11b64d31
ML
651 dbg("TX: sample %8d (%s)", raw_tx * sample_period,
652 pulse ? "pulse" : "space");
653 if (pulse)
654 raw_tx |= ENE_CIRRLC_OUT_PULSE;
655
656 ene_write_reg(dev,
657 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
9ea53b74 658
9ea53b74
ML
659 dev->tx_reg = !dev->tx_reg;
660exit:
661 /* simulate TX done interrupt */
662 if (txsim)
663 mod_timer(&dev->tx_sim_timer, jiffies + HZ / 500);
664}
665
666/* timer to simulate tx done interrupt */
667static void ene_tx_irqsim(unsigned long data)
668{
669 struct ene_device *dev = (struct ene_device *)data;
670 unsigned long flags;
671
672 spin_lock_irqsave(&dev->hw_lock, flags);
673 ene_tx_sample(dev);
674 spin_unlock_irqrestore(&dev->hw_lock, flags);
675}
676
677
678/* read irq status and ack it */
679static int ene_irq_status(struct ene_device *dev)
680{
681 u8 irq_status;
682 u8 fw_flags1, fw_flags2;
9ea53b74
ML
683 int retval = 0;
684
11b64d31 685 fw_flags2 = ene_read_reg(dev, ENE_FW2);
9ea53b74
ML
686
687 if (dev->hw_revision < ENE_HW_C) {
11b64d31 688 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
9ea53b74
ML
689
690 if (!(irq_status & ENEB_IRQ_STATUS_IR))
691 return 0;
692
11b64d31 693 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
9ea53b74
ML
694 return ENE_IRQ_RX;
695 }
696
11b64d31
ML
697 irq_status = ene_read_reg(dev, ENE_IRQ);
698 if (!(irq_status & ENE_IRQ_STATUS))
9ea53b74
ML
699 return 0;
700
701 /* original driver does that twice - a workaround ? */
11b64d31
ML
702 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
703 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
9ea53b74 704
11b64d31
ML
705 /* check RX interrupt */
706 if (fw_flags2 & ENE_FW2_RXIRQ) {
707 retval |= ENE_IRQ_RX;
708 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
709 }
9ea53b74 710
11b64d31
ML
711 /* check TX interrupt */
712 fw_flags1 = ene_read_reg(dev, ENE_FW1);
9ea53b74 713 if (fw_flags1 & ENE_FW1_TXIRQ) {
11b64d31 714 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
9ea53b74
ML
715 retval |= ENE_IRQ_TX;
716 }
717
11b64d31
ML
718 return retval;
719}
9ea53b74 720
9ea53b74
ML
721/* interrupt handler */
722static irqreturn_t ene_isr(int irq, void *data)
723{
11b64d31
ML
724 u16 hw_value, reg;
725 int hw_sample, irq_status;
726 bool pulse;
9ea53b74 727 unsigned long flags;
9ea53b74
ML
728 irqreturn_t retval = IRQ_NONE;
729 struct ene_device *dev = (struct ene_device *)data;
4651918a 730 DEFINE_IR_RAW_EVENT(ev);
9ea53b74 731
9ea53b74 732 spin_lock_irqsave(&dev->hw_lock, flags);
11b64d31
ML
733
734 dbg_verbose("ISR called");
c29bc4d7 735 ene_rx_read_hw_pointer(dev);
9ea53b74
ML
736 irq_status = ene_irq_status(dev);
737
738 if (!irq_status)
739 goto unlock;
740
741 retval = IRQ_HANDLED;
742
743 if (irq_status & ENE_IRQ_TX) {
11b64d31 744 dbg_verbose("TX interrupt");
9ea53b74 745 if (!dev->hw_learning_and_tx_capable) {
11b64d31 746 dbg("TX interrupt on unsupported device!");
9ea53b74
ML
747 goto unlock;
748 }
749 ene_tx_sample(dev);
750 }
751
752 if (!(irq_status & ENE_IRQ_RX))
753 goto unlock;
754
11b64d31 755 dbg_verbose("RX interrupt");
9ea53b74 756
e1b1ddbe 757 if (dev->hw_learning_and_tx_capable)
11b64d31
ML
758 ene_rx_sense_carrier(dev);
759
760 /* On hardware that don't support extra buffer we need to trust
761 the interrupt and not track the read pointer */
762 if (!dev->hw_extra_buffer)
763 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
764
765 while (1) {
9ea53b74 766
c29bc4d7 767 reg = ene_rx_get_sample_reg(dev);
11b64d31
ML
768
769 dbg_verbose("next sample to read at: %04x", reg);
770 if (!reg)
771 break;
772
773 hw_value = ene_read_reg(dev, reg);
9ea53b74
ML
774
775 if (dev->rx_fan_input_inuse) {
11b64d31
ML
776
777 int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER;
778
9ea53b74 779 /* read high part of the sample */
11b64d31
ML
780 hw_value |= ene_read_reg(dev, reg + offset) << 8;
781 pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS;
9ea53b74
ML
782
783 /* clear space bit, and other unused bits */
11b64d31
ML
784 hw_value &= ENE_FW_SMPL_BUF_FAN_MSK;
785 hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN;
9ea53b74
ML
786
787 } else {
11b64d31
ML
788 pulse = !(hw_value & ENE_FW_SAMPLE_SPACE);
789 hw_value &= ~ENE_FW_SAMPLE_SPACE;
9ea53b74 790 hw_sample = hw_value * sample_period;
931e39a1
ML
791
792 if (dev->rx_period_adjust) {
11b64d31
ML
793 hw_sample *= 100;
794 hw_sample /= (100 + dev->rx_period_adjust);
931e39a1 795 }
9ea53b74 796 }
9ea53b74 797
11b64d31
ML
798 if (!dev->hw_extra_buffer && !hw_sample) {
799 dev->r_pointer = dev->w_pointer;
800 continue;
801 }
931e39a1 802
11b64d31 803 dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
931e39a1 804
5aad7242 805 ev.duration = US_TO_NS(hw_sample);
931e39a1 806 ev.pulse = pulse;
d8b4b582 807 ir_raw_event_store_with_filter(dev->rdev, &ev);
9ea53b74 808 }
931e39a1 809
d8b4b582 810 ir_raw_event_handle(dev->rdev);
9ea53b74
ML
811unlock:
812 spin_unlock_irqrestore(&dev->hw_lock, flags);
813 return retval;
814}
815
816/* Initialize default settings */
c29bc4d7 817static void ene_setup_default_settings(struct ene_device *dev)
9ea53b74 818{
9ea53b74 819 dev->tx_period = 32;
11b64d31
ML
820 dev->tx_duty_cycle = 50; /*%*/
821 dev->transmitter_mask = 0x03;
c29bc4d7 822 dev->learning_mode_enabled = learning_mode_force;
9ea53b74 823
11b64d31 824 /* Set reasonable default timeout */
5aad7242 825 dev->rdev->timeout = US_TO_NS(150000);
9ea53b74
ML
826}
827
c29bc4d7
ML
828/* Upload all hardware settings at once. Used at load and resume time */
829static void ene_setup_hw_settings(struct ene_device *dev)
830{
831 if (dev->hw_learning_and_tx_capable) {
832 ene_tx_set_carrier(dev);
833 ene_tx_set_transmitters(dev);
834 }
835
836 ene_rx_setup(dev);
837}
838
9ea53b74 839/* outside interface: called on first open*/
d8b4b582 840static int ene_open(struct rc_dev *rdev)
9ea53b74 841{
d8b4b582 842 struct ene_device *dev = rdev->priv;
9ea53b74
ML
843 unsigned long flags;
844
845 spin_lock_irqsave(&dev->hw_lock, flags);
9ea53b74
ML
846 ene_rx_enable(dev);
847 spin_unlock_irqrestore(&dev->hw_lock, flags);
848 return 0;
849}
850
851/* outside interface: called on device close*/
d8b4b582 852static void ene_close(struct rc_dev *rdev)
9ea53b74 853{
d8b4b582 854 struct ene_device *dev = rdev->priv;
9ea53b74
ML
855 unsigned long flags;
856 spin_lock_irqsave(&dev->hw_lock, flags);
857
858 ene_rx_disable(dev);
9ea53b74
ML
859 spin_unlock_irqrestore(&dev->hw_lock, flags);
860}
861
931e39a1 862/* outside interface: set transmitter mask */
d8b4b582 863static int ene_set_tx_mask(struct rc_dev *rdev, u32 tx_mask)
9ea53b74 864{
d8b4b582 865 struct ene_device *dev = rdev->priv;
11b64d31 866 dbg("TX: attempt to set transmitter mask %02x", tx_mask);
931e39a1
ML
867
868 /* invalid txmask */
11b64d31
ML
869 if (!tx_mask || tx_mask & ~0x03) {
870 dbg("TX: invalid mask");
931e39a1
ML
871 /* return count of transmitters */
872 return 2;
9ea53b74
ML
873 }
874
931e39a1 875 dev->transmitter_mask = tx_mask;
c29bc4d7 876 ene_tx_set_transmitters(dev);
931e39a1
ML
877 return 0;
878}
9ea53b74 879
931e39a1 880/* outside interface : set tx carrier */
d8b4b582 881static int ene_set_tx_carrier(struct rc_dev *rdev, u32 carrier)
931e39a1 882{
d8b4b582 883 struct ene_device *dev = rdev->priv;
11b64d31 884 u32 period = 2000000 / carrier;
9ea53b74 885
11b64d31 886 dbg("TX: attempt to set tx carrier to %d kHz", carrier);
9ea53b74 887
11b64d31
ML
888 if (period && (period > ENE_CIRMOD_PRD_MAX ||
889 period < ENE_CIRMOD_PRD_MIN)) {
9ea53b74 890
11b64d31 891 dbg("TX: out of range %d-%d kHz carrier",
c29bc4d7 892 2000 / ENE_CIRMOD_PRD_MIN, 2000 / ENE_CIRMOD_PRD_MAX);
11b64d31 893 return -1;
9ea53b74
ML
894 }
895
931e39a1 896 dev->tx_period = period;
c29bc4d7 897 ene_tx_set_carrier(dev);
931e39a1 898 return 0;
9ea53b74
ML
899}
900
11b64d31 901/*outside interface : set tx duty cycle */
d8b4b582 902static int ene_set_tx_duty_cycle(struct rc_dev *rdev, u32 duty_cycle)
11b64d31 903{
d8b4b582 904 struct ene_device *dev = rdev->priv;
11b64d31 905 dbg("TX: setting duty cycle to %d%%", duty_cycle);
11b64d31 906 dev->tx_duty_cycle = duty_cycle;
c29bc4d7 907 ene_tx_set_carrier(dev);
11b64d31
ML
908 return 0;
909}
931e39a1
ML
910
911/* outside interface: enable learning mode */
d8b4b582 912static int ene_set_learning_mode(struct rc_dev *rdev, int enable)
9ea53b74 913{
d8b4b582 914 struct ene_device *dev = rdev->priv;
9ea53b74 915 unsigned long flags;
c29bc4d7 916 if (enable == dev->learning_mode_enabled)
931e39a1 917 return 0;
9ea53b74 918
931e39a1 919 spin_lock_irqsave(&dev->hw_lock, flags);
c29bc4d7 920 dev->learning_mode_enabled = enable;
11b64d31
ML
921 ene_rx_disable(dev);
922 ene_rx_setup(dev);
923 ene_rx_enable(dev);
931e39a1
ML
924 spin_unlock_irqrestore(&dev->hw_lock, flags);
925 return 0;
926}
9ea53b74 927
d8b4b582 928static int ene_set_carrier_report(struct rc_dev *rdev, int enable)
e1b1ddbe 929{
d8b4b582 930 struct ene_device *dev = rdev->priv;
e1b1ddbe
ML
931 unsigned long flags;
932
933 if (enable == dev->carrier_detect_enabled)
934 return 0;
935
936 spin_lock_irqsave(&dev->hw_lock, flags);
937 dev->carrier_detect_enabled = enable;
938 ene_rx_disable(dev);
939 ene_rx_setup(dev);
940 ene_rx_enable(dev);
941 spin_unlock_irqrestore(&dev->hw_lock, flags);
942 return 0;
943}
944
931e39a1 945/* outside interface: enable or disable idle mode */
d8b4b582 946static void ene_set_idle(struct rc_dev *rdev, bool idle)
931e39a1 947{
d8b4b582
DH
948 struct ene_device *dev = rdev->priv;
949
c29bc4d7 950 if (idle) {
d8b4b582 951 ene_rx_reset(dev);
c29bc4d7
ML
952 dbg("RX: end of data");
953 }
11b64d31 954}
9ea53b74 955
931e39a1 956/* outside interface: transmit */
5588dc2b 957static int ene_transmit(struct rc_dev *rdev, unsigned *buf, unsigned n)
931e39a1 958{
d8b4b582 959 struct ene_device *dev = rdev->priv;
931e39a1
ML
960 unsigned long flags;
961
962 dev->tx_buffer = buf;
5588dc2b 963 dev->tx_len = n;
9ea53b74
ML
964 dev->tx_pos = 0;
965 dev->tx_reg = 0;
966 dev->tx_done = 0;
967 dev->tx_sample = 0;
968 dev->tx_sample_pulse = 0;
969
11b64d31 970 dbg("TX: %d samples", dev->tx_len);
9ea53b74
ML
971
972 spin_lock_irqsave(&dev->hw_lock, flags);
973
c29bc4d7 974 ene_tx_enable(dev);
9ea53b74
ML
975
976 /* Transmit first two samples */
977 ene_tx_sample(dev);
978 ene_tx_sample(dev);
979
980 spin_unlock_irqrestore(&dev->hw_lock, flags);
981
982 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
11b64d31 983 dbg("TX: timeout");
9ea53b74 984 spin_lock_irqsave(&dev->hw_lock, flags);
c29bc4d7 985 ene_tx_disable(dev);
9ea53b74
ML
986 spin_unlock_irqrestore(&dev->hw_lock, flags);
987 } else
11b64d31 988 dbg("TX: done");
9ea53b74
ML
989 return n;
990}
991
931e39a1
ML
992/* probe entry */
993static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
9ea53b74 994{
9ea53b74 995 int error = -ENOMEM;
d8b4b582 996 struct rc_dev *rdev;
931e39a1 997 struct ene_device *dev;
9ea53b74 998
931e39a1 999 /* allocate memory */
9ea53b74 1000 dev = kzalloc(sizeof(struct ene_device), GFP_KERNEL);
d8b4b582
DH
1001 rdev = rc_allocate_device();
1002 if (!dev || !rdev)
2e75bcea 1003 goto error1;
9ea53b74
ML
1004
1005 /* validate resources */
931e39a1
ML
1006 error = -ENODEV;
1007
2e4c5562
KM
1008 /* init these to -1, as 0 is valid for both */
1009 dev->hw_io = -1;
1010 dev->irq = -1;
1011
9ea53b74 1012 if (!pnp_port_valid(pnp_dev, 0) ||
11b64d31 1013 pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE)
931e39a1 1014 goto error;
9ea53b74
ML
1015
1016 if (!pnp_irq_valid(pnp_dev, 0))
931e39a1 1017 goto error;
9ea53b74 1018
9ea53b74
ML
1019 spin_lock_init(&dev->hw_lock);
1020
931e39a1
ML
1021 pnp_set_drvdata(pnp_dev, dev);
1022 dev->pnp_dev = pnp_dev;
9ea53b74 1023
11b64d31
ML
1024 /* don't allow too short/long sample periods */
1025 if (sample_period < 5 || sample_period > 0x7F)
1026 sample_period = ENE_DEFAULT_SAMPLE_PERIOD;
1027
9ea53b74
ML
1028 /* detect hardware version and features */
1029 error = ene_hw_detect(dev);
1030 if (error)
931e39a1 1031 goto error;
9ea53b74 1032
9ea53b74 1033 if (!dev->hw_learning_and_tx_capable && txsim) {
11b64d31 1034 dev->hw_learning_and_tx_capable = true;
9ea53b74
ML
1035 setup_timer(&dev->tx_sim_timer, ene_tx_irqsim,
1036 (long unsigned int)dev);
7de3461c 1037 pr_warn("Simulation of TX activated\n");
9ea53b74
ML
1038 }
1039
a06423c9 1040 if (!dev->hw_learning_and_tx_capable)
c29bc4d7 1041 learning_mode_force = false;
a06423c9 1042
d8b4b582 1043 rdev->driver_type = RC_DRIVER_IR_RAW;
52b66144 1044 rdev->allowed_protos = RC_TYPE_ALL;
d8b4b582
DH
1045 rdev->priv = dev;
1046 rdev->open = ene_open;
1047 rdev->close = ene_close;
1048 rdev->s_idle = ene_set_idle;
1049 rdev->driver_name = ENE_DRIVER_NAME;
1050 rdev->map_name = RC_MAP_RC6_MCE;
1051 rdev->input_name = "ENE eHome Infrared Remote Receiver";
9ea53b74 1052
931e39a1 1053 if (dev->hw_learning_and_tx_capable) {
d8b4b582 1054 rdev->s_learning_mode = ene_set_learning_mode;
931e39a1 1055 init_completion(&dev->tx_complete);
d8b4b582
DH
1056 rdev->tx_ir = ene_transmit;
1057 rdev->s_tx_mask = ene_set_tx_mask;
1058 rdev->s_tx_carrier = ene_set_tx_carrier;
1059 rdev->s_tx_duty_cycle = ene_set_tx_duty_cycle;
1060 rdev->s_carrier_report = ene_set_carrier_report;
1061 rdev->input_name = "ENE eHome Infrared Remote Transceiver";
931e39a1
ML
1062 }
1063
2e4c5562
KM
1064 dev->rdev = rdev;
1065
c29bc4d7
ML
1066 ene_rx_setup_hw_buffer(dev);
1067 ene_setup_default_settings(dev);
1068 ene_setup_hw_settings(dev);
931e39a1 1069
11b64d31
ML
1070 device_set_wakeup_capable(&pnp_dev->dev, true);
1071 device_set_wakeup_enable(&pnp_dev->dev, true);
9ea53b74 1072
9ef449c6
LH
1073 /* claim the resources */
1074 error = -EBUSY;
1075 dev->hw_io = pnp_port_start(pnp_dev, 0);
1076 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
1077 dev->hw_io = -1;
1078 dev->irq = -1;
1079 goto error;
1080 }
1081
1082 dev->irq = pnp_irq(pnp_dev, 0);
1083 if (request_irq(dev->irq, ene_isr,
1084 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
1085 dev->irq = -1;
1086 goto error;
1087 }
1088
d8b4b582
DH
1089 error = rc_register_device(rdev);
1090 if (error < 0)
931e39a1
ML
1091 goto error;
1092
7de3461c 1093 pr_notice("driver has been successfully loaded\n");
9ea53b74 1094 return 0;
931e39a1 1095error:
11b64d31 1096 if (dev && dev->irq >= 0)
931e39a1 1097 free_irq(dev->irq, dev);
11b64d31
ML
1098 if (dev && dev->hw_io >= 0)
1099 release_region(dev->hw_io, ENE_IO_SIZE);
2e75bcea 1100error1:
d8b4b582 1101 rc_free_device(rdev);
9ea53b74 1102 kfree(dev);
9ea53b74
ML
1103 return error;
1104}
1105
1106/* main unload function */
1107static void ene_remove(struct pnp_dev *pnp_dev)
1108{
1109 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
1110 unsigned long flags;
1111
1112 spin_lock_irqsave(&dev->hw_lock, flags);
1113 ene_rx_disable(dev);
c29bc4d7 1114 ene_rx_restore_hw_buffer(dev);
9ea53b74
ML
1115 spin_unlock_irqrestore(&dev->hw_lock, flags);
1116
1117 free_irq(dev->irq, dev);
11b64d31 1118 release_region(dev->hw_io, ENE_IO_SIZE);
d8b4b582 1119 rc_unregister_device(dev->rdev);
9ea53b74
ML
1120 kfree(dev);
1121}
1122
1123/* enable wake on IR (wakes on specific button on original remote) */
1124static void ene_enable_wake(struct ene_device *dev, int enable)
1125{
1126 enable = enable && device_may_wakeup(&dev->pnp_dev->dev);
11b64d31
ML
1127 dbg("wake on IR %s", enable ? "enabled" : "disabled");
1128 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
9ea53b74
ML
1129}
1130
1131#ifdef CONFIG_PM
1132static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
1133{
1134 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
11b64d31
ML
1135 ene_enable_wake(dev, true);
1136
1137 /* TODO: add support for wake pattern */
9ea53b74
ML
1138 return 0;
1139}
1140
1141static int ene_resume(struct pnp_dev *pnp_dev)
1142{
1143 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
c29bc4d7
ML
1144 ene_setup_hw_settings(dev);
1145
1146 if (dev->rx_enabled)
9ea53b74 1147 ene_rx_enable(dev);
c29bc4d7 1148
11b64d31 1149 ene_enable_wake(dev, false);
9ea53b74
ML
1150 return 0;
1151}
1152#endif
1153
1154static void ene_shutdown(struct pnp_dev *pnp_dev)
1155{
1156 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
11b64d31 1157 ene_enable_wake(dev, true);
9ea53b74
ML
1158}
1159
1160static const struct pnp_device_id ene_ids[] = {
1161 {.id = "ENE0100",},
1162 {.id = "ENE0200",},
1163 {.id = "ENE0201",},
931e39a1 1164 {.id = "ENE0202",},
9ea53b74
ML
1165 {},
1166};
1167
1168static struct pnp_driver ene_driver = {
1169 .name = ENE_DRIVER_NAME,
1170 .id_table = ene_ids,
1171 .flags = PNP_DRIVER_RES_DO_NOT_CHANGE,
1172
1173 .probe = ene_probe,
1174 .remove = __devexit_p(ene_remove),
1175#ifdef CONFIG_PM
1176 .suspend = ene_suspend,
1177 .resume = ene_resume,
1178#endif
1179 .shutdown = ene_shutdown,
1180};
1181
1182static int __init ene_init(void)
1183{
1184 return pnp_register_driver(&ene_driver);
1185}
1186
1187static void ene_exit(void)
1188{
1189 pnp_unregister_driver(&ene_driver);
1190}
1191
1192module_param(sample_period, int, S_IRUGO);
1193MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
1194
c29bc4d7
ML
1195module_param(learning_mode_force, bool, S_IRUGO);
1196MODULE_PARM_DESC(learning_mode_force, "Enable learning mode by default");
9ea53b74
ML
1197
1198module_param(debug, int, S_IRUGO | S_IWUSR);
11b64d31 1199MODULE_PARM_DESC(debug, "Debug level");
9ea53b74
ML
1200
1201module_param(txsim, bool, S_IRUGO);
1202MODULE_PARM_DESC(txsim,
1203 "Simulate TX features on unsupported hardware (dangerous)");
1204
9ea53b74
ML
1205MODULE_DEVICE_TABLE(pnp, ene_ids);
1206MODULE_DESCRIPTION
11b64d31
ML
1207 ("Infrared input driver for KB3926B/C/D/E/F "
1208 "(aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port");
9ea53b74
ML
1209
1210MODULE_AUTHOR("Maxim Levitsky");
1211MODULE_LICENSE("GPL");
1212
1213module_init(ene_init);
1214module_exit(ene_exit);