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net: tulip: Adjust indentation in {dmfe, uli526x}_init_module
[mirror_ubuntu-bionic-kernel.git] / drivers / net / ethernet / dec / tulip / uli526x.c
CommitLineData
4689ced9
PC		 1/*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
f3b197ac 12
4689ced9
PC		 13*/
14
e02fb7aa
JP		 15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
4689ced9
PC		 17#define DRV_NAME "uli526x"
18#define DRV_VERSION "0.9.3"
19#define DRV_RELDATE "2005-7-29"
20
21#include <linux/module.h>
22
23#include <linux/kernel.h>
24#include <linux/string.h>
25#include <linux/timer.h>
4689ced9
PC		 26#include <linux/errno.h>
27#include <linux/ioport.h>
4689ced9
PC		 28#include <linux/interrupt.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/skbuff.h>
35#include <linux/delay.h>
36#include <linux/spinlock.h>
6cafa99f 37#include <linux/dma-mapping.h>
1977f032 38#include <linux/bitops.h>
4689ced9
PC		 39
40#include <asm/processor.h>
4689ced9
PC		 41#include <asm/io.h>
42#include <asm/dma.h>
7c0f6ba6 43#include <linux/uaccess.h>
4689ced9 44
3acf4b5c
FR		 45#define uw32(reg, val) iowrite32(val, ioaddr + (reg))
46#define ur32(reg) ioread32(ioaddr + (reg))
4689ced9
PC		 47
48/* Board/System/Debug information/definition ---------------- */
49#define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
50#define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
51
52#define ULI526X_IO_SIZE 0x100
53#define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
54#define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
55#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
56#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
57#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
58#define TX_BUF_ALLOC 0x600
59#define RX_ALLOC_SIZE 0x620
60#define ULI526X_RESET 1
61#define CR0_DEFAULT 0
945a7876 62#define CR6_DEFAULT 0x22200000
4689ced9
PC		 63#define CR7_DEFAULT 0x180c1
64#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
65#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
66#define MAX_PACKET_SIZE 1514
67#define ULI5261_MAX_MULTICAST 14
68#define RX_COPY_SIZE 100
69#define MAX_CHECK_PACKET 0x8000
70
71#define ULI526X_10MHF 0
72#define ULI526X_100MHF 1
73#define ULI526X_10MFD 4
74#define ULI526X_100MFD 5
75#define ULI526X_AUTO 8
76
77#define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
78#define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
79#define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
80#define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
81#define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
82#define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
83
84#define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
85#define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
86#define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
87
e02fb7aa
JP		 88#define ULI526X_DBUG(dbug_now, msg, value) \
89do { \
90 if (uli526x_debug || (dbug_now)) \
91 pr_err("%s %lx\n", (msg), (long) (value)); \
92} while (0)
4689ced9 93
e02fb7aa
JP		 94#define SHOW_MEDIA_TYPE(mode) \
95 pr_err("Change Speed to %sMhz %s duplex\n", \
96 mode & 1 ? "100" : "10", \
97 mode & 4 ? "full" : "half");
4689ced9
PC		 98
99
100/* CR9 definition: SROM/MII */
101#define CR9_SROM_READ 0x4800
102#define CR9_SRCS 0x1
103#define CR9_SRCLK 0x2
104#define CR9_CRDOUT 0x8
105#define SROM_DATA_0 0x0
106#define SROM_DATA_1 0x4
107#define PHY_DATA_1 0x20000
108#define PHY_DATA_0 0x00000
109#define MDCLKH 0x10000
110
111#define PHY_POWER_DOWN 0x800
112
113#define SROM_V41_CODE 0x14
114
4689ced9
PC		 115/* Structure/enum declaration ------------------------------- */
116struct tx_desc {
c559a5bc 117 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
4689ced9
PC		 118 char *tx_buf_ptr; /* Data for us */
119 struct tx_desc *next_tx_desc;
120} __attribute__(( aligned(32) ));
121
122struct rx_desc {
c559a5bc 123 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
4689ced9
PC		 124 struct sk_buff *rx_skb_ptr; /* Data for us */
125 struct rx_desc *next_rx_desc;
126} __attribute__(( aligned(32) ));
127
128struct uli526x_board_info {
3acf4b5c
FR		 129 struct uli_phy_ops {
130 void (*write)(struct uli526x_board_info *, u8, u8, u16);
131 u16 (*read)(struct uli526x_board_info *, u8, u8);
132 } phy;
945a7876 133 struct net_device *next_dev; /* next device */
4689ced9
PC		 134 struct pci_dev *pdev; /* PCI device */
135 spinlock_t lock;
136
3acf4b5c 137 void __iomem *ioaddr; /* I/O base address */
4689ced9
PC		 138 u32 cr0_data;
139 u32 cr5_data;
140 u32 cr6_data;
141 u32 cr7_data;
142 u32 cr15_data;
143
144 /* pointer for memory physical address */
145 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
146 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
147 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
148 dma_addr_t first_tx_desc_dma;
149 dma_addr_t first_rx_desc_dma;
150
151 /* descriptor pointer */
152 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
153 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
154 unsigned char *desc_pool_ptr; /* descriptor pool memory */
155 struct tx_desc *first_tx_desc;
156 struct tx_desc *tx_insert_ptr;
157 struct tx_desc *tx_remove_ptr;
158 struct rx_desc *first_rx_desc;
159 struct rx_desc *rx_insert_ptr;
160 struct rx_desc *rx_ready_ptr; /* packet come pointer */
161 unsigned long tx_packet_cnt; /* transmitted packet count */
162 unsigned long rx_avail_cnt; /* available rx descriptor count */
163 unsigned long interval_rx_cnt; /* rx packet count a callback time */
164
165 u16 dbug_cnt;
166 u16 NIC_capability; /* NIC media capability */
167 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
168
169 u8 media_mode; /* user specify media mode */
170 u8 op_mode; /* real work media mode */
171 u8 phy_addr;
172 u8 link_failed; /* Ever link failed */
173 u8 wait_reset; /* Hardware failed, need to reset */
174 struct timer_list timer;
175
4689ced9
PC		 176 /* Driver defined statistic counter */
177 unsigned long tx_fifo_underrun;
178 unsigned long tx_loss_carrier;
179 unsigned long tx_no_carrier;
180 unsigned long tx_late_collision;
181 unsigned long tx_excessive_collision;
182 unsigned long tx_jabber_timeout;
183 unsigned long reset_count;
184 unsigned long reset_cr8;
185 unsigned long reset_fatal;
186 unsigned long reset_TXtimeout;
187
188 /* NIC SROM data */
189 unsigned char srom[128];
f3b197ac 190 u8 init;
4689ced9
PC		 191};
192
193enum uli526x_offsets {
194 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
195 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
196 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
197 DCR15 = 0x78
198};
199
200enum uli526x_CR6_bits {
201 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
202 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
203 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
204};
205
206/* Global variable declaration ----------------------------- */
779c1a85
BP		 207static int printed_version;
208static const char version[] =
1c3319fb 209 "ULi M5261/M5263 net driver, version " DRV_VERSION " (" DRV_RELDATE ")";
4689ced9
PC		 210
211static int uli526x_debug;
212static unsigned char uli526x_media_mode = ULI526X_AUTO;
213static u32 uli526x_cr6_user_set;
214
215/* For module input parameter */
216static int debug;
217static u32 cr6set;
99bb2579 218static int mode = 8;
4689ced9
PC		 219
220/* function declaration ------------------------------------- */
945a7876 221static int uli526x_open(struct net_device *);
ad096463
SH		 222static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
223 struct net_device *);
945a7876 224static int uli526x_stop(struct net_device *);
945a7876 225static void uli526x_set_filter_mode(struct net_device *);
7282d491 226static const struct ethtool_ops netdev_ethtool_ops;
3acf4b5c 227static u16 read_srom_word(struct uli526x_board_info *, int);
7d12e780 228static irqreturn_t uli526x_interrupt(int, void *);
7fa0cba3
AV		 229#ifdef CONFIG_NET_POLL_CONTROLLER
230static void uli526x_poll(struct net_device *dev);
231#endif
3acf4b5c 232static void uli526x_descriptor_init(struct net_device *, void __iomem *);
1ab0d2ec 233static void allocate_rx_buffer(struct net_device *);
3acf4b5c 234static void update_cr6(u32, void __iomem *);
945a7876 235static void send_filter_frame(struct net_device *, int);
3acf4b5c
FR		 236static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
237static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
238static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
239static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
240static void phy_write_1bit(struct uli526x_board_info *db, u32);
241static u16 phy_read_1bit(struct uli526x_board_info *db);
4689ced9
PC		 242static u8 uli526x_sense_speed(struct uli526x_board_info *);
243static void uli526x_process_mode(struct uli526x_board_info *);
a8c22a2b 244static void uli526x_timer(struct timer_list *t);
945a7876
PC		 245static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
246static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
4689ced9 247static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
945a7876 248static void uli526x_dynamic_reset(struct net_device *);
4689ced9 249static void uli526x_free_rxbuffer(struct uli526x_board_info *);
945a7876 250static void uli526x_init(struct net_device *);
4689ced9
PC		 251static void uli526x_set_phyxcer(struct uli526x_board_info *);
252
3acf4b5c
FR		 253static void srom_clk_write(struct uli526x_board_info *db, u32 data)
254{
255 void __iomem *ioaddr = db->ioaddr;
256
257 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
258 udelay(5);
259 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
260 udelay(5);
261 uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
262 udelay(5);
263}
264
945a7876 265/* ULI526X network board routine ---------------------------- */
4689ced9 266
dfefe02b
SH		 267static const struct net_device_ops netdev_ops = {
268 .ndo_open = uli526x_open,
269 .ndo_stop = uli526x_stop,
270 .ndo_start_xmit = uli526x_start_xmit,
afc4b13d 271 .ndo_set_rx_mode = uli526x_set_filter_mode,
dfefe02b
SH		 272 .ndo_set_mac_address = eth_mac_addr,
273 .ndo_validate_addr = eth_validate_addr,
274#ifdef CONFIG_NET_POLL_CONTROLLER
275 .ndo_poll_controller = uli526x_poll,
276#endif
277};
278
4689ced9 279/*
945a7876 280 * Search ULI526X board, allocate space and register it
4689ced9
PC		 281 */
282
779c1a85
BP		 283static int uli526x_init_one(struct pci_dev *pdev,
284 const struct pci_device_id *ent)
4689ced9
PC		 285{
286 struct uli526x_board_info *db; /* board information structure */
287 struct net_device *dev;
3acf4b5c 288 void __iomem *ioaddr;
4689ced9 289 int i, err;
f3b197ac 290
4689ced9
PC		 291 ULI526X_DBUG(0, "uli526x_init_one()", 0);
292
293 if (!printed_version++)
1c3319fb 294 pr_info("%s\n", version);
4689ced9
PC		 295
296 /* Init network device */
297 dev = alloc_etherdev(sizeof(*db));
298 if (dev == NULL)
299 return -ENOMEM;
4689ced9
PC		 300 SET_NETDEV_DEV(dev, &pdev->dev);
301
284901a9 302 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
163ef0b5 303 pr_warn("32-bit PCI DMA not available\n");
4689ced9
PC		 304 err = -ENODEV;
305 goto err_out_free;
306 }
307
308 /* Enable Master/IO access, Disable memory access */
309 err = pci_enable_device(pdev);
310 if (err)
311 goto err_out_free;
312
313 if (!pci_resource_start(pdev, 0)) {
e02fb7aa 314 pr_err("I/O base is zero\n");
4689ced9
PC		 315 err = -ENODEV;
316 goto err_out_disable;
317 }
318
319 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
e02fb7aa 320 pr_err("Allocated I/O size too small\n");
4689ced9
PC		 321 err = -ENODEV;
322 goto err_out_disable;
323 }
324
5e58deb9
FR		 325 err = pci_request_regions(pdev, DRV_NAME);
326 if (err < 0) {
e02fb7aa 327 pr_err("Failed to request PCI regions\n");
4689ced9
PC		 328 goto err_out_disable;
329 }
330
4689ced9
PC		 331 /* Init system & device */
332 db = netdev_priv(dev);
333
334 /* Allocate Tx/Rx descriptor memory */
5e58deb9
FR		 335 err = -ENOMEM;
336
4689ced9 337 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
5e58deb9
FR		 338 if (!db->desc_pool_ptr)
339 goto err_out_release;
340
4689ced9 341 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
5e58deb9
FR		 342 if (!db->buf_pool_ptr)
343 goto err_out_free_tx_desc;
f3b197ac 344
4689ced9
PC		 345 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
346 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
347 db->buf_pool_start = db->buf_pool_ptr;
348 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
349
3acf4b5c
FR		 350 switch (ent->driver_data) {
351 case PCI_ULI5263_ID:
352 db->phy.write = phy_writeby_cr10;
353 db->phy.read = phy_readby_cr10;
354 break;
355 default:
356 db->phy.write = phy_writeby_cr9;
357 db->phy.read = phy_readby_cr9;
358 break;
359 }
360
361 /* IO region. */
362 ioaddr = pci_iomap(pdev, 0, 0);
363 if (!ioaddr)
364 goto err_out_free_tx_buf;
f3b197ac 365
3acf4b5c 366 db->ioaddr = ioaddr;
4689ced9
PC		 367 db->pdev = pdev;
368 db->init = 1;
f3b197ac 369
4689ced9 370 pci_set_drvdata(pdev, dev);
f3b197ac 371
4689ced9 372 /* Register some necessary functions */
dfefe02b 373 dev->netdev_ops = &netdev_ops;
4689ced9 374 dev->ethtool_ops = &netdev_ethtool_ops;
dfefe02b 375
4689ced9
PC		 376 spin_lock_init(&db->lock);
377
f3b197ac 378
4689ced9
PC		 379 /* read 64 word srom data */
380 for (i = 0; i < 64; i++)
3acf4b5c 381 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
4689ced9
PC		 382
383 /* Set Node address */
945a7876 384 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
4689ced9 385 {
3acf4b5c
FR		 386 uw32(DCR0, 0x10000); //Diagnosis mode
387 uw32(DCR13, 0x1c0); //Reset dianostic pointer port
388 uw32(DCR14, 0); //Clear reset port
389 uw32(DCR14, 0x10); //Reset ID Table pointer
390 uw32(DCR14, 0); //Clear reset port
391 uw32(DCR13, 0); //Clear CR13
392 uw32(DCR13, 0x1b0); //Select ID Table access port
4689ced9
PC		 393 //Read MAC address from CR14
394 for (i = 0; i < 6; i++)
3acf4b5c 395 dev->dev_addr[i] = ur32(DCR14);
4689ced9 396 //Read end
3acf4b5c
FR		 397 uw32(DCR13, 0); //Clear CR13
398 uw32(DCR0, 0); //Clear CR0
4689ced9
PC		 399 udelay(10);
400 }
401 else /*Exist SROM*/
402 {
403 for (i = 0; i < 6; i++)
404 dev->dev_addr[i] = db->srom[20 + i];
405 }
406 err = register_netdev (dev);
407 if (err)
3acf4b5c 408 goto err_out_unmap;
4689ced9 409
163ef0b5
JP		 410 netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
411 ent->driver_data >> 16, pci_name(pdev),
3acf4b5c 412 dev->dev_addr, pdev->irq);
4689ced9
PC		 413
414 pci_set_master(pdev);
415
416 return 0;
417
3acf4b5c
FR		 418err_out_unmap:
419 pci_iounmap(pdev, db->ioaddr);
5e58deb9
FR		 420err_out_free_tx_buf:
421 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
422 db->buf_pool_ptr, db->buf_pool_dma_ptr);
423err_out_free_tx_desc:
424 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
425 db->desc_pool_ptr, db->desc_pool_dma_ptr);
426err_out_release:
4689ced9
PC		 427 pci_release_regions(pdev);
428err_out_disable:
429 pci_disable_device(pdev);
430err_out_free:
4689ced9
PC		 431 free_netdev(dev);
432
433 return err;
434}
435
436
779c1a85 437static void uli526x_remove_one(struct pci_dev *pdev)
4689ced9
PC		 438{
439 struct net_device *dev = pci_get_drvdata(pdev);
440 struct uli526x_board_info *db = netdev_priv(dev);
441
5e58deb9 442 unregister_netdev(dev);
3acf4b5c 443 pci_iounmap(pdev, db->ioaddr);
945a7876
PC		 444 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
445 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
446 db->desc_pool_dma_ptr);
447 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
448 db->buf_pool_ptr, db->buf_pool_dma_ptr);
945a7876 449 pci_release_regions(pdev);
945a7876 450 pci_disable_device(pdev);
5e58deb9 451 free_netdev(dev);
4689ced9
PC		 452}
453
454
455/*
456 * Open the interface.
945a7876 457 * The interface is opened whenever "ifconfig" activates it.
4689ced9
PC		 458 */
459
945a7876 460static int uli526x_open(struct net_device *dev)
4689ced9
PC		 461{
462 int ret;
463 struct uli526x_board_info *db = netdev_priv(dev);
f3b197ac 464
4689ced9
PC		 465 ULI526X_DBUG(0, "uli526x_open", 0);
466
4689ced9
PC		 467 /* system variable init */
468 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
4689ced9
PC		 469 db->tx_packet_cnt = 0;
470 db->rx_avail_cnt = 0;
471 db->link_failed = 1;
472 netif_carrier_off(dev);
473 db->wait_reset = 0;
474
475 db->NIC_capability = 0xf; /* All capability*/
476 db->PHY_reg4 = 0x1e0;
477
478 /* CR6 operation mode decision */
479 db->cr6_data |= ULI526X_TXTH_256;
480 db->cr0_data = CR0_DEFAULT;
f3b197ac 481
945a7876 482 /* Initialize ULI526X board */
4689ced9
PC		 483 uli526x_init(dev);
484
3acf4b5c
FR		 485 ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
486 dev->name, dev);
afd8e399
AV		 487 if (ret)
488 return ret;
489
4689ced9
PC		 490 /* Active System Interface */
491 netif_wake_queue(dev);
492
493 /* set and active a timer process */
a8c22a2b 494 timer_setup(&db->timer, uli526x_timer, 0);
4689ced9 495 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
4689ced9
PC		 496 add_timer(&db->timer);
497
498 return 0;
499}
500
501
945a7876 502/* Initialize ULI526X board
4689ced9 503 * Reset ULI526X board
945a7876 504 * Initialize TX/Rx descriptor chain structure
4689ced9
PC		 505 * Send the set-up frame
506 * Enable Tx/Rx machine
507 */
508
945a7876 509static void uli526x_init(struct net_device *dev)
4689ced9
PC		 510{
511 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c
FR		 512 struct uli_phy_ops *phy = &db->phy;
513 void __iomem *ioaddr = db->ioaddr;
4689ced9 514 u8 phy_tmp;
7a7d23da 515 u8 timeout;
4689ced9
PC		 516 u16 phy_reg_reset;
517
7a7d23da 518
4689ced9
PC		 519 ULI526X_DBUG(0, "uli526x_init()", 0);
520
521 /* Reset M526x MAC controller */
3acf4b5c 522 uw32(DCR0, ULI526X_RESET); /* RESET MAC */
4689ced9 523 udelay(100);
3acf4b5c 524 uw32(DCR0, db->cr0_data);
4689ced9
PC		 525 udelay(5);
526
527 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
528 db->phy_addr = 1;
3acf4b5c
FR		 529 for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
530 u16 phy_value;
531
532 phy_value = phy->read(db, phy_tmp, 3); //peer add
533 if (phy_value != 0xffff && phy_value != 0) {
4689ced9
PC		 534 db->phy_addr = phy_tmp;
535 break;
536 }
537 }
3acf4b5c
FR		 538
539 if (phy_tmp == 32)
163ef0b5 540 pr_warn("Can not find the phy address!!!\n");
4689ced9
PC		 541 /* Parser SROM and media mode */
542 db->media_mode = uli526x_media_mode;
543
7a7d23da 544 /* phyxcer capability setting */
3acf4b5c 545 phy_reg_reset = phy->read(db, db->phy_addr, 0);
4689ced9 546 phy_reg_reset = (phy_reg_reset | 0x8000);
3acf4b5c 547 phy->write(db, db->phy_addr, 0, phy_reg_reset);
7a7d23da
GG		 548
549 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
550 * functions") or phy data sheet for details on phy reset
551 */
4689ced9 552 udelay(500);
7a7d23da 553 timeout = 10;
3acf4b5c
FR		 554 while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
555 udelay(100);
4689ced9
PC		 556
557 /* Process Phyxcer Media Mode */
558 uli526x_set_phyxcer(db);
559
560 /* Media Mode Process */
561 if ( !(db->media_mode & ULI526X_AUTO) )
3acf4b5c 562 db->op_mode = db->media_mode; /* Force Mode */
4689ced9 563
dbedd44e 564 /* Initialize Transmit/Receive descriptor and CR3/4 */
1ab0d2ec 565 uli526x_descriptor_init(dev, ioaddr);
4689ced9
PC		 566
567 /* Init CR6 to program M526X operation */
568 update_cr6(db->cr6_data, ioaddr);
569
570 /* Send setup frame */
4cd24eaf 571 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 572
573 /* Init CR7, interrupt active bit */
574 db->cr7_data = CR7_DEFAULT;
3acf4b5c 575 uw32(DCR7, db->cr7_data);
4689ced9
PC		 576
577 /* Init CR15, Tx jabber and Rx watchdog timer */
3acf4b5c 578 uw32(DCR15, db->cr15_data);
4689ced9
PC		 579
580 /* Enable ULI526X Tx/Rx function */
581 db->cr6_data |= CR6_RXSC | CR6_TXSC;
582 update_cr6(db->cr6_data, ioaddr);
583}
584
585
586/*
587 * Hardware start transmission.
588 * Send a packet to media from the upper layer.
589 */
590
ad096463
SH		 591static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
592 struct net_device *dev)
4689ced9
PC		 593{
594 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 595 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 596 struct tx_desc *txptr;
597 unsigned long flags;
598
599 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
600
601 /* Resource flag check */
602 netif_stop_queue(dev);
603
604 /* Too large packet check */
605 if (skb->len > MAX_PACKET_SIZE) {
163ef0b5 606 netdev_err(dev, "big packet = %d\n", (u16)skb->len);
290a79db 607 dev_kfree_skb_any(skb);
6ed10654 608 return NETDEV_TX_OK;
4689ced9
PC		 609 }
610
611 spin_lock_irqsave(&db->lock, flags);
612
613 /* No Tx resource check, it never happen nromally */
614 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
615 spin_unlock_irqrestore(&db->lock, flags);
163ef0b5 616 netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
5b548140 617 return NETDEV_TX_BUSY;
4689ced9
PC		 618 }
619
620 /* Disable NIC interrupt */
3acf4b5c 621 uw32(DCR7, 0);
4689ced9
PC		 622
623 /* transmit this packet */
624 txptr = db->tx_insert_ptr;
d626f62b 625 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
4689ced9
PC		 626 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
627
628 /* Point to next transmit free descriptor */
629 db->tx_insert_ptr = txptr->next_tx_desc;
630
631 /* Transmit Packet Process */
3acf4b5c 632 if (db->tx_packet_cnt < TX_DESC_CNT) {
4689ced9
PC		 633 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
634 db->tx_packet_cnt++; /* Ready to send */
3acf4b5c 635 uw32(DCR1, 0x1); /* Issue Tx polling */
860e9538 636 netif_trans_update(dev); /* saved time stamp */
4689ced9
PC		 637 }
638
639 /* Tx resource check */
640 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
641 netif_wake_queue(dev);
642
643 /* Restore CR7 to enable interrupt */
644 spin_unlock_irqrestore(&db->lock, flags);
3acf4b5c 645 uw32(DCR7, db->cr7_data);
f3b197ac 646
4689ced9 647 /* free this SKB */
290a79db 648 dev_consume_skb_any(skb);
4689ced9 649
6ed10654 650 return NETDEV_TX_OK;
4689ced9
PC		 651}
652
653
654/*
655 * Stop the interface.
656 * The interface is stopped when it is brought.
657 */
658
945a7876 659static int uli526x_stop(struct net_device *dev)
4689ced9
PC		 660{
661 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 662 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 663
664 /* disable system */
665 netif_stop_queue(dev);
666
667 /* deleted timer */
668 del_timer_sync(&db->timer);
669
670 /* Reset & stop ULI526X board */
3acf4b5c 671 uw32(DCR0, ULI526X_RESET);
4689ced9 672 udelay(5);
3acf4b5c 673 db->phy.write(db, db->phy_addr, 0, 0x8000);
4689ced9
PC		 674
675 /* free interrupt */
3acf4b5c 676 free_irq(db->pdev->irq, dev);
4689ced9
PC		 677
678 /* free allocated rx buffer */
679 uli526x_free_rxbuffer(db);
680
4689ced9
PC		 681 return 0;
682}
683
684
685/*
686 * M5261/M5263 insterrupt handler
687 * receive the packet to upper layer, free the transmitted packet
688 */
689
7d12e780 690static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
4689ced9 691{
945a7876 692 struct net_device *dev = dev_id;
4689ced9 693 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 694 void __iomem *ioaddr = db->ioaddr;
4689ced9
PC		 695 unsigned long flags;
696
4689ced9 697 spin_lock_irqsave(&db->lock, flags);
3acf4b5c 698 uw32(DCR7, 0);
4689ced9
PC		 699
700 /* Got ULI526X status */
3acf4b5c
FR		 701 db->cr5_data = ur32(DCR5);
702 uw32(DCR5, db->cr5_data);
4689ced9 703 if ( !(db->cr5_data & 0x180c1) ) {
7fa0cba3 704 /* Restore CR7 to enable interrupt mask */
3acf4b5c 705 uw32(DCR7, db->cr7_data);
7fa0cba3 706 spin_unlock_irqrestore(&db->lock, flags);
4689ced9
PC		 707 return IRQ_HANDLED;
708 }
709
4689ced9
PC		 710 /* Check system status */
711 if (db->cr5_data & 0x2000) {
712 /* system bus error happen */
713 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
714 db->reset_fatal++;
715 db->wait_reset = 1; /* Need to RESET */
716 spin_unlock_irqrestore(&db->lock, flags);
717 return IRQ_HANDLED;
718 }
719
720 /* Received the coming packet */
721 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
722 uli526x_rx_packet(dev, db);
723
724 /* reallocate rx descriptor buffer */
725 if (db->rx_avail_cnt<RX_DESC_CNT)
1ab0d2ec 726 allocate_rx_buffer(dev);
4689ced9
PC		 727
728 /* Free the transmitted descriptor */
729 if ( db->cr5_data & 0x01)
730 uli526x_free_tx_pkt(dev, db);
731
732 /* Restore CR7 to enable interrupt mask */
3acf4b5c 733 uw32(DCR7, db->cr7_data);
4689ced9
PC		 734
735 spin_unlock_irqrestore(&db->lock, flags);
736 return IRQ_HANDLED;
737}
738
7fa0cba3
AV		 739#ifdef CONFIG_NET_POLL_CONTROLLER
740static void uli526x_poll(struct net_device *dev)
741{
3acf4b5c
FR		 742 struct uli526x_board_info *db = netdev_priv(dev);
743
7fa0cba3 744 /* ISR grabs the irqsave lock, so this should be safe */
3acf4b5c 745 uli526x_interrupt(db->pdev->irq, dev);
7fa0cba3
AV		 746}
747#endif
4689ced9
PC		 748
749/*
750 * Free TX resource after TX complete
751 */
752
dfefe02b
SH		 753static void uli526x_free_tx_pkt(struct net_device *dev,
754 struct uli526x_board_info * db)
4689ced9
PC		 755{
756 struct tx_desc *txptr;
4689ced9
PC		 757 u32 tdes0;
758
759 txptr = db->tx_remove_ptr;
760 while(db->tx_packet_cnt) {
761 tdes0 = le32_to_cpu(txptr->tdes0);
4689ced9
PC		 762 if (tdes0 & 0x80000000)
763 break;
764
765 /* A packet sent completed */
766 db->tx_packet_cnt--;
dfefe02b 767 dev->stats.tx_packets++;
4689ced9
PC		 768
769 /* Transmit statistic counter */
770 if ( tdes0 != 0x7fffffff ) {
dfefe02b
SH		 771 dev->stats.collisions += (tdes0 >> 3) & 0xf;
772 dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
4689ced9 773 if (tdes0 & TDES0_ERR_MASK) {
dfefe02b 774 dev->stats.tx_errors++;
4689ced9
PC		 775 if (tdes0 & 0x0002) { /* UnderRun */
776 db->tx_fifo_underrun++;
777 if ( !(db->cr6_data & CR6_SFT) ) {
778 db->cr6_data = db->cr6_data | CR6_SFT;
779 update_cr6(db->cr6_data, db->ioaddr);
780 }
781 }
782 if (tdes0 & 0x0100)
783 db->tx_excessive_collision++;
784 if (tdes0 & 0x0200)
785 db->tx_late_collision++;
786 if (tdes0 & 0x0400)
787 db->tx_no_carrier++;
788 if (tdes0 & 0x0800)
789 db->tx_loss_carrier++;
790 if (tdes0 & 0x4000)
791 db->tx_jabber_timeout++;
792 }
793 }
794
795 txptr = txptr->next_tx_desc;
796 }/* End of while */
797
798 /* Update TX remove pointer to next */
799 db->tx_remove_ptr = txptr;
800
801 /* Resource available check */
802 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
803 netif_wake_queue(dev); /* Active upper layer, send again */
804}
805
806
807/*
808 * Receive the come packet and pass to upper layer
809 */
810
945a7876 811static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
4689ced9
PC		 812{
813 struct rx_desc *rxptr;
814 struct sk_buff *skb;
815 int rxlen;
816 u32 rdes0;
f3b197ac 817
4689ced9
PC		 818 rxptr = db->rx_ready_ptr;
819
820 while(db->rx_avail_cnt) {
821 rdes0 = le32_to_cpu(rxptr->rdes0);
822 if (rdes0 & 0x80000000) /* packet owner check */
823 {
824 break;
825 }
826
827 db->rx_avail_cnt--;
828 db->interval_rx_cnt++;
829
830 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
831 if ( (rdes0 & 0x300) != 0x300) {
832 /* A packet without First/Last flag */
833 /* reuse this SKB */
834 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
835 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
836 } else {
837 /* A packet with First/Last flag */
838 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
839
840 /* error summary bit check */
841 if (rdes0 & 0x8000) {
842 /* This is a error packet */
dfefe02b 843 dev->stats.rx_errors++;
4689ced9 844 if (rdes0 & 1)
dfefe02b 845 dev->stats.rx_fifo_errors++;
4689ced9 846 if (rdes0 & 2)
dfefe02b 847 dev->stats.rx_crc_errors++;
4689ced9 848 if (rdes0 & 0x80)
dfefe02b 849 dev->stats.rx_length_errors++;
4689ced9
PC		 850 }
851
852 if ( !(rdes0 & 0x8000) ||
853 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
ac90a149
KM		 854 struct sk_buff *new_skb = NULL;
855
4689ced9 856 skb = rxptr->rx_skb_ptr;
f3b197ac 857
4689ced9
PC		 858 /* Good packet, send to upper layer */
859 /* Shorst packet used new SKB */
ac90a149 860 if ((rxlen < RX_COPY_SIZE) &&
1ab0d2ec 861 (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
ac90a149 862 skb = new_skb;
4689ced9 863 /* size less than COPY_SIZE, allocate a rxlen SKB */
4689ced9 864 skb_reserve(skb, 2); /* 16byte align */
59ae1d12
JB		 865 skb_put_data(skb,
866 skb_tail_pointer(rxptr->rx_skb_ptr),
867 rxlen);
4689ced9 868 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
4c13eb66 869 } else
4689ced9 870 skb_put(skb, rxlen);
4c13eb66 871
4689ced9
PC		 872 skb->protocol = eth_type_trans(skb, dev);
873 netif_rx(skb);
dfefe02b
SH		 874 dev->stats.rx_packets++;
875 dev->stats.rx_bytes += rxlen;
f3b197ac 876
4689ced9
PC		 877 } else {
878 /* Reuse SKB buffer when the packet is error */
879 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
880 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
881 }
882 }
883
884 rxptr = rxptr->next_rx_desc;
885 }
886
887 db->rx_ready_ptr = rxptr;
888}
889
890
4689ced9
PC		 891/*
892 * Set ULI526X multicast address
893 */
894
945a7876 895static void uli526x_set_filter_mode(struct net_device * dev)
4689ced9 896{
8f15ea42 897 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 898 unsigned long flags;
899
900 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
901 spin_lock_irqsave(&db->lock, flags);
902
903 if (dev->flags & IFF_PROMISC) {
904 ULI526X_DBUG(0, "Enable PROM Mode", 0);
905 db->cr6_data |= CR6_PM | CR6_PBF;
906 update_cr6(db->cr6_data, db->ioaddr);
907 spin_unlock_irqrestore(&db->lock, flags);
908 return;
909 }
910
4cd24eaf
JP		 911 if (dev->flags & IFF_ALLMULTI ||
912 netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
913 ULI526X_DBUG(0, "Pass all multicast address",
914 netdev_mc_count(dev));
4689ced9
PC		 915 db->cr6_data &= ~(CR6_PM | CR6_PBF);
916 db->cr6_data |= CR6_PAM;
917 spin_unlock_irqrestore(&db->lock, flags);
918 return;
919 }
920
4cd24eaf
JP		 921 ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
922 send_filter_frame(dev, netdev_mc_count(dev)); /* M5261/M5263 */
4689ced9
PC		 923 spin_unlock_irqrestore(&db->lock, flags);
924}
925
926static void
6711a87a
PR		 927ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
928 struct ethtool_link_ksettings *cmd)
4689ced9 929{
6711a87a
PR		 930 u32 supported, advertising;
931
932 supported = (SUPPORTED_10baseT_Half |
945a7876
PC		 933 SUPPORTED_10baseT_Full |
934 SUPPORTED_100baseT_Half |
935 SUPPORTED_100baseT_Full |
936 SUPPORTED_Autoneg |
937 SUPPORTED_MII);
f3b197ac 938
6711a87a 939 advertising = (ADVERTISED_10baseT_Half |
945a7876
PC		 940 ADVERTISED_10baseT_Full |
941 ADVERTISED_100baseT_Half |
942 ADVERTISED_100baseT_Full |
943 ADVERTISED_Autoneg |
944 ADVERTISED_MII);
4689ced9 945
6711a87a
PR		 946 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
947 supported);
948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
949 advertising);
4689ced9 950
6711a87a
PR		 951 cmd->base.port = PORT_MII;
952 cmd->base.phy_address = db->phy_addr;
f3b197ac 953
6711a87a
PR		 954 cmd->base.speed = SPEED_10;
955 cmd->base.duplex = DUPLEX_HALF;
f3b197ac 956
4689ced9
PC		 957 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
958 {
6711a87a 959 cmd->base.speed = SPEED_100;
4689ced9
PC		 960 }
961 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
962 {
6711a87a 963 cmd->base.duplex = DUPLEX_FULL;
4689ced9
PC		 964 }
965 if(db->link_failed)
966 {
6711a87a
PR		 967 cmd->base.speed = SPEED_UNKNOWN;
968 cmd->base.duplex = DUPLEX_UNKNOWN;
4689ced9 969 }
f3b197ac 970
4689ced9 971 if (db->media_mode & ULI526X_AUTO)
f3b197ac 972 {
6711a87a 973 cmd->base.autoneg = AUTONEG_ENABLE;
4689ced9 974 }
4689ced9
PC		 975}
976
977static void netdev_get_drvinfo(struct net_device *dev,
978 struct ethtool_drvinfo *info)
979{
980 struct uli526x_board_info *np = netdev_priv(dev);
981
68aad78c
RJ		 982 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
983 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
3acf4b5c 984 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
4689ced9
PC		 985}
986
6711a87a
PR		 987static int netdev_get_link_ksettings(struct net_device *dev,
988 struct ethtool_link_ksettings *cmd)
989{
4689ced9 990 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 991
6711a87a 992 ULi_ethtool_get_link_ksettings(np, cmd);
f3b197ac 993
4689ced9
PC		 994 return 0;
995}
996
997static u32 netdev_get_link(struct net_device *dev) {
998 struct uli526x_board_info *np = netdev_priv(dev);
f3b197ac 999
4689ced9
PC		 1000 if(np->link_failed)
1001 return 0;
1002 else
1003 return 1;
1004}
1005
1006static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1007{
1008 wol->supported = WAKE_PHY | WAKE_MAGIC;
1009 wol->wolopts = 0;
1010}
1011
7282d491 1012static const struct ethtool_ops netdev_ethtool_ops = {
4689ced9 1013 .get_drvinfo = netdev_get_drvinfo,
4689ced9
PC		 1014 .get_link = netdev_get_link,
1015 .get_wol = uli526x_get_wol,
6711a87a 1016 .get_link_ksettings = netdev_get_link_ksettings,
4689ced9
PC		 1017};
1018
1019/*
1020 * A periodic timer routine
1021 * Dynamic media sense, allocate Rx buffer...
1022 */
1023
a8c22a2b 1024static void uli526x_timer(struct timer_list *t)
4689ced9 1025{
a8c22a2b
KC		 1026 struct uli526x_board_info *db = from_timer(db, t, timer);
1027 struct net_device *dev = pci_get_drvdata(db->pdev);
3acf4b5c
FR		 1028 struct uli_phy_ops *phy = &db->phy;
1029 void __iomem *ioaddr = db->ioaddr;
4689ced9 1030 unsigned long flags;
3acf4b5c
FR		 1031 u8 tmp_cr12 = 0;
1032 u32 tmp_cr8;
f3b197ac 1033
4689ced9
PC		 1034 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1035 spin_lock_irqsave(&db->lock, flags);
1036
f3b197ac 1037
4689ced9 1038 /* Dynamic reset ULI526X : system error or transmit time-out */
3acf4b5c 1039 tmp_cr8 = ur32(DCR8);
4689ced9
PC		 1040 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1041 db->reset_cr8++;
1042 db->wait_reset = 1;
1043 }
1044 db->interval_rx_cnt = 0;
1045
1046 /* TX polling kick monitor */
1047 if ( db->tx_packet_cnt &&
1ae5dc34 1048 time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
3acf4b5c 1049 uw32(DCR1, 0x1); // Tx polling again
4689ced9 1050
f3b197ac 1051 // TX Timeout
1ae5dc34 1052 if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
4689ced9
PC		 1053 db->reset_TXtimeout++;
1054 db->wait_reset = 1;
1c3319fb 1055 netdev_err(dev, " Tx timeout - resetting\n");
4689ced9
PC		 1056 }
1057 }
1058
1059 if (db->wait_reset) {
1060 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1061 db->reset_count++;
1062 uli526x_dynamic_reset(dev);
1063 db->timer.expires = ULI526X_TIMER_WUT;
1064 add_timer(&db->timer);
1065 spin_unlock_irqrestore(&db->lock, flags);
1066 return;
1067 }
1068
1069 /* Link status check, Dynamic media type change */
3acf4b5c 1070 if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
4689ced9
PC		 1071 tmp_cr12 = 3;
1072
1073 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1074 /* Link Failed */
1075 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1076 netif_carrier_off(dev);
163ef0b5 1077 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1078 db->link_failed = 1;
1079
1080 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1081 /* AUTO don't need */
1082 if ( !(db->media_mode & 0x8) )
3acf4b5c 1083 phy->write(db, db->phy_addr, 0, 0x1000);
4689ced9
PC		 1084
1085 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1086 if (db->media_mode & ULI526X_AUTO) {
1087 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1088 update_cr6(db->cr6_data, db->ioaddr);
1089 }
1090 } else
1091 if ((tmp_cr12 & 0x3) && db->link_failed) {
1092 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1093 db->link_failed = 0;
1094
1095 /* Auto Sense Speed */
1096 if ( (db->media_mode & ULI526X_AUTO) &&
1097 uli526x_sense_speed(db) )
1098 db->link_failed = 1;
1099 uli526x_process_mode(db);
f3b197ac 1100
4689ced9
PC		 1101 if(db->link_failed==0)
1102 {
163ef0b5
JP		 1103 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1104 (db->op_mode == ULI526X_100MHF ||
1105 db->op_mode == ULI526X_100MFD)
1106 ? 100 : 10,
1107 (db->op_mode == ULI526X_10MFD ||
1108 db->op_mode == ULI526X_100MFD)
1109 ? "Full" : "Half");
4689ced9
PC		 1110 netif_carrier_on(dev);
1111 }
1112 /* SHOW_MEDIA_TYPE(db->op_mode); */
1113 }
1114 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1115 {
1116 if(db->init==1)
1117 {
163ef0b5 1118 netdev_info(dev, "NIC Link is Down\n");
4689ced9
PC		 1119 netif_carrier_off(dev);
1120 }
1121 }
e1395a32 1122 db->init = 0;
4689ced9
PC		 1123
1124 /* Timer active again */
1125 db->timer.expires = ULI526X_TIMER_WUT;
1126 add_timer(&db->timer);
1127 spin_unlock_irqrestore(&db->lock, flags);
1128}
1129
1130
1131/*
4689ced9
PC		 1132 * Stop ULI526X board
1133 * Free Tx/Rx allocated memory
b6aec32a 1134 * Init system variable
4689ced9
PC		 1135 */
1136
b6aec32a 1137static void uli526x_reset_prepare(struct net_device *dev)
4689ced9
PC		 1138{
1139 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 1140 void __iomem *ioaddr = db->ioaddr;
4689ced9 1141
4689ced9
PC		 1142 /* Sopt MAC controller */
1143 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
3acf4b5c
FR		 1144 update_cr6(db->cr6_data, ioaddr);
1145 uw32(DCR7, 0); /* Disable Interrupt */
1146 uw32(DCR5, ur32(DCR5));
4689ced9
PC		 1147
1148 /* Disable upper layer interface */
1149 netif_stop_queue(dev);
1150
1151 /* Free Rx Allocate buffer */
1152 uli526x_free_rxbuffer(db);
1153
1154 /* system variable init */
1155 db->tx_packet_cnt = 0;
1156 db->rx_avail_cnt = 0;
1157 db->link_failed = 1;
1158 db->init=1;
1159 db->wait_reset = 0;
b6aec32a
RW		 1160}
1161
1162
1163/*
1164 * Dynamic reset the ULI526X board
1165 * Stop ULI526X board
1166 * Free Tx/Rx allocated memory
1167 * Reset ULI526X board
1168 * Re-initialize ULI526X board
1169 */
1170
1171static void uli526x_dynamic_reset(struct net_device *dev)
1172{
1173 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1174
1175 uli526x_reset_prepare(dev);
4689ced9 1176
945a7876 1177 /* Re-initialize ULI526X board */
4689ced9
PC		 1178 uli526x_init(dev);
1179
1180 /* Restart upper layer interface */
1181 netif_wake_queue(dev);
1182}
1183
1184
b6aec32a
RW		 1185#ifdef CONFIG_PM
1186
1187/*
1188 * Suspend the interface.
1189 */
1190
1191static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1192{
1193 struct net_device *dev = pci_get_drvdata(pdev);
1194 pci_power_t power_state;
1195 int err;
1196
1197 ULI526X_DBUG(0, "uli526x_suspend", 0);
1198
b6aec32a
RW		 1199 pci_save_state(pdev);
1200
1201 if (!netif_running(dev))
1202 return 0;
1203
1204 netif_device_detach(dev);
1205 uli526x_reset_prepare(dev);
1206
1207 power_state = pci_choose_state(pdev, state);
1208 pci_enable_wake(pdev, power_state, 0);
1209 err = pci_set_power_state(pdev, power_state);
1210 if (err) {
1211 netif_device_attach(dev);
1212 /* Re-initialize ULI526X board */
1213 uli526x_init(dev);
1214 /* Restart upper layer interface */
1215 netif_wake_queue(dev);
1216 }
1217
1218 return err;
1219}
1220
1221/*
1222 * Resume the interface.
1223 */
1224
1225static int uli526x_resume(struct pci_dev *pdev)
1226{
1227 struct net_device *dev = pci_get_drvdata(pdev);
1228 int err;
1229
1230 ULI526X_DBUG(0, "uli526x_resume", 0);
1231
b6aec32a
RW		 1232 pci_restore_state(pdev);
1233
1234 if (!netif_running(dev))
1235 return 0;
1236
1237 err = pci_set_power_state(pdev, PCI_D0);
1238 if (err) {
163ef0b5 1239 netdev_warn(dev, "Could not put device into D0\n");
b6aec32a
RW		 1240 return err;
1241 }
1242
1243 netif_device_attach(dev);
1244 /* Re-initialize ULI526X board */
1245 uli526x_init(dev);
1246 /* Restart upper layer interface */
1247 netif_wake_queue(dev);
1248
1249 return 0;
1250}
1251
1252#else /* !CONFIG_PM */
1253
1254#define uli526x_suspend NULL
1255#define uli526x_resume NULL
1256
1257#endif /* !CONFIG_PM */
1258
1259
4689ced9
PC		 1260/*
1261 * free all allocated rx buffer
1262 */
1263
1264static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1265{
1266 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1267
1268 /* free allocated rx buffer */
1269 while (db->rx_avail_cnt) {
1270 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1271 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1272 db->rx_avail_cnt--;
1273 }
1274}
1275
1276
1277/*
1278 * Reuse the SK buffer
1279 */
1280
1281static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1282{
1283 struct rx_desc *rxptr = db->rx_insert_ptr;
1284
1285 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1286 rxptr->rx_skb_ptr = skb;
27a884dc
ACM		 1287 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1288 skb_tail_pointer(skb),
1289 RX_ALLOC_SIZE,
1290 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1291 wmb();
1292 rxptr->rdes0 = cpu_to_le32(0x80000000);
1293 db->rx_avail_cnt++;
1294 db->rx_insert_ptr = rxptr->next_rx_desc;
1295 } else
1296 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1297}
1298
1299
1300/*
1301 * Initialize transmit/Receive descriptor
1302 * Using Chain structure, and allocate Tx/Rx buffer
1303 */
1304
3acf4b5c 1305static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
4689ced9 1306{
1ab0d2ec 1307 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 1308 struct tx_desc *tmp_tx;
1309 struct rx_desc *tmp_rx;
1310 unsigned char *tmp_buf;
1311 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1312 dma_addr_t tmp_buf_dma;
1313 int i;
1314
1315 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1316
1317 /* tx descriptor start pointer */
1318 db->tx_insert_ptr = db->first_tx_desc;
1319 db->tx_remove_ptr = db->first_tx_desc;
3acf4b5c 1320 uw32(DCR4, db->first_tx_desc_dma); /* TX DESC address */
4689ced9
PC		 1321
1322 /* rx descriptor start pointer */
1323 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1324 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1325 db->rx_insert_ptr = db->first_rx_desc;
1326 db->rx_ready_ptr = db->first_rx_desc;
3acf4b5c 1327 uw32(DCR3, db->first_rx_desc_dma); /* RX DESC address */
4689ced9
PC		 1328
1329 /* Init Transmit chain */
1330 tmp_buf = db->buf_pool_start;
1331 tmp_buf_dma = db->buf_pool_dma_start;
1332 tmp_tx_dma = db->first_tx_desc_dma;
1333 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1334 tmp_tx->tx_buf_ptr = tmp_buf;
1335 tmp_tx->tdes0 = cpu_to_le32(0);
1336 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1337 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1338 tmp_tx_dma += sizeof(struct tx_desc);
1339 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1340 tmp_tx->next_tx_desc = tmp_tx + 1;
1341 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1342 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1343 }
1344 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1345 tmp_tx->next_tx_desc = db->first_tx_desc;
1346
1347 /* Init Receive descriptor chain */
1348 tmp_rx_dma=db->first_rx_desc_dma;
1349 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1350 tmp_rx->rdes0 = cpu_to_le32(0);
1351 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1352 tmp_rx_dma += sizeof(struct rx_desc);
1353 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1354 tmp_rx->next_rx_desc = tmp_rx + 1;
1355 }
1356 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1357 tmp_rx->next_rx_desc = db->first_rx_desc;
1358
1359 /* pre-allocate Rx buffer */
1ab0d2ec 1360 allocate_rx_buffer(dev);
4689ced9
PC		 1361}
1362
1363
1364/*
1365 * Update CR6 value
945a7876 1366 * Firstly stop ULI526X, then written value and start
4689ced9 1367 */
3acf4b5c 1368static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
4689ced9 1369{
3acf4b5c 1370 uw32(DCR6, cr6_data);
4689ced9
PC		 1371 udelay(5);
1372}
1373
1374
1375/*
1376 * Send a setup frame for M5261/M5263
945a7876 1377 * This setup frame initialize ULI526X address filter mode
4689ced9
PC		 1378 */
1379
e284e5c6
AV		 1380#ifdef __BIG_ENDIAN
1381#define FLT_SHIFT 16
1382#else
1383#define FLT_SHIFT 0
1384#endif
1385
945a7876 1386static void send_filter_frame(struct net_device *dev, int mc_cnt)
4689ced9
PC		 1387{
1388 struct uli526x_board_info *db = netdev_priv(dev);
3acf4b5c 1389 void __iomem *ioaddr = db->ioaddr;
22bedad3 1390 struct netdev_hw_addr *ha;
4689ced9
PC		 1391 struct tx_desc *txptr;
1392 u16 * addrptr;
1393 u32 * suptr;
1394 int i;
1395
1396 ULI526X_DBUG(0, "send_filter_frame()", 0);
1397
1398 txptr = db->tx_insert_ptr;
1399 suptr = (u32 *) txptr->tx_buf_ptr;
1400
1401 /* Node address */
1402 addrptr = (u16 *) dev->dev_addr;
e284e5c6
AV		 1403 *suptr++ = addrptr[0] << FLT_SHIFT;
1404 *suptr++ = addrptr[1] << FLT_SHIFT;
1405 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1406
1407 /* broadcast address */
e284e5c6
AV		 1408 *suptr++ = 0xffff << FLT_SHIFT;
1409 *suptr++ = 0xffff << FLT_SHIFT;
1410 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1411
1412 /* fit the multicast address */
22bedad3
JP		 1413 netdev_for_each_mc_addr(ha, dev) {
1414 addrptr = (u16 *) ha->addr;
e284e5c6
AV		 1415 *suptr++ = addrptr[0] << FLT_SHIFT;
1416 *suptr++ = addrptr[1] << FLT_SHIFT;
1417 *suptr++ = addrptr[2] << FLT_SHIFT;
4689ced9
PC		 1418 }
1419
4302b67e 1420 for (i = netdev_mc_count(dev); i < 14; i++) {
e284e5c6
AV		 1421 *suptr++ = 0xffff << FLT_SHIFT;
1422 *suptr++ = 0xffff << FLT_SHIFT;
1423 *suptr++ = 0xffff << FLT_SHIFT;
4689ced9
PC		 1424 }
1425
1426 /* prepare the setup frame */
1427 db->tx_insert_ptr = txptr->next_tx_desc;
1428 txptr->tdes1 = cpu_to_le32(0x890000c0);
1429
1430 /* Resource Check and Send the setup packet */
1431 if (db->tx_packet_cnt < TX_DESC_CNT) {
1432 /* Resource Empty */
1433 db->tx_packet_cnt++;
1434 txptr->tdes0 = cpu_to_le32(0x80000000);
3acf4b5c
FR		 1435 update_cr6(db->cr6_data | 0x2000, ioaddr);
1436 uw32(DCR1, 0x1); /* Issue Tx polling */
1437 update_cr6(db->cr6_data, ioaddr);
860e9538 1438 netif_trans_update(dev);
4689ced9 1439 } else
163ef0b5 1440 netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
4689ced9
PC		 1441}
1442
1443
1444/*
1445 * Allocate rx buffer,
1446 * As possible as allocate maxiumn Rx buffer
1447 */
1448
1ab0d2ec 1449static void allocate_rx_buffer(struct net_device *dev)
4689ced9 1450{
1ab0d2ec 1451 struct uli526x_board_info *db = netdev_priv(dev);
4689ced9
PC		 1452 struct rx_desc *rxptr;
1453 struct sk_buff *skb;
1454
1455 rxptr = db->rx_insert_ptr;
1456
1457 while(db->rx_avail_cnt < RX_DESC_CNT) {
1ab0d2ec
PD		 1458 skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1459 if (skb == NULL)
4689ced9
PC		 1460 break;
1461 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
27a884dc
ACM		 1462 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1463 skb_tail_pointer(skb),
1464 RX_ALLOC_SIZE,
1465 PCI_DMA_FROMDEVICE));
4689ced9
PC		 1466 wmb();
1467 rxptr->rdes0 = cpu_to_le32(0x80000000);
1468 rxptr = rxptr->next_rx_desc;
1469 db->rx_avail_cnt++;
1470 }
1471
1472 db->rx_insert_ptr = rxptr;
1473}
1474
1475
1476/*
1477 * Read one word data from the serial ROM
1478 */
1479
3acf4b5c 1480static u16 read_srom_word(struct uli526x_board_info *db, int offset)
4689ced9 1481{
3acf4b5c 1482 void __iomem *ioaddr = db->ioaddr;
4689ced9 1483 u16 srom_data = 0;
3acf4b5c 1484 int i;
4689ced9 1485
3acf4b5c
FR		 1486 uw32(DCR9, CR9_SROM_READ);
1487 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1488
1489 /* Send the Read Command 110b */
3acf4b5c
FR		 1490 srom_clk_write(db, SROM_DATA_1);
1491 srom_clk_write(db, SROM_DATA_1);
1492 srom_clk_write(db, SROM_DATA_0);
4689ced9
PC		 1493
1494 /* Send the offset */
1495 for (i = 5; i >= 0; i--) {
1496 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
3acf4b5c 1497 srom_clk_write(db, srom_data);
4689ced9
PC		 1498 }
1499
3acf4b5c 1500 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1501
1502 for (i = 16; i > 0; i--) {
3acf4b5c 1503 uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
4689ced9 1504 udelay(5);
3acf4b5c
FR		 1505 srom_data = (srom_data << 1) |
1506 ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1507 uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
4689ced9
PC		 1508 udelay(5);
1509 }
1510
3acf4b5c 1511 uw32(DCR9, CR9_SROM_READ);
4689ced9
PC		 1512 return srom_data;
1513}
1514
1515
1516/*
1517 * Auto sense the media mode
1518 */
1519
1520static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1521{
3acf4b5c 1522 struct uli_phy_ops *phy = &db->phy;
4689ced9
PC		 1523 u8 ErrFlag = 0;
1524 u16 phy_mode;
1525
3acf4b5c
FR		 1526 phy_mode = phy->read(db, db->phy_addr, 1);
1527 phy_mode = phy->read(db, db->phy_addr, 1);
4689ced9
PC		 1528
1529 if ( (phy_mode & 0x24) == 0x24 ) {
f3b197ac 1530
3acf4b5c 1531 phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
4689ced9
PC		 1532 if(phy_mode&0x8000)
1533 phy_mode = 0x8000;
1534 else if(phy_mode&0x4000)
1535 phy_mode = 0x4000;
1536 else if(phy_mode&0x2000)
1537 phy_mode = 0x2000;
1538 else
1539 phy_mode = 0x1000;
f3b197ac 1540
4689ced9
PC		 1541 switch (phy_mode) {
1542 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1543 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1544 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1545 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1546 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1547 }
1548 } else {
1549 db->op_mode = ULI526X_10MHF;
1550 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1551 ErrFlag = 1;
1552 }
1553
1554 return ErrFlag;
1555}
1556
1557
1558/*
1559 * Set 10/100 phyxcer capability
1560 * AUTO mode : phyxcer register4 is NIC capability
1561 * Force mode: phyxcer register4 is the force media
1562 */
1563
1564static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1565{
3acf4b5c 1566 struct uli_phy_ops *phy = &db->phy;
4689ced9 1567 u16 phy_reg;
f3b197ac 1568
4689ced9 1569 /* Phyxcer capability setting */
3acf4b5c 1570 phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
4689ced9
PC		 1571
1572 if (db->media_mode & ULI526X_AUTO) {
1573 /* AUTO Mode */
1574 phy_reg |= db->PHY_reg4;
1575 } else {
1576 /* Force Mode */
1577 switch(db->media_mode) {
1578 case ULI526X_10MHF: phy_reg |= 0x20; break;
1579 case ULI526X_10MFD: phy_reg |= 0x40; break;
1580 case ULI526X_100MHF: phy_reg |= 0x80; break;
1581 case ULI526X_100MFD: phy_reg |= 0x100; break;
1582 }
f3b197ac 1583
4689ced9
PC		 1584 }
1585
1586 /* Write new capability to Phyxcer Reg4 */
1587 if ( !(phy_reg & 0x01e0)) {
1588 phy_reg|=db->PHY_reg4;
1589 db->media_mode|=ULI526X_AUTO;
1590 }
3acf4b5c 1591 phy->write(db, db->phy_addr, 4, phy_reg);
4689ced9
PC		 1592
1593 /* Restart Auto-Negotiation */
3acf4b5c 1594 phy->write(db, db->phy_addr, 0, 0x1200);
4689ced9
PC		 1595 udelay(50);
1596}
1597
1598
1599/*
1600 * Process op-mode
1601 AUTO mode : PHY controller in Auto-negotiation Mode
1602 * Force mode: PHY controller in force mode with HUB
1603 * N-way force capability with SWITCH
1604 */
1605
1606static void uli526x_process_mode(struct uli526x_board_info *db)
1607{
3acf4b5c 1608 struct uli_phy_ops *phy = &db->phy;
4689ced9
PC		 1609 u16 phy_reg;
1610
1611 /* Full Duplex Mode Check */
1612 if (db->op_mode & 0x4)
1613 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1614 else
1615 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1616
1617 update_cr6(db->cr6_data, db->ioaddr);
1618
1619 /* 10/100M phyxcer force mode need */
3acf4b5c 1620 if (!(db->media_mode & 0x8)) {
4689ced9 1621 /* Forece Mode */
3acf4b5c
FR		 1622 phy_reg = phy->read(db, db->phy_addr, 6);
1623 if (!(phy_reg & 0x1)) {
4689ced9
PC		 1624 /* parter without N-Way capability */
1625 phy_reg = 0x0;
1626 switch(db->op_mode) {
1627 case ULI526X_10MHF: phy_reg = 0x0; break;
1628 case ULI526X_10MFD: phy_reg = 0x100; break;
1629 case ULI526X_100MHF: phy_reg = 0x2000; break;
1630 case ULI526X_100MFD: phy_reg = 0x2100; break;
1631 }
3acf4b5c 1632 phy->write(db, db->phy_addr, 0, phy_reg);
4689ced9
PC		 1633 }
1634 }
1635}
1636
1637
3acf4b5c
FR		 1638/* M5261/M5263 Chip */
1639static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1640 u8 offset, u16 phy_data)
4689ced9
PC		 1641{
1642 u16 i;
4689ced9
PC		 1643
1644 /* Send 33 synchronization clock to Phy controller */
1645 for (i = 0; i < 35; i++)
3acf4b5c 1646 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1647
1648 /* Send start command(01) to Phy */
3acf4b5c
FR		 1649 phy_write_1bit(db, PHY_DATA_0);
1650 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1651
1652 /* Send write command(01) to Phy */
3acf4b5c
FR		 1653 phy_write_1bit(db, PHY_DATA_0);
1654 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1655
1656 /* Send Phy address */
1657 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1658 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1659
1660 /* Send register address */
1661 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1662 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1663
1664 /* written trasnition */
3acf4b5c
FR		 1665 phy_write_1bit(db, PHY_DATA_1);
1666 phy_write_1bit(db, PHY_DATA_0);
4689ced9
PC		 1667
1668 /* Write a word data to PHY controller */
3acf4b5c
FR		 1669 for (i = 0x8000; i > 0; i >>= 1)
1670 phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1671}
1672
3acf4b5c 1673static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
4689ced9 1674{
4689ced9 1675 u16 phy_data;
3acf4b5c 1676 int i;
f3b197ac 1677
4689ced9
PC		 1678 /* Send 33 synchronization clock to Phy controller */
1679 for (i = 0; i < 35; i++)
3acf4b5c 1680 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1681
1682 /* Send start command(01) to Phy */
3acf4b5c
FR		 1683 phy_write_1bit(db, PHY_DATA_0);
1684 phy_write_1bit(db, PHY_DATA_1);
4689ced9
PC		 1685
1686 /* Send read command(10) to Phy */
3acf4b5c
FR		 1687 phy_write_1bit(db, PHY_DATA_1);
1688 phy_write_1bit(db, PHY_DATA_0);
4689ced9
PC		 1689
1690 /* Send Phy address */
1691 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1692 phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1693
1694 /* Send register address */
1695 for (i = 0x10; i > 0; i = i >> 1)
3acf4b5c 1696 phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
4689ced9
PC		 1697
1698 /* Skip transition state */
3acf4b5c 1699 phy_read_1bit(db);
4689ced9
PC		 1700
1701 /* read 16bit data */
1702 for (phy_data = 0, i = 0; i < 16; i++) {
1703 phy_data <<= 1;
3acf4b5c 1704 phy_data |= phy_read_1bit(db);
4689ced9
PC		 1705 }
1706
1707 return phy_data;
1708}
1709
3acf4b5c
FR		 1710static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1711 u8 offset)
4689ced9 1712{
3acf4b5c
FR		 1713 void __iomem *ioaddr = db->ioaddr;
1714 u32 cr10_value = phy_addr;
f3b197ac 1715
3acf4b5c
FR		 1716 cr10_value = (cr10_value << 5) + offset;
1717 cr10_value = (cr10_value << 16) + 0x08000000;
1718 uw32(DCR10, cr10_value);
4689ced9 1719 udelay(1);
3acf4b5c
FR		 1720 while (1) {
1721 cr10_value = ur32(DCR10);
1722 if (cr10_value & 0x10000000)
4689ced9
PC		 1723 break;
1724 }
807540ba 1725 return cr10_value & 0x0ffff;
4689ced9
PC		 1726}
1727
3acf4b5c
FR		 1728static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1729 u8 offset, u16 phy_data)
4689ced9 1730{
3acf4b5c
FR		 1731 void __iomem *ioaddr = db->ioaddr;
1732 u32 cr10_value = phy_addr;
f3b197ac 1733
3acf4b5c
FR		 1734 cr10_value = (cr10_value << 5) + offset;
1735 cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1736 uw32(DCR10, cr10_value);
4689ced9
PC		 1737 udelay(1);
1738}
1739/*
1740 * Write one bit data to Phy Controller
1741 */
1742
3acf4b5c 1743static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
4689ced9 1744{
3acf4b5c
FR		 1745 void __iomem *ioaddr = db->ioaddr;
1746
1747 uw32(DCR9, data); /* MII Clock Low */
4689ced9 1748 udelay(1);
3acf4b5c 1749 uw32(DCR9, data | MDCLKH); /* MII Clock High */
4689ced9 1750 udelay(1);
3acf4b5c 1751 uw32(DCR9, data); /* MII Clock Low */
4689ced9
PC		 1752 udelay(1);
1753}
1754
1755
1756/*
1757 * Read one bit phy data from PHY controller
1758 */
1759
3acf4b5c 1760static u16 phy_read_1bit(struct uli526x_board_info *db)
4689ced9 1761{
3acf4b5c 1762 void __iomem *ioaddr = db->ioaddr;
4689ced9 1763 u16 phy_data;
f3b197ac 1764
3acf4b5c 1765 uw32(DCR9, 0x50000);
4689ced9 1766 udelay(1);
3acf4b5c
FR		 1767 phy_data = (ur32(DCR9) >> 19) & 0x1;
1768 uw32(DCR9, 0x40000);
4689ced9
PC		 1769 udelay(1);
1770
1771 return phy_data;
1772}
1773
1774
9baa3c34 1775static const struct pci_device_id uli526x_pci_tbl[] = {
4689ced9
PC		 1776 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1777 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1778 { 0, }
1779};
1780MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1781
1782
1783static struct pci_driver uli526x_driver = {
1784 .name = "uli526x",
1785 .id_table = uli526x_pci_tbl,
1786 .probe = uli526x_init_one,
779c1a85 1787 .remove = uli526x_remove_one,
b6aec32a
RW		 1788 .suspend = uli526x_suspend,
1789 .resume = uli526x_resume,
4689ced9
PC		 1790};
1791
1792MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1793MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1794MODULE_LICENSE("GPL");
1795
c213460f
ES		 1796module_param(debug, int, 0644);
1797module_param(mode, int, 0);
1798module_param(cr6set, int, 0);
4689ced9
PC		 1799MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1800MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1801
1802/* Description:
1803 * when user used insmod to add module, system invoked init_module()
945a7876 1804 * to register the services.
4689ced9
PC		 1805 */
1806
1807static int __init uli526x_init_module(void)
1808{
4689ced9 1809
1c3319fb 1810 pr_info("%s\n", version);
4689ced9
PC		 1811 printed_version = 1;
1812
1813 ULI526X_DBUG(0, "init_module() ", debug);
1814
1815 if (debug)
1816 uli526x_debug = debug; /* set debug flag */
1817 if (cr6set)
1818 uli526x_cr6_user_set = cr6set;
1819
b111c84b
NC		 1820 switch (mode) {
1821 case ULI526X_10MHF:
4689ced9
PC		 1822 case ULI526X_100MHF:
1823 case ULI526X_10MFD:
1824 case ULI526X_100MFD:
1825 uli526x_media_mode = mode;
1826 break;
e1c3e501
HK		 1827 default:
1828 uli526x_media_mode = ULI526X_AUTO;
4689ced9
PC		 1829 break;
1830 }
1831
e1c3e501 1832 return pci_register_driver(&uli526x_driver);
4689ced9
PC		 1833}
1834
1835
1836/*
1837 * Description:
1838 * when user used rmmod to delete module, system invoked clean_module()
1839 * to un-register all registered services.
1840 */
1841
1842static void __exit uli526x_cleanup_module(void)
1843{
791a1ddd 1844 ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
4689ced9
PC		 1845 pci_unregister_driver(&uli526x_driver);
1846}
1847
1848module_init(uli526x_init_module);
1849module_exit(uli526x_cleanup_module);
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