| c07b8f83 |
1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* Copyright (c) 2018-2019 Hisilicon Limited. */ |
| 3 | |
| 4 | #ifndef __HCLGE_DEBUGFS_H |
| 5 | #define __HCLGE_DEBUGFS_H |
| 6 | |
| 6e87b62b |
7 | #define HCLGE_DBG_BUF_LEN 256 |
| 8 | #define HCLGE_DBG_MNG_TBL_MAX 64 |
| 9 | |
| 10 | #define HCLGE_DBG_MNG_VLAN_MASK_B BIT(0) |
| 11 | #define HCLGE_DBG_MNG_MAC_MASK_B BIT(1) |
| 12 | #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2) |
| 13 | #define HCLGE_DBG_MNG_E_TYPE_B BIT(11) |
| 14 | #define HCLGE_DBG_MNG_DROP_B BIT(13) |
| 15 | #define HCLGE_DBG_MNG_VLAN_TAG 0x0FFF |
| 16 | #define HCLGE_DBG_MNG_PF_ID 0x0007 |
| 17 | #define HCLGE_DBG_MNG_VF_ID 0x00FF |
| 18 | |
| fe84b06d |
19 | /* Get DFX BD number offset */ |
| 20 | #define HCLGE_DBG_DFX_BIOS_OFFSET 1 |
| 21 | #define HCLGE_DBG_DFX_SSU_0_OFFSET 2 |
| 22 | #define HCLGE_DBG_DFX_SSU_1_OFFSET 3 |
| 23 | #define HCLGE_DBG_DFX_IGU_OFFSET 4 |
| 24 | #define HCLGE_DBG_DFX_RPU_0_OFFSET 5 |
| 25 | |
| 26 | #define HCLGE_DBG_DFX_RPU_1_OFFSET 6 |
| 27 | #define HCLGE_DBG_DFX_NCSI_OFFSET 7 |
| 28 | #define HCLGE_DBG_DFX_RTC_OFFSET 8 |
| 29 | #define HCLGE_DBG_DFX_PPP_OFFSET 9 |
| 30 | #define HCLGE_DBG_DFX_RCB_OFFSET 10 |
| 31 | #define HCLGE_DBG_DFX_TQP_OFFSET 11 |
| 32 | |
| 33 | #define HCLGE_DBG_DFX_SSU_2_OFFSET 12 |
| 34 | |
| c07b8f83 |
35 | #pragma pack(1) |
| 36 | |
| 37 | struct hclge_qos_pri_map_cmd { |
| 38 | u8 pri0_tc : 4, |
| 39 | pri1_tc : 4; |
| 40 | u8 pri2_tc : 4, |
| 41 | pri3_tc : 4; |
| 42 | u8 pri4_tc : 4, |
| 43 | pri5_tc : 4; |
| 44 | u8 pri6_tc : 4, |
| 45 | pri7_tc : 4; |
| 46 | u8 vlan_pri : 4, |
| 47 | rev : 4; |
| 48 | }; |
| 49 | |
| fe84b06d |
50 | struct hclge_dbg_dfx_message { |
| 51 | int flag; |
| 52 | char message[60]; |
| 53 | }; |
| 54 | |
| c07b8f83 |
55 | #pragma pack() |
| fe84b06d |
56 | |
| 57 | static struct hclge_dbg_dfx_message hclge_dbg_bios_common_reg[] = { |
| 58 | {false, "Reserved"}, |
| 59 | {true, "BP_CPU_STATE"}, |
| 60 | {true, "DFX_MSIX_INFO_NIC_0"}, |
| 61 | {true, "DFX_MSIX_INFO_NIC_1"}, |
| 62 | {true, "DFX_MSIX_INFO_NIC_2"}, |
| 63 | {true, "DFX_MSIX_INFO_NIC_3"}, |
| 64 | |
| 65 | {true, "DFX_MSIX_INFO_ROC_0"}, |
| 66 | {true, "DFX_MSIX_INFO_ROC_1"}, |
| 67 | {true, "DFX_MSIX_INFO_ROC_2"}, |
| 68 | {true, "DFX_MSIX_INFO_ROC_3"}, |
| 69 | {false, "Reserved"}, |
| 70 | {false, "Reserved"}, |
| 71 | }; |
| 72 | |
| 73 | static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_0[] = { |
| 74 | {false, "Reserved"}, |
| 75 | {true, "SSU_ETS_PORT_STATUS"}, |
| 76 | {true, "SSU_ETS_TCG_STATUS"}, |
| 77 | {false, "Reserved"}, |
| 78 | {false, "Reserved"}, |
| 79 | {true, "SSU_BP_STATUS_0"}, |
| 80 | |
| 81 | {true, "SSU_BP_STATUS_1"}, |
| 82 | {true, "SSU_BP_STATUS_2"}, |
| 83 | {true, "SSU_BP_STATUS_3"}, |
| 84 | {true, "SSU_BP_STATUS_4"}, |
| 85 | {true, "SSU_BP_STATUS_5"}, |
| 86 | {true, "SSU_MAC_TX_PFC_IND"}, |
| 87 | |
| 88 | {true, "MAC_SSU_RX_PFC_IND"}, |
| 89 | {true, "BTMP_AGEING_ST_B0"}, |
| 90 | {true, "BTMP_AGEING_ST_B1"}, |
| 91 | {true, "BTMP_AGEING_ST_B2"}, |
| 92 | {false, "Reserved"}, |
| 93 | {false, "Reserved"}, |
| 94 | |
| 95 | {true, "FULL_DROP_NUM"}, |
| 96 | {true, "PART_DROP_NUM"}, |
| 97 | {true, "PPP_KEY_DROP_NUM"}, |
| 98 | {true, "PPP_RLT_DROP_NUM"}, |
| 99 | {true, "LO_PRI_UNICAST_RLT_DROP_NUM"}, |
| 100 | {true, "HI_PRI_MULTICAST_RLT_DROP_NUM"}, |
| 101 | |
| 102 | {true, "LO_PRI_MULTICAST_RLT_DROP_NUM"}, |
| 103 | {true, "NCSI_PACKET_CURR_BUFFER_CNT"}, |
| 104 | {true, "BTMP_AGEING_RLS_CNT_BANK0"}, |
| 105 | {true, "BTMP_AGEING_RLS_CNT_BANK1"}, |
| 106 | {true, "BTMP_AGEING_RLS_CNT_BANK2"}, |
| 107 | {true, "SSU_MB_RD_RLT_DROP_CNT"}, |
| 108 | |
| 109 | {true, "SSU_PPP_MAC_KEY_NUM_L"}, |
| 110 | {true, "SSU_PPP_MAC_KEY_NUM_H"}, |
| 111 | {true, "SSU_PPP_HOST_KEY_NUM_L"}, |
| 112 | {true, "SSU_PPP_HOST_KEY_NUM_H"}, |
| 113 | {true, "PPP_SSU_MAC_RLT_NUM_L"}, |
| 114 | {true, "PPP_SSU_MAC_RLT_NUM_H"}, |
| 115 | |
| 116 | {true, "PPP_SSU_HOST_RLT_NUM_L"}, |
| 117 | {true, "PPP_SSU_HOST_RLT_NUM_H"}, |
| 118 | {true, "NCSI_RX_PACKET_IN_CNT_L"}, |
| 119 | {true, "NCSI_RX_PACKET_IN_CNT_H"}, |
| 120 | {true, "NCSI_TX_PACKET_OUT_CNT_L"}, |
| 121 | {true, "NCSI_TX_PACKET_OUT_CNT_H"}, |
| 122 | |
| 123 | {true, "SSU_KEY_DROP_NUM"}, |
| 124 | {true, "MB_UNCOPY_NUM"}, |
| 125 | {true, "RX_OQ_DROP_PKT_CNT"}, |
| 126 | {true, "TX_OQ_DROP_PKT_CNT"}, |
| 127 | {true, "BANK_UNBALANCE_DROP_CNT"}, |
| 128 | {true, "BANK_UNBALANCE_RX_DROP_CNT"}, |
| 129 | |
| 130 | {true, "NIC_L2_ERR_DROP_PKT_CNT"}, |
| 131 | {true, "ROC_L2_ERR_DROP_PKT_CNT"}, |
| 132 | {true, "NIC_L2_ERR_DROP_PKT_CNT_RX"}, |
| 133 | {true, "ROC_L2_ERR_DROP_PKT_CNT_RX"}, |
| 134 | {true, "RX_OQ_GLB_DROP_PKT_CNT"}, |
| 135 | {false, "Reserved"}, |
| 136 | |
| 137 | {true, "LO_PRI_UNICAST_CUR_CNT"}, |
| 138 | {true, "HI_PRI_MULTICAST_CUR_CNT"}, |
| 139 | {true, "LO_PRI_MULTICAST_CUR_CNT"}, |
| 140 | {false, "Reserved"}, |
| 141 | {false, "Reserved"}, |
| 142 | {false, "Reserved"}, |
| 143 | }; |
| 144 | |
| 145 | static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_1[] = { |
| 146 | {true, "prt_id"}, |
| 147 | {true, "PACKET_TC_CURR_BUFFER_CNT_0"}, |
| 148 | {true, "PACKET_TC_CURR_BUFFER_CNT_1"}, |
| 149 | {true, "PACKET_TC_CURR_BUFFER_CNT_2"}, |
| 150 | {true, "PACKET_TC_CURR_BUFFER_CNT_3"}, |
| 151 | {true, "PACKET_TC_CURR_BUFFER_CNT_4"}, |
| 152 | |
| 153 | {true, "PACKET_TC_CURR_BUFFER_CNT_5"}, |
| 154 | {true, "PACKET_TC_CURR_BUFFER_CNT_6"}, |
| 155 | {true, "PACKET_TC_CURR_BUFFER_CNT_7"}, |
| 156 | {true, "PACKET_CURR_BUFFER_CNT"}, |
| 157 | {false, "Reserved"}, |
| 158 | {false, "Reserved"}, |
| 159 | |
| 160 | {true, "RX_PACKET_IN_CNT_L"}, |
| 161 | {true, "RX_PACKET_IN_CNT_H"}, |
| 162 | {true, "RX_PACKET_OUT_CNT_L"}, |
| 163 | {true, "RX_PACKET_OUT_CNT_H"}, |
| 164 | {true, "TX_PACKET_IN_CNT_L"}, |
| 165 | {true, "TX_PACKET_IN_CNT_H"}, |
| 166 | |
| 167 | {true, "TX_PACKET_OUT_CNT_L"}, |
| 168 | {true, "TX_PACKET_OUT_CNT_H"}, |
| 169 | {true, "ROC_RX_PACKET_IN_CNT_L"}, |
| 170 | {true, "ROC_RX_PACKET_IN_CNT_H"}, |
| 171 | {true, "ROC_TX_PACKET_OUT_CNT_L"}, |
| 172 | {true, "ROC_TX_PACKET_OUT_CNT_H"}, |
| 173 | |
| 174 | {true, "RX_PACKET_TC_IN_CNT_0_L"}, |
| 175 | {true, "RX_PACKET_TC_IN_CNT_0_H"}, |
| 176 | {true, "RX_PACKET_TC_IN_CNT_1_L"}, |
| 177 | {true, "RX_PACKET_TC_IN_CNT_1_H"}, |
| 178 | {true, "RX_PACKET_TC_IN_CNT_2_L"}, |
| 179 | {true, "RX_PACKET_TC_IN_CNT_2_H"}, |
| 180 | |
| 181 | {true, "RX_PACKET_TC_IN_CNT_3_L"}, |
| 182 | {true, "RX_PACKET_TC_IN_CNT_3_H"}, |
| 183 | {true, "RX_PACKET_TC_IN_CNT_4_L"}, |
| 184 | {true, "RX_PACKET_TC_IN_CNT_4_H"}, |
| 185 | {true, "RX_PACKET_TC_IN_CNT_5_L"}, |
| 186 | {true, "RX_PACKET_TC_IN_CNT_5_H"}, |
| 187 | |
| 188 | {true, "RX_PACKET_TC_IN_CNT_6_L"}, |
| 189 | {true, "RX_PACKET_TC_IN_CNT_6_H"}, |
| 190 | {true, "RX_PACKET_TC_IN_CNT_7_L"}, |
| 191 | {true, "RX_PACKET_TC_IN_CNT_7_H"}, |
| 192 | {true, "RX_PACKET_TC_OUT_CNT_0_L"}, |
| 193 | {true, "RX_PACKET_TC_OUT_CNT_0_H"}, |
| 194 | |
| 195 | {true, "RX_PACKET_TC_OUT_CNT_1_L"}, |
| 196 | {true, "RX_PACKET_TC_OUT_CNT_1_H"}, |
| 197 | {true, "RX_PACKET_TC_OUT_CNT_2_L"}, |
| 198 | {true, "RX_PACKET_TC_OUT_CNT_2_H"}, |
| 199 | {true, "RX_PACKET_TC_OUT_CNT_3_L"}, |
| 200 | {true, "RX_PACKET_TC_OUT_CNT_3_H"}, |
| 201 | |
| 202 | {true, "RX_PACKET_TC_OUT_CNT_4_L"}, |
| 203 | {true, "RX_PACKET_TC_OUT_CNT_4_H"}, |
| 204 | {true, "RX_PACKET_TC_OUT_CNT_5_L"}, |
| 205 | {true, "RX_PACKET_TC_OUT_CNT_5_H"}, |
| 206 | {true, "RX_PACKET_TC_OUT_CNT_6_L"}, |
| 207 | {true, "RX_PACKET_TC_OUT_CNT_6_H"}, |
| 208 | |
| 209 | {true, "RX_PACKET_TC_OUT_CNT_7_L"}, |
| 210 | {true, "RX_PACKET_TC_OUT_CNT_7_H"}, |
| 211 | {true, "TX_PACKET_TC_IN_CNT_0_L"}, |
| 212 | {true, "TX_PACKET_TC_IN_CNT_0_H"}, |
| 213 | {true, "TX_PACKET_TC_IN_CNT_1_L"}, |
| 214 | {true, "TX_PACKET_TC_IN_CNT_1_H"}, |
| 215 | |
| 216 | {true, "TX_PACKET_TC_IN_CNT_2_L"}, |
| 217 | {true, "TX_PACKET_TC_IN_CNT_2_H"}, |
| 218 | {true, "TX_PACKET_TC_IN_CNT_3_L"}, |
| 219 | {true, "TX_PACKET_TC_IN_CNT_3_H"}, |
| 220 | {true, "TX_PACKET_TC_IN_CNT_4_L"}, |
| 221 | {true, "TX_PACKET_TC_IN_CNT_4_H"}, |
| 222 | |
| 223 | {true, "TX_PACKET_TC_IN_CNT_5_L"}, |
| 224 | {true, "TX_PACKET_TC_IN_CNT_5_H"}, |
| 225 | {true, "TX_PACKET_TC_IN_CNT_6_L"}, |
| 226 | {true, "TX_PACKET_TC_IN_CNT_6_H"}, |
| 227 | {true, "TX_PACKET_TC_IN_CNT_7_L"}, |
| 228 | {true, "TX_PACKET_TC_IN_CNT_7_H"}, |
| 229 | |
| 230 | {true, "TX_PACKET_TC_OUT_CNT_0_L"}, |
| 231 | {true, "TX_PACKET_TC_OUT_CNT_0_H"}, |
| 232 | {true, "TX_PACKET_TC_OUT_CNT_1_L"}, |
| 233 | {true, "TX_PACKET_TC_OUT_CNT_1_H"}, |
| 234 | {true, "TX_PACKET_TC_OUT_CNT_2_L"}, |
| 235 | {true, "TX_PACKET_TC_OUT_CNT_2_H"}, |
| 236 | |
| 237 | {true, "TX_PACKET_TC_OUT_CNT_3_L"}, |
| 238 | {true, "TX_PACKET_TC_OUT_CNT_3_H"}, |
| 239 | {true, "TX_PACKET_TC_OUT_CNT_4_L"}, |
| 240 | {true, "TX_PACKET_TC_OUT_CNT_4_H"}, |
| 241 | {true, "TX_PACKET_TC_OUT_CNT_5_L"}, |
| 242 | {true, "TX_PACKET_TC_OUT_CNT_5_H"}, |
| 243 | |
| 244 | {true, "TX_PACKET_TC_OUT_CNT_6_L"}, |
| 245 | {true, "TX_PACKET_TC_OUT_CNT_6_H"}, |
| 246 | {true, "TX_PACKET_TC_OUT_CNT_7_L"}, |
| 247 | {true, "TX_PACKET_TC_OUT_CNT_7_H"}, |
| 248 | {false, "Reserved"}, |
| 249 | {false, "Reserved"}, |
| 250 | }; |
| 251 | |
| 252 | static struct hclge_dbg_dfx_message hclge_dbg_ssu_reg_2[] = { |
| 253 | {true, "OQ_INDEX"}, |
| 254 | {true, "QUEUE_CNT"}, |
| 255 | {false, "Reserved"}, |
| 256 | {false, "Reserved"}, |
| 257 | {false, "Reserved"}, |
| 258 | {false, "Reserved"}, |
| 259 | }; |
| 260 | |
| 261 | static struct hclge_dbg_dfx_message hclge_dbg_igu_egu_reg[] = { |
| 262 | {true, "prt_id"}, |
| 263 | {true, "IGU_RX_ERR_PKT"}, |
| 264 | {true, "IGU_RX_NO_SOF_PKT"}, |
| 265 | {true, "EGU_TX_1588_SHORT_PKT"}, |
| 266 | {true, "EGU_TX_1588_PKT"}, |
| 267 | {true, "EGU_TX_ERR_PKT"}, |
| 268 | |
| 269 | {true, "IGU_RX_OUT_L2_PKT"}, |
| 270 | {true, "IGU_RX_OUT_L3_PKT"}, |
| 271 | {true, "IGU_RX_OUT_L4_PKT"}, |
| 272 | {true, "IGU_RX_IN_L2_PKT"}, |
| 273 | {true, "IGU_RX_IN_L3_PKT"}, |
| 274 | {true, "IGU_RX_IN_L4_PKT"}, |
| 275 | |
| 276 | {true, "IGU_RX_EL3E_PKT"}, |
| 277 | {true, "IGU_RX_EL4E_PKT"}, |
| 278 | {true, "IGU_RX_L3E_PKT"}, |
| 279 | {true, "IGU_RX_L4E_PKT"}, |
| 280 | {true, "IGU_RX_ROCEE_PKT"}, |
| 281 | {true, "IGU_RX_OUT_UDP0_PKT"}, |
| 282 | |
| 283 | {true, "IGU_RX_IN_UDP0_PKT"}, |
| 284 | {false, "Reserved"}, |
| 285 | {false, "Reserved"}, |
| 286 | {false, "Reserved"}, |
| 287 | {false, "Reserved"}, |
| 288 | {false, "Reserved"}, |
| 289 | |
| 290 | {true, "IGU_RX_OVERSIZE_PKT_L"}, |
| 291 | {true, "IGU_RX_OVERSIZE_PKT_H"}, |
| 292 | {true, "IGU_RX_UNDERSIZE_PKT_L"}, |
| 293 | {true, "IGU_RX_UNDERSIZE_PKT_H"}, |
| 294 | {true, "IGU_RX_OUT_ALL_PKT_L"}, |
| 295 | {true, "IGU_RX_OUT_ALL_PKT_H"}, |
| 296 | |
| 297 | {true, "IGU_TX_OUT_ALL_PKT_L"}, |
| 298 | {true, "IGU_TX_OUT_ALL_PKT_H"}, |
| 299 | {true, "IGU_RX_UNI_PKT_L"}, |
| 300 | {true, "IGU_RX_UNI_PKT_H"}, |
| 301 | {true, "IGU_RX_MULTI_PKT_L"}, |
| 302 | {true, "IGU_RX_MULTI_PKT_H"}, |
| 303 | |
| 304 | {true, "IGU_RX_BROAD_PKT_L"}, |
| 305 | {true, "IGU_RX_BROAD_PKT_H"}, |
| 306 | {true, "EGU_TX_OUT_ALL_PKT_L"}, |
| 307 | {true, "EGU_TX_OUT_ALL_PKT_H"}, |
| 308 | {true, "EGU_TX_UNI_PKT_L"}, |
| 309 | {true, "EGU_TX_UNI_PKT_H"}, |
| 310 | |
| 311 | {true, "EGU_TX_MULTI_PKT_L"}, |
| 312 | {true, "EGU_TX_MULTI_PKT_H"}, |
| 313 | {true, "EGU_TX_BROAD_PKT_L"}, |
| 314 | {true, "EGU_TX_BROAD_PKT_H"}, |
| 315 | {true, "IGU_TX_KEY_NUM_L"}, |
| 316 | {true, "IGU_TX_KEY_NUM_H"}, |
| 317 | |
| 318 | {true, "IGU_RX_NON_TUN_PKT_L"}, |
| 319 | {true, "IGU_RX_NON_TUN_PKT_H"}, |
| 320 | {true, "IGU_RX_TUN_PKT_L"}, |
| 321 | {true, "IGU_RX_TUN_PKT_H"}, |
| 322 | {false, "Reserved"}, |
| 323 | {false, "Reserved"}, |
| 324 | }; |
| 325 | |
| 326 | static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_0[] = { |
| 327 | {true, "tc_queue_num"}, |
| 328 | {true, "FSM_DFX_ST0"}, |
| 329 | {true, "FSM_DFX_ST1"}, |
| 330 | {true, "RPU_RX_PKT_DROP_CNT"}, |
| 331 | {true, "BUF_WAIT_TIMEOUT"}, |
| 332 | {true, "BUF_WAIT_TIMEOUT_QID"}, |
| 333 | }; |
| 334 | |
| 335 | static struct hclge_dbg_dfx_message hclge_dbg_rpu_reg_1[] = { |
| 336 | {false, "Reserved"}, |
| 337 | {true, "FIFO_DFX_ST0"}, |
| 338 | {true, "FIFO_DFX_ST1"}, |
| 339 | {true, "FIFO_DFX_ST2"}, |
| 340 | {true, "FIFO_DFX_ST3"}, |
| 341 | {true, "FIFO_DFX_ST4"}, |
| 342 | |
| 343 | {true, "FIFO_DFX_ST5"}, |
| 344 | {false, "Reserved"}, |
| 345 | {false, "Reserved"}, |
| 346 | {false, "Reserved"}, |
| 347 | {false, "Reserved"}, |
| 348 | {false, "Reserved"}, |
| 349 | }; |
| 350 | |
| 351 | static struct hclge_dbg_dfx_message hclge_dbg_ncsi_reg[] = { |
| 352 | {false, "Reserved"}, |
| 353 | {true, "NCSI_EGU_TX_FIFO_STS"}, |
| 354 | {true, "NCSI_PAUSE_STATUS"}, |
| 355 | {true, "NCSI_RX_CTRL_DMAC_ERR_CNT"}, |
| 356 | {true, "NCSI_RX_CTRL_SMAC_ERR_CNT"}, |
| 357 | {true, "NCSI_RX_CTRL_CKS_ERR_CNT"}, |
| 358 | |
| 359 | {true, "NCSI_RX_CTRL_PKT_CNT"}, |
| 360 | {true, "NCSI_RX_PT_DMAC_ERR_CNT"}, |
| 361 | {true, "NCSI_RX_PT_SMAC_ERR_CNT"}, |
| 362 | {true, "NCSI_RX_PT_PKT_CNT"}, |
| 363 | {true, "NCSI_RX_FCS_ERR_CNT"}, |
| 364 | {true, "NCSI_TX_CTRL_DMAC_ERR_CNT"}, |
| 365 | |
| 366 | {true, "NCSI_TX_CTRL_SMAC_ERR_CNT"}, |
| 367 | {true, "NCSI_TX_CTRL_PKT_CNT"}, |
| 368 | {true, "NCSI_TX_PT_DMAC_ERR_CNT"}, |
| 369 | {true, "NCSI_TX_PT_SMAC_ERR_CNT"}, |
| 370 | {true, "NCSI_TX_PT_PKT_CNT"}, |
| 371 | {true, "NCSI_TX_PT_PKT_TRUNC_CNT"}, |
| 372 | |
| 373 | {true, "NCSI_TX_PT_PKT_ERR_CNT"}, |
| 374 | {true, "NCSI_TX_CTRL_PKT_ERR_CNT"}, |
| 375 | {true, "NCSI_RX_CTRL_PKT_TRUNC_CNT"}, |
| 376 | {true, "NCSI_RX_CTRL_PKT_CFLIT_CNT"}, |
| 377 | {false, "Reserved"}, |
| 378 | {false, "Reserved"}, |
| 379 | |
| 380 | {true, "NCSI_MAC_RX_OCTETS_OK"}, |
| 381 | {true, "NCSI_MAC_RX_OCTETS_BAD"}, |
| 382 | {true, "NCSI_MAC_RX_UC_PKTS"}, |
| 383 | {true, "NCSI_MAC_RX_MC_PKTS"}, |
| 384 | {true, "NCSI_MAC_RX_BC_PKTS"}, |
| 385 | {true, "NCSI_MAC_RX_PKTS_64OCTETS"}, |
| 386 | |
| 387 | {true, "NCSI_MAC_RX_PKTS_65TO127OCTETS"}, |
| 388 | {true, "NCSI_MAC_RX_PKTS_128TO255OCTETS"}, |
| 389 | {true, "NCSI_MAC_RX_PKTS_255TO511OCTETS"}, |
| 390 | {true, "NCSI_MAC_RX_PKTS_512TO1023OCTETS"}, |
| 391 | {true, "NCSI_MAC_RX_PKTS_1024TO1518OCTETS"}, |
| 392 | {true, "NCSI_MAC_RX_PKTS_1519TOMAXOCTETS"}, |
| 393 | |
| 394 | {true, "NCSI_MAC_RX_FCS_ERRORS"}, |
| 395 | {true, "NCSI_MAC_RX_LONG_ERRORS"}, |
| 396 | {true, "NCSI_MAC_RX_JABBER_ERRORS"}, |
| 397 | {true, "NCSI_MAC_RX_RUNT_ERR_CNT"}, |
| 398 | {true, "NCSI_MAC_RX_SHORT_ERR_CNT"}, |
| 399 | {true, "NCSI_MAC_RX_FILT_PKT_CNT"}, |
| 400 | |
| 401 | {true, "NCSI_MAC_RX_OCTETS_TOTAL_FILT"}, |
| 402 | {true, "NCSI_MAC_TX_OCTETS_OK"}, |
| 403 | {true, "NCSI_MAC_TX_OCTETS_BAD"}, |
| 404 | {true, "NCSI_MAC_TX_UC_PKTS"}, |
| 405 | {true, "NCSI_MAC_TX_MC_PKTS"}, |
| 406 | {true, "NCSI_MAC_TX_BC_PKTS"}, |
| 407 | |
| 408 | {true, "NCSI_MAC_TX_PKTS_64OCTETS"}, |
| 409 | {true, "NCSI_MAC_TX_PKTS_65TO127OCTETS"}, |
| 410 | {true, "NCSI_MAC_TX_PKTS_128TO255OCTETS"}, |
| 411 | {true, "NCSI_MAC_TX_PKTS_256TO511OCTETS"}, |
| 412 | {true, "NCSI_MAC_TX_PKTS_512TO1023OCTETS"}, |
| 413 | {true, "NCSI_MAC_TX_PKTS_1024TO1518OCTETS"}, |
| 414 | |
| 415 | {true, "NCSI_MAC_TX_PKTS_1519TOMAXOCTETS"}, |
| 416 | {true, "NCSI_MAC_TX_UNDERRUN"}, |
| 417 | {true, "NCSI_MAC_TX_CRC_ERROR"}, |
| 418 | {true, "NCSI_MAC_TX_PAUSE_FRAMES"}, |
| 419 | {true, "NCSI_MAC_RX_PAD_PKTS"}, |
| 420 | {true, "NCSI_MAC_RX_PAUSE_FRAMES"}, |
| 421 | }; |
| 422 | |
| 423 | static struct hclge_dbg_dfx_message hclge_dbg_rtc_reg[] = { |
| 424 | {false, "Reserved"}, |
| 425 | {true, "LGE_IGU_AFIFO_DFX_0"}, |
| 426 | {true, "LGE_IGU_AFIFO_DFX_1"}, |
| 427 | {true, "LGE_IGU_AFIFO_DFX_2"}, |
| 428 | {true, "LGE_IGU_AFIFO_DFX_3"}, |
| 429 | {true, "LGE_IGU_AFIFO_DFX_4"}, |
| 430 | |
| 431 | {true, "LGE_IGU_AFIFO_DFX_5"}, |
| 432 | {true, "LGE_IGU_AFIFO_DFX_6"}, |
| 433 | {true, "LGE_IGU_AFIFO_DFX_7"}, |
| 434 | {true, "LGE_EGU_AFIFO_DFX_0"}, |
| 435 | {true, "LGE_EGU_AFIFO_DFX_1"}, |
| 436 | {true, "LGE_EGU_AFIFO_DFX_2"}, |
| 437 | |
| 438 | {true, "LGE_EGU_AFIFO_DFX_3"}, |
| 439 | {true, "LGE_EGU_AFIFO_DFX_4"}, |
| 440 | {true, "LGE_EGU_AFIFO_DFX_5"}, |
| 441 | {true, "LGE_EGU_AFIFO_DFX_6"}, |
| 442 | {true, "LGE_EGU_AFIFO_DFX_7"}, |
| 443 | {true, "CGE_IGU_AFIFO_DFX_0"}, |
| 444 | |
| 445 | {true, "CGE_IGU_AFIFO_DFX_1"}, |
| 446 | {true, "CGE_EGU_AFIFO_DFX_0"}, |
| 447 | {true, "CGE_EGU_AFIFO_DFX_1"}, |
| 448 | {false, "Reserved"}, |
| 449 | {false, "Reserved"}, |
| 450 | {false, "Reserved"}, |
| 451 | }; |
| 452 | |
| 453 | static struct hclge_dbg_dfx_message hclge_dbg_ppp_reg[] = { |
| 454 | {false, "Reserved"}, |
| 455 | {true, "DROP_FROM_PRT_PKT_CNT"}, |
| 456 | {true, "DROP_FROM_HOST_PKT_CNT"}, |
| 457 | {true, "DROP_TX_VLAN_PROC_CNT"}, |
| 458 | {true, "DROP_MNG_CNT"}, |
| 459 | {true, "DROP_FD_CNT"}, |
| 460 | |
| 461 | {true, "DROP_NO_DST_CNT"}, |
| 462 | {true, "DROP_MC_MBID_FULL_CNT"}, |
| 463 | {true, "DROP_SC_FILTERED"}, |
| 464 | {true, "PPP_MC_DROP_PKT_CNT"}, |
| 465 | {true, "DROP_PT_CNT"}, |
| 466 | {true, "DROP_MAC_ANTI_SPOOF_CNT"}, |
| 467 | |
| 468 | {true, "DROP_IG_VFV_CNT"}, |
| 469 | {true, "DROP_IG_PRTV_CNT"}, |
| 470 | {true, "DROP_CNM_PFC_PAUSE_CNT"}, |
| 471 | {true, "DROP_TORUS_TC_CNT"}, |
| 472 | {true, "DROP_TORUS_LPBK_CNT"}, |
| 473 | {true, "PPP_HFS_STS"}, |
| 474 | |
| 475 | {true, "PPP_MC_RSLT_STS"}, |
| 476 | {true, "PPP_P3U_STS"}, |
| 477 | {true, "PPP_RSLT_DESCR_STS"}, |
| 478 | {true, "PPP_UMV_STS_0"}, |
| 479 | {true, "PPP_UMV_STS_1"}, |
| 480 | {true, "PPP_VFV_STS"}, |
| 481 | |
| 482 | {true, "PPP_GRO_KEY_CNT"}, |
| 483 | {true, "PPP_GRO_INFO_CNT"}, |
| 484 | {true, "PPP_GRO_DROP_CNT"}, |
| 485 | {true, "PPP_GRO_OUT_CNT"}, |
| 486 | {true, "PPP_GRO_KEY_MATCH_DATA_CNT"}, |
| 487 | {true, "PPP_GRO_KEY_MATCH_TCAM_CNT"}, |
| 488 | |
| 489 | {true, "PPP_GRO_INFO_MATCH_CNT"}, |
| 490 | {true, "PPP_GRO_FREE_ENTRY_CNT"}, |
| 491 | {true, "PPP_GRO_INNER_DFX_SIGNAL"}, |
| 492 | {false, "Reserved"}, |
| 493 | {false, "Reserved"}, |
| 494 | {false, "Reserved"}, |
| 495 | |
| 496 | {true, "GET_RX_PKT_CNT_L"}, |
| 497 | {true, "GET_RX_PKT_CNT_H"}, |
| 498 | {true, "GET_TX_PKT_CNT_L"}, |
| 499 | {true, "GET_TX_PKT_CNT_H"}, |
| 500 | {true, "SEND_UC_PRT2HOST_PKT_CNT_L"}, |
| 501 | {true, "SEND_UC_PRT2HOST_PKT_CNT_H"}, |
| 502 | |
| 503 | {true, "SEND_UC_PRT2PRT_PKT_CNT_L"}, |
| 504 | {true, "SEND_UC_PRT2PRT_PKT_CNT_H"}, |
| 505 | {true, "SEND_UC_HOST2HOST_PKT_CNT_L"}, |
| 506 | {true, "SEND_UC_HOST2HOST_PKT_CNT_H"}, |
| 507 | {true, "SEND_UC_HOST2PRT_PKT_CNT_L"}, |
| 508 | {true, "SEND_UC_HOST2PRT_PKT_CNT_H"}, |
| 509 | |
| 510 | {true, "SEND_MC_FROM_PRT_CNT_L"}, |
| 511 | {true, "SEND_MC_FROM_PRT_CNT_H"}, |
| 512 | {true, "SEND_MC_FROM_HOST_CNT_L"}, |
| 513 | {true, "SEND_MC_FROM_HOST_CNT_H"}, |
| 514 | {true, "SSU_MC_RD_CNT_L"}, |
| 515 | {true, "SSU_MC_RD_CNT_H"}, |
| 516 | |
| 517 | {true, "SSU_MC_DROP_CNT_L"}, |
| 518 | {true, "SSU_MC_DROP_CNT_H"}, |
| 519 | {true, "SSU_MC_RD_PKT_CNT_L"}, |
| 520 | {true, "SSU_MC_RD_PKT_CNT_H"}, |
| 521 | {true, "PPP_MC_2HOST_PKT_CNT_L"}, |
| 522 | {true, "PPP_MC_2HOST_PKT_CNT_H"}, |
| 523 | |
| 524 | {true, "PPP_MC_2PRT_PKT_CNT_L"}, |
| 525 | {true, "PPP_MC_2PRT_PKT_CNT_H"}, |
| 526 | {true, "NTSNOS_PKT_CNT_L"}, |
| 527 | {true, "NTSNOS_PKT_CNT_H"}, |
| 528 | {true, "NTUP_PKT_CNT_L"}, |
| 529 | {true, "NTUP_PKT_CNT_H"}, |
| 530 | |
| 531 | {true, "NTLCL_PKT_CNT_L"}, |
| 532 | {true, "NTLCL_PKT_CNT_H"}, |
| 533 | {true, "NTTGT_PKT_CNT_L"}, |
| 534 | {true, "NTTGT_PKT_CNT_H"}, |
| 535 | {true, "RTNS_PKT_CNT_L"}, |
| 536 | {true, "RTNS_PKT_CNT_H"}, |
| 537 | |
| 538 | {true, "RTLPBK_PKT_CNT_L"}, |
| 539 | {true, "RTLPBK_PKT_CNT_H"}, |
| 540 | {true, "NR_PKT_CNT_L"}, |
| 541 | {true, "NR_PKT_CNT_H"}, |
| 542 | {true, "RR_PKT_CNT_L"}, |
| 543 | {true, "RR_PKT_CNT_H"}, |
| 544 | |
| 545 | {true, "MNG_TBL_HIT_CNT_L"}, |
| 546 | {true, "MNG_TBL_HIT_CNT_H"}, |
| 547 | {true, "FD_TBL_HIT_CNT_L"}, |
| 548 | {true, "FD_TBL_HIT_CNT_H"}, |
| 549 | {true, "FD_LKUP_CNT_L"}, |
| 550 | {true, "FD_LKUP_CNT_H"}, |
| 551 | |
| 552 | {true, "BC_HIT_CNT_L"}, |
| 553 | {true, "BC_HIT_CNT_H"}, |
| 554 | {true, "UM_TBL_UC_HIT_CNT_L"}, |
| 555 | {true, "UM_TBL_UC_HIT_CNT_H"}, |
| 556 | {true, "UM_TBL_MC_HIT_CNT_L"}, |
| 557 | {true, "UM_TBL_MC_HIT_CNT_H"}, |
| 558 | |
| 559 | {true, "UM_TBL_VMDQ1_HIT_CNT_L"}, |
| 560 | {true, "UM_TBL_VMDQ1_HIT_CNT_H"}, |
| 561 | {true, "MTA_TBL_HIT_CNT_L"}, |
| 562 | {true, "MTA_TBL_HIT_CNT_H"}, |
| 563 | {true, "FWD_BONDING_HIT_CNT_L"}, |
| 564 | {true, "FWD_BONDING_HIT_CNT_H"}, |
| 565 | |
| 566 | {true, "PROMIS_TBL_HIT_CNT_L"}, |
| 567 | {true, "PROMIS_TBL_HIT_CNT_H"}, |
| 568 | {true, "GET_TUNL_PKT_CNT_L"}, |
| 569 | {true, "GET_TUNL_PKT_CNT_H"}, |
| 570 | {true, "GET_BMC_PKT_CNT_L"}, |
| 571 | {true, "GET_BMC_PKT_CNT_H"}, |
| 572 | |
| 573 | {true, "SEND_UC_PRT2BMC_PKT_CNT_L"}, |
| 574 | {true, "SEND_UC_PRT2BMC_PKT_CNT_H"}, |
| 575 | {true, "SEND_UC_HOST2BMC_PKT_CNT_L"}, |
| 576 | {true, "SEND_UC_HOST2BMC_PKT_CNT_H"}, |
| 577 | {true, "SEND_UC_BMC2HOST_PKT_CNT_L"}, |
| 578 | {true, "SEND_UC_BMC2HOST_PKT_CNT_H"}, |
| 579 | |
| 580 | {true, "SEND_UC_BMC2PRT_PKT_CNT_L"}, |
| 581 | {true, "SEND_UC_BMC2PRT_PKT_CNT_H"}, |
| 582 | {true, "PPP_MC_2BMC_PKT_CNT_L"}, |
| 583 | {true, "PPP_MC_2BMC_PKT_CNT_H"}, |
| 584 | {true, "VLAN_MIRR_CNT_L"}, |
| 585 | {true, "VLAN_MIRR_CNT_H"}, |
| 586 | |
| 587 | {true, "IG_MIRR_CNT_L"}, |
| 588 | {true, "IG_MIRR_CNT_H"}, |
| 589 | {true, "EG_MIRR_CNT_L"}, |
| 590 | {true, "EG_MIRR_CNT_H"}, |
| 591 | {true, "RX_DEFAULT_HOST_HIT_CNT_L"}, |
| 592 | {true, "RX_DEFAULT_HOST_HIT_CNT_H"}, |
| 593 | |
| 594 | {true, "LAN_PAIR_CNT_L"}, |
| 595 | {true, "LAN_PAIR_CNT_H"}, |
| 596 | {true, "UM_TBL_MC_HIT_PKT_CNT_L"}, |
| 597 | {true, "UM_TBL_MC_HIT_PKT_CNT_H"}, |
| 598 | {true, "MTA_TBL_HIT_PKT_CNT_L"}, |
| 599 | {true, "MTA_TBL_HIT_PKT_CNT_H"}, |
| 600 | |
| 601 | {true, "PROMIS_TBL_HIT_PKT_CNT_L"}, |
| 602 | {true, "PROMIS_TBL_HIT_PKT_CNT_H"}, |
| 603 | {false, "Reserved"}, |
| 604 | {false, "Reserved"}, |
| 605 | {false, "Reserved"}, |
| 606 | {false, "Reserved"}, |
| 607 | }; |
| 608 | |
| 609 | static struct hclge_dbg_dfx_message hclge_dbg_rcb_reg[] = { |
| 610 | {false, "Reserved"}, |
| 611 | {true, "FSM_DFX_ST0"}, |
| 612 | {true, "FSM_DFX_ST1"}, |
| 613 | {true, "FSM_DFX_ST2"}, |
| 614 | {true, "FIFO_DFX_ST0"}, |
| 615 | {true, "FIFO_DFX_ST1"}, |
| 616 | |
| 617 | {true, "FIFO_DFX_ST2"}, |
| 618 | {true, "FIFO_DFX_ST3"}, |
| 619 | {true, "FIFO_DFX_ST4"}, |
| 620 | {true, "FIFO_DFX_ST5"}, |
| 621 | {true, "FIFO_DFX_ST6"}, |
| 622 | {true, "FIFO_DFX_ST7"}, |
| 623 | |
| 624 | {true, "FIFO_DFX_ST8"}, |
| 625 | {true, "FIFO_DFX_ST9"}, |
| 626 | {true, "FIFO_DFX_ST10"}, |
| 627 | {true, "FIFO_DFX_ST11"}, |
| 628 | {true, "Q_CREDIT_VLD_0"}, |
| 629 | {true, "Q_CREDIT_VLD_1"}, |
| 630 | |
| 631 | {true, "Q_CREDIT_VLD_2"}, |
| 632 | {true, "Q_CREDIT_VLD_3"}, |
| 633 | {true, "Q_CREDIT_VLD_4"}, |
| 634 | {true, "Q_CREDIT_VLD_5"}, |
| 635 | {true, "Q_CREDIT_VLD_6"}, |
| 636 | {true, "Q_CREDIT_VLD_7"}, |
| 637 | |
| 638 | {true, "Q_CREDIT_VLD_8"}, |
| 639 | {true, "Q_CREDIT_VLD_9"}, |
| 640 | {true, "Q_CREDIT_VLD_10"}, |
| 641 | {true, "Q_CREDIT_VLD_11"}, |
| 642 | {true, "Q_CREDIT_VLD_12"}, |
| 643 | {true, "Q_CREDIT_VLD_13"}, |
| 644 | |
| 645 | {true, "Q_CREDIT_VLD_14"}, |
| 646 | {true, "Q_CREDIT_VLD_15"}, |
| 647 | {true, "Q_CREDIT_VLD_16"}, |
| 648 | {true, "Q_CREDIT_VLD_17"}, |
| 649 | {true, "Q_CREDIT_VLD_18"}, |
| 650 | {true, "Q_CREDIT_VLD_19"}, |
| 651 | |
| 652 | {true, "Q_CREDIT_VLD_20"}, |
| 653 | {true, "Q_CREDIT_VLD_21"}, |
| 654 | {true, "Q_CREDIT_VLD_22"}, |
| 655 | {true, "Q_CREDIT_VLD_23"}, |
| 656 | {true, "Q_CREDIT_VLD_24"}, |
| 657 | {true, "Q_CREDIT_VLD_25"}, |
| 658 | |
| 659 | {true, "Q_CREDIT_VLD_26"}, |
| 660 | {true, "Q_CREDIT_VLD_27"}, |
| 661 | {true, "Q_CREDIT_VLD_28"}, |
| 662 | {true, "Q_CREDIT_VLD_29"}, |
| 663 | {true, "Q_CREDIT_VLD_30"}, |
| 664 | {true, "Q_CREDIT_VLD_31"}, |
| 665 | |
| 666 | {true, "GRO_BD_SERR_CNT"}, |
| 667 | {true, "GRO_CONTEXT_SERR_CNT"}, |
| 668 | {true, "RX_STASH_CFG_SERR_CNT"}, |
| 669 | {true, "AXI_RD_FBD_SERR_CNT"}, |
| 670 | {true, "GRO_BD_MERR_CNT"}, |
| 671 | {true, "GRO_CONTEXT_MERR_CNT"}, |
| 672 | |
| 673 | {true, "RX_STASH_CFG_MERR_CNT"}, |
| 674 | {true, "AXI_RD_FBD_MERR_CNT"}, |
| 675 | {false, "Reserved"}, |
| 676 | {false, "Reserved"}, |
| 677 | {false, "Reserved"}, |
| 678 | {false, "Reserved"}, |
| 679 | }; |
| 680 | |
| 681 | static struct hclge_dbg_dfx_message hclge_dbg_tqp_reg[] = { |
| 682 | {true, "q_num"}, |
| 683 | {true, "RCB_CFG_RX_RING_TAIL"}, |
| 684 | {true, "RCB_CFG_RX_RING_HEAD"}, |
| 685 | {true, "RCB_CFG_RX_RING_FBDNUM"}, |
| 686 | {true, "RCB_CFG_RX_RING_OFFSET"}, |
| 687 | {true, "RCB_CFG_RX_RING_FBDOFFSET"}, |
| 688 | |
| 689 | {true, "RCB_CFG_RX_RING_PKTNUM_RECORD"}, |
| 690 | {true, "RCB_CFG_TX_RING_TAIL"}, |
| 691 | {true, "RCB_CFG_TX_RING_HEAD"}, |
| 692 | {true, "RCB_CFG_TX_RING_FBDNUM"}, |
| 693 | {true, "RCB_CFG_TX_RING_OFFSET"}, |
| 694 | {true, "RCB_CFG_TX_RING_EBDNUM"}, |
| 695 | }; |
| 696 | |
| c07b8f83 |
697 | #endif |
projects / mirror_ubuntu-bionic-kernel.git / blame