]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/nvme/host/core.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
nvme: Export get and set features
[mirror_ubuntu-bionic-kernel.git] / drivers / nvme / host / core.c
CommitLineData
21d34711
CH		 1/*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15#include <linux/blkdev.h>
16#include <linux/blk-mq.h>
5fd4ce1b 17#include <linux/delay.h>
21d34711 18#include <linux/errno.h>
1673f1f0 19#include <linux/hdreg.h>
21d34711 20#include <linux/kernel.h>
5bae7f73
CH		 21#include <linux/module.h>
22#include <linux/list_sort.h>
21d34711
CH		 23#include <linux/slab.h>
24#include <linux/types.h>
1673f1f0
CH		 25#include <linux/pr.h>
26#include <linux/ptrace.h>
27#include <linux/nvme_ioctl.h>
28#include <linux/t10-pi.h>
c5552fde 29#include <linux/pm_qos.h>
1673f1f0 30#include <asm/unaligned.h>
21d34711
CH		 31
32#include "nvme.h"
038bd4cb 33#include "fabrics.h"
21d34711 34
f3ca80fc
CH		 35#define NVME_MINORS (1U << MINORBITS)
36
8ae4e447
MO		 37unsigned int admin_timeout = 60;
38module_param(admin_timeout, uint, 0644);
ba0ba7d3 39MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
576d55d6 40EXPORT_SYMBOL_GPL(admin_timeout);
ba0ba7d3 41
8ae4e447
MO		 42unsigned int nvme_io_timeout = 30;
43module_param_named(io_timeout, nvme_io_timeout, uint, 0644);
ba0ba7d3 44MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
576d55d6 45EXPORT_SYMBOL_GPL(nvme_io_timeout);
ba0ba7d3 46
b3b1b0b0 47static unsigned char shutdown_timeout = 5;
ba0ba7d3
ML		 48module_param(shutdown_timeout, byte, 0644);
49MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
50
44e44b29
CH		 51static u8 nvme_max_retries = 5;
52module_param_named(max_retries, nvme_max_retries, byte, 0644);
f80ec966 53MODULE_PARM_DESC(max_retries, "max number of retries a command may have");
5bae7f73 54
9947d6a0 55static unsigned long default_ps_max_latency_us = 100000;
c5552fde
AL		 56module_param(default_ps_max_latency_us, ulong, 0644);
57MODULE_PARM_DESC(default_ps_max_latency_us,
58 "max power saving latency for new devices; use PM QOS to change per device");
59
c35e30b4
AL		 60static bool force_apst;
61module_param(force_apst, bool, 0644);
62MODULE_PARM_DESC(force_apst, "allow APST for newly enumerated devices even if quirked off");
63
f5d11840
JA		 64static bool streams;
65module_param(streams, bool, 0644);
66MODULE_PARM_DESC(streams, "turn on support for Streams write directives");
67
9a6327d2
SG		 68struct workqueue_struct *nvme_wq;
69EXPORT_SYMBOL_GPL(nvme_wq);
70
ab9e00cc
CH		 71static DEFINE_IDA(nvme_subsystems_ida);
72static LIST_HEAD(nvme_subsystems);
73static DEFINE_MUTEX(nvme_subsystems_lock);
1673f1f0 74
9843f685 75static DEFINE_IDA(nvme_instance_ida);
a6a5149b 76static dev_t nvme_chr_devt;
f3ca80fc 77static struct class *nvme_class;
ab9e00cc 78static struct class *nvme_subsys_class;
f3ca80fc 79
84fef62d
KB		 80static void nvme_ns_remove(struct nvme_ns *ns);
81static int nvme_revalidate_disk(struct gendisk *disk);
a085d765 82static void nvme_put_subsystem(struct nvme_subsystem *subsys);
f3ca80fc 83
b6dccf7f
AD		 84static __le32 nvme_get_log_dw10(u8 lid, size_t size)
85{
86 return cpu_to_le32((((size / 4) - 1) << 16) | lid);
87}
88
d86c4d8e
CH		 89int nvme_reset_ctrl(struct nvme_ctrl *ctrl)
90{
91 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING))
92 return -EBUSY;
93 if (!queue_work(nvme_wq, &ctrl->reset_work))
94 return -EBUSY;
95 return 0;
96}
97EXPORT_SYMBOL_GPL(nvme_reset_ctrl);
98
99static int nvme_reset_ctrl_sync(struct nvme_ctrl *ctrl)
100{
101 int ret;
102
103 ret = nvme_reset_ctrl(ctrl);
104 if (!ret)
105 flush_work(&ctrl->reset_work);
106 return ret;
107}
108
c5017e85
CH		 109static void nvme_delete_ctrl_work(struct work_struct *work)
110{
111 struct nvme_ctrl *ctrl =
112 container_of(work, struct nvme_ctrl, delete_work);
113
4054637c 114 flush_work(&ctrl->reset_work);
6cd53d14
CH		 115 nvme_stop_ctrl(ctrl);
116 nvme_remove_namespaces(ctrl);
c5017e85 117 ctrl->ops->delete_ctrl(ctrl);
6cd53d14
CH		 118 nvme_uninit_ctrl(ctrl);
119 nvme_put_ctrl(ctrl);
c5017e85
CH		 120}
121
122int nvme_delete_ctrl(struct nvme_ctrl *ctrl)
123{
124 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_DELETING))
125 return -EBUSY;
126 if (!queue_work(nvme_wq, &ctrl->delete_work))
127 return -EBUSY;
128 return 0;
129}
130EXPORT_SYMBOL_GPL(nvme_delete_ctrl);
131
132int nvme_delete_ctrl_sync(struct nvme_ctrl *ctrl)
133{
134 int ret = 0;
135
136 /*
137 * Keep a reference until the work is flushed since ->delete_ctrl
138 * can free the controller.
139 */
140 nvme_get_ctrl(ctrl);
141 ret = nvme_delete_ctrl(ctrl);
142 if (!ret)
143 flush_work(&ctrl->delete_work);
144 nvme_put_ctrl(ctrl);
145 return ret;
146}
147EXPORT_SYMBOL_GPL(nvme_delete_ctrl_sync);
148
715ea9e0
CH		 149static inline bool nvme_ns_has_pi(struct nvme_ns *ns)
150{
151 return ns->pi_type && ns->ms == sizeof(struct t10_pi_tuple);
152}
153
2a842aca 154static blk_status_t nvme_error_status(struct request *req)
27fa9bc5
CH		 155{
156 switch (nvme_req(req)->status & 0x7ff) {
157 case NVME_SC_SUCCESS:
2a842aca 158 return BLK_STS_OK;
27fa9bc5 159 case NVME_SC_CAP_EXCEEDED:
2a842aca 160 return BLK_STS_NOSPC;
e02ab023 161 case NVME_SC_ONCS_NOT_SUPPORTED:
2a842aca 162 return BLK_STS_NOTSUPP;
e02ab023
JG		 163 case NVME_SC_WRITE_FAULT:
164 case NVME_SC_READ_ERROR:
165 case NVME_SC_UNWRITTEN_BLOCK:
a751da33
CH		 166 case NVME_SC_ACCESS_DENIED:
167 case NVME_SC_READ_ONLY:
2a842aca 168 return BLK_STS_MEDIUM;
a751da33
CH		 169 case NVME_SC_GUARD_CHECK:
170 case NVME_SC_APPTAG_CHECK:
171 case NVME_SC_REFTAG_CHECK:
172 case NVME_SC_INVALID_PI:
173 return BLK_STS_PROTECTION;
174 case NVME_SC_RESERVATION_CONFLICT:
175 return BLK_STS_NEXUS;
2a842aca
CH		 176 default:
177 return BLK_STS_IOERR;
27fa9bc5
CH		 178 }
179}
27fa9bc5 180
f6324b1b 181static inline bool nvme_req_needs_retry(struct request *req)
77f02a7a 182{
f6324b1b
CH		 183 if (blk_noretry_request(req))
184 return false;
27fa9bc5 185 if (nvme_req(req)->status & NVME_SC_DNR)
f6324b1b 186 return false;
44e44b29 187 if (nvme_req(req)->retries >= nvme_max_retries)
f6324b1b
CH		 188 return false;
189 return true;
77f02a7a
CH		 190}
191
192void nvme_complete_rq(struct request *req)
193{
27fa9bc5 194 if (unlikely(nvme_req(req)->status && nvme_req_needs_retry(req))) {
32acab31
CH		 195 if (nvme_req_needs_failover(req)) {
196 nvme_failover_req(req);
197 return;
198 }
199
200 if (!blk_queue_dying(req->q)) {
201 nvme_req(req)->retries++;
202 blk_mq_requeue_request(req, true);
203 return;
204 }
77f02a7a
CH		 205 }
206
27fa9bc5 207 blk_mq_end_request(req, nvme_error_status(req));
77f02a7a
CH		 208}
209EXPORT_SYMBOL_GPL(nvme_complete_rq);
210
c55a2fd4
ML		 211void nvme_cancel_request(struct request *req, void *data, bool reserved)
212{
c55a2fd4
ML		 213 if (!blk_mq_request_started(req))
214 return;
215
216 dev_dbg_ratelimited(((struct nvme_ctrl *) data)->device,
217 "Cancelling I/O %d", req->tag);
218
e54b064c 219 nvme_req(req)->status = NVME_SC_ABORT_REQ;
08e0029a 220 blk_mq_complete_request(req);
27fa9bc5 221
c55a2fd4
ML		 222}
223EXPORT_SYMBOL_GPL(nvme_cancel_request);
224
bb8d261e
CH		 225bool nvme_change_ctrl_state(struct nvme_ctrl *ctrl,
226 enum nvme_ctrl_state new_state)
227{
f6b6a28e 228 enum nvme_ctrl_state old_state;
0a72bbba 229 unsigned long flags;
bb8d261e
CH		 230 bool changed = false;
231
0a72bbba 232 spin_lock_irqsave(&ctrl->lock, flags);
f6b6a28e
GKB		 233
234 old_state = ctrl->state;
bb8d261e
CH		 235 switch (new_state) {
236 case NVME_CTRL_LIVE:
237 switch (old_state) {
7d2e8008 238 case NVME_CTRL_NEW:
bb8d261e 239 case NVME_CTRL_RESETTING:
def61eca 240 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 241 changed = true;
242 /* FALLTHRU */
243 default:
244 break;
245 }
246 break;
247 case NVME_CTRL_RESETTING:
248 switch (old_state) {
249 case NVME_CTRL_NEW:
def61eca 250 case NVME_CTRL_LIVE:
def61eca
CH		 251 changed = true;
252 /* FALLTHRU */
253 default:
254 break;
255 }
256 break;
257 case NVME_CTRL_RECONNECTING:
258 switch (old_state) {
bb8d261e 259 case NVME_CTRL_LIVE:
3cec7f9d 260 case NVME_CTRL_RESETTING:
bb8d261e
CH		 261 changed = true;
262 /* FALLTHRU */
263 default:
264 break;
265 }
266 break;
267 case NVME_CTRL_DELETING:
268 switch (old_state) {
269 case NVME_CTRL_LIVE:
270 case NVME_CTRL_RESETTING:
def61eca 271 case NVME_CTRL_RECONNECTING:
bb8d261e
CH		 272 changed = true;
273 /* FALLTHRU */
274 default:
275 break;
276 }
277 break;
0ff9d4e1
KB		 278 case NVME_CTRL_DEAD:
279 switch (old_state) {
280 case NVME_CTRL_DELETING:
281 changed = true;
282 /* FALLTHRU */
283 default:
284 break;
285 }
286 break;
bb8d261e
CH		 287 default:
288 break;
289 }
bb8d261e
CH		 290
291 if (changed)
292 ctrl->state = new_state;
293
0a72bbba 294 spin_unlock_irqrestore(&ctrl->lock, flags);
32acab31
CH		 295 if (changed && ctrl->state == NVME_CTRL_LIVE)
296 nvme_kick_requeue_lists(ctrl);
bb8d261e
CH		 297 return changed;
298}
299EXPORT_SYMBOL_GPL(nvme_change_ctrl_state);
300
ed754e5d
CH		 301static void nvme_free_ns_head(struct kref *ref)
302{
303 struct nvme_ns_head *head =
304 container_of(ref, struct nvme_ns_head, ref);
305
32acab31 306 nvme_mpath_remove_disk(head);
ed754e5d
CH		 307 ida_simple_remove(&head->subsys->ns_ida, head->instance);
308 list_del_init(&head->entry);
309 cleanup_srcu_struct(&head->srcu);
a085d765 310 nvme_put_subsystem(head->subsys);
ed754e5d
CH		 311 kfree(head);
312}
313
314static void nvme_put_ns_head(struct nvme_ns_head *head)
315{
316 kref_put(&head->ref, nvme_free_ns_head);
317}
318
1673f1f0
CH		 319static void nvme_free_ns(struct kref *kref)
320{
321 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
322
b0b4e09c
MB		 323 if (ns->ndev)
324 nvme_nvm_unregister(ns);
1673f1f0 325
1673f1f0 326 put_disk(ns->disk);
ed754e5d 327 nvme_put_ns_head(ns->head);
075790eb 328 nvme_put_ctrl(ns->ctrl);
1673f1f0
CH		 329 kfree(ns);
330}
331
5bae7f73 332static void nvme_put_ns(struct nvme_ns *ns)
1673f1f0
CH		 333{
334 kref_put(&ns->kref, nvme_free_ns);
335}
336
4160982e 337struct request *nvme_alloc_request(struct request_queue *q,
9a95e4ef 338 struct nvme_command *cmd, blk_mq_req_flags_t flags, int qid)
21d34711 339{
aebf526b 340 unsigned op = nvme_is_write(cmd) ? REQ_OP_DRV_OUT : REQ_OP_DRV_IN;
21d34711 341 struct request *req;
21d34711 342
eb71f435 343 if (qid == NVME_QID_ANY) {
aebf526b 344 req = blk_mq_alloc_request(q, op, flags);
eb71f435 345 } else {
aebf526b 346 req = blk_mq_alloc_request_hctx(q, op, flags,
eb71f435
CH		 347 qid ? qid - 1 : 0);
348 }
21d34711 349 if (IS_ERR(req))
4160982e 350 return req;
21d34711 351
21d34711 352 req->cmd_flags |= REQ_FAILFAST_DRIVER;
d49187e9 353 nvme_req(req)->cmd = cmd;
21d34711 354
4160982e
CH		 355 return req;
356}
576d55d6 357EXPORT_SYMBOL_GPL(nvme_alloc_request);
4160982e 358
f5d11840
JA		 359static int nvme_toggle_streams(struct nvme_ctrl *ctrl, bool enable)
360{
361 struct nvme_command c;
362
363 memset(&c, 0, sizeof(c));
364
365 c.directive.opcode = nvme_admin_directive_send;
62346eae 366 c.directive.nsid = cpu_to_le32(NVME_NSID_ALL);
f5d11840
JA		 367 c.directive.doper = NVME_DIR_SND_ID_OP_ENABLE;
368 c.directive.dtype = NVME_DIR_IDENTIFY;
369 c.directive.tdtype = NVME_DIR_STREAMS;
370 c.directive.endir = enable ? NVME_DIR_ENDIR : 0;
371
372 return nvme_submit_sync_cmd(ctrl->admin_q, &c, NULL, 0);
373}
374
375static int nvme_disable_streams(struct nvme_ctrl *ctrl)
376{
377 return nvme_toggle_streams(ctrl, false);
378}
379
380static int nvme_enable_streams(struct nvme_ctrl *ctrl)
381{
382 return nvme_toggle_streams(ctrl, true);
383}
384
385static int nvme_get_stream_params(struct nvme_ctrl *ctrl,
386 struct streams_directive_params *s, u32 nsid)
387{
388 struct nvme_command c;
389
390 memset(&c, 0, sizeof(c));
391 memset(s, 0, sizeof(*s));
392
393 c.directive.opcode = nvme_admin_directive_recv;
394 c.directive.nsid = cpu_to_le32(nsid);
a082b426 395 c.directive.numd = cpu_to_le32((sizeof(*s) >> 2) - 1);
f5d11840
JA		 396 c.directive.doper = NVME_DIR_RCV_ST_OP_PARAM;
397 c.directive.dtype = NVME_DIR_STREAMS;
398
399 return nvme_submit_sync_cmd(ctrl->admin_q, &c, s, sizeof(*s));
400}
401
402static int nvme_configure_directives(struct nvme_ctrl *ctrl)
403{
404 struct streams_directive_params s;
405 int ret;
406
407 if (!(ctrl->oacs & NVME_CTRL_OACS_DIRECTIVES))
408 return 0;
409 if (!streams)
410 return 0;
411
412 ret = nvme_enable_streams(ctrl);
413 if (ret)
414 return ret;
415
62346eae 416 ret = nvme_get_stream_params(ctrl, &s, NVME_NSID_ALL);
f5d11840
JA		 417 if (ret)
418 return ret;
419
420 ctrl->nssa = le16_to_cpu(s.nssa);
421 if (ctrl->nssa < BLK_MAX_WRITE_HINTS - 1) {
422 dev_info(ctrl->device, "too few streams (%u) available\n",
423 ctrl->nssa);
424 nvme_disable_streams(ctrl);
425 return 0;
426 }
427
428 ctrl->nr_streams = min_t(unsigned, ctrl->nssa, BLK_MAX_WRITE_HINTS - 1);
429 dev_info(ctrl->device, "Using %u streams\n", ctrl->nr_streams);
430 return 0;
431}
432
433/*
434 * Check if 'req' has a write hint associated with it. If it does, assign
435 * a valid namespace stream to the write.
436 */
437static void nvme_assign_write_stream(struct nvme_ctrl *ctrl,
438 struct request *req, u16 *control,
439 u32 *dsmgmt)
440{
441 enum rw_hint streamid = req->write_hint;
442
443 if (streamid == WRITE_LIFE_NOT_SET || streamid == WRITE_LIFE_NONE)
444 streamid = 0;
445 else {
446 streamid--;
447 if (WARN_ON_ONCE(streamid > ctrl->nr_streams))
448 return;
449
450 *control |= NVME_RW_DTYPE_STREAMS;
451 *dsmgmt |= streamid << 16;
452 }
453
454 if (streamid < ARRAY_SIZE(req->q->write_hints))
455 req->q->write_hints[streamid] += blk_rq_bytes(req) >> 9;
456}
457
8093f7ca
ML		 458static inline void nvme_setup_flush(struct nvme_ns *ns,
459 struct nvme_command *cmnd)
460{
461 memset(cmnd, 0, sizeof(*cmnd));
462 cmnd->common.opcode = nvme_cmd_flush;
ed754e5d 463 cmnd->common.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 464}
465
fc17b653 466static blk_status_t nvme_setup_discard(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 467 struct nvme_command *cmnd)
468{
b35ba01e 469 unsigned short segments = blk_rq_nr_discard_segments(req), n = 0;
8093f7ca 470 struct nvme_dsm_range *range;
b35ba01e 471 struct bio *bio;
8093f7ca 472
b35ba01e 473 range = kmalloc_array(segments, sizeof(*range), GFP_ATOMIC);
8093f7ca 474 if (!range)
fc17b653 475 return BLK_STS_RESOURCE;
8093f7ca 476
b35ba01e
CH		 477 __rq_for_each_bio(bio, req) {
478 u64 slba = nvme_block_nr(ns, bio->bi_iter.bi_sector);
479 u32 nlb = bio->bi_iter.bi_size >> ns->lba_shift;
480
481 range[n].cattr = cpu_to_le32(0);
482 range[n].nlb = cpu_to_le32(nlb);
483 range[n].slba = cpu_to_le64(slba);
484 n++;
485 }
486
487 if (WARN_ON_ONCE(n != segments)) {
488 kfree(range);
fc17b653 489 return BLK_STS_IOERR;
b35ba01e 490 }
8093f7ca
ML		 491
492 memset(cmnd, 0, sizeof(*cmnd));
493 cmnd->dsm.opcode = nvme_cmd_dsm;
ed754e5d 494 cmnd->dsm.nsid = cpu_to_le32(ns->head->ns_id);
f1dd03a8 495 cmnd->dsm.nr = cpu_to_le32(segments - 1);
8093f7ca
ML		 496 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
497
f9d03f96
CH		 498 req->special_vec.bv_page = virt_to_page(range);
499 req->special_vec.bv_offset = offset_in_page(range);
b35ba01e 500 req->special_vec.bv_len = sizeof(*range) * segments;
f9d03f96 501 req->rq_flags |= RQF_SPECIAL_PAYLOAD;
8093f7ca 502
fc17b653 503 return BLK_STS_OK;
8093f7ca 504}
8093f7ca 505
ebe6d874
CH		 506static inline blk_status_t nvme_setup_rw(struct nvme_ns *ns,
507 struct request *req, struct nvme_command *cmnd)
8093f7ca 508{
f5d11840 509 struct nvme_ctrl *ctrl = ns->ctrl;
8093f7ca
ML		 510 u16 control = 0;
511 u32 dsmgmt = 0;
512
513 if (req->cmd_flags & REQ_FUA)
514 control |= NVME_RW_FUA;
515 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
516 control |= NVME_RW_LR;
517
518 if (req->cmd_flags & REQ_RAHEAD)
519 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
520
521 memset(cmnd, 0, sizeof(*cmnd));
522 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
ed754e5d 523 cmnd->rw.nsid = cpu_to_le32(ns->head->ns_id);
8093f7ca
ML		 524 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
525 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
526
f5d11840
JA		 527 if (req_op(req) == REQ_OP_WRITE && ctrl->nr_streams)
528 nvme_assign_write_stream(ctrl, req, &control, &dsmgmt);
529
8093f7ca 530 if (ns->ms) {
715ea9e0
CH		 531 /*
532 * If formated with metadata, the block layer always provides a
533 * metadata buffer if CONFIG_BLK_DEV_INTEGRITY is enabled. Else
534 * we enable the PRACT bit for protection information or set the
535 * namespace capacity to zero to prevent any I/O.
536 */
537 if (!blk_integrity_rq(req)) {
538 if (WARN_ON_ONCE(!nvme_ns_has_pi(ns)))
539 return BLK_STS_NOTSUPP;
540 control |= NVME_RW_PRINFO_PRACT;
541 }
542
8093f7ca
ML		 543 switch (ns->pi_type) {
544 case NVME_NS_DPS_PI_TYPE3:
545 control |= NVME_RW_PRINFO_PRCHK_GUARD;
546 break;
547 case NVME_NS_DPS_PI_TYPE1:
548 case NVME_NS_DPS_PI_TYPE2:
549 control |= NVME_RW_PRINFO_PRCHK_GUARD |
550 NVME_RW_PRINFO_PRCHK_REF;
551 cmnd->rw.reftag = cpu_to_le32(
552 nvme_block_nr(ns, blk_rq_pos(req)));
553 break;
554 }
8093f7ca
ML		 555 }
556
557 cmnd->rw.control = cpu_to_le16(control);
558 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
ebe6d874 559 return 0;
8093f7ca
ML		 560}
561
fc17b653 562blk_status_t nvme_setup_cmd(struct nvme_ns *ns, struct request *req,
8093f7ca
ML		 563 struct nvme_command *cmd)
564{
fc17b653 565 blk_status_t ret = BLK_STS_OK;
8093f7ca 566
987f699a 567 if (!(req->rq_flags & RQF_DONTPREP)) {
44e44b29 568 nvme_req(req)->retries = 0;
27fa9bc5 569 nvme_req(req)->flags = 0;
987f699a
CH		 570 req->rq_flags |= RQF_DONTPREP;
571 }
572
aebf526b
CH		 573 switch (req_op(req)) {
574 case REQ_OP_DRV_IN:
575 case REQ_OP_DRV_OUT:
d49187e9 576 memcpy(cmd, nvme_req(req)->cmd, sizeof(*cmd));
aebf526b
CH		 577 break;
578 case REQ_OP_FLUSH:
8093f7ca 579 nvme_setup_flush(ns, cmd);
aebf526b 580 break;
e850fd16
CH		 581 case REQ_OP_WRITE_ZEROES:
582 /* currently only aliased to deallocate for a few ctrls: */
aebf526b 583 case REQ_OP_DISCARD:
8093f7ca 584 ret = nvme_setup_discard(ns, req, cmd);
aebf526b
CH		 585 break;
586 case REQ_OP_READ:
587 case REQ_OP_WRITE:
ebe6d874 588 ret = nvme_setup_rw(ns, req, cmd);
aebf526b
CH		 589 break;
590 default:
591 WARN_ON_ONCE(1);
fc17b653 592 return BLK_STS_IOERR;
aebf526b 593 }
8093f7ca 594
721b3917 595 cmd->common.command_id = req->tag;
8093f7ca
ML		 596 return ret;
597}
598EXPORT_SYMBOL_GPL(nvme_setup_cmd);
599
4160982e
CH		 600/*
601 * Returns 0 on success. If the result is negative, it's a Linux error code;
602 * if the result is positive, it's an NVM Express status code
603 */
604int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
d49187e9 605 union nvme_result *result, void *buffer, unsigned bufflen,
9a95e4ef
BVA		 606 unsigned timeout, int qid, int at_head,
607 blk_mq_req_flags_t flags)
4160982e
CH		 608{
609 struct request *req;
610 int ret;
611
eb71f435 612 req = nvme_alloc_request(q, cmd, flags, qid);
4160982e
CH		 613 if (IS_ERR(req))
614 return PTR_ERR(req);
615
616 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
617
21d34711
CH		 618 if (buffer && bufflen) {
619 ret = blk_rq_map_kern(q, req, buffer, bufflen, GFP_KERNEL);
620 if (ret)
621 goto out;
4160982e
CH		 622 }
623
eb71f435 624 blk_execute_rq(req->q, NULL, req, at_head);
d49187e9
CH		 625 if (result)
626 *result = nvme_req(req)->result;
27fa9bc5
CH		 627 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
628 ret = -EINTR;
629 else
630 ret = nvme_req(req)->status;
4160982e
CH		 631 out:
632 blk_mq_free_request(req);
633 return ret;
634}
eb71f435 635EXPORT_SYMBOL_GPL(__nvme_submit_sync_cmd);
4160982e
CH		 636
637int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
638 void *buffer, unsigned bufflen)
639{
eb71f435
CH		 640 return __nvme_submit_sync_cmd(q, cmd, NULL, buffer, bufflen, 0,
641 NVME_QID_ANY, 0, 0);
4160982e 642}
576d55d6 643EXPORT_SYMBOL_GPL(nvme_submit_sync_cmd);
4160982e 644
1cad6562
CH		 645static void *nvme_add_user_metadata(struct bio *bio, void __user *ubuf,
646 unsigned len, u32 seed, bool write)
647{
648 struct bio_integrity_payload *bip;
649 int ret = -ENOMEM;
650 void *buf;
651
652 buf = kmalloc(len, GFP_KERNEL);
653 if (!buf)
654 goto out;
655
656 ret = -EFAULT;
657 if (write && copy_from_user(buf, ubuf, len))
658 goto out_free_meta;
659
660 bip = bio_integrity_alloc(bio, GFP_KERNEL, 1);
661 if (IS_ERR(bip)) {
662 ret = PTR_ERR(bip);
663 goto out_free_meta;
664 }
665
666 bip->bip_iter.bi_size = len;
667 bip->bip_iter.bi_sector = seed;
668 ret = bio_integrity_add_page(bio, virt_to_page(buf), len,
669 offset_in_page(buf));
670 if (ret == len)
671 return buf;
672 ret = -ENOMEM;
673out_free_meta:
674 kfree(buf);
675out:
676 return ERR_PTR(ret);
677}
678
63263d60 679static int nvme_submit_user_cmd(struct request_queue *q,
485783ca
KB		 680 struct nvme_command *cmd, void __user *ubuffer,
681 unsigned bufflen, void __user *meta_buffer, unsigned meta_len,
682 u32 meta_seed, u32 *result, unsigned timeout)
4160982e 683{
7a5abb4b 684 bool write = nvme_is_write(cmd);
0b7f1f26
KB		 685 struct nvme_ns *ns = q->queuedata;
686 struct gendisk *disk = ns ? ns->disk : NULL;
4160982e 687 struct request *req;
0b7f1f26
KB		 688 struct bio *bio = NULL;
689 void *meta = NULL;
4160982e
CH		 690 int ret;
691
eb71f435 692 req = nvme_alloc_request(q, cmd, 0, NVME_QID_ANY);
4160982e
CH		 693 if (IS_ERR(req))
694 return PTR_ERR(req);
695
696 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
697
698 if (ubuffer && bufflen) {
21d34711
CH		 699 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
700 GFP_KERNEL);
701 if (ret)
702 goto out;
703 bio = req->bio;
74d46992 704 bio->bi_disk = disk;
1cad6562
CH		 705 if (disk && meta_buffer && meta_len) {
706 meta = nvme_add_user_metadata(bio, meta_buffer, meta_len,
707 meta_seed, write);
708 if (IS_ERR(meta)) {
709 ret = PTR_ERR(meta);
0b7f1f26
KB		 710 goto out_unmap;
711 }
43786815 712 req->cmd_flags |= REQ_INTEGRITY;
0b7f1f26
KB		 713 }
714 }
1cad6562 715
0b7f1f26 716 blk_execute_rq(req->q, disk, req, 0);
27fa9bc5
CH		 717 if (nvme_req(req)->flags & NVME_REQ_CANCELLED)
718 ret = -EINTR;
719 else
720 ret = nvme_req(req)->status;
21d34711 721 if (result)
d49187e9 722 *result = le32_to_cpu(nvme_req(req)->result.u32);
0b7f1f26
KB		 723 if (meta && !ret && !write) {
724 if (copy_to_user(meta_buffer, meta, meta_len))
725 ret = -EFAULT;
726 }
0b7f1f26
KB		 727 kfree(meta);
728 out_unmap:
74d46992 729 if (bio)
0b7f1f26 730 blk_rq_unmap_user(bio);
21d34711
CH		 731 out:
732 blk_mq_free_request(req);
733 return ret;
734}
735
2a842aca 736static void nvme_keep_alive_end_io(struct request *rq, blk_status_t status)
038bd4cb
SG		 737{
738 struct nvme_ctrl *ctrl = rq->end_io_data;
739
740 blk_mq_free_request(rq);
741
2a842aca 742 if (status) {
038bd4cb 743 dev_err(ctrl->device,
2a842aca
CH		 744 "failed nvme_keep_alive_end_io error=%d\n",
745 status);
038bd4cb
SG		 746 return;
747 }
748
749 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
750}
751
752static int nvme_keep_alive(struct nvme_ctrl *ctrl)
753{
754 struct nvme_command c;
755 struct request *rq;
756
757 memset(&c, 0, sizeof(c));
758 c.common.opcode = nvme_admin_keep_alive;
759
760 rq = nvme_alloc_request(ctrl->admin_q, &c, BLK_MQ_REQ_RESERVED,
761 NVME_QID_ANY);
762 if (IS_ERR(rq))
763 return PTR_ERR(rq);
764
765 rq->timeout = ctrl->kato * HZ;
766 rq->end_io_data = ctrl;
767
768 blk_execute_rq_nowait(rq->q, NULL, rq, 0, nvme_keep_alive_end_io);
769
770 return 0;
771}
772
773static void nvme_keep_alive_work(struct work_struct *work)
774{
775 struct nvme_ctrl *ctrl = container_of(to_delayed_work(work),
776 struct nvme_ctrl, ka_work);
777
778 if (nvme_keep_alive(ctrl)) {
779 /* allocation failure, reset the controller */
780 dev_err(ctrl->device, "keep-alive failed\n");
39bdc590 781 nvme_reset_ctrl(ctrl);
038bd4cb
SG		 782 return;
783 }
784}
785
786void nvme_start_keep_alive(struct nvme_ctrl *ctrl)
787{
788 if (unlikely(ctrl->kato == 0))
789 return;
790
791 INIT_DELAYED_WORK(&ctrl->ka_work, nvme_keep_alive_work);
792 schedule_delayed_work(&ctrl->ka_work, ctrl->kato * HZ);
793}
794EXPORT_SYMBOL_GPL(nvme_start_keep_alive);
795
796void nvme_stop_keep_alive(struct nvme_ctrl *ctrl)
797{
798 if (unlikely(ctrl->kato == 0))
799 return;
800
801 cancel_delayed_work_sync(&ctrl->ka_work);
802}
803EXPORT_SYMBOL_GPL(nvme_stop_keep_alive);
804
3f7f25a9 805static int nvme_identify_ctrl(struct nvme_ctrl *dev, struct nvme_id_ctrl **id)
21d34711
CH		 806{
807 struct nvme_command c = { };
808 int error;
809
810 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
811 c.identify.opcode = nvme_admin_identify;
986994a2 812 c.identify.cns = NVME_ID_CNS_CTRL;
21d34711
CH		 813
814 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
815 if (!*id)
816 return -ENOMEM;
817
818 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
819 sizeof(struct nvme_id_ctrl));
820 if (error)
821 kfree(*id);
822 return error;
823}
824
cdbff4f2 825static int nvme_identify_ns_descs(struct nvme_ctrl *ctrl, unsigned nsid,
002fab04 826 struct nvme_ns_ids *ids)
3b22ba26
JT		 827{
828 struct nvme_command c = { };
829 int status;
830 void *data;
831 int pos;
832 int len;
833
834 c.identify.opcode = nvme_admin_identify;
835 c.identify.nsid = cpu_to_le32(nsid);
836 c.identify.cns = NVME_ID_CNS_NS_DESC_LIST;
837
838 data = kzalloc(NVME_IDENTIFY_DATA_SIZE, GFP_KERNEL);
839 if (!data)
840 return -ENOMEM;
841
cdbff4f2 842 status = nvme_submit_sync_cmd(ctrl->admin_q, &c, data,
3b22ba26
JT		 843 NVME_IDENTIFY_DATA_SIZE);
844 if (status)
845 goto free_data;
846
847 for (pos = 0; pos < NVME_IDENTIFY_DATA_SIZE; pos += len) {
848 struct nvme_ns_id_desc *cur = data + pos;
849
850 if (cur->nidl == 0)
851 break;
852
853 switch (cur->nidt) {
854 case NVME_NIDT_EUI64:
855 if (cur->nidl != NVME_NIDT_EUI64_LEN) {
cdbff4f2 856 dev_warn(ctrl->device,
3b22ba26
JT		 857 "ctrl returned bogus length: %d for NVME_NIDT_EUI64\n",
858 cur->nidl);
859 goto free_data;
860 }
861 len = NVME_NIDT_EUI64_LEN;
002fab04 862 memcpy(ids->eui64, data + pos + sizeof(*cur), len);
3b22ba26
JT		 863 break;
864 case NVME_NIDT_NGUID:
865 if (cur->nidl != NVME_NIDT_NGUID_LEN) {
cdbff4f2 866 dev_warn(ctrl->device,
3b22ba26
JT		 867 "ctrl returned bogus length: %d for NVME_NIDT_NGUID\n",
868 cur->nidl);
869 goto free_data;
870 }
871 len = NVME_NIDT_NGUID_LEN;
002fab04 872 memcpy(ids->nguid, data + pos + sizeof(*cur), len);
3b22ba26
JT		 873 break;
874 case NVME_NIDT_UUID:
875 if (cur->nidl != NVME_NIDT_UUID_LEN) {
cdbff4f2 876 dev_warn(ctrl->device,
3b22ba26
JT		 877 "ctrl returned bogus length: %d for NVME_NIDT_UUID\n",
878 cur->nidl);
879 goto free_data;
880 }
881 len = NVME_NIDT_UUID_LEN;
002fab04 882 uuid_copy(&ids->uuid, data + pos + sizeof(*cur));
3b22ba26
JT		 883 break;
884 default:
885 /* Skip unnkown types */
886 len = cur->nidl;
887 break;
888 }
889
890 len += sizeof(*cur);
891 }
892free_data:
893 kfree(data);
894 return status;
895}
896
540c801c
KB		 897static int nvme_identify_ns_list(struct nvme_ctrl *dev, unsigned nsid, __le32 *ns_list)
898{
899 struct nvme_command c = { };
900
901 c.identify.opcode = nvme_admin_identify;
986994a2 902 c.identify.cns = NVME_ID_CNS_NS_ACTIVE_LIST;
540c801c
KB		 903 c.identify.nsid = cpu_to_le32(nsid);
904 return nvme_submit_sync_cmd(dev->admin_q, &c, ns_list, 0x1000);
905}
906
cdbff4f2
CH		 907static struct nvme_id_ns *nvme_identify_ns(struct nvme_ctrl *ctrl,
908 unsigned nsid)
21d34711 909{
cdbff4f2 910 struct nvme_id_ns *id;
21d34711
CH		 911 struct nvme_command c = { };
912 int error;
913
914 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
778f067c
MG		 915 c.identify.opcode = nvme_admin_identify;
916 c.identify.nsid = cpu_to_le32(nsid);
986994a2 917 c.identify.cns = NVME_ID_CNS_NS;
21d34711 918
cdbff4f2
CH		 919 id = kmalloc(sizeof(*id), GFP_KERNEL);
920 if (!id)
921 return NULL;
21d34711 922
cdbff4f2
CH		 923 error = nvme_submit_sync_cmd(ctrl->admin_q, &c, id, sizeof(*id));
924 if (error) {
925 dev_warn(ctrl->device, "Identify namespace failed\n");
926 kfree(id);
927 return NULL;
928 }
929
930 return id;
21d34711
CH		 931}
932
e8f55d43
KB		 933static int nvme_features(struct nvme_ctrl *dev, u8 op, unsigned int fid,
934 unsigned int dword11, void *buffer, size_t buflen, u32 *result)
21d34711
CH		 935{
936 struct nvme_command c;
d49187e9 937 union nvme_result res;
1cb3cce5 938 int ret;
21d34711
CH		 939
940 memset(&c, 0, sizeof(c));
e8f55d43 941 c.features.opcode = op;
21d34711
CH		 942 c.features.fid = cpu_to_le32(fid);
943 c.features.dword11 = cpu_to_le32(dword11);
944
d49187e9 945 ret = __nvme_submit_sync_cmd(dev->admin_q, &c, &res,
1a6fe74d 946 buffer, buflen, 0, NVME_QID_ANY, 0, 0);
9b47f77a 947 if (ret >= 0 && result)
d49187e9 948 *result = le32_to_cpu(res.u32);
1cb3cce5 949 return ret;
21d34711
CH		 950}
951
e8f55d43
KB		 952int nvme_set_features(struct nvme_ctrl *dev, unsigned int fid,
953 unsigned int dword11, void *buffer, size_t buflen,
954 u32 *result)
955{
956 return nvme_features(dev, nvme_admin_set_features, fid, dword11, buffer,
957 buflen, result);
958}
959EXPORT_SYMBOL_GPL(nvme_set_features);
960
961int nvme_get_features(struct nvme_ctrl *dev, unsigned int fid,
962 unsigned int dword11, void *buffer, size_t buflen,
963 u32 *result)
964{
965 return nvme_features(dev, nvme_admin_get_features, fid, dword11, buffer,
966 buflen, result);
967}
968EXPORT_SYMBOL_GPL(nvme_get_features);
969
9a0be7ab
CH		 970int nvme_set_queue_count(struct nvme_ctrl *ctrl, int *count)
971{
972 u32 q_count = (*count - 1) | ((*count - 1) << 16);
973 u32 result;
974 int status, nr_io_queues;
975
1a6fe74d 976 status = nvme_set_features(ctrl, NVME_FEAT_NUM_QUEUES, q_count, NULL, 0,
9a0be7ab 977 &result);
f5fa90dc 978 if (status < 0)
9a0be7ab
CH		 979 return status;
980
f5fa90dc
CH		 981 /*
982 * Degraded controllers might return an error when setting the queue
983 * count. We still want to be able to bring them online and offer
984 * access to the admin queue, as that might be only way to fix them up.
985 */
986 if (status > 0) {
f0425db0 987 dev_err(ctrl->device, "Could not set queue count (%d)\n", status);
f5fa90dc
CH		 988 *count = 0;
989 } else {
990 nr_io_queues = min(result & 0xffff, result >> 16) + 1;
991 *count = min(*count, nr_io_queues);
992 }
993
9a0be7ab
CH		 994 return 0;
995}
576d55d6 996EXPORT_SYMBOL_GPL(nvme_set_queue_count);
9a0be7ab 997
1673f1f0
CH		 998static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
999{
1000 struct nvme_user_io io;
1001 struct nvme_command c;
1002 unsigned length, meta_len;
1003 void __user *metadata;
1004
1005 if (copy_from_user(&io, uio, sizeof(io)))
1006 return -EFAULT;
63088ec7
KB		 1007 if (io.flags)
1008 return -EINVAL;
1673f1f0
CH		 1009
1010 switch (io.opcode) {
1011 case nvme_cmd_write:
1012 case nvme_cmd_read:
1013 case nvme_cmd_compare:
1014 break;
1015 default:
1016 return -EINVAL;
1017 }
1018
1019 length = (io.nblocks + 1) << ns->lba_shift;
1020 meta_len = (io.nblocks + 1) * ns->ms;
1021 metadata = (void __user *)(uintptr_t)io.metadata;
1022
1023 if (ns->ext) {
1024 length += meta_len;
1025 meta_len = 0;
1026 } else if (meta_len) {
1027 if ((io.metadata & 3) || !io.metadata)
1028 return -EINVAL;
1029 }
1030
1031 memset(&c, 0, sizeof(c));
1032 c.rw.opcode = io.opcode;
1033 c.rw.flags = io.flags;
ed754e5d 1034 c.rw.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1035 c.rw.slba = cpu_to_le64(io.slba);
1036 c.rw.length = cpu_to_le16(io.nblocks);
1037 c.rw.control = cpu_to_le16(io.control);
1038 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1039 c.rw.reftag = cpu_to_le32(io.reftag);
1040 c.rw.apptag = cpu_to_le16(io.apptag);
1041 c.rw.appmask = cpu_to_le16(io.appmask);
1042
63263d60 1043 return nvme_submit_user_cmd(ns->queue, &c,
1673f1f0
CH		 1044 (void __user *)(uintptr_t)io.addr, length,
1045 metadata, meta_len, io.slba, NULL, 0);
1046}
1047
84fef62d
KB		 1048static u32 nvme_known_admin_effects(u8 opcode)
1049{
1050 switch (opcode) {
1051 case nvme_admin_format_nvm:
1052 return NVME_CMD_EFFECTS_CSUPP | NVME_CMD_EFFECTS_LBCC |
1053 NVME_CMD_EFFECTS_CSE_MASK;
1054 case nvme_admin_sanitize_nvm:
1055 return NVME_CMD_EFFECTS_CSE_MASK;
1056 default:
1057 break;
1058 }
1059 return 0;
1060}
1061
1062static u32 nvme_passthru_start(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1063 u8 opcode)
1064{
1065 u32 effects = 0;
1066
1067 if (ns) {
1068 if (ctrl->effects)
1069 effects = le32_to_cpu(ctrl->effects->iocs[opcode]);
1070 if (effects & ~NVME_CMD_EFFECTS_CSUPP)
1071 dev_warn(ctrl->device,
1072 "IO command:%02x has unhandled effects:%08x\n",
1073 opcode, effects);
1074 return 0;
1075 }
1076
1077 if (ctrl->effects)
a49afe0f 1078 effects = le32_to_cpu(ctrl->effects->acs[opcode]);
84fef62d
KB		 1079 else
1080 effects = nvme_known_admin_effects(opcode);
1081
1082 /*
1083 * For simplicity, IO to all namespaces is quiesced even if the command
1084 * effects say only one namespace is affected.
1085 */
1086 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK)) {
1087 nvme_start_freeze(ctrl);
1088 nvme_wait_freeze(ctrl);
1089 }
1090 return effects;
1091}
1092
1093static void nvme_update_formats(struct nvme_ctrl *ctrl)
1094{
1095 struct nvme_ns *ns;
1096
1097 mutex_lock(&ctrl->namespaces_mutex);
1098 list_for_each_entry(ns, &ctrl->namespaces, list) {
1099 if (ns->disk && nvme_revalidate_disk(ns->disk))
1100 nvme_ns_remove(ns);
1101 }
1102 mutex_unlock(&ctrl->namespaces_mutex);
1103}
1104
1105static void nvme_passthru_end(struct nvme_ctrl *ctrl, u32 effects)
1106{
1107 /*
1108 * Revalidate LBA changes prior to unfreezing. This is necessary to
1109 * prevent memory corruption if a logical block size was changed by
1110 * this command.
1111 */
1112 if (effects & NVME_CMD_EFFECTS_LBCC)
1113 nvme_update_formats(ctrl);
1114 if (effects & (NVME_CMD_EFFECTS_LBCC | NVME_CMD_EFFECTS_CSE_MASK))
1115 nvme_unfreeze(ctrl);
1116 if (effects & NVME_CMD_EFFECTS_CCC)
1117 nvme_init_identify(ctrl);
1118 if (effects & (NVME_CMD_EFFECTS_NIC | NVME_CMD_EFFECTS_NCC))
1119 nvme_queue_scan(ctrl);
1120}
1121
f3ca80fc 1122static int nvme_user_cmd(struct nvme_ctrl *ctrl, struct nvme_ns *ns,
1673f1f0
CH		 1123 struct nvme_passthru_cmd __user *ucmd)
1124{
1125 struct nvme_passthru_cmd cmd;
1126 struct nvme_command c;
1127 unsigned timeout = 0;
84fef62d 1128 u32 effects;
1673f1f0
CH		 1129 int status;
1130
1131 if (!capable(CAP_SYS_ADMIN))
1132 return -EACCES;
1133 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1134 return -EFAULT;
63088ec7
KB		 1135 if (cmd.flags)
1136 return -EINVAL;
1673f1f0
CH		 1137
1138 memset(&c, 0, sizeof(c));
1139 c.common.opcode = cmd.opcode;
1140 c.common.flags = cmd.flags;
1141 c.common.nsid = cpu_to_le32(cmd.nsid);
1142 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1143 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1144 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1145 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1146 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1147 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1148 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1149 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1150
1151 if (cmd.timeout_ms)
1152 timeout = msecs_to_jiffies(cmd.timeout_ms);
1153
84fef62d 1154 effects = nvme_passthru_start(ctrl, ns, cmd.opcode);
1673f1f0 1155 status = nvme_submit_user_cmd(ns ? ns->queue : ctrl->admin_q, &c,
d1ea7be5 1156 (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
63263d60
KB		 1157 (void __user *)(uintptr_t)cmd.metadata, cmd.metadata,
1158 0, &cmd.result, timeout);
84fef62d
KB		 1159 nvme_passthru_end(ctrl, effects);
1160
1673f1f0
CH		 1161 if (status >= 0) {
1162 if (put_user(cmd.result, &ucmd->result))
1163 return -EFAULT;
1164 }
1165
1166 return status;
1167}
1168
32acab31
CH		 1169/*
1170 * Issue ioctl requests on the first available path. Note that unlike normal
1171 * block layer requests we will not retry failed request on another controller.
1172 */
1173static struct nvme_ns *nvme_get_ns_from_disk(struct gendisk *disk,
1174 struct nvme_ns_head **head, int *srcu_idx)
1673f1f0 1175{
32acab31
CH		 1176#ifdef CONFIG_NVME_MULTIPATH
1177 if (disk->fops == &nvme_ns_head_ops) {
1178 *head = disk->private_data;
1179 *srcu_idx = srcu_read_lock(&(*head)->srcu);
1180 return nvme_find_path(*head);
1181 }
1182#endif
1183 *head = NULL;
1184 *srcu_idx = -1;
1185 return disk->private_data;
1186}
1673f1f0 1187
32acab31
CH		 1188static void nvme_put_ns_from_disk(struct nvme_ns_head *head, int idx)
1189{
1190 if (head)
1191 srcu_read_unlock(&head->srcu, idx);
1192}
1673f1f0 1193
32acab31
CH		 1194static int nvme_ns_ioctl(struct nvme_ns *ns, unsigned cmd, unsigned long arg)
1195{
1673f1f0
CH		 1196 switch (cmd) {
1197 case NVME_IOCTL_ID:
1198 force_successful_syscall_return();
ed754e5d 1199 return ns->head->ns_id;
1673f1f0
CH		 1200 case NVME_IOCTL_ADMIN_CMD:
1201 return nvme_user_cmd(ns->ctrl, NULL, (void __user *)arg);
1202 case NVME_IOCTL_IO_CMD:
1203 return nvme_user_cmd(ns->ctrl, ns, (void __user *)arg);
1204 case NVME_IOCTL_SUBMIT_IO:
1205 return nvme_submit_io(ns, (void __user *)arg);
1673f1f0 1206 default:
84d4add7
MB		 1207#ifdef CONFIG_NVM
1208 if (ns->ndev)
1209 return nvme_nvm_ioctl(ns, cmd, arg);
1210#endif
a98e58e5 1211 if (is_sed_ioctl(cmd))
4f1244c8 1212 return sed_ioctl(ns->ctrl->opal_dev, cmd,
e225c20e 1213 (void __user *) arg);
1673f1f0
CH		 1214 return -ENOTTY;
1215 }
1216}
1217
32acab31
CH		 1218static int nvme_ioctl(struct block_device *bdev, fmode_t mode,
1219 unsigned int cmd, unsigned long arg)
1673f1f0 1220{
32acab31
CH		 1221 struct nvme_ns_head *head = NULL;
1222 struct nvme_ns *ns;
1223 int srcu_idx, ret;
1224
1225 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1226 if (unlikely(!ns))
1227 ret = -EWOULDBLOCK;
1228 else
1229 ret = nvme_ns_ioctl(ns, cmd, arg);
1230 nvme_put_ns_from_disk(head, srcu_idx);
1231 return ret;
1673f1f0 1232}
1673f1f0
CH		 1233
1234static int nvme_open(struct block_device *bdev, fmode_t mode)
1235{
c6424a90
CH		 1236 struct nvme_ns *ns = bdev->bd_disk->private_data;
1237
32acab31
CH		 1238#ifdef CONFIG_NVME_MULTIPATH
1239 /* should never be called due to GENHD_FL_HIDDEN */
1240 if (WARN_ON_ONCE(ns->head->disk))
1241 return -ENXIO;
1242#endif
c6424a90
CH		 1243 if (!kref_get_unless_zero(&ns->kref))
1244 return -ENXIO;
c6424a90 1245 return 0;
1673f1f0
CH		 1246}
1247
1248static void nvme_release(struct gendisk *disk, fmode_t mode)
1249{
a6a5149b 1250 nvme_put_ns(disk->private_data);
1673f1f0
CH		 1251}
1252
1253static int nvme_getgeo(struct block_device *bdev, struct hd_geometry *geo)
1254{
1255 /* some standard values */
1256 geo->heads = 1 << 6;
1257 geo->sectors = 1 << 5;
1258 geo->cylinders = get_capacity(bdev->bd_disk) >> 11;
1259 return 0;
1260}
1261
1262#ifdef CONFIG_BLK_DEV_INTEGRITY
39b7baa4 1263static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1264{
1265 struct blk_integrity integrity;
1266
fa9a89fc 1267 memset(&integrity, 0, sizeof(integrity));
39b7baa4 1268 switch (pi_type) {
1673f1f0
CH		 1269 case NVME_NS_DPS_PI_TYPE3:
1270 integrity.profile = &t10_pi_type3_crc;
ba36c21b
NB		 1271 integrity.tag_size = sizeof(u16) + sizeof(u32);
1272 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1273 break;
1274 case NVME_NS_DPS_PI_TYPE1:
1275 case NVME_NS_DPS_PI_TYPE2:
1276 integrity.profile = &t10_pi_type1_crc;
ba36c21b
NB		 1277 integrity.tag_size = sizeof(u16);
1278 integrity.flags |= BLK_INTEGRITY_DEVICE_CAPABLE;
1673f1f0
CH		 1279 break;
1280 default:
1281 integrity.profile = NULL;
1282 break;
1283 }
39b7baa4
CH		 1284 integrity.tuple_size = ms;
1285 blk_integrity_register(disk, &integrity);
1286 blk_queue_max_integrity_segments(disk->queue, 1);
1673f1f0
CH		 1287}
1288#else
39b7baa4 1289static void nvme_init_integrity(struct gendisk *disk, u16 ms, u8 pi_type)
1673f1f0
CH		 1290{
1291}
1292#endif /* CONFIG_BLK_DEV_INTEGRITY */
1293
6b8190d6
SB		 1294static void nvme_set_chunk_size(struct nvme_ns *ns)
1295{
1296 u32 chunk_size = (((u32)ns->noiob) << (ns->lba_shift - 9));
1297 blk_queue_chunk_sectors(ns->queue, rounddown_pow_of_two(chunk_size));
1298}
1299
30e5e929
CH		 1300static void nvme_config_discard(struct nvme_ctrl *ctrl,
1301 unsigned stream_alignment, struct request_queue *queue)
1673f1f0 1302{
30e5e929
CH		 1303 u32 size = queue_logical_block_size(queue);
1304
1305 if (stream_alignment)
1306 size *= stream_alignment;
08095e70 1307
b35ba01e
CH		 1308 BUILD_BUG_ON(PAGE_SIZE / sizeof(struct nvme_dsm_range) <
1309 NVME_DSM_MAX_RANGES);
1310
b224f613 1311 queue->limits.discard_alignment = 0;
30e5e929 1312 queue->limits.discard_granularity = size;
f5d11840 1313
30e5e929
CH		 1314 blk_queue_max_discard_sectors(queue, UINT_MAX);
1315 blk_queue_max_discard_segments(queue, NVME_DSM_MAX_RANGES);
1316 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, queue);
e850fd16
CH		 1317
1318 if (ctrl->quirks & NVME_QUIRK_DEALLOCATE_ZEROES)
30e5e929 1319 blk_queue_max_write_zeroes_sectors(queue, UINT_MAX);
1673f1f0
CH		 1320}
1321
cdbff4f2 1322static void nvme_report_ns_ids(struct nvme_ctrl *ctrl, unsigned int nsid,
002fab04 1323 struct nvme_id_ns *id, struct nvme_ns_ids *ids)
1673f1f0 1324{
002fab04
CH		 1325 memset(ids, 0, sizeof(*ids));
1326
cdbff4f2 1327 if (ctrl->vs >= NVME_VS(1, 1, 0))
002fab04 1328 memcpy(ids->eui64, id->eui64, sizeof(id->eui64));
cdbff4f2 1329 if (ctrl->vs >= NVME_VS(1, 2, 0))
002fab04 1330 memcpy(ids->nguid, id->nguid, sizeof(id->nguid));
cdbff4f2 1331 if (ctrl->vs >= NVME_VS(1, 3, 0)) {
3b22ba26
JT		 1332 /* Don't treat error as fatal we potentially
1333 * already have a NGUID or EUI-64
1334 */
002fab04 1335 if (nvme_identify_ns_descs(ctrl, nsid, ids))
cdbff4f2 1336 dev_warn(ctrl->device,
3b22ba26
JT		 1337 "%s: Identify Descriptors failed\n", __func__);
1338 }
ac81bfa9
MB		 1339}
1340
ed754e5d
CH		 1341static bool nvme_ns_ids_valid(struct nvme_ns_ids *ids)
1342{
1343 return !uuid_is_null(&ids->uuid) ||
1344 memchr_inv(ids->nguid, 0, sizeof(ids->nguid)) ||
1345 memchr_inv(ids->eui64, 0, sizeof(ids->eui64));
1346}
1347
002fab04
CH		 1348static bool nvme_ns_ids_equal(struct nvme_ns_ids *a, struct nvme_ns_ids *b)
1349{
1350 return uuid_equal(&a->uuid, &b->uuid) &&
1351 memcmp(&a->nguid, &b->nguid, sizeof(a->nguid)) == 0 &&
1352 memcmp(&a->eui64, &b->eui64, sizeof(a->eui64)) == 0;
1353}
1354
24b0b58c
CH		 1355static void nvme_update_disk_info(struct gendisk *disk,
1356 struct nvme_ns *ns, struct nvme_id_ns *id)
1357{
1358 sector_t capacity = le64_to_cpup(&id->nsze) << (ns->lba_shift - 9);
cee160fd 1359 unsigned short bs = 1 << ns->lba_shift;
24b0b58c
CH		 1360 unsigned stream_alignment = 0;
1361
1362 if (ns->ctrl->nr_streams && ns->sws && ns->sgs)
1363 stream_alignment = ns->sws * ns->sgs;
1364
1365 blk_mq_freeze_queue(disk->queue);
1366 blk_integrity_unregister(disk);
1367
cee160fd
JL		 1368 blk_queue_logical_block_size(disk->queue, bs);
1369 blk_queue_physical_block_size(disk->queue, bs);
1370 blk_queue_io_min(disk->queue, bs);
1371
24b0b58c
CH		 1372 if (ns->ms && !ns->ext &&
1373 (ns->ctrl->ops->flags & NVME_F_METADATA_SUPPORTED))
1374 nvme_init_integrity(disk, ns->ms, ns->pi_type);
715ea9e0 1375 if (ns->ms && !nvme_ns_has_pi(ns) && !blk_get_integrity(disk))
24b0b58c
CH		 1376 capacity = 0;
1377 set_capacity(disk, capacity);
1378
1379 if (ns->ctrl->oncs & NVME_CTRL_ONCS_DSM)
1380 nvme_config_discard(ns->ctrl, stream_alignment, disk->queue);
1381 blk_mq_unfreeze_queue(disk->queue);
1382}
1383
ac81bfa9
MB		 1384static void __nvme_revalidate_disk(struct gendisk *disk, struct nvme_id_ns *id)
1385{
1386 struct nvme_ns *ns = disk->private_data;
1673f1f0
CH		 1387
1388 /*
1389 * If identify namespace failed, use default 512 byte block size so
1390 * block layer can use before failing read/write for 0 capacity.
1391 */
c81bfba9 1392 ns->lba_shift = id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ds;
1673f1f0
CH		 1393 if (ns->lba_shift == 0)
1394 ns->lba_shift = 9;
6b8190d6 1395 ns->noiob = le16_to_cpu(id->noiob);
b5be3b39 1396 ns->ms = le16_to_cpu(id->lbaf[id->flbas & NVME_NS_FLBAS_LBA_MASK].ms);
3d2118e0 1397 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
b5be3b39
CH		 1398 /* the PI implementation requires metadata equal t10 pi tuple size */
1399 if (ns->ms == sizeof(struct t10_pi_tuple))
1400 ns->pi_type = id->dps & NVME_NS_DPS_PI_MASK;
1401 else
1402 ns->pi_type = 0;
1673f1f0 1403
6b8190d6
SB		 1404 if (ns->noiob)
1405 nvme_set_chunk_size(ns);
24b0b58c 1406 nvme_update_disk_info(disk, ns, id);
32acab31
CH		 1407#ifdef CONFIG_NVME_MULTIPATH
1408 if (ns->head->disk)
1409 nvme_update_disk_info(ns->head->disk, ns, id);
1410#endif
ac81bfa9 1411}
1673f1f0 1412
ac81bfa9
MB		 1413static int nvme_revalidate_disk(struct gendisk *disk)
1414{
1415 struct nvme_ns *ns = disk->private_data;
cdbff4f2
CH		 1416 struct nvme_ctrl *ctrl = ns->ctrl;
1417 struct nvme_id_ns *id;
002fab04 1418 struct nvme_ns_ids ids;
cdbff4f2 1419 int ret = 0;
ac81bfa9
MB		 1420
1421 if (test_bit(NVME_NS_DEAD, &ns->flags)) {
1422 set_capacity(disk, 0);
1423 return -ENODEV;
1424 }
1425
ed754e5d 1426 id = nvme_identify_ns(ctrl, ns->head->ns_id);
cdbff4f2
CH		 1427 if (!id)
1428 return -ENODEV;
ac81bfa9 1429
cdbff4f2
CH		 1430 if (id->ncap == 0) {
1431 ret = -ENODEV;
1432 goto out;
1433 }
ac81bfa9 1434
5e0fab57 1435 __nvme_revalidate_disk(disk, id);
ed754e5d
CH		 1436 nvme_report_ns_ids(ctrl, ns->head->ns_id, id, &ids);
1437 if (!nvme_ns_ids_equal(&ns->head->ids, &ids)) {
1d5df6af 1438 dev_err(ctrl->device,
ed754e5d 1439 "identifiers changed for nsid %d\n", ns->head->ns_id);
1d5df6af
CH		 1440 ret = -ENODEV;
1441 }
1442
cdbff4f2
CH		 1443out:
1444 kfree(id);
1445 return ret;
1673f1f0
CH		 1446}
1447
1448static char nvme_pr_type(enum pr_type type)
1449{
1450 switch (type) {
1451 case PR_WRITE_EXCLUSIVE:
1452 return 1;
1453 case PR_EXCLUSIVE_ACCESS:
1454 return 2;
1455 case PR_WRITE_EXCLUSIVE_REG_ONLY:
1456 return 3;
1457 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
1458 return 4;
1459 case PR_WRITE_EXCLUSIVE_ALL_REGS:
1460 return 5;
1461 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
1462 return 6;
1463 default:
1464 return 0;
1465 }
1466};
1467
1468static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
1469 u64 key, u64 sa_key, u8 op)
1470{
32acab31
CH		 1471 struct nvme_ns_head *head = NULL;
1472 struct nvme_ns *ns;
1673f1f0 1473 struct nvme_command c;
32acab31 1474 int srcu_idx, ret;
1673f1f0
CH		 1475 u8 data[16] = { 0, };
1476
b0d61d58
KB		 1477 ns = nvme_get_ns_from_disk(bdev->bd_disk, &head, &srcu_idx);
1478 if (unlikely(!ns))
1479 return -EWOULDBLOCK;
1480
1673f1f0
CH		 1481 put_unaligned_le64(key, &data[0]);
1482 put_unaligned_le64(sa_key, &data[8]);
1483
1484 memset(&c, 0, sizeof(c));
1485 c.common.opcode = op;
b0d61d58 1486 c.common.nsid = cpu_to_le32(ns->head->ns_id);
1673f1f0
CH		 1487 c.common.cdw10[0] = cpu_to_le32(cdw10);
1488
b0d61d58 1489 ret = nvme_submit_sync_cmd(ns->queue, &c, data, 16);
32acab31
CH		 1490 nvme_put_ns_from_disk(head, srcu_idx);
1491 return ret;
1673f1f0
CH		 1492}
1493
1494static int nvme_pr_register(struct block_device *bdev, u64 old,
1495 u64 new, unsigned flags)
1496{
1497 u32 cdw10;
1498
1499 if (flags & ~PR_FL_IGNORE_KEY)
1500 return -EOPNOTSUPP;
1501
1502 cdw10 = old ? 2 : 0;
1503 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
1504 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
1505 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
1506}
1507
1508static int nvme_pr_reserve(struct block_device *bdev, u64 key,
1509 enum pr_type type, unsigned flags)
1510{
1511 u32 cdw10;
1512
1513 if (flags & ~PR_FL_IGNORE_KEY)
1514 return -EOPNOTSUPP;
1515
1516 cdw10 = nvme_pr_type(type) << 8;
1517 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
1518 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
1519}
1520
1521static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
1522 enum pr_type type, bool abort)
1523{
1524 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
1525 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
1526}
1527
1528static int nvme_pr_clear(struct block_device *bdev, u64 key)
1529{
8c0b3915 1530 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
1673f1f0
CH		 1531 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
1532}
1533
1534static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
1535{
1536 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
1537 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
1538}
1539
1540static const struct pr_ops nvme_pr_ops = {
1541 .pr_register = nvme_pr_register,
1542 .pr_reserve = nvme_pr_reserve,
1543 .pr_release = nvme_pr_release,
1544 .pr_preempt = nvme_pr_preempt,
1545 .pr_clear = nvme_pr_clear,
1546};
1547
a98e58e5 1548#ifdef CONFIG_BLK_SED_OPAL
4f1244c8
CH		 1549int nvme_sec_submit(void *data, u16 spsp, u8 secp, void *buffer, size_t len,
1550 bool send)
a98e58e5 1551{
4f1244c8 1552 struct nvme_ctrl *ctrl = data;
a98e58e5 1553 struct nvme_command cmd;
a98e58e5
SB		 1554
1555 memset(&cmd, 0, sizeof(cmd));
1556 if (send)
1557 cmd.common.opcode = nvme_admin_security_send;
1558 else
1559 cmd.common.opcode = nvme_admin_security_recv;
a98e58e5
SB		 1560 cmd.common.nsid = 0;
1561 cmd.common.cdw10[0] = cpu_to_le32(((u32)secp) << 24 | ((u32)spsp) << 8);
1562 cmd.common.cdw10[1] = cpu_to_le32(len);
1563
1564 return __nvme_submit_sync_cmd(ctrl->admin_q, &cmd, NULL, buffer, len,
1565 ADMIN_TIMEOUT, NVME_QID_ANY, 1, 0);
1566}
1567EXPORT_SYMBOL_GPL(nvme_sec_submit);
1568#endif /* CONFIG_BLK_SED_OPAL */
1569
5bae7f73 1570static const struct block_device_operations nvme_fops = {
1673f1f0
CH		 1571 .owner = THIS_MODULE,
1572 .ioctl = nvme_ioctl,
761f2e1e 1573 .compat_ioctl = nvme_ioctl,
1673f1f0
CH		 1574 .open = nvme_open,
1575 .release = nvme_release,
1576 .getgeo = nvme_getgeo,
1577 .revalidate_disk= nvme_revalidate_disk,
1578 .pr_ops = &nvme_pr_ops,
1579};
1580
32acab31
CH		 1581#ifdef CONFIG_NVME_MULTIPATH
1582static int nvme_ns_head_open(struct block_device *bdev, fmode_t mode)
1583{
1584 struct nvme_ns_head *head = bdev->bd_disk->private_data;
1585
1586 if (!kref_get_unless_zero(&head->ref))
1587 return -ENXIO;
1588 return 0;
1589}
1590
1591static void nvme_ns_head_release(struct gendisk *disk, fmode_t mode)
1592{
1593 nvme_put_ns_head(disk->private_data);
1594}
1595
1596const struct block_device_operations nvme_ns_head_ops = {
1597 .owner = THIS_MODULE,
1598 .open = nvme_ns_head_open,
1599 .release = nvme_ns_head_release,
1600 .ioctl = nvme_ioctl,
1601 .compat_ioctl = nvme_ioctl,
1602 .getgeo = nvme_getgeo,
1603 .pr_ops = &nvme_pr_ops,
1604};
1605#endif /* CONFIG_NVME_MULTIPATH */
1606
5fd4ce1b
CH		 1607static int nvme_wait_ready(struct nvme_ctrl *ctrl, u64 cap, bool enabled)
1608{
1609 unsigned long timeout =
1610 ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1611 u32 csts, bit = enabled ? NVME_CSTS_RDY : 0;
1612 int ret;
1613
1614 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
0df1e4f5
KB		 1615 if (csts == ~0)
1616 return -ENODEV;
5fd4ce1b
CH		 1617 if ((csts & NVME_CSTS_RDY) == bit)
1618 break;
1619
1620 msleep(100);
1621 if (fatal_signal_pending(current))
1622 return -EINTR;
1623 if (time_after(jiffies, timeout)) {
1b3c47c1 1624 dev_err(ctrl->device,
5fd4ce1b
CH		 1625 "Device not ready; aborting %s\n", enabled ?
1626 "initialisation" : "reset");
1627 return -ENODEV;
1628 }
1629 }
1630
1631 return ret;
1632}
1633
1634/*
1635 * If the device has been passed off to us in an enabled state, just clear
1636 * the enabled bit. The spec says we should set the 'shutdown notification
1637 * bits', but doing so may cause the device to complete commands to the
1638 * admin queue ... and we don't know what memory that might be pointing at!
1639 */
1640int nvme_disable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1641{
1642 int ret;
1643
1644 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1645 ctrl->ctrl_config &= ~NVME_CC_ENABLE;
1646
1647 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1648 if (ret)
1649 return ret;
54adc010 1650
b5a10c5f 1651 if (ctrl->quirks & NVME_QUIRK_DELAY_BEFORE_CHK_RDY)
54adc010
GP		 1652 msleep(NVME_QUIRK_DELAY_AMOUNT);
1653
5fd4ce1b
CH		 1654 return nvme_wait_ready(ctrl, cap, false);
1655}
576d55d6 1656EXPORT_SYMBOL_GPL(nvme_disable_ctrl);
5fd4ce1b
CH		 1657
1658int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
1659{
1660 /*
1661 * Default to a 4K page size, with the intention to update this
1662 * path in the future to accomodate architectures with differing
1663 * kernel and IO page sizes.
1664 */
1665 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12, page_shift = 12;
1666 int ret;
1667
1668 if (page_shift < dev_page_min) {
1b3c47c1 1669 dev_err(ctrl->device,
5fd4ce1b
CH		 1670 "Minimum device page size %u too large for host (%u)\n",
1671 1 << dev_page_min, 1 << page_shift);
1672 return -ENODEV;
1673 }
1674
1675 ctrl->page_size = 1 << page_shift;
1676
1677 ctrl->ctrl_config = NVME_CC_CSS_NVM;
1678 ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
60b43f62 1679 ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
5fd4ce1b
CH		 1680 ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1681 ctrl->ctrl_config |= NVME_CC_ENABLE;
1682
1683 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1684 if (ret)
1685 return ret;
1686 return nvme_wait_ready(ctrl, cap, true);
1687}
576d55d6 1688EXPORT_SYMBOL_GPL(nvme_enable_ctrl);
5fd4ce1b
CH		 1689
1690int nvme_shutdown_ctrl(struct nvme_ctrl *ctrl)
1691{
07fbd32a 1692 unsigned long timeout = jiffies + (ctrl->shutdown_timeout * HZ);
5fd4ce1b
CH		 1693 u32 csts;
1694 int ret;
1695
1696 ctrl->ctrl_config &= ~NVME_CC_SHN_MASK;
1697 ctrl->ctrl_config |= NVME_CC_SHN_NORMAL;
1698
1699 ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC, ctrl->ctrl_config);
1700 if (ret)
1701 return ret;
1702
1703 while ((ret = ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts)) == 0) {
1704 if ((csts & NVME_CSTS_SHST_MASK) == NVME_CSTS_SHST_CMPLT)
1705 break;
1706
1707 msleep(100);
1708 if (fatal_signal_pending(current))
1709 return -EINTR;
1710 if (time_after(jiffies, timeout)) {
1b3c47c1 1711 dev_err(ctrl->device,
5fd4ce1b
CH		 1712 "Device shutdown incomplete; abort shutdown\n");
1713 return -ENODEV;
1714 }
1715 }
1716
1717 return ret;
1718}
576d55d6 1719EXPORT_SYMBOL_GPL(nvme_shutdown_ctrl);
5fd4ce1b 1720
da35825d
CH		 1721static void nvme_set_queue_limits(struct nvme_ctrl *ctrl,
1722 struct request_queue *q)
1723{
7c88cb00
JA		 1724 bool vwc = false;
1725
da35825d 1726 if (ctrl->max_hw_sectors) {
45686b61
CH		 1727 u32 max_segments =
1728 (ctrl->max_hw_sectors / (ctrl->page_size >> 9)) + 1;
1729
da35825d 1730 blk_queue_max_hw_sectors(q, ctrl->max_hw_sectors);
45686b61 1731 blk_queue_max_segments(q, min_t(u32, max_segments, USHRT_MAX));
da35825d 1732 }
249159c5
KB		 1733 if ((ctrl->quirks & NVME_QUIRK_STRIPE_SIZE) &&
1734 is_power_of_2(ctrl->max_hw_sectors))
e6282aef 1735 blk_queue_chunk_sectors(q, ctrl->max_hw_sectors);
da35825d 1736 blk_queue_virt_boundary(q, ctrl->page_size - 1);
7c88cb00
JA		 1737 if (ctrl->vwc & NVME_CTRL_VWC_PRESENT)
1738 vwc = true;
1739 blk_queue_write_cache(q, vwc, vwc);
da35825d
CH		 1740}
1741
dbf86b39
JD		 1742static int nvme_configure_timestamp(struct nvme_ctrl *ctrl)
1743{
1744 __le64 ts;
1745 int ret;
1746
1747 if (!(ctrl->oncs & NVME_CTRL_ONCS_TIMESTAMP))
1748 return 0;
1749
1750 ts = cpu_to_le64(ktime_to_ms(ktime_get_real()));
1751 ret = nvme_set_features(ctrl, NVME_FEAT_TIMESTAMP, 0, &ts, sizeof(ts),
1752 NULL);
1753 if (ret)
1754 dev_warn_once(ctrl->device,
1755 "could not set timestamp (%d)\n", ret);
1756 return ret;
1757}
1758
634b8325 1759static int nvme_configure_apst(struct nvme_ctrl *ctrl)
c5552fde
AL		 1760{
1761 /*
1762 * APST (Autonomous Power State Transition) lets us program a
1763 * table of power state transitions that the controller will
1764 * perform automatically. We configure it with a simple
1765 * heuristic: we are willing to spend at most 2% of the time
1766 * transitioning between power states. Therefore, when running
1767 * in any given state, we will enter the next lower-power
76e4ad09 1768 * non-operational state after waiting 50 * (enlat + exlat)
da87591b 1769 * microseconds, as long as that state's exit latency is under
c5552fde
AL		 1770 * the requested maximum latency.
1771 *
1772 * We will not autonomously enter any non-operational state for
1773 * which the total latency exceeds ps_max_latency_us. Users
1774 * can set ps_max_latency_us to zero to turn off APST.
1775 */
1776
1777 unsigned apste;
1778 struct nvme_feat_auto_pst *table;
fb0dc399
AL		 1779 u64 max_lat_us = 0;
1780 int max_ps = -1;
c5552fde
AL		 1781 int ret;
1782
1783 /*
1784 * If APST isn't supported or if we haven't been initialized yet,
1785 * then don't do anything.
1786 */
1787 if (!ctrl->apsta)
634b8325 1788 return 0;
c5552fde
AL		 1789
1790 if (ctrl->npss > 31) {
1791 dev_warn(ctrl->device, "NPSS is invalid; not using APST\n");
634b8325 1792 return 0;
c5552fde
AL		 1793 }
1794
1795 table = kzalloc(sizeof(*table), GFP_KERNEL);
1796 if (!table)
634b8325 1797 return 0;
c5552fde 1798
76a5af84 1799 if (!ctrl->apst_enabled || ctrl->ps_max_latency_us == 0) {
c5552fde
AL		 1800 /* Turn off APST. */
1801 apste = 0;
fb0dc399 1802 dev_dbg(ctrl->device, "APST disabled\n");
c5552fde
AL		 1803 } else {
1804 __le64 target = cpu_to_le64(0);
1805 int state;
1806
1807 /*
1808 * Walk through all states from lowest- to highest-power.
1809 * According to the spec, lower-numbered states use more
1810 * power. NPSS, despite the name, is the index of the
1811 * lowest-power state, not the number of states.
1812 */
1813 for (state = (int)ctrl->npss; state >= 0; state--) {
da87591b 1814 u64 total_latency_us, exit_latency_us, transition_ms;
c5552fde
AL		 1815
1816 if (target)
1817 table->entries[state] = target;
1818
ff5350a8
AL		 1819 /*
1820 * Don't allow transitions to the deepest state
1821 * if it's quirked off.
1822 */
1823 if (state == ctrl->npss &&
1824 (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS))
1825 continue;
1826
c5552fde
AL		 1827 /*
1828 * Is this state a useful non-operational state for
1829 * higher-power states to autonomously transition to?
1830 */
1831 if (!(ctrl->psd[state].flags &
1832 NVME_PS_FLAGS_NON_OP_STATE))
1833 continue;
1834
da87591b
KHF		 1835 exit_latency_us =
1836 (u64)le32_to_cpu(ctrl->psd[state].exit_lat);
1837 if (exit_latency_us > ctrl->ps_max_latency_us)
c5552fde
AL		 1838 continue;
1839
da87591b
KHF		 1840 total_latency_us =
1841 exit_latency_us +
1842 le32_to_cpu(ctrl->psd[state].entry_lat);
1843
c5552fde
AL		 1844 /*
1845 * This state is good. Use it as the APST idle
1846 * target for higher power states.
1847 */
1848 transition_ms = total_latency_us + 19;
1849 do_div(transition_ms, 20);
1850 if (transition_ms > (1 << 24) - 1)
1851 transition_ms = (1 << 24) - 1;
1852
1853 target = cpu_to_le64((state << 3) |
1854 (transition_ms << 8));
fb0dc399
AL		 1855
1856 if (max_ps == -1)
1857 max_ps = state;
1858
1859 if (total_latency_us > max_lat_us)
1860 max_lat_us = total_latency_us;
c5552fde
AL		 1861 }
1862
1863 apste = 1;
fb0dc399
AL		 1864
1865 if (max_ps == -1) {
1866 dev_dbg(ctrl->device, "APST enabled but no non-operational states are available\n");
1867 } else {
1868 dev_dbg(ctrl->device, "APST enabled: max PS = %d, max round-trip latency = %lluus, table = %*phN\n",
1869 max_ps, max_lat_us, (int)sizeof(*table), table);
1870 }
c5552fde
AL		 1871 }
1872
1873 ret = nvme_set_features(ctrl, NVME_FEAT_AUTO_PST, apste,
1874 table, sizeof(*table), NULL);
1875 if (ret)
1876 dev_err(ctrl->device, "failed to set APST feature (%d)\n", ret);
1877
1878 kfree(table);
634b8325 1879 return ret;
c5552fde
AL		 1880}
1881
1882static void nvme_set_latency_tolerance(struct device *dev, s32 val)
1883{
1884 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
1885 u64 latency;
1886
1887 switch (val) {
1888 case PM_QOS_LATENCY_TOLERANCE_NO_CONSTRAINT:
1889 case PM_QOS_LATENCY_ANY:
1890 latency = U64_MAX;
1891 break;
1892
1893 default:
1894 latency = val;
1895 }
1896
1897 if (ctrl->ps_max_latency_us != latency) {
1898 ctrl->ps_max_latency_us = latency;
1899 nvme_configure_apst(ctrl);
1900 }
1901}
1902
bd4da3ab
AL		 1903struct nvme_core_quirk_entry {
1904 /*
1905 * NVMe model and firmware strings are padded with spaces. For
1906 * simplicity, strings in the quirk table are padded with NULLs
1907 * instead.
1908 */
1909 u16 vid;
1910 const char *mn;
1911 const char *fr;
1912 unsigned long quirks;
1913};
1914
1915static const struct nvme_core_quirk_entry core_quirks[] = {
c5552fde 1916 {
be56945c
AL		 1917 /*
1918 * This Toshiba device seems to die using any APST states. See:
1919 * https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1678184/comments/11
1920 */
1921 .vid = 0x1179,
1922 .mn = "THNSF5256GPUK TOSHIBA",
c5552fde 1923 .quirks = NVME_QUIRK_NO_APST,
be56945c 1924 }
bd4da3ab
AL		 1925};
1926
1927/* match is null-terminated but idstr is space-padded. */
1928static bool string_matches(const char *idstr, const char *match, size_t len)
1929{
1930 size_t matchlen;
1931
1932 if (!match)
1933 return true;
1934
1935 matchlen = strlen(match);
1936 WARN_ON_ONCE(matchlen > len);
1937
1938 if (memcmp(idstr, match, matchlen))
1939 return false;
1940
1941 for (; matchlen < len; matchlen++)
1942 if (idstr[matchlen] != ' ')
1943 return false;
1944
1945 return true;
1946}
1947
1948static bool quirk_matches(const struct nvme_id_ctrl *id,
1949 const struct nvme_core_quirk_entry *q)
1950{
1951 return q->vid == le16_to_cpu(id->vid) &&
1952 string_matches(id->mn, q->mn, sizeof(id->mn)) &&
1953 string_matches(id->fr, q->fr, sizeof(id->fr));
1954}
1955
ab9e00cc
CH		 1956static void nvme_init_subnqn(struct nvme_subsystem *subsys, struct nvme_ctrl *ctrl,
1957 struct nvme_id_ctrl *id)
180de007
CH		 1958{
1959 size_t nqnlen;
1960 int off;
1961
a676e05d
JD		 1962 if(!(ctrl->quirks & NVME_QUIRK_IGNORE_DEV_SUBNQN)) {
1963 nqnlen = strnlen(id->subnqn, NVMF_NQN_SIZE);
1964 if (nqnlen > 0 && nqnlen < NVMF_NQN_SIZE) {
1965 strlcpy(subsys->subnqn, id->subnqn, NVMF_NQN_SIZE);
1966 return;
1967 }
180de007 1968
a676e05d
JD		 1969 if (ctrl->vs >= NVME_VS(1, 2, 1))
1970 dev_warn(ctrl->device, "missing or invalid SUBNQN field.\n");
1971 }
180de007
CH		 1972
1973 /* Generate a "fake" NQN per Figure 254 in NVMe 1.3 + ECN 001 */
ab9e00cc 1974 off = snprintf(subsys->subnqn, NVMF_NQN_SIZE,
d0780857 1975 "nqn.2014.08.org.nvmexpress:%04x%04x",
180de007 1976 le16_to_cpu(id->vid), le16_to_cpu(id->ssvid));
ab9e00cc 1977 memcpy(subsys->subnqn + off, id->sn, sizeof(id->sn));
180de007 1978 off += sizeof(id->sn);
ab9e00cc 1979 memcpy(subsys->subnqn + off, id->mn, sizeof(id->mn));
180de007 1980 off += sizeof(id->mn);
ab9e00cc
CH		 1981 memset(subsys->subnqn + off, 0, sizeof(subsys->subnqn) - off);
1982}
1983
1984static void __nvme_release_subsystem(struct nvme_subsystem *subsys)
1985{
1986 ida_simple_remove(&nvme_subsystems_ida, subsys->instance);
1987 kfree(subsys);
1988}
1989
1990static void nvme_release_subsystem(struct device *dev)
1991{
1992 __nvme_release_subsystem(container_of(dev, struct nvme_subsystem, dev));
1993}
1994
1995static void nvme_destroy_subsystem(struct kref *ref)
1996{
1997 struct nvme_subsystem *subsys =
1998 container_of(ref, struct nvme_subsystem, ref);
1999
2000 mutex_lock(&nvme_subsystems_lock);
2001 list_del(&subsys->entry);
2002 mutex_unlock(&nvme_subsystems_lock);
2003
ed754e5d 2004 ida_destroy(&subsys->ns_ida);
ab9e00cc
CH		 2005 device_del(&subsys->dev);
2006 put_device(&subsys->dev);
2007}
2008
2009static void nvme_put_subsystem(struct nvme_subsystem *subsys)
2010{
2011 kref_put(&subsys->ref, nvme_destroy_subsystem);
2012}
2013
2014static struct nvme_subsystem *__nvme_find_get_subsystem(const char *subsysnqn)
2015{
2016 struct nvme_subsystem *subsys;
2017
2018 lockdep_assert_held(&nvme_subsystems_lock);
2019
2020 list_for_each_entry(subsys, &nvme_subsystems, entry) {
2021 if (strcmp(subsys->subnqn, subsysnqn))
2022 continue;
2023 if (!kref_get_unless_zero(&subsys->ref))
2024 continue;
2025 return subsys;
2026 }
2027
2028 return NULL;
2029}
2030
1e496938
HR		 2031#define SUBSYS_ATTR_RO(_name, _mode, _show) \
2032 struct device_attribute subsys_attr_##_name = \
2033 __ATTR(_name, _mode, _show, NULL)
2034
2035static ssize_t nvme_subsys_show_nqn(struct device *dev,
2036 struct device_attribute *attr,
2037 char *buf)
2038{
2039 struct nvme_subsystem *subsys =
2040 container_of(dev, struct nvme_subsystem, dev);
2041
2042 return snprintf(buf, PAGE_SIZE, "%s\n", subsys->subnqn);
2043}
2044static SUBSYS_ATTR_RO(subsysnqn, S_IRUGO, nvme_subsys_show_nqn);
2045
2046#define nvme_subsys_show_str_function(field) \
2047static ssize_t subsys_##field##_show(struct device *dev, \
2048 struct device_attribute *attr, char *buf) \
2049{ \
2050 struct nvme_subsystem *subsys = \
2051 container_of(dev, struct nvme_subsystem, dev); \
2052 return sprintf(buf, "%.*s\n", \
2053 (int)sizeof(subsys->field), subsys->field); \
2054} \
2055static SUBSYS_ATTR_RO(field, S_IRUGO, subsys_##field##_show);
2056
2057nvme_subsys_show_str_function(model);
2058nvme_subsys_show_str_function(serial);
2059nvme_subsys_show_str_function(firmware_rev);
2060
2061static struct attribute *nvme_subsys_attrs[] = {
2062 &subsys_attr_model.attr,
2063 &subsys_attr_serial.attr,
2064 &subsys_attr_firmware_rev.attr,
2065 &subsys_attr_subsysnqn.attr,
2066 NULL,
2067};
2068
2069static struct attribute_group nvme_subsys_attrs_group = {
2070 .attrs = nvme_subsys_attrs,
2071};
2072
2073static const struct attribute_group *nvme_subsys_attrs_groups[] = {
2074 &nvme_subsys_attrs_group,
2075 NULL,
2076};
2077
3537b1cb
IR		 2078static int nvme_active_ctrls(struct nvme_subsystem *subsys)
2079{
2080 int count = 0;
2081 struct nvme_ctrl *ctrl;
2082
2083 mutex_lock(&subsys->lock);
2084 list_for_each_entry(ctrl, &subsys->ctrls, subsys_entry) {
2085 if (ctrl->state != NVME_CTRL_DELETING &&
2086 ctrl->state != NVME_CTRL_DEAD)
2087 count++;
2088 }
2089 mutex_unlock(&subsys->lock);
2090
2091 return count;
2092}
2093
ab9e00cc
CH		 2094static int nvme_init_subsystem(struct nvme_ctrl *ctrl, struct nvme_id_ctrl *id)
2095{
2096 struct nvme_subsystem *subsys, *found;
2097 int ret;
2098
2099 subsys = kzalloc(sizeof(*subsys), GFP_KERNEL);
2100 if (!subsys)
2101 return -ENOMEM;
2102 ret = ida_simple_get(&nvme_subsystems_ida, 0, 0, GFP_KERNEL);
2103 if (ret < 0) {
2104 kfree(subsys);
2105 return ret;
2106 }
2107 subsys->instance = ret;
2108 mutex_init(&subsys->lock);
2109 kref_init(&subsys->ref);
2110 INIT_LIST_HEAD(&subsys->ctrls);
ed754e5d 2111 INIT_LIST_HEAD(&subsys->nsheads);
ab9e00cc
CH		 2112 nvme_init_subnqn(subsys, ctrl, id);
2113 memcpy(subsys->serial, id->sn, sizeof(subsys->serial));
2114 memcpy(subsys->model, id->mn, sizeof(subsys->model));
2115 memcpy(subsys->firmware_rev, id->fr, sizeof(subsys->firmware_rev));
2116 subsys->vendor_id = le16_to_cpu(id->vid);
2117 subsys->cmic = id->cmic;
2118
2119 subsys->dev.class = nvme_subsys_class;
2120 subsys->dev.release = nvme_release_subsystem;
1e496938 2121 subsys->dev.groups = nvme_subsys_attrs_groups;
ab9e00cc
CH		 2122 dev_set_name(&subsys->dev, "nvme-subsys%d", subsys->instance);
2123 device_initialize(&subsys->dev);
2124
2125 mutex_lock(&nvme_subsystems_lock);
2126 found = __nvme_find_get_subsystem(subsys->subnqn);
2127 if (found) {
2128 /*
2129 * Verify that the subsystem actually supports multiple
2130 * controllers, else bail out.
2131 */
3537b1cb 2132 if (nvme_active_ctrls(found) && !(id->cmic & (1 << 1))) {
ab9e00cc
CH		 2133 dev_err(ctrl->device,
2134 "ignoring ctrl due to duplicate subnqn (%s).\n",
2135 found->subnqn);
2136 nvme_put_subsystem(found);
2137 ret = -EINVAL;
2138 goto out_unlock;
2139 }
2140
2141 __nvme_release_subsystem(subsys);
2142 subsys = found;
2143 } else {
2144 ret = device_add(&subsys->dev);
2145 if (ret) {
2146 dev_err(ctrl->device,
2147 "failed to register subsystem device.\n");
2148 goto out_unlock;
2149 }
ed754e5d 2150 ida_init(&subsys->ns_ida);
ab9e00cc
CH		 2151 list_add_tail(&subsys->entry, &nvme_subsystems);
2152 }
2153
2154 ctrl->subsys = subsys;
2155 mutex_unlock(&nvme_subsystems_lock);
2156
2157 if (sysfs_create_link(&subsys->dev.kobj, &ctrl->device->kobj,
2158 dev_name(ctrl->device))) {
2159 dev_err(ctrl->device,
2160 "failed to create sysfs link from subsystem.\n");
2161 /* the transport driver will eventually put the subsystem */
2162 return -EINVAL;
2163 }
2164
2165 mutex_lock(&subsys->lock);
2166 list_add_tail(&ctrl->subsys_entry, &subsys->ctrls);
2167 mutex_unlock(&subsys->lock);
2168
2169 return 0;
2170
2171out_unlock:
2172 mutex_unlock(&nvme_subsystems_lock);
2173 put_device(&subsys->dev);
2174 return ret;
180de007
CH		 2175}
2176
c627c487
KB		 2177static int nvme_get_log(struct nvme_ctrl *ctrl, u8 log_page, void *log,
2178 size_t size)
2179{
2180 struct nvme_command c = { };
2181
2182 c.common.opcode = nvme_admin_get_log_page;
2183 c.common.nsid = cpu_to_le32(NVME_NSID_ALL);
2184 c.common.cdw10[0] = nvme_get_log_dw10(log_page, size);
2185
2186 return nvme_submit_sync_cmd(ctrl->admin_q, &c, log, size);
2187}
2188
84fef62d
KB		 2189static int nvme_get_effects_log(struct nvme_ctrl *ctrl)
2190{
2191 int ret;
2192
2193 if (!ctrl->effects)
2194 ctrl->effects = kzalloc(sizeof(*ctrl->effects), GFP_KERNEL);
2195
2196 if (!ctrl->effects)
2197 return 0;
2198
2199 ret = nvme_get_log(ctrl, NVME_LOG_CMD_EFFECTS, ctrl->effects,
2200 sizeof(*ctrl->effects));
2201 if (ret) {
2202 kfree(ctrl->effects);
2203 ctrl->effects = NULL;
2204 }
2205 return ret;
180de007
CH		 2206}
2207
7fd8930f
CH		 2208/*
2209 * Initialize the cached copies of the Identify data and various controller
2210 * register in our nvme_ctrl structure. This should be called as soon as
2211 * the admin queue is fully up and running.
2212 */
2213int nvme_init_identify(struct nvme_ctrl *ctrl)
2214{
2215 struct nvme_id_ctrl *id;
2216 u64 cap;
2217 int ret, page_shift;
a229dbf6 2218 u32 max_hw_sectors;
76a5af84 2219 bool prev_apst_enabled;
7fd8930f 2220
f3ca80fc
CH		 2221 ret = ctrl->ops->reg_read32(ctrl, NVME_REG_VS, &ctrl->vs);
2222 if (ret) {
1b3c47c1 2223 dev_err(ctrl->device, "Reading VS failed (%d)\n", ret);
f3ca80fc
CH		 2224 return ret;
2225 }
2226
7fd8930f
CH		 2227 ret = ctrl->ops->reg_read64(ctrl, NVME_REG_CAP, &cap);
2228 if (ret) {
1b3c47c1 2229 dev_err(ctrl->device, "Reading CAP failed (%d)\n", ret);
7fd8930f
CH		 2230 return ret;
2231 }
2232 page_shift = NVME_CAP_MPSMIN(cap) + 12;
2233
8ef2074d 2234 if (ctrl->vs >= NVME_VS(1, 1, 0))
f3ca80fc
CH		 2235 ctrl->subsystem = NVME_CAP_NSSRC(cap);
2236
7fd8930f
CH		 2237 ret = nvme_identify_ctrl(ctrl, &id);
2238 if (ret) {
1b3c47c1 2239 dev_err(ctrl->device, "Identify Controller failed (%d)\n", ret);
7fd8930f
CH		 2240 return -EIO;
2241 }
2242
84fef62d
KB		 2243 if (id->lpa & NVME_CTRL_LPA_CMD_EFFECTS_LOG) {
2244 ret = nvme_get_effects_log(ctrl);
2245 if (ret < 0)
2246 return ret;
2247 }
180de007 2248
bd4da3ab 2249 if (!ctrl->identified) {
ab9e00cc
CH		 2250 int i;
2251
2252 ret = nvme_init_subsystem(ctrl, id);
2253 if (ret)
2254 goto out_free;
2255
bd4da3ab
AL		 2256 /*
2257 * Check for quirks. Quirk can depend on firmware version,
2258 * so, in principle, the set of quirks present can change
2259 * across a reset. As a possible future enhancement, we
2260 * could re-scan for quirks every time we reinitialize
2261 * the device, but we'd have to make sure that the driver
2262 * behaves intelligently if the quirks change.
2263 */
bd4da3ab
AL		 2264 for (i = 0; i < ARRAY_SIZE(core_quirks); i++) {
2265 if (quirk_matches(id, &core_quirks[i]))
2266 ctrl->quirks |= core_quirks[i].quirks;
2267 }
2268 }
2269
c35e30b4 2270 if (force_apst && (ctrl->quirks & NVME_QUIRK_NO_DEEPEST_PS)) {
f0425db0 2271 dev_warn(ctrl->device, "forcibly allowing all power states due to nvme_core.force_apst -- use at your own risk\n");
c35e30b4
AL		 2272 ctrl->quirks &= ~NVME_QUIRK_NO_DEEPEST_PS;
2273 }
2274
8a9ae523 2275 ctrl->oacs = le16_to_cpu(id->oacs);
7fd8930f 2276 ctrl->oncs = le16_to_cpup(&id->oncs);
6bf25d16 2277 atomic_set(&ctrl->abort_limit, id->acl + 1);
7fd8930f 2278 ctrl->vwc = id->vwc;
931e1c22 2279 ctrl->cntlid = le16_to_cpup(&id->cntlid);
7fd8930f 2280 if (id->mdts)
a229dbf6 2281 max_hw_sectors = 1 << (id->mdts + page_shift - 9);
7fd8930f 2282 else
a229dbf6
CH		 2283 max_hw_sectors = UINT_MAX;
2284 ctrl->max_hw_sectors =
2285 min_not_zero(ctrl->max_hw_sectors, max_hw_sectors);
7fd8930f 2286
da35825d 2287 nvme_set_queue_limits(ctrl, ctrl->admin_q);
07bfcd09 2288 ctrl->sgls = le32_to_cpu(id->sgls);
038bd4cb 2289 ctrl->kas = le16_to_cpu(id->kas);
07bfcd09 2290
07fbd32a
MP		 2291 if (id->rtd3e) {
2292 /* us -> s */
2293 u32 transition_time = le32_to_cpu(id->rtd3e) / 1000000;
2294
2295 ctrl->shutdown_timeout = clamp_t(unsigned int, transition_time,
2296 shutdown_timeout, 60);
2297
2298 if (ctrl->shutdown_timeout != shutdown_timeout)
2299 dev_warn(ctrl->device,
2300 "Shutdown timeout set to %u seconds\n",
2301 ctrl->shutdown_timeout);
2302 } else
2303 ctrl->shutdown_timeout = shutdown_timeout;
2304
c5552fde 2305 ctrl->npss = id->npss;
76a5af84
KHF		 2306 ctrl->apsta = id->apsta;
2307 prev_apst_enabled = ctrl->apst_enabled;
c35e30b4
AL		 2308 if (ctrl->quirks & NVME_QUIRK_NO_APST) {
2309 if (force_apst && id->apsta) {
f0425db0 2310 dev_warn(ctrl->device, "forcibly allowing APST due to nvme_core.force_apst -- use at your own risk\n");
76a5af84 2311 ctrl->apst_enabled = true;
c35e30b4 2312 } else {
76a5af84 2313 ctrl->apst_enabled = false;
c35e30b4
AL		 2314 }
2315 } else {
76a5af84 2316 ctrl->apst_enabled = id->apsta;
c35e30b4 2317 }
c5552fde
AL		 2318 memcpy(ctrl->psd, id->psd, sizeof(ctrl->psd));
2319
d3d5b87d 2320 if (ctrl->ops->flags & NVME_F_FABRICS) {
07bfcd09
CH		 2321 ctrl->icdoff = le16_to_cpu(id->icdoff);
2322 ctrl->ioccsz = le32_to_cpu(id->ioccsz);
2323 ctrl->iorcsz = le32_to_cpu(id->iorcsz);
2324 ctrl->maxcmd = le16_to_cpu(id->maxcmd);
2325
2326 /*
2327 * In fabrics we need to verify the cntlid matches the
2328 * admin connect
2329 */
634b8325 2330 if (ctrl->cntlid != le16_to_cpu(id->cntlid)) {
07bfcd09 2331 ret = -EINVAL;
634b8325
KB		 2332 goto out_free;
2333 }
038bd4cb
SG		 2334
2335 if (!ctrl->opts->discovery_nqn && !ctrl->kas) {
f0425db0 2336 dev_err(ctrl->device,
038bd4cb
SG		 2337 "keep-alive support is mandatory for fabrics\n");
2338 ret = -EINVAL;
634b8325 2339 goto out_free;
038bd4cb 2340 }
07bfcd09
CH		 2341 } else {
2342 ctrl->cntlid = le16_to_cpu(id->cntlid);
fe6d53c9
CH		 2343 ctrl->hmpre = le32_to_cpu(id->hmpre);
2344 ctrl->hmmin = le32_to_cpu(id->hmmin);
044a9df1
CH		 2345 ctrl->hmminds = le32_to_cpu(id->hmminds);
2346 ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
07bfcd09 2347 }
da35825d 2348
7fd8930f 2349 kfree(id);
bd4da3ab 2350
76a5af84 2351 if (ctrl->apst_enabled && !prev_apst_enabled)
c5552fde 2352 dev_pm_qos_expose_latency_tolerance(ctrl->device);
76a5af84 2353 else if (!ctrl->apst_enabled && prev_apst_enabled)
c5552fde
AL		 2354 dev_pm_qos_hide_latency_tolerance(ctrl->device);
2355
634b8325
KB		 2356 ret = nvme_configure_apst(ctrl);
2357 if (ret < 0)
2358 return ret;
dbf86b39
JD		 2359
2360 ret = nvme_configure_timestamp(ctrl);
2361 if (ret < 0)
2362 return ret;
634b8325
KB		 2363
2364 ret = nvme_configure_directives(ctrl);
2365 if (ret < 0)
2366 return ret;
c5552fde 2367
bd4da3ab 2368 ctrl->identified = true;
c5552fde 2369
634b8325
KB		 2370 return 0;
2371
2372out_free:
2373 kfree(id);
07bfcd09 2374 return ret;
7fd8930f 2375}
576d55d6 2376EXPORT_SYMBOL_GPL(nvme_init_identify);
7fd8930f 2377
f3ca80fc 2378static int nvme_dev_open(struct inode *inode, struct file *file)
1673f1f0 2379{
a6a5149b
CH		 2380 struct nvme_ctrl *ctrl =
2381 container_of(inode->i_cdev, struct nvme_ctrl, cdev);
1673f1f0 2382
999ada28 2383 if (ctrl->state != NVME_CTRL_LIVE)
a6a5149b
CH		 2384 return -EWOULDBLOCK;
2385 file->private_data = ctrl;
f3ca80fc
CH		 2386 return 0;
2387}
2388
bfd89471
CH		 2389static int nvme_dev_user_cmd(struct nvme_ctrl *ctrl, void __user *argp)
2390{
2391 struct nvme_ns *ns;
2392 int ret;
2393
2394 mutex_lock(&ctrl->namespaces_mutex);
2395 if (list_empty(&ctrl->namespaces)) {
2396 ret = -ENOTTY;
2397 goto out_unlock;
2398 }
2399
2400 ns = list_first_entry(&ctrl->namespaces, struct nvme_ns, list);
2401 if (ns != list_last_entry(&ctrl->namespaces, struct nvme_ns, list)) {
1b3c47c1 2402 dev_warn(ctrl->device,
bfd89471
CH		 2403 "NVME_IOCTL_IO_CMD not supported when multiple namespaces present!\n");
2404 ret = -EINVAL;
2405 goto out_unlock;
2406 }
2407
1b3c47c1 2408 dev_warn(ctrl->device,
bfd89471
CH		 2409 "using deprecated NVME_IOCTL_IO_CMD ioctl on the char device!\n");
2410 kref_get(&ns->kref);
2411 mutex_unlock(&ctrl->namespaces_mutex);
2412
2413 ret = nvme_user_cmd(ctrl, ns, argp);
2414 nvme_put_ns(ns);
2415 return ret;
2416
2417out_unlock:
2418 mutex_unlock(&ctrl->namespaces_mutex);
2419 return ret;
2420}
2421
f3ca80fc
CH		 2422static long nvme_dev_ioctl(struct file *file, unsigned int cmd,
2423 unsigned long arg)
2424{
2425 struct nvme_ctrl *ctrl = file->private_data;
2426 void __user *argp = (void __user *)arg;
f3ca80fc
CH		 2427
2428 switch (cmd) {
2429 case NVME_IOCTL_ADMIN_CMD:
2430 return nvme_user_cmd(ctrl, NULL, argp);
2431 case NVME_IOCTL_IO_CMD:
bfd89471 2432 return nvme_dev_user_cmd(ctrl, argp);
f3ca80fc 2433 case NVME_IOCTL_RESET:
1b3c47c1 2434 dev_warn(ctrl->device, "resetting controller\n");
d86c4d8e 2435 return nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2436 case NVME_IOCTL_SUBSYS_RESET:
2437 return nvme_reset_subsystem(ctrl);
9ec3bb2f
KB		 2438 case NVME_IOCTL_RESCAN:
2439 nvme_queue_scan(ctrl);
2440 return 0;
f3ca80fc
CH		 2441 default:
2442 return -ENOTTY;
2443 }
2444}
2445
2446static const struct file_operations nvme_dev_fops = {
2447 .owner = THIS_MODULE,
2448 .open = nvme_dev_open,
f3ca80fc
CH		 2449 .unlocked_ioctl = nvme_dev_ioctl,
2450 .compat_ioctl = nvme_dev_ioctl,
2451};
2452
2453static ssize_t nvme_sysfs_reset(struct device *dev,
2454 struct device_attribute *attr, const char *buf,
2455 size_t count)
2456{
2457 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2458 int ret;
2459
d86c4d8e 2460 ret = nvme_reset_ctrl_sync(ctrl);
f3ca80fc
CH		 2461 if (ret < 0)
2462 return ret;
2463 return count;
1673f1f0 2464}
f3ca80fc 2465static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
1673f1f0 2466
9ec3bb2f
KB		 2467static ssize_t nvme_sysfs_rescan(struct device *dev,
2468 struct device_attribute *attr, const char *buf,
2469 size_t count)
2470{
2471 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2472
2473 nvme_queue_scan(ctrl);
2474 return count;
2475}
2476static DEVICE_ATTR(rescan_controller, S_IWUSR, NULL, nvme_sysfs_rescan);
2477
5b85b826
CH		 2478static inline struct nvme_ns_head *dev_to_ns_head(struct device *dev)
2479{
2480 struct gendisk *disk = dev_to_disk(dev);
2481
2482 if (disk->fops == &nvme_fops)
2483 return nvme_get_ns_from_dev(dev)->head;
2484 else
2485 return disk->private_data;
2486}
2487
118472ab 2488static ssize_t wwid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2489 char *buf)
118472ab 2490{
5b85b826
CH		 2491 struct nvme_ns_head *head = dev_to_ns_head(dev);
2492 struct nvme_ns_ids *ids = &head->ids;
2493 struct nvme_subsystem *subsys = head->subsys;
ab9e00cc
CH		 2494 int serial_len = sizeof(subsys->serial);
2495 int model_len = sizeof(subsys->model);
118472ab 2496
002fab04
CH		 2497 if (!uuid_is_null(&ids->uuid))
2498 return sprintf(buf, "uuid.%pU\n", &ids->uuid);
6484f5d1 2499
002fab04
CH		 2500 if (memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2501 return sprintf(buf, "eui.%16phN\n", ids->nguid);
118472ab 2502
002fab04
CH		 2503 if (memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2504 return sprintf(buf, "eui.%8phN\n", ids->eui64);
118472ab 2505
ab9e00cc
CH		 2506 while (serial_len > 0 && (subsys->serial[serial_len - 1] == ' ' ||
2507 subsys->serial[serial_len - 1] == '\0'))
118472ab 2508 serial_len--;
ab9e00cc
CH		 2509 while (model_len > 0 && (subsys->model[model_len - 1] == ' ' ||
2510 subsys->model[model_len - 1] == '\0'))
118472ab
KB		 2511 model_len--;
2512
ab9e00cc
CH		 2513 return sprintf(buf, "nvme.%04x-%*phN-%*phN-%08x\n", subsys->vendor_id,
2514 serial_len, subsys->serial, model_len, subsys->model,
5b85b826 2515 head->ns_id);
118472ab 2516}
6096bb34 2517static DEVICE_ATTR_RO(wwid);
118472ab 2518
d934f984 2519static ssize_t nguid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2520 char *buf)
d934f984 2521{
5b85b826 2522 return sprintf(buf, "%pU\n", dev_to_ns_head(dev)->ids.nguid);
d934f984 2523}
6096bb34 2524static DEVICE_ATTR_RO(nguid);
d934f984 2525
2b9b6e86 2526static ssize_t uuid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2527 char *buf)
2b9b6e86 2528{
5b85b826 2529 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
d934f984
JT		 2530
2531 /* For backward compatibility expose the NGUID to userspace if
2532 * we have no UUID set
2533 */
002fab04 2534 if (uuid_is_null(&ids->uuid)) {
d934f984
JT		 2535 printk_ratelimited(KERN_WARNING
2536 "No UUID available providing old NGUID\n");
002fab04 2537 return sprintf(buf, "%pU\n", ids->nguid);
d934f984 2538 }
002fab04 2539 return sprintf(buf, "%pU\n", &ids->uuid);
2b9b6e86 2540}
6096bb34 2541static DEVICE_ATTR_RO(uuid);
2b9b6e86
KB		 2542
2543static ssize_t eui_show(struct device *dev, struct device_attribute *attr,
5b85b826 2544 char *buf)
2b9b6e86 2545{
5b85b826 2546 return sprintf(buf, "%8ph\n", dev_to_ns_head(dev)->ids.eui64);
2b9b6e86 2547}
6096bb34 2548static DEVICE_ATTR_RO(eui);
2b9b6e86
KB		 2549
2550static ssize_t nsid_show(struct device *dev, struct device_attribute *attr,
5b85b826 2551 char *buf)
2b9b6e86 2552{
5b85b826 2553 return sprintf(buf, "%d\n", dev_to_ns_head(dev)->ns_id);
2b9b6e86 2554}
6096bb34 2555static DEVICE_ATTR_RO(nsid);
2b9b6e86 2556
5b85b826 2557static struct attribute *nvme_ns_id_attrs[] = {
118472ab 2558 &dev_attr_wwid.attr,
2b9b6e86 2559 &dev_attr_uuid.attr,
d934f984 2560 &dev_attr_nguid.attr,
2b9b6e86
KB		 2561 &dev_attr_eui.attr,
2562 &dev_attr_nsid.attr,
2563 NULL,
2564};
2565
5b85b826 2566static umode_t nvme_ns_id_attrs_are_visible(struct kobject *kobj,
2b9b6e86
KB		 2567 struct attribute *a, int n)
2568{
2569 struct device *dev = container_of(kobj, struct device, kobj);
5b85b826 2570 struct nvme_ns_ids *ids = &dev_to_ns_head(dev)->ids;
2b9b6e86
KB		 2571
2572 if (a == &dev_attr_uuid.attr) {
a04b5de5 2573 if (uuid_is_null(&ids->uuid) &&
002fab04 2574 !memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
d934f984
JT		 2575 return 0;
2576 }
2577 if (a == &dev_attr_nguid.attr) {
002fab04 2578 if (!memchr_inv(ids->nguid, 0, sizeof(ids->nguid)))
2b9b6e86
KB		 2579 return 0;
2580 }
2581 if (a == &dev_attr_eui.attr) {
002fab04 2582 if (!memchr_inv(ids->eui64, 0, sizeof(ids->eui64)))
2b9b6e86
KB		 2583 return 0;
2584 }
2585 return a->mode;
2586}
2587
5b85b826
CH		 2588const struct attribute_group nvme_ns_id_attr_group = {
2589 .attrs = nvme_ns_id_attrs,
2590 .is_visible = nvme_ns_id_attrs_are_visible,
2b9b6e86
KB		 2591};
2592
931e1c22 2593#define nvme_show_str_function(field) \
779ff756
KB		 2594static ssize_t field##_show(struct device *dev, \
2595 struct device_attribute *attr, char *buf) \
2596{ \
2597 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
ab9e00cc
CH		 2598 return sprintf(buf, "%.*s\n", \
2599 (int)sizeof(ctrl->subsys->field), ctrl->subsys->field); \
779ff756
KB		 2600} \
2601static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2602
ab9e00cc
CH		 2603nvme_show_str_function(model);
2604nvme_show_str_function(serial);
2605nvme_show_str_function(firmware_rev);
2606
931e1c22
ML		 2607#define nvme_show_int_function(field) \
2608static ssize_t field##_show(struct device *dev, \
2609 struct device_attribute *attr, char *buf) \
2610{ \
2611 struct nvme_ctrl *ctrl = dev_get_drvdata(dev); \
2612 return sprintf(buf, "%d\n", ctrl->field); \
2613} \
2614static DEVICE_ATTR(field, S_IRUGO, field##_show, NULL);
2615
931e1c22 2616nvme_show_int_function(cntlid);
779ff756 2617
1a353d85
ML		 2618static ssize_t nvme_sysfs_delete(struct device *dev,
2619 struct device_attribute *attr, const char *buf,
2620 size_t count)
2621{
2622 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2623
2624 if (device_remove_file_self(dev, attr))
c5017e85 2625 nvme_delete_ctrl_sync(ctrl);
1a353d85
ML		 2626 return count;
2627}
2628static DEVICE_ATTR(delete_controller, S_IWUSR, NULL, nvme_sysfs_delete);
2629
2630static ssize_t nvme_sysfs_show_transport(struct device *dev,
2631 struct device_attribute *attr,
2632 char *buf)
2633{
2634 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2635
2636 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->ops->name);
2637}
2638static DEVICE_ATTR(transport, S_IRUGO, nvme_sysfs_show_transport, NULL);
2639
8432bdb2
SG		 2640static ssize_t nvme_sysfs_show_state(struct device *dev,
2641 struct device_attribute *attr,
2642 char *buf)
2643{
2644 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2645 static const char *const state_name[] = {
2646 [NVME_CTRL_NEW] = "new",
2647 [NVME_CTRL_LIVE] = "live",
2648 [NVME_CTRL_RESETTING] = "resetting",
2649 [NVME_CTRL_RECONNECTING]= "reconnecting",
2650 [NVME_CTRL_DELETING] = "deleting",
2651 [NVME_CTRL_DEAD] = "dead",
2652 };
2653
2654 if ((unsigned)ctrl->state < ARRAY_SIZE(state_name) &&
2655 state_name[ctrl->state])
2656 return sprintf(buf, "%s\n", state_name[ctrl->state]);
2657
2658 return sprintf(buf, "unknown state\n");
2659}
2660
2661static DEVICE_ATTR(state, S_IRUGO, nvme_sysfs_show_state, NULL);
2662
1a353d85
ML		 2663static ssize_t nvme_sysfs_show_subsysnqn(struct device *dev,
2664 struct device_attribute *attr,
2665 char *buf)
2666{
2667 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2668
ab9e00cc 2669 return snprintf(buf, PAGE_SIZE, "%s\n", ctrl->subsys->subnqn);
1a353d85
ML		 2670}
2671static DEVICE_ATTR(subsysnqn, S_IRUGO, nvme_sysfs_show_subsysnqn, NULL);
2672
2673static ssize_t nvme_sysfs_show_address(struct device *dev,
2674 struct device_attribute *attr,
2675 char *buf)
2676{
2677 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2678
2679 return ctrl->ops->get_address(ctrl, buf, PAGE_SIZE);
2680}
2681static DEVICE_ATTR(address, S_IRUGO, nvme_sysfs_show_address, NULL);
2682
779ff756
KB		 2683static struct attribute *nvme_dev_attrs[] = {
2684 &dev_attr_reset_controller.attr,
9ec3bb2f 2685 &dev_attr_rescan_controller.attr,
779ff756
KB		 2686 &dev_attr_model.attr,
2687 &dev_attr_serial.attr,
2688 &dev_attr_firmware_rev.attr,
931e1c22 2689 &dev_attr_cntlid.attr,
1a353d85
ML		 2690 &dev_attr_delete_controller.attr,
2691 &dev_attr_transport.attr,
2692 &dev_attr_subsysnqn.attr,
2693 &dev_attr_address.attr,
8432bdb2 2694 &dev_attr_state.attr,
779ff756
KB		 2695 NULL
2696};
2697
1a353d85
ML		 2698static umode_t nvme_dev_attrs_are_visible(struct kobject *kobj,
2699 struct attribute *a, int n)
2700{
2701 struct device *dev = container_of(kobj, struct device, kobj);
2702 struct nvme_ctrl *ctrl = dev_get_drvdata(dev);
2703
49d3d50b
CH		 2704 if (a == &dev_attr_delete_controller.attr && !ctrl->ops->delete_ctrl)
2705 return 0;
2706 if (a == &dev_attr_address.attr && !ctrl->ops->get_address)
2707 return 0;
1a353d85
ML		 2708
2709 return a->mode;
2710}
2711
779ff756 2712static struct attribute_group nvme_dev_attrs_group = {
1a353d85
ML		 2713 .attrs = nvme_dev_attrs,
2714 .is_visible = nvme_dev_attrs_are_visible,
779ff756
KB		 2715};
2716
2717static const struct attribute_group *nvme_dev_attr_groups[] = {
2718 &nvme_dev_attrs_group,
2719 NULL,
2720};
2721
ed754e5d
CH		 2722static struct nvme_ns_head *__nvme_find_ns_head(struct nvme_subsystem *subsys,
2723 unsigned nsid)
2724{
2725 struct nvme_ns_head *h;
2726
2727 lockdep_assert_held(&subsys->lock);
2728
2729 list_for_each_entry(h, &subsys->nsheads, entry) {
2730 if (h->ns_id == nsid && kref_get_unless_zero(&h->ref))
2731 return h;
2732 }
2733
2734 return NULL;
2735}
2736
2737static int __nvme_check_ids(struct nvme_subsystem *subsys,
2738 struct nvme_ns_head *new)
2739{
2740 struct nvme_ns_head *h;
2741
2742 lockdep_assert_held(&subsys->lock);
2743
2744 list_for_each_entry(h, &subsys->nsheads, entry) {
2745 if (nvme_ns_ids_valid(&new->ids) &&
ef7ba593 2746 !list_empty(&h->list) &&
ed754e5d
CH		 2747 nvme_ns_ids_equal(&new->ids, &h->ids))
2748 return -EINVAL;
2749 }
2750
2751 return 0;
2752}
2753
2754static struct nvme_ns_head *nvme_alloc_ns_head(struct nvme_ctrl *ctrl,
2755 unsigned nsid, struct nvme_id_ns *id)
2756{
2757 struct nvme_ns_head *head;
2758 int ret = -ENOMEM;
2759
2760 head = kzalloc(sizeof(*head), GFP_KERNEL);
2761 if (!head)
2762 goto out;
2763 ret = ida_simple_get(&ctrl->subsys->ns_ida, 1, 0, GFP_KERNEL);
2764 if (ret < 0)
2765 goto out_free_head;
2766 head->instance = ret;
2767 INIT_LIST_HEAD(&head->list);
2768 init_srcu_struct(&head->srcu);
2769 head->subsys = ctrl->subsys;
2770 head->ns_id = nsid;
2771 kref_init(&head->ref);
2772
2773 nvme_report_ns_ids(ctrl, nsid, id, &head->ids);
2774
2775 ret = __nvme_check_ids(ctrl->subsys, head);
2776 if (ret) {
2777 dev_err(ctrl->device,
2778 "duplicate IDs for nsid %d\n", nsid);
2779 goto out_cleanup_srcu;
2780 }
2781
32acab31
CH		 2782 ret = nvme_mpath_alloc_disk(ctrl, head);
2783 if (ret)
2784 goto out_cleanup_srcu;
2785
ed754e5d 2786 list_add_tail(&head->entry, &ctrl->subsys->nsheads);
a085d765
JW		 2787
2788 kref_get(&ctrl->subsys->ref);
2789
ed754e5d
CH		 2790 return head;
2791out_cleanup_srcu:
2792 cleanup_srcu_struct(&head->srcu);
2793 ida_simple_remove(&ctrl->subsys->ns_ida, head->instance);
2794out_free_head:
2795 kfree(head);
2796out:
2797 return ERR_PTR(ret);
2798}
2799
2800static int nvme_init_ns_head(struct nvme_ns *ns, unsigned nsid,
2801 struct nvme_id_ns *id, bool *new)
2802{
2803 struct nvme_ctrl *ctrl = ns->ctrl;
2804 bool is_shared = id->nmic & (1 << 0);
2805 struct nvme_ns_head *head = NULL;
2806 int ret = 0;
2807
2808 mutex_lock(&ctrl->subsys->lock);
2809 if (is_shared)
2810 head = __nvme_find_ns_head(ctrl->subsys, nsid);
2811 if (!head) {
2812 head = nvme_alloc_ns_head(ctrl, nsid, id);
2813 if (IS_ERR(head)) {
2814 ret = PTR_ERR(head);
2815 goto out_unlock;
2816 }
2817
2818 *new = true;
2819 } else {
2820 struct nvme_ns_ids ids;
2821
2822 nvme_report_ns_ids(ctrl, nsid, id, &ids);
2823 if (!nvme_ns_ids_equal(&head->ids, &ids)) {
2824 dev_err(ctrl->device,
2825 "IDs don't match for shared namespace %d\n",
2826 nsid);
2827 ret = -EINVAL;
2828 goto out_unlock;
2829 }
2830
2831 *new = false;
2832 }
2833
2834 list_add_tail(&ns->siblings, &head->list);
2835 ns->head = head;
2836
2837out_unlock:
2838 mutex_unlock(&ctrl->subsys->lock);
2839 return ret;
2840}
2841
5bae7f73
CH		 2842static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2843{
2844 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2845 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2846
ed754e5d 2847 return nsa->head->ns_id - nsb->head->ns_id;
5bae7f73
CH		 2848}
2849
32f0c4af 2850static struct nvme_ns *nvme_find_get_ns(struct nvme_ctrl *ctrl, unsigned nsid)
5bae7f73 2851{
32f0c4af 2852 struct nvme_ns *ns, *ret = NULL;
69d3b8ac 2853
32f0c4af 2854 mutex_lock(&ctrl->namespaces_mutex);
5bae7f73 2855 list_for_each_entry(ns, &ctrl->namespaces, list) {
ed754e5d 2856 if (ns->head->ns_id == nsid) {
2dd41228
CH		 2857 if (!kref_get_unless_zero(&ns->kref))
2858 continue;
32f0c4af
KB		 2859 ret = ns;
2860 break;
2861 }
ed754e5d 2862 if (ns->head->ns_id > nsid)
5bae7f73
CH		 2863 break;
2864 }
32f0c4af
KB		 2865 mutex_unlock(&ctrl->namespaces_mutex);
2866 return ret;
5bae7f73
CH		 2867}
2868
f5d11840
JA		 2869static int nvme_setup_streams_ns(struct nvme_ctrl *ctrl, struct nvme_ns *ns)
2870{
2871 struct streams_directive_params s;
2872 int ret;
2873
2874 if (!ctrl->nr_streams)
2875 return 0;
2876
ed754e5d 2877 ret = nvme_get_stream_params(ctrl, &s, ns->head->ns_id);
f5d11840
JA		 2878 if (ret)
2879 return ret;
2880
2881 ns->sws = le32_to_cpu(s.sws);
2882 ns->sgs = le16_to_cpu(s.sgs);
2883
2884 if (ns->sws) {
2885 unsigned int bs = 1 << ns->lba_shift;
2886
2887 blk_queue_io_min(ns->queue, bs * ns->sws);
2888 if (ns->sgs)
2889 blk_queue_io_opt(ns->queue, bs * ns->sws * ns->sgs);
2890 }
2891
2892 return 0;
2893}
2894
5bae7f73
CH		 2895static void nvme_alloc_ns(struct nvme_ctrl *ctrl, unsigned nsid)
2896{
2897 struct nvme_ns *ns;
2898 struct gendisk *disk;
ac81bfa9
MB		 2899 struct nvme_id_ns *id;
2900 char disk_name[DISK_NAME_LEN];
32acab31 2901 int node = dev_to_node(ctrl->dev), flags = GENHD_FL_EXT_DEVT;
ed754e5d 2902 bool new = true;
5bae7f73
CH		 2903
2904 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2905 if (!ns)
2906 return;
2907
2908 ns->queue = blk_mq_init_queue(ctrl->tagset);
2909 if (IS_ERR(ns->queue))
ed754e5d 2910 goto out_free_ns;
5bae7f73
CH		 2911 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2912 ns->queue->queuedata = ns;
2913 ns->ctrl = ctrl;
2914
5bae7f73 2915 kref_init(&ns->kref);
5bae7f73 2916 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
5bae7f73
CH		 2917
2918 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
da35825d 2919 nvme_set_queue_limits(ctrl, ns->queue);
5bae7f73 2920
cdbff4f2
CH		 2921 id = nvme_identify_ns(ctrl, nsid);
2922 if (!id)
ac81bfa9
MB		 2923 goto out_free_queue;
2924
cdbff4f2
CH		 2925 if (id->ncap == 0)
2926 goto out_free_id;
2927
ed754e5d
CH		 2928 if (nvme_init_ns_head(ns, nsid, id, &new))
2929 goto out_free_id;
654b4a4a 2930 nvme_setup_streams_ns(ctrl, ns);
e4b107a7 2931 nvme_set_disk_name(disk_name, ns, ctrl, &flags);
cdbff4f2 2932
608cc4b1
CH		 2933 if ((ctrl->quirks & NVME_QUIRK_LIGHTNVM) && id->vs[0] == 0x1) {
2934 if (nvme_nvm_register(ns, disk_name, node)) {
2935 dev_warn(ctrl->device, "LightNVM init failure\n");
ed754e5d 2936 goto out_unlink_ns;
608cc4b1 2937 }
3dc87dd0 2938 }
ac81bfa9 2939
3dc87dd0
MB		 2940 disk = alloc_disk_node(0, node);
2941 if (!disk)
ed754e5d 2942 goto out_unlink_ns;
ac81bfa9 2943
3dc87dd0
MB		 2944 disk->fops = &nvme_fops;
2945 disk->private_data = ns;
2946 disk->queue = ns->queue;
32acab31 2947 disk->flags = flags;
3dc87dd0
MB		 2948 memcpy(disk->disk_name, disk_name, DISK_NAME_LEN);
2949 ns->disk = disk;
2950
2951 __nvme_revalidate_disk(disk, id);
5bae7f73 2952
32f0c4af
KB		 2953 mutex_lock(&ctrl->namespaces_mutex);
2954 list_add_tail(&ns->list, &ctrl->namespaces);
2955 mutex_unlock(&ctrl->namespaces_mutex);
2956
d22524a4 2957 nvme_get_ctrl(ctrl);
ac81bfa9
MB		 2958
2959 kfree(id);
2960
0d52c756 2961 device_add_disk(ctrl->device, ns->disk);
2b9b6e86 2962 if (sysfs_create_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 2963 &nvme_ns_id_attr_group))
2b9b6e86
KB		 2964 pr_warn("%s: failed to create sysfs group for identification\n",
2965 ns->disk->disk_name);
3dc87dd0
MB		 2966 if (ns->ndev && nvme_nvm_register_sysfs(ns))
2967 pr_warn("%s: failed to register lightnvm sysfs group for identification\n",
2968 ns->disk->disk_name);
32acab31
CH		 2969
2970 if (new)
2971 nvme_mpath_add_disk(ns->head);
5bae7f73 2972 return;
ed754e5d
CH		 2973 out_unlink_ns:
2974 mutex_lock(&ctrl->subsys->lock);
2975 list_del_rcu(&ns->siblings);
2976 mutex_unlock(&ctrl->subsys->lock);
ac81bfa9
MB		 2977 out_free_id:
2978 kfree(id);
5bae7f73
CH		 2979 out_free_queue:
2980 blk_cleanup_queue(ns->queue);
2981 out_free_ns:
2982 kfree(ns);
2983}
2984
2985static void nvme_ns_remove(struct nvme_ns *ns)
2986{
646017a6
KB		 2987 if (test_and_set_bit(NVME_NS_REMOVING, &ns->flags))
2988 return;
69d3b8ac 2989
b0b4e09c 2990 if (ns->disk && ns->disk->flags & GENHD_FL_UP) {
2b9b6e86 2991 sysfs_remove_group(&disk_to_dev(ns->disk)->kobj,
5b85b826 2992 &nvme_ns_id_attr_group);
3dc87dd0
MB		 2993 if (ns->ndev)
2994 nvme_nvm_unregister_sysfs(ns);
5bae7f73 2995 del_gendisk(ns->disk);
5bae7f73 2996 blk_cleanup_queue(ns->queue);
bd9f5d65
ML		 2997 if (blk_get_integrity(ns->disk))
2998 blk_integrity_unregister(ns->disk);
5bae7f73 2999 }
32f0c4af 3000
ed754e5d 3001 mutex_lock(&ns->ctrl->subsys->lock);
32acab31 3002 nvme_mpath_clear_current_path(ns);
9941a862 3003 list_del_rcu(&ns->siblings);
ed754e5d
CH		 3004 mutex_unlock(&ns->ctrl->subsys->lock);
3005
32f0c4af 3006 mutex_lock(&ns->ctrl->namespaces_mutex);
5bae7f73 3007 list_del_init(&ns->list);
32f0c4af
KB		 3008 mutex_unlock(&ns->ctrl->namespaces_mutex);
3009
9941a862 3010 synchronize_srcu(&ns->head->srcu);
479a322f 3011 nvme_mpath_check_last_path(ns);
5bae7f73
CH		 3012 nvme_put_ns(ns);
3013}
3014
540c801c
KB		 3015static void nvme_validate_ns(struct nvme_ctrl *ctrl, unsigned nsid)
3016{
3017 struct nvme_ns *ns;
3018
32f0c4af 3019 ns = nvme_find_get_ns(ctrl, nsid);
540c801c 3020 if (ns) {
b0b4e09c 3021 if (ns->disk && revalidate_disk(ns->disk))
540c801c 3022 nvme_ns_remove(ns);
32f0c4af 3023 nvme_put_ns(ns);
540c801c
KB		 3024 } else
3025 nvme_alloc_ns(ctrl, nsid);
3026}
3027
47b0e50a
SB		 3028static void nvme_remove_invalid_namespaces(struct nvme_ctrl *ctrl,
3029 unsigned nsid)
3030{
3031 struct nvme_ns *ns, *next;
3032
3033 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list) {
ed754e5d 3034 if (ns->head->ns_id > nsid)
47b0e50a
SB		 3035 nvme_ns_remove(ns);
3036 }
3037}
3038
540c801c
KB		 3039static int nvme_scan_ns_list(struct nvme_ctrl *ctrl, unsigned nn)
3040{
3041 struct nvme_ns *ns;
3042 __le32 *ns_list;
3043 unsigned i, j, nsid, prev = 0, num_lists = DIV_ROUND_UP(nn, 1024);
3044 int ret = 0;
3045
3046 ns_list = kzalloc(0x1000, GFP_KERNEL);
3047 if (!ns_list)
3048 return -ENOMEM;
3049
3050 for (i = 0; i < num_lists; i++) {
3051 ret = nvme_identify_ns_list(ctrl, prev, ns_list);
3052 if (ret)
47b0e50a 3053 goto free;
540c801c
KB		 3054
3055 for (j = 0; j < min(nn, 1024U); j++) {
3056 nsid = le32_to_cpu(ns_list[j]);
3057 if (!nsid)
3058 goto out;
3059
3060 nvme_validate_ns(ctrl, nsid);
3061
3062 while (++prev < nsid) {
32f0c4af
KB		 3063 ns = nvme_find_get_ns(ctrl, prev);
3064 if (ns) {
540c801c 3065 nvme_ns_remove(ns);
32f0c4af
KB		 3066 nvme_put_ns(ns);
3067 }
540c801c
KB		 3068 }
3069 }
3070 nn -= j;
3071 }
3072 out:
47b0e50a
SB		 3073 nvme_remove_invalid_namespaces(ctrl, prev);
3074 free:
540c801c
KB		 3075 kfree(ns_list);
3076 return ret;
3077}
3078
5955be21 3079static void nvme_scan_ns_sequential(struct nvme_ctrl *ctrl, unsigned nn)
5bae7f73 3080{
5bae7f73
CH		 3081 unsigned i;
3082
540c801c
KB		 3083 for (i = 1; i <= nn; i++)
3084 nvme_validate_ns(ctrl, i);
3085
47b0e50a 3086 nvme_remove_invalid_namespaces(ctrl, nn);
5bae7f73
CH		 3087}
3088
5955be21 3089static void nvme_scan_work(struct work_struct *work)
5bae7f73 3090{
5955be21
CH		 3091 struct nvme_ctrl *ctrl =
3092 container_of(work, struct nvme_ctrl, scan_work);
5bae7f73 3093 struct nvme_id_ctrl *id;
540c801c 3094 unsigned nn;
5bae7f73 3095
5955be21
CH		 3096 if (ctrl->state != NVME_CTRL_LIVE)
3097 return;
3098
5bae7f73
CH		 3099 if (nvme_identify_ctrl(ctrl, &id))
3100 return;
540c801c
KB		 3101
3102 nn = le32_to_cpu(id->nn);
8ef2074d 3103 if (ctrl->vs >= NVME_VS(1, 1, 0) &&
540c801c
KB		 3104 !(ctrl->quirks & NVME_QUIRK_IDENTIFY_CNS)) {
3105 if (!nvme_scan_ns_list(ctrl, nn))
3106 goto done;
3107 }
5955be21 3108 nvme_scan_ns_sequential(ctrl, nn);
540c801c 3109 done:
32f0c4af 3110 mutex_lock(&ctrl->namespaces_mutex);
540c801c 3111 list_sort(NULL, &ctrl->namespaces, ns_cmp);
69d3b8ac 3112 mutex_unlock(&ctrl->namespaces_mutex);
5bae7f73
CH		 3113 kfree(id);
3114}
5955be21
CH		 3115
3116void nvme_queue_scan(struct nvme_ctrl *ctrl)
3117{
3118 /*
3119 * Do not queue new scan work when a controller is reset during
3120 * removal.
3121 */
3122 if (ctrl->state == NVME_CTRL_LIVE)
c669ccdc 3123 queue_work(nvme_wq, &ctrl->scan_work);
5955be21
CH		 3124}
3125EXPORT_SYMBOL_GPL(nvme_queue_scan);
5bae7f73 3126
32f0c4af
KB		 3127/*
3128 * This function iterates the namespace list unlocked to allow recovery from
3129 * controller failure. It is up to the caller to ensure the namespace list is
3130 * not modified by scan work while this function is executing.
3131 */
5bae7f73
CH		 3132void nvme_remove_namespaces(struct nvme_ctrl *ctrl)
3133{
3134 struct nvme_ns *ns, *next;
3135
0ff9d4e1
KB		 3136 /*
3137 * The dead states indicates the controller was not gracefully
3138 * disconnected. In that case, we won't be able to flush any data while
3139 * removing the namespaces' disks; fail all the queues now to avoid
3140 * potentially having to clean up the failed sync later.
3141 */
3142 if (ctrl->state == NVME_CTRL_DEAD)
3143 nvme_kill_queues(ctrl);
3144
5bae7f73
CH		 3145 list_for_each_entry_safe(ns, next, &ctrl->namespaces, list)
3146 nvme_ns_remove(ns);
3147}
576d55d6 3148EXPORT_SYMBOL_GPL(nvme_remove_namespaces);
5bae7f73 3149
e3d7874d
KB		 3150static void nvme_aen_uevent(struct nvme_ctrl *ctrl)
3151{
3152 char *envp[2] = { NULL, NULL };
3153 u32 aen_result = ctrl->aen_result;
3154
3155 ctrl->aen_result = 0;
3156 if (!aen_result)
3157 return;
3158
3159 envp[0] = kasprintf(GFP_KERNEL, "NVME_AEN=%#08x", aen_result);
3160 if (!envp[0])
3161 return;
3162 kobject_uevent_env(&ctrl->device->kobj, KOBJ_CHANGE, envp);
3163 kfree(envp[0]);
3164}
3165
f866fc42
CH		 3166static void nvme_async_event_work(struct work_struct *work)
3167{
3168 struct nvme_ctrl *ctrl =
3169 container_of(work, struct nvme_ctrl, async_event_work);
3170
e3d7874d 3171 nvme_aen_uevent(ctrl);
ad22c355 3172 ctrl->ops->submit_async_event(ctrl);
f866fc42
CH		 3173}
3174
b6dccf7f
AD		 3175static bool nvme_ctrl_pp_status(struct nvme_ctrl *ctrl)
3176{
3177
3178 u32 csts;
3179
3180 if (ctrl->ops->reg_read32(ctrl, NVME_REG_CSTS, &csts))
3181 return false;
3182
3183 if (csts == ~0)
3184 return false;
3185
3186 return ((ctrl->ctrl_config & NVME_CC_ENABLE) && (csts & NVME_CSTS_PP));
3187}
3188
3189static void nvme_get_fw_slot_info(struct nvme_ctrl *ctrl)
3190{
b6dccf7f
AD		 3191 struct nvme_fw_slot_info_log *log;
3192
3193 log = kmalloc(sizeof(*log), GFP_KERNEL);
3194 if (!log)
3195 return;
3196
c627c487 3197 if (nvme_get_log(ctrl, NVME_LOG_FW_SLOT, log, sizeof(*log)))
b6dccf7f
AD		 3198 dev_warn(ctrl->device,
3199 "Get FW SLOT INFO log error\n");
3200 kfree(log);
3201}
3202
3203static void nvme_fw_act_work(struct work_struct *work)
3204{
3205 struct nvme_ctrl *ctrl = container_of(work,
3206 struct nvme_ctrl, fw_act_work);
3207 unsigned long fw_act_timeout;
3208
3209 if (ctrl->mtfa)
3210 fw_act_timeout = jiffies +
3211 msecs_to_jiffies(ctrl->mtfa * 100);
3212 else
3213 fw_act_timeout = jiffies +
3214 msecs_to_jiffies(admin_timeout * 1000);
3215
3216 nvme_stop_queues(ctrl);
3217 while (nvme_ctrl_pp_status(ctrl)) {
3218 if (time_after(jiffies, fw_act_timeout)) {
3219 dev_warn(ctrl->device,
3220 "Fw activation timeout, reset controller\n");
3221 nvme_reset_ctrl(ctrl);
3222 break;
3223 }
3224 msleep(100);
3225 }
3226
3227 if (ctrl->state != NVME_CTRL_LIVE)
3228 return;
3229
3230 nvme_start_queues(ctrl);
a806c6c8 3231 /* read FW slot information to clear the AER */
b6dccf7f
AD		 3232 nvme_get_fw_slot_info(ctrl);
3233}
3234
7bf58533
CH		 3235void nvme_complete_async_event(struct nvme_ctrl *ctrl, __le16 status,
3236 union nvme_result *res)
f866fc42 3237{
7bf58533 3238 u32 result = le32_to_cpu(res->u32);
f866fc42 3239
ad22c355 3240 if (le16_to_cpu(status) >> 1 != NVME_SC_SUCCESS)
f866fc42
CH		 3241 return;
3242
e3d7874d
KB		 3243 switch (result & 0x7) {
3244 case NVME_AER_ERROR:
3245 case NVME_AER_SMART:
3246 case NVME_AER_CSS:
3247 case NVME_AER_VS:
3248 ctrl->aen_result = result;
7bf58533
CH		 3249 break;
3250 default:
3251 break;
f866fc42
CH		 3252 }
3253
f866fc42
CH		 3254 switch (result & 0xff07) {
3255 case NVME_AER_NOTICE_NS_CHANGED:
3256 dev_info(ctrl->device, "rescanning\n");
3257 nvme_queue_scan(ctrl);
3258 break;
b6dccf7f 3259 case NVME_AER_NOTICE_FW_ACT_STARTING:
1a40d972 3260 queue_work(nvme_wq, &ctrl->fw_act_work);
b6dccf7f 3261 break;
f866fc42
CH		 3262 default:
3263 dev_warn(ctrl->device, "async event result %08x\n", result);
3264 }
c669ccdc 3265 queue_work(nvme_wq, &ctrl->async_event_work);
f866fc42 3266}
f866fc42 3267EXPORT_SYMBOL_GPL(nvme_complete_async_event);
f3ca80fc 3268
d09f2b45 3269void nvme_stop_ctrl(struct nvme_ctrl *ctrl)
576d55d6 3270{
d09f2b45 3271 nvme_stop_keep_alive(ctrl);
f866fc42 3272 flush_work(&ctrl->async_event_work);
5955be21 3273 flush_work(&ctrl->scan_work);
b6dccf7f 3274 cancel_work_sync(&ctrl->fw_act_work);
d09f2b45
SG		 3275}
3276EXPORT_SYMBOL_GPL(nvme_stop_ctrl);
3277
3278void nvme_start_ctrl(struct nvme_ctrl *ctrl)
3279{
3280 if (ctrl->kato)
3281 nvme_start_keep_alive(ctrl);
3282
3283 if (ctrl->queue_count > 1) {
3284 nvme_queue_scan(ctrl);
d99ca609 3285 queue_work(nvme_wq, &ctrl->async_event_work);
d09f2b45
SG		 3286 nvme_start_queues(ctrl);
3287 }
3288}
3289EXPORT_SYMBOL_GPL(nvme_start_ctrl);
5955be21 3290
d09f2b45
SG		 3291void nvme_uninit_ctrl(struct nvme_ctrl *ctrl)
3292{
a6a5149b 3293 cdev_device_del(&ctrl->cdev, ctrl->device);
53029b04 3294}
576d55d6 3295EXPORT_SYMBOL_GPL(nvme_uninit_ctrl);
53029b04 3296
d22524a4 3297static void nvme_free_ctrl(struct device *dev)
53029b04 3298{
d22524a4
CH		 3299 struct nvme_ctrl *ctrl =
3300 container_of(dev, struct nvme_ctrl, ctrl_device);
ab9e00cc 3301 struct nvme_subsystem *subsys = ctrl->subsys;
f3ca80fc 3302
9843f685 3303 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
84fef62d 3304 kfree(ctrl->effects);
f3ca80fc 3305
ab9e00cc
CH		 3306 if (subsys) {
3307 mutex_lock(&subsys->lock);
3308 list_del(&ctrl->subsys_entry);
3309 mutex_unlock(&subsys->lock);
3310 sysfs_remove_link(&subsys->dev.kobj, dev_name(ctrl->device));
3311 }
f3ca80fc
CH		 3312
3313 ctrl->ops->free_ctrl(ctrl);
f3ca80fc 3314
ab9e00cc
CH		 3315 if (subsys)
3316 nvme_put_subsystem(subsys);
f3ca80fc
CH		 3317}
3318
3319/*
3320 * Initialize a NVMe controller structures. This needs to be called during
3321 * earliest initialization so that we have the initialized structured around
3322 * during probing.
3323 */
3324int nvme_init_ctrl(struct nvme_ctrl *ctrl, struct device *dev,
3325 const struct nvme_ctrl_ops *ops, unsigned long quirks)
3326{
3327 int ret;
3328
bb8d261e
CH		 3329 ctrl->state = NVME_CTRL_NEW;
3330 spin_lock_init(&ctrl->lock);
f3ca80fc 3331 INIT_LIST_HEAD(&ctrl->namespaces);
69d3b8ac 3332 mutex_init(&ctrl->namespaces_mutex);
f3ca80fc
CH		 3333 ctrl->dev = dev;
3334 ctrl->ops = ops;
3335 ctrl->quirks = quirks;
5955be21 3336 INIT_WORK(&ctrl->scan_work, nvme_scan_work);
f866fc42 3337 INIT_WORK(&ctrl->async_event_work, nvme_async_event_work);
b6dccf7f 3338 INIT_WORK(&ctrl->fw_act_work, nvme_fw_act_work);
c5017e85 3339 INIT_WORK(&ctrl->delete_work, nvme_delete_ctrl_work);
f3ca80fc 3340
9843f685
CH		 3341 ret = ida_simple_get(&nvme_instance_ida, 0, 0, GFP_KERNEL);
3342 if (ret < 0)
f3ca80fc 3343 goto out;
9843f685 3344 ctrl->instance = ret;
f3ca80fc 3345
d22524a4
CH		 3346 device_initialize(&ctrl->ctrl_device);
3347 ctrl->device = &ctrl->ctrl_device;
a6a5149b 3348 ctrl->device->devt = MKDEV(MAJOR(nvme_chr_devt), ctrl->instance);
d22524a4
CH		 3349 ctrl->device->class = nvme_class;
3350 ctrl->device->parent = ctrl->dev;
3351 ctrl->device->groups = nvme_dev_attr_groups;
3352 ctrl->device->release = nvme_free_ctrl;
3353 dev_set_drvdata(ctrl->device, ctrl);
3354 ret = dev_set_name(ctrl->device, "nvme%d", ctrl->instance);
3355 if (ret)
f3ca80fc 3356 goto out_release_instance;
f3ca80fc 3357
a6a5149b
CH		 3358 cdev_init(&ctrl->cdev, &nvme_dev_fops);
3359 ctrl->cdev.owner = ops->module;
3360 ret = cdev_device_add(&ctrl->cdev, ctrl->device);
d22524a4
CH		 3361 if (ret)
3362 goto out_free_name;
f3ca80fc 3363
c5552fde
AL		 3364 /*
3365 * Initialize latency tolerance controls. The sysfs files won't
3366 * be visible to userspace unless the device actually supports APST.
3367 */
3368 ctrl->device->power.set_latency_tolerance = nvme_set_latency_tolerance;
3369 dev_pm_qos_update_user_latency_tolerance(ctrl->device,
3370 min(default_ps_max_latency_us, (unsigned long)S32_MAX));
3371
f3ca80fc 3372 return 0;
d22524a4
CH		 3373out_free_name:
3374 kfree_const(dev->kobj.name);
f3ca80fc 3375out_release_instance:
9843f685 3376 ida_simple_remove(&nvme_instance_ida, ctrl->instance);
f3ca80fc
CH		 3377out:
3378 return ret;
3379}
576d55d6 3380EXPORT_SYMBOL_GPL(nvme_init_ctrl);
f3ca80fc 3381
69d9a99c
KB		 3382/**
3383 * nvme_kill_queues(): Ends all namespace queues
3384 * @ctrl: the dead controller that needs to end
3385 *
3386 * Call this function when the driver determines it is unable to get the
3387 * controller in a state capable of servicing IO.
3388 */
3389void nvme_kill_queues(struct nvme_ctrl *ctrl)
3390{
3391 struct nvme_ns *ns;
3392
32f0c4af 3393 mutex_lock(&ctrl->namespaces_mutex);
82654b6b 3394
443bd90f 3395 /* Forcibly unquiesce queues to avoid blocking dispatch */
7dd1ab16
SB		 3396 if (ctrl->admin_q)
3397 blk_mq_unquiesce_queue(ctrl->admin_q);
443bd90f 3398
32f0c4af 3399 list_for_each_entry(ns, &ctrl->namespaces, list) {
69d9a99c
KB		 3400 /*
3401 * Revalidating a dead namespace sets capacity to 0. This will
3402 * end buffered writers dirtying pages that can't be synced.
3403 */
f33447b9
KB		 3404 if (!ns->disk || test_and_set_bit(NVME_NS_DEAD, &ns->flags))
3405 continue;
3406 revalidate_disk(ns->disk);
69d9a99c 3407 blk_set_queue_dying(ns->queue);
806f026f 3408
443bd90f
ML		 3409 /* Forcibly unquiesce queues to avoid blocking dispatch */
3410 blk_mq_unquiesce_queue(ns->queue);
69d9a99c 3411 }
32f0c4af 3412 mutex_unlock(&ctrl->namespaces_mutex);
69d9a99c 3413}
237045fc 3414EXPORT_SYMBOL_GPL(nvme_kill_queues);
69d9a99c 3415
302ad8cc
KB		 3416void nvme_unfreeze(struct nvme_ctrl *ctrl)
3417{
3418 struct nvme_ns *ns;
3419
3420 mutex_lock(&ctrl->namespaces_mutex);
3421 list_for_each_entry(ns, &ctrl->namespaces, list)
3422 blk_mq_unfreeze_queue(ns->queue);
3423 mutex_unlock(&ctrl->namespaces_mutex);
3424}
3425EXPORT_SYMBOL_GPL(nvme_unfreeze);
3426
3427void nvme_wait_freeze_timeout(struct nvme_ctrl *ctrl, long timeout)
3428{
3429 struct nvme_ns *ns;
3430
3431 mutex_lock(&ctrl->namespaces_mutex);
3432 list_for_each_entry(ns, &ctrl->namespaces, list) {
3433 timeout = blk_mq_freeze_queue_wait_timeout(ns->queue, timeout);
3434 if (timeout <= 0)
3435 break;
3436 }
3437 mutex_unlock(&ctrl->namespaces_mutex);
3438}
3439EXPORT_SYMBOL_GPL(nvme_wait_freeze_timeout);
3440
3441void nvme_wait_freeze(struct nvme_ctrl *ctrl)
3442{
3443 struct nvme_ns *ns;
3444
3445 mutex_lock(&ctrl->namespaces_mutex);
3446 list_for_each_entry(ns, &ctrl->namespaces, list)
3447 blk_mq_freeze_queue_wait(ns->queue);
3448 mutex_unlock(&ctrl->namespaces_mutex);
3449}
3450EXPORT_SYMBOL_GPL(nvme_wait_freeze);
3451
3452void nvme_start_freeze(struct nvme_ctrl *ctrl)
3453{
3454 struct nvme_ns *ns;
3455
3456 mutex_lock(&ctrl->namespaces_mutex);
3457 list_for_each_entry(ns, &ctrl->namespaces, list)
1671d522 3458 blk_freeze_queue_start(ns->queue);
302ad8cc
KB		 3459 mutex_unlock(&ctrl->namespaces_mutex);
3460}
3461EXPORT_SYMBOL_GPL(nvme_start_freeze);
3462
25646264 3463void nvme_stop_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3464{
3465 struct nvme_ns *ns;
3466
32f0c4af 3467 mutex_lock(&ctrl->namespaces_mutex);
a6eaa884 3468 list_for_each_entry(ns, &ctrl->namespaces, list)
3174dd33 3469 blk_mq_quiesce_queue(ns->queue);
32f0c4af 3470 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 3471}
576d55d6 3472EXPORT_SYMBOL_GPL(nvme_stop_queues);
363c9aac 3473
25646264 3474void nvme_start_queues(struct nvme_ctrl *ctrl)
363c9aac
SG		 3475{
3476 struct nvme_ns *ns;
3477
32f0c4af 3478 mutex_lock(&ctrl->namespaces_mutex);
8d7b8faf 3479 list_for_each_entry(ns, &ctrl->namespaces, list)
f660174e 3480 blk_mq_unquiesce_queue(ns->queue);
32f0c4af 3481 mutex_unlock(&ctrl->namespaces_mutex);
363c9aac 3482}
576d55d6 3483EXPORT_SYMBOL_GPL(nvme_start_queues);
363c9aac 3484
31b84460
SG		 3485int nvme_reinit_tagset(struct nvme_ctrl *ctrl, struct blk_mq_tag_set *set)
3486{
3487 if (!ctrl->ops->reinit_request)
3488 return 0;
3489
3490 return blk_mq_tagset_iter(set, set->driver_data,
3491 ctrl->ops->reinit_request);
3492}
3493EXPORT_SYMBOL_GPL(nvme_reinit_tagset);
3494
80bc535d
KB		 3495void nvme_sync_queues(struct nvme_ctrl *ctrl)
3496{
3497 struct nvme_ns *ns;
3498
3499 mutex_lock(&ctrl->namespaces_mutex);
3500 list_for_each_entry(ns, &ctrl->namespaces, list)
3501 blk_sync_queue(ns->queue);
3502 mutex_unlock(&ctrl->namespaces_mutex);
3503}
3504EXPORT_SYMBOL_GPL(nvme_sync_queues);
3505
5bae7f73
CH		 3506int __init nvme_core_init(void)
3507{
3508 int result;
3509
9a6327d2
SG		 3510 nvme_wq = alloc_workqueue("nvme-wq",
3511 WQ_UNBOUND | WQ_MEM_RECLAIM | WQ_SYSFS, 0);
3512 if (!nvme_wq)
3513 return -ENOMEM;
3514
a6a5149b 3515 result = alloc_chrdev_region(&nvme_chr_devt, 0, NVME_MINORS, "nvme");
f3ca80fc 3516 if (result < 0)
9a6327d2 3517 goto destroy_wq;
f3ca80fc
CH		 3518
3519 nvme_class = class_create(THIS_MODULE, "nvme");
3520 if (IS_ERR(nvme_class)) {
3521 result = PTR_ERR(nvme_class);
3522 goto unregister_chrdev;
3523 }
3524
ab9e00cc
CH		 3525 nvme_subsys_class = class_create(THIS_MODULE, "nvme-subsystem");
3526 if (IS_ERR(nvme_subsys_class)) {
3527 result = PTR_ERR(nvme_subsys_class);
3528 goto destroy_class;
3529 }
5bae7f73 3530 return 0;
f3ca80fc 3531
ab9e00cc
CH		 3532destroy_class:
3533 class_destroy(nvme_class);
9a6327d2 3534unregister_chrdev:
a6a5149b 3535 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
9a6327d2
SG		 3536destroy_wq:
3537 destroy_workqueue(nvme_wq);
f3ca80fc 3538 return result;
5bae7f73
CH		 3539}
3540
3541void nvme_core_exit(void)
3542{
ab9e00cc
CH		 3543 ida_destroy(&nvme_subsystems_ida);
3544 class_destroy(nvme_subsys_class);
f3ca80fc 3545 class_destroy(nvme_class);
a6a5149b 3546 unregister_chrdev_region(nvme_chr_devt, NVME_MINORS);
9a6327d2 3547 destroy_workqueue(nvme_wq);
5bae7f73 3548}
576d55d6
ML		 3549
3550MODULE_LICENSE("GPL");
3551MODULE_VERSION("1.0");
3552module_init(nvme_core_init);
3553module_exit(nvme_core_exit);
ubuntu-bionic-kernel mirror