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scsi: qla2xxx: Convert timers to use timer_setup()
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_init.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
73208dfd 8#include "qla_gbl.h"
1da177e4
LT		 9
10#include <linux/delay.h>
5a0e3ad6 11#include <linux/slab.h>
0107109e 12#include <linux/vmalloc.h>
1da177e4
LT		 13
14#include "qla_devtbl.h"
15
4e08df3f
DM		 16#ifdef CONFIG_SPARC
17#include <asm/prom.h>
4e08df3f
DM		 18#endif
19
2d70c103
NB		 20#include <target/target_core_base.h>
21#include "qla_target.h"
22
1da177e4
LT		 23/*
24* QLogic ISP2x00 Hardware Support Function Prototypes.
25*/
1da177e4 26static int qla2x00_isp_firmware(scsi_qla_host_t *);
1da177e4 27static int qla2x00_setup_chip(scsi_qla_host_t *);
1da177e4
LT		 28static int qla2x00_fw_ready(scsi_qla_host_t *);
29static int qla2x00_configure_hba(scsi_qla_host_t *);
1da177e4
LT		 30static int qla2x00_configure_loop(scsi_qla_host_t *);
31static int qla2x00_configure_local_loop(scsi_qla_host_t *);
1da177e4 32static int qla2x00_configure_fabric(scsi_qla_host_t *);
726b8548 33static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
1da177e4 34static int qla2x00_restart_isp(scsi_qla_host_t *);
1da177e4 35
4d4df193
HK		 36static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
37static int qla84xx_init_chip(scsi_qla_host_t *);
73208dfd 38static int qla25xx_init_queues(struct qla_hw_data *);
a5d42f4c 39static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
726b8548
QT		 40static void qla24xx_handle_plogi_done_event(struct scsi_qla_host *,
41 struct event_arg *);
a5d42f4c
DG		 42static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
43 struct event_arg *);
4d4df193 44
ac280b67
AV		 45/* SRB Extensions ---------------------------------------------------------- */
46
9ba56b95 47void
8e5f4ba0 48qla2x00_sp_timeout(struct timer_list *t)
ac280b67 49{
8e5f4ba0 50 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
4916392b 51 struct srb_iocb *iocb;
25ff6af1 52 scsi_qla_host_t *vha = sp->vha;
ac280b67
AV		 53 struct req_que *req;
54 unsigned long flags;
55
25ff6af1
JC		 56 spin_lock_irqsave(&vha->hw->hardware_lock, flags);
57 req = vha->hw->req_q_map[0];
ac280b67 58 req->outstanding_cmds[sp->handle] = NULL;
9ba56b95 59 iocb = &sp->u.iocb_cmd;
4916392b 60 iocb->timeout(sp);
25ff6af1
JC		 61 sp->free(sp);
62 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
ac280b67
AV		 63}
64
9ba56b95 65void
25ff6af1 66qla2x00_sp_free(void *ptr)
ac280b67 67{
25ff6af1 68 srb_t *sp = ptr;
9ba56b95 69 struct srb_iocb *iocb = &sp->u.iocb_cmd;
ac280b67 70
4d97cc53 71 del_timer(&iocb->timer);
25ff6af1 72 qla2x00_rel_sp(sp);
ac280b67
AV		 73}
74
ac280b67
AV		 75/* Asynchronous Login/Logout Routines -------------------------------------- */
76
a9b6f722 77unsigned long
5b91490e
AV		 78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83 /* Firmware should use switch negotiated r_a_tov for timeout. */
84 tmo = ha->r_a_tov / 10 * 2;
8ae6d9c7
GM		 85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
5b91490e
AV		 88 /*
89 * Except for earlier ISPs where the timeout is seeded from the
90 * initialization control block.
91 */
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
ac280b67 96
726b8548 97void
9ba56b95 98qla2x00_async_iocb_timeout(void *data)
ac280b67 99{
25ff6af1 100 srb_t *sp = data;
ac280b67 101 fc_port_t *fcport = sp->fcport;
726b8548
QT		 102 struct srb_iocb *lio = &sp->u.iocb_cmd;
103 struct event_arg ea;
ac280b67 104
7c3df132 105 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
726b8548
QT		 106 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
107 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
ac280b67 108
5ff1d584 109 fcport->flags &= ~FCF_ASYNC_SENT;
726b8548
QT		 110
111 switch (sp->type) {
112 case SRB_LOGIN_CMD:
6ac52608
AV		 113 /* Retry as needed. */
114 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
115 lio->u.logio.data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
116 QLA_LOGIO_LOGIN_RETRIED : 0;
726b8548
QT		 117 memset(&ea, 0, sizeof(ea));
118 ea.event = FCME_PLOGI_DONE;
119 ea.fcport = sp->fcport;
120 ea.data[0] = lio->u.logio.data[0];
121 ea.data[1] = lio->u.logio.data[1];
122 ea.sp = sp;
123 qla24xx_handle_plogi_done_event(fcport->vha, &ea);
124 break;
125 case SRB_LOGOUT_CMD:
a6ca8878 126 qlt_logo_completion_handler(fcport, QLA_FUNCTION_TIMEOUT);
726b8548
QT		 127 break;
128 case SRB_CT_PTHRU_CMD:
129 case SRB_MB_IOCB:
130 case SRB_NACK_PLOGI:
131 case SRB_NACK_PRLI:
132 case SRB_NACK_LOGO:
25ff6af1 133 sp->done(sp, QLA_FUNCTION_TIMEOUT);
726b8548 134 break;
6ac52608 135 }
ac280b67
AV		 136}
137
99b0bec7 138static void
25ff6af1 139qla2x00_async_login_sp_done(void *ptr, int res)
99b0bec7 140{
25ff6af1
JC		 141 srb_t *sp = ptr;
142 struct scsi_qla_host *vha = sp->vha;
9ba56b95 143 struct srb_iocb *lio = &sp->u.iocb_cmd;
726b8548 144 struct event_arg ea;
9ba56b95 145
83548fe2 146 ql_dbg(ql_dbg_disc, vha, 0x20dd,
25ff6af1 147 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
726b8548
QT		 148
149 sp->fcport->flags &= ~FCF_ASYNC_SENT;
150 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
151 memset(&ea, 0, sizeof(ea));
152 ea.event = FCME_PLOGI_DONE;
153 ea.fcport = sp->fcport;
154 ea.data[0] = lio->u.logio.data[0];
155 ea.data[1] = lio->u.logio.data[1];
156 ea.iop[0] = lio->u.logio.iop[0];
157 ea.iop[1] = lio->u.logio.iop[1];
158 ea.sp = sp;
159 qla2x00_fcport_event_handler(vha, &ea);
160 }
9ba56b95 161
25ff6af1 162 sp->free(sp);
99b0bec7
AV		 163}
164
ac280b67
AV		 165int
166qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
167 uint16_t *data)
168{
ac280b67 169 srb_t *sp;
4916392b 170 struct srb_iocb *lio;
726b8548
QT		 171 int rval = QLA_FUNCTION_FAILED;
172
173 if (!vha->flags.online)
174 goto done;
175
176 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
177 (fcport->fw_login_state == DSC_LS_PLOGI_COMP) ||
178 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
179 goto done;
ac280b67 180
9ba56b95 181 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 182 if (!sp)
183 goto done;
184
726b8548
QT		 185 fcport->flags |= FCF_ASYNC_SENT;
186 fcport->logout_completed = 0;
187
9ba56b95
GM		 188 sp->type = SRB_LOGIN_CMD;
189 sp->name = "login";
190 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
191
192 lio = &sp->u.iocb_cmd;
3822263e 193 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 194 sp->done = qla2x00_async_login_sp_done;
4916392b 195 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
a5d42f4c
DG		 196
197 if (fcport->fc4f_nvme)
198 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
199
ac280b67 200 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 201 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
ac280b67 202 rval = qla2x00_start_sp(sp);
080c9517
CD		 203 if (rval != QLA_SUCCESS) {
204 fcport->flags &= ~FCF_ASYNC_SENT;
205 fcport->flags |= FCF_LOGIN_NEEDED;
206 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
ac280b67 207 goto done_free_sp;
080c9517 208 }
ac280b67 209
7c3df132 210 ql_dbg(ql_dbg_disc, vha, 0x2072,
726b8548
QT		 211 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x "
212 "retries=%d.\n", fcport->port_name, sp->handle, fcport->loop_id,
cfb0919c
CD		 213 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
214 fcport->login_retry);
ac280b67
AV		 215 return rval;
216
217done_free_sp:
25ff6af1 218 sp->free(sp);
ac280b67 219done:
726b8548 220 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 221 return rval;
222}
223
99b0bec7 224static void
25ff6af1 225qla2x00_async_logout_sp_done(void *ptr, int res)
99b0bec7 226{
25ff6af1 227 srb_t *sp = ptr;
9ba56b95 228 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95 229
726b8548 230 sp->fcport->flags &= ~FCF_ASYNC_SENT;
25ff6af1
JC		 231 if (!test_bit(UNLOADING, &sp->vha->dpc_flags))
232 qla2x00_post_async_logout_done_work(sp->vha, sp->fcport,
9ba56b95 233 lio->u.logio.data);
25ff6af1 234 sp->free(sp);
99b0bec7
AV		 235}
236
ac280b67
AV		 237int
238qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
239{
ac280b67 240 srb_t *sp;
4916392b 241 struct srb_iocb *lio;
ac280b67
AV		 242 int rval;
243
244 rval = QLA_FUNCTION_FAILED;
726b8548 245 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 246 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
ac280b67
AV		 247 if (!sp)
248 goto done;
249
9ba56b95
GM		 250 sp->type = SRB_LOGOUT_CMD;
251 sp->name = "logout";
252 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
253
254 lio = &sp->u.iocb_cmd;
3822263e 255 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 256 sp->done = qla2x00_async_logout_sp_done;
ac280b67
AV		 257 rval = qla2x00_start_sp(sp);
258 if (rval != QLA_SUCCESS)
259 goto done_free_sp;
260
7c3df132 261 ql_dbg(ql_dbg_disc, vha, 0x2070,
726b8548 262 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
cfb0919c 263 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
726b8548
QT		 264 fcport->d_id.b.area, fcport->d_id.b.al_pa,
265 fcport->port_name);
ac280b67
AV		 266 return rval;
267
268done_free_sp:
25ff6af1 269 sp->free(sp);
ac280b67 270done:
726b8548 271 fcport->flags &= ~FCF_ASYNC_SENT;
ac280b67
AV		 272 return rval;
273}
274
5ff1d584 275static void
25ff6af1 276qla2x00_async_adisc_sp_done(void *ptr, int res)
5ff1d584 277{
25ff6af1
JC		 278 srb_t *sp = ptr;
279 struct scsi_qla_host *vha = sp->vha;
9ba56b95 280 struct srb_iocb *lio = &sp->u.iocb_cmd;
9ba56b95
GM		 281
282 if (!test_bit(UNLOADING, &vha->dpc_flags))
25ff6af1 283 qla2x00_post_async_adisc_done_work(sp->vha, sp->fcport,
9ba56b95 284 lio->u.logio.data);
25ff6af1 285 sp->free(sp);
5ff1d584
AV		 286}
287
288int
289qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
290 uint16_t *data)
291{
5ff1d584 292 srb_t *sp;
4916392b 293 struct srb_iocb *lio;
5ff1d584
AV		 294 int rval;
295
296 rval = QLA_FUNCTION_FAILED;
726b8548 297 fcport->flags |= FCF_ASYNC_SENT;
9ba56b95 298 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
5ff1d584
AV		 299 if (!sp)
300 goto done;
301
9ba56b95
GM		 302 sp->type = SRB_ADISC_CMD;
303 sp->name = "adisc";
304 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
305
306 lio = &sp->u.iocb_cmd;
3822263e 307 lio->timeout = qla2x00_async_iocb_timeout;
9ba56b95 308 sp->done = qla2x00_async_adisc_sp_done;
5ff1d584 309 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
4916392b 310 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
5ff1d584
AV		 311 rval = qla2x00_start_sp(sp);
312 if (rval != QLA_SUCCESS)
313 goto done_free_sp;
314
7c3df132 315 ql_dbg(ql_dbg_disc, vha, 0x206f,
cfb0919c
CD		 316 "Async-adisc - hdl=%x loopid=%x portid=%02x%02x%02x.\n",
317 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
318 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5ff1d584
AV		 319 return rval;
320
321done_free_sp:
25ff6af1 322 sp->free(sp);
5ff1d584 323done:
726b8548
QT		 324 fcport->flags &= ~FCF_ASYNC_SENT;
325 return rval;
326}
327
328static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
329 struct event_arg *ea)
330{
331 fc_port_t *fcport, *conflict_fcport;
332 struct get_name_list_extended *e;
333 u16 i, n, found = 0, loop_id;
334 port_id_t id;
335 u64 wwn;
a5d42f4c 336 u8 opt = 0, current_login_state;
726b8548
QT		 337
338 fcport = ea->fcport;
339
340 if (ea->rc) { /* rval */
341 if (fcport->login_retry == 0) {
342 fcport->login_retry = vha->hw->login_retry_count;
83548fe2
QT		 343 ql_dbg(ql_dbg_disc, vha, 0x20de,
344 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
345 fcport->port_name, fcport->login_retry);
726b8548
QT		 346 }
347 return;
348 }
349
350 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 351 ql_dbg(ql_dbg_disc, vha, 0x20df,
726b8548
QT		 352 "%s %8phC rscn gen changed rscn %d|%d \n",
353 __func__, fcport->port_name,
354 fcport->last_rscn_gen, fcport->rscn_gen);
355 qla24xx_post_gidpn_work(vha, fcport);
356 return;
357 } else if (fcport->last_login_gen != fcport->login_gen) {
83548fe2
QT		 358 ql_dbg(ql_dbg_disc, vha, 0x20e0,
359 "%s %8phC login gen changed login %d|%d\n",
360 __func__, fcport->port_name,
361 fcport->last_login_gen, fcport->login_gen);
726b8548
QT		 362 return;
363 }
364
365 n = ea->data[0] / sizeof(struct get_name_list_extended);
366
83548fe2 367 ql_dbg(ql_dbg_disc, vha, 0x20e1,
726b8548
QT		 368 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
369 __func__, __LINE__, fcport->port_name, n,
370 fcport->d_id.b.domain, fcport->d_id.b.area,
371 fcport->d_id.b.al_pa, fcport->loop_id);
372
373 for (i = 0; i < n; i++) {
374 e = &vha->gnl.l[i];
375 wwn = wwn_to_u64(e->port_name);
376
377 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
378 continue;
379
380 found = 1;
381 id.b.domain = e->port_id[2];
382 id.b.area = e->port_id[1];
383 id.b.al_pa = e->port_id[0];
384 id.b.rsvd_1 = 0;
385
386 loop_id = le16_to_cpu(e->nport_handle);
387 loop_id = (loop_id & 0x7fff);
388
83548fe2
QT		 389 ql_dbg(ql_dbg_disc, vha, 0x20e2,
390 "%s found %8phC CLS [%d|%d] ID[%02x%02x%02x|%02x%02x%02x] lid[%d|%d]\n",
391 __func__, fcport->port_name,
392 e->current_login_state, fcport->fw_login_state,
393 id.b.domain, id.b.area, id.b.al_pa,
394 fcport->d_id.b.domain, fcport->d_id.b.area,
395 fcport->d_id.b.al_pa, loop_id, fcport->loop_id);
726b8548
QT		 396
397 if ((id.b24 != fcport->d_id.b24) ||
398 ((fcport->loop_id != FC_NO_LOOP_ID) &&
399 (fcport->loop_id != loop_id))) {
83548fe2
QT		 400 ql_dbg(ql_dbg_disc, vha, 0x20e3,
401 "%s %d %8phC post del sess\n",
402 __func__, __LINE__, fcport->port_name);
726b8548
QT		 403 qlt_schedule_sess_for_deletion(fcport, 1);
404 return;
405 }
406
407 fcport->loop_id = loop_id;
408
409 wwn = wwn_to_u64(fcport->port_name);
410 qlt_find_sess_invalidate_other(vha, wwn,
411 id, loop_id, &conflict_fcport);
412
413 if (conflict_fcport) {
414 /*
415 * Another share fcport share the same loop_id &
416 * nport id. Conflict fcport needs to finish
417 * cleanup before this fcport can proceed to login.
418 */
419 conflict_fcport->conflict = fcport;
420 fcport->login_pause = 1;
421 }
422
a5d42f4c
DG		 423 if (fcport->fc4f_nvme)
424 current_login_state = e->current_login_state >> 4;
425 else
426 current_login_state = e->current_login_state & 0xf;
427
428 switch (current_login_state) {
726b8548 429 case DSC_LS_PRLI_COMP:
83548fe2
QT		 430 ql_dbg(ql_dbg_disc, vha, 0x20e4,
431 "%s %d %8phC post gpdb\n",
432 __func__, __LINE__, fcport->port_name);
726b8548
QT		 433 opt = PDO_FORCE_ADISC;
434 qla24xx_post_gpdb_work(vha, fcport, opt);
435 break;
726b8548
QT		 436 case DSC_LS_PORT_UNAVAIL:
437 default:
438 if (fcport->loop_id == FC_NO_LOOP_ID) {
439 qla2x00_find_new_loop_id(vha, fcport);
440 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
441 }
83548fe2
QT		 442 ql_dbg(ql_dbg_disc, vha, 0x20e5,
443 "%s %d %8phC\n",
444 __func__, __LINE__, fcport->port_name);
726b8548
QT		 445 qla24xx_fcport_handle_login(vha, fcport);
446 break;
447 }
448 }
449
450 if (!found) {
451 /* fw has no record of this port */
452 if (fcport->loop_id == FC_NO_LOOP_ID) {
453 qla2x00_find_new_loop_id(vha, fcport);
454 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
455 } else {
456 for (i = 0; i < n; i++) {
457 e = &vha->gnl.l[i];
458 id.b.domain = e->port_id[0];
459 id.b.area = e->port_id[1];
460 id.b.al_pa = e->port_id[2];
461 id.b.rsvd_1 = 0;
462 loop_id = le16_to_cpu(e->nport_handle);
463
464 if (fcport->d_id.b24 == id.b24) {
465 conflict_fcport =
466 qla2x00_find_fcport_by_wwpn(vha,
467 e->port_name, 0);
468
83548fe2 469 ql_dbg(ql_dbg_disc, vha, 0x20e6,
726b8548
QT		 470 "%s %d %8phC post del sess\n",
471 __func__, __LINE__,
472 conflict_fcport->port_name);
473 qlt_schedule_sess_for_deletion
474 (conflict_fcport, 1);
475 }
476
477 if (fcport->loop_id == loop_id) {
478 /* FW already picked this loop id for another fcport */
479 qla2x00_find_new_loop_id(vha, fcport);
480 }
481 }
482 }
483 qla24xx_fcport_handle_login(vha, fcport);
484 }
485} /* gnl_event */
486
487static void
25ff6af1 488qla24xx_async_gnl_sp_done(void *s, int res)
726b8548 489{
25ff6af1
JC		 490 struct srb *sp = s;
491 struct scsi_qla_host *vha = sp->vha;
726b8548
QT		 492 unsigned long flags;
493 struct fc_port *fcport = NULL, *tf;
494 u16 i, n = 0, loop_id;
495 struct event_arg ea;
496 struct get_name_list_extended *e;
497 u64 wwn;
498 struct list_head h;
499
83548fe2 500 ql_dbg(ql_dbg_disc, vha, 0x20e7,
726b8548
QT		 501 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
502 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
503 sp->u.iocb_cmd.u.mbx.in_mb[2]);
504
505 memset(&ea, 0, sizeof(ea));
506 ea.sp = sp;
507 ea.rc = res;
508 ea.event = FCME_GNL_DONE;
509
510 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
511 sizeof(struct get_name_list_extended)) {
512 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
513 sizeof(struct get_name_list_extended);
514 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */
515 }
516
517 for (i = 0; i < n; i++) {
518 e = &vha->gnl.l[i];
519 loop_id = le16_to_cpu(e->nport_handle);
520 /* mask out reserve bit */
521 loop_id = (loop_id & 0x7fff);
522 set_bit(loop_id, vha->hw->loop_id_map);
523 wwn = wwn_to_u64(e->port_name);
524
83548fe2 525 ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x20e8,
726b8548
QT		 526 "%s %8phC %02x:%02x:%02x state %d/%d lid %x \n",
527 __func__, (void *)&wwn, e->port_id[2], e->port_id[1],
528 e->port_id[0], e->current_login_state, e->last_login_state,
529 (loop_id & 0x7fff));
530 }
531
532 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
533 vha->gnl.sent = 0;
534
535 INIT_LIST_HEAD(&h);
536 fcport = tf = NULL;
537 if (!list_empty(&vha->gnl.fcports))
538 list_splice_init(&vha->gnl.fcports, &h);
539
540 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
541 list_del_init(&fcport->gnl_entry);
542 fcport->flags &= ~FCF_ASYNC_SENT;
543 ea.fcport = fcport;
544
545 qla2x00_fcport_event_handler(vha, &ea);
546 }
547
548 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
549
25ff6af1 550 sp->free(sp);
726b8548
QT		 551}
552
553int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
554{
555 srb_t *sp;
556 struct srb_iocb *mbx;
557 int rval = QLA_FUNCTION_FAILED;
558 unsigned long flags;
559 u16 *mb;
560
561 if (!vha->flags.online)
562 goto done;
563
83548fe2 564 ql_dbg(ql_dbg_disc, vha, 0x20d9,
726b8548
QT		 565 "Async-gnlist WWPN %8phC \n", fcport->port_name);
566
567 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
568 fcport->flags |= FCF_ASYNC_SENT;
569 fcport->disc_state = DSC_GNL;
570 fcport->last_rscn_gen = fcport->rscn_gen;
571 fcport->last_login_gen = fcport->login_gen;
572
573 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
574 if (vha->gnl.sent) {
575 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
576 rval = QLA_SUCCESS;
577 goto done;
578 }
579 vha->gnl.sent = 1;
580 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
581
582 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
583 if (!sp)
584 goto done;
585 sp->type = SRB_MB_IOCB;
586 sp->name = "gnlist";
587 sp->gen1 = fcport->rscn_gen;
588 sp->gen2 = fcport->login_gen;
589
590 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
591
592 mb = sp->u.iocb_cmd.u.mbx.out_mb;
593 mb[0] = MBC_PORT_NODE_NAME_LIST;
594 mb[1] = BIT_2 | BIT_3;
595 mb[2] = MSW(vha->gnl.ldma);
596 mb[3] = LSW(vha->gnl.ldma);
597 mb[6] = MSW(MSD(vha->gnl.ldma));
598 mb[7] = LSW(MSD(vha->gnl.ldma));
599 mb[8] = vha->gnl.size;
600 mb[9] = vha->vp_idx;
601
602 mbx = &sp->u.iocb_cmd;
603 mbx->timeout = qla2x00_async_iocb_timeout;
604
605 sp->done = qla24xx_async_gnl_sp_done;
606
607 rval = qla2x00_start_sp(sp);
608 if (rval != QLA_SUCCESS)
609 goto done_free_sp;
610
83548fe2
QT		 611 ql_dbg(ql_dbg_disc, vha, 0x20da,
612 "Async-%s - OUT WWPN %8phC hndl %x\n",
613 sp->name, fcport->port_name, sp->handle);
726b8548
QT		 614
615 return rval;
616
617done_free_sp:
25ff6af1 618 sp->free(sp);
726b8548
QT		 619done:
620 fcport->flags &= ~FCF_ASYNC_SENT;
621 return rval;
622}
623
624int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
625{
626 struct qla_work_evt *e;
627
628 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
629 if (!e)
630 return QLA_FUNCTION_FAILED;
631
632 e->u.fcport.fcport = fcport;
633 return qla2x00_post_work(vha, e);
634}
635
636static
25ff6af1 637void qla24xx_async_gpdb_sp_done(void *s, int res)
726b8548 638{
25ff6af1
JC		 639 struct srb *sp = s;
640 struct scsi_qla_host *vha = sp->vha;
726b8548 641 struct qla_hw_data *ha = vha->hw;
726b8548
QT		 642 struct port_database_24xx *pd;
643 fc_port_t *fcport = sp->fcport;
644 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
645 int rval = QLA_SUCCESS;
646 struct event_arg ea;
647
83548fe2 648 ql_dbg(ql_dbg_disc, vha, 0x20db,
726b8548
QT		 649 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
650 sp->name, res, fcport->port_name, mb[1], mb[2]);
651
652 fcport->flags &= ~FCF_ASYNC_SENT;
653
654 if (res) {
655 rval = res;
656 goto gpd_error_out;
657 }
658
659 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
660
15f30a57 661 rval = __qla24xx_parse_gpdb(vha, fcport, pd);
726b8548
QT		 662
663gpd_error_out:
664 memset(&ea, 0, sizeof(ea));
665 ea.event = FCME_GPDB_DONE;
666 ea.rc = rval;
667 ea.fcport = fcport;
668 ea.sp = sp;
669
670 qla2x00_fcport_event_handler(vha, &ea);
671
672 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
673 sp->u.iocb_cmd.u.mbx.in_dma);
674
25ff6af1 675 sp->free(sp);
726b8548
QT		 676}
677
a5d42f4c
DG		 678static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
679{
680 struct qla_work_evt *e;
681
682 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
683 if (!e)
684 return QLA_FUNCTION_FAILED;
685
686 e->u.fcport.fcport = fcport;
687
688 return qla2x00_post_work(vha, e);
689}
690
691static void
692qla2x00_async_prli_sp_done(void *ptr, int res)
693{
694 srb_t *sp = ptr;
695 struct scsi_qla_host *vha = sp->vha;
696 struct srb_iocb *lio = &sp->u.iocb_cmd;
697 struct event_arg ea;
698
699 ql_dbg(ql_dbg_disc, vha, 0x2129,
700 "%s %8phC res %d \n", __func__,
701 sp->fcport->port_name, res);
702
703 sp->fcport->flags &= ~FCF_ASYNC_SENT;
704
705 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
706 memset(&ea, 0, sizeof(ea));
707 ea.event = FCME_PRLI_DONE;
708 ea.fcport = sp->fcport;
709 ea.data[0] = lio->u.logio.data[0];
710 ea.data[1] = lio->u.logio.data[1];
711 ea.iop[0] = lio->u.logio.iop[0];
712 ea.iop[1] = lio->u.logio.iop[1];
713 ea.sp = sp;
714
715 qla2x00_fcport_event_handler(vha, &ea);
716 }
717
718 sp->free(sp);
719}
720
721int
722qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
723{
724 srb_t *sp;
725 struct srb_iocb *lio;
726 int rval = QLA_FUNCTION_FAILED;
727
728 if (!vha->flags.online)
729 return rval;
730
731 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
732 fcport->fw_login_state == DSC_LS_PLOGI_COMP ||
733 fcport->fw_login_state == DSC_LS_PRLI_PEND)
734 return rval;
735
736 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
737 if (!sp)
738 return rval;
739
740 fcport->flags |= FCF_ASYNC_SENT;
741 fcport->logout_completed = 0;
742
743 sp->type = SRB_PRLI_CMD;
744 sp->name = "prli";
745 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
746
747 lio = &sp->u.iocb_cmd;
748 lio->timeout = qla2x00_async_iocb_timeout;
749 sp->done = qla2x00_async_prli_sp_done;
750 lio->u.logio.flags = 0;
751
752 if (fcport->fc4f_nvme)
753 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
754
755 rval = qla2x00_start_sp(sp);
756 if (rval != QLA_SUCCESS) {
757 fcport->flags &= ~FCF_ASYNC_SENT;
758 fcport->flags |= FCF_LOGIN_NEEDED;
759 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
760 goto done_free_sp;
761 }
762
763 ql_dbg(ql_dbg_disc, vha, 0x211b,
764 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d.\n",
765 fcport->port_name, sp->handle, fcport->loop_id,
766 fcport->d_id.b24, fcport->login_retry);
767
768 return rval;
769
770done_free_sp:
771 sp->free(sp);
772 fcport->flags &= ~FCF_ASYNC_SENT;
773 return rval;
774}
775
a07fc0a4 776int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
726b8548
QT		 777{
778 struct qla_work_evt *e;
779
780 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
781 if (!e)
782 return QLA_FUNCTION_FAILED;
783
784 e->u.fcport.fcport = fcport;
785 e->u.fcport.opt = opt;
786 return qla2x00_post_work(vha, e);
787}
788
789int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
790{
791 srb_t *sp;
792 struct srb_iocb *mbx;
793 int rval = QLA_FUNCTION_FAILED;
794 u16 *mb;
795 dma_addr_t pd_dma;
796 struct port_database_24xx *pd;
797 struct qla_hw_data *ha = vha->hw;
798
799 if (!vha->flags.online)
800 goto done;
801
802 fcport->flags |= FCF_ASYNC_SENT;
803 fcport->disc_state = DSC_GPDB;
804
805 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
806 if (!sp)
807 goto done;
808
e0824e69
JC		 809 sp->type = SRB_MB_IOCB;
810 sp->name = "gpdb";
811 sp->gen1 = fcport->rscn_gen;
812 sp->gen2 = fcport->login_gen;
813 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
814
726b8548
QT		 815 pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
816 if (pd == NULL) {
83548fe2
QT		 817 ql_log(ql_log_warn, vha, 0xd043,
818 "Failed to allocate port database structure.\n");
726b8548
QT		 819 goto done_free_sp;
820 }
821 memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
822
726b8548
QT		 823 mb = sp->u.iocb_cmd.u.mbx.out_mb;
824 mb[0] = MBC_GET_PORT_DATABASE;
825 mb[1] = fcport->loop_id;
826 mb[2] = MSW(pd_dma);
827 mb[3] = LSW(pd_dma);
828 mb[6] = MSW(MSD(pd_dma));
829 mb[7] = LSW(MSD(pd_dma));
830 mb[9] = vha->vp_idx;
831 mb[10] = opt;
832
833 mbx = &sp->u.iocb_cmd;
834 mbx->timeout = qla2x00_async_iocb_timeout;
835 mbx->u.mbx.in = (void *)pd;
836 mbx->u.mbx.in_dma = pd_dma;
837
838 sp->done = qla24xx_async_gpdb_sp_done;
839
840 rval = qla2x00_start_sp(sp);
841 if (rval != QLA_SUCCESS)
842 goto done_free_sp;
843
83548fe2
QT		 844 ql_dbg(ql_dbg_disc, vha, 0x20dc,
845 "Async-%s %8phC hndl %x opt %x\n",
846 sp->name, fcport->port_name, sp->handle, opt);
726b8548
QT		 847
848 return rval;
849
850done_free_sp:
851 if (pd)
852 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
853
25ff6af1 854 sp->free(sp);
726b8548
QT		 855done:
856 fcport->flags &= ~FCF_ASYNC_SENT;
857 qla24xx_post_gpdb_work(vha, fcport, opt);
5ff1d584
AV		 858 return rval;
859}
860
726b8548
QT		 861static
862void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
863{
864 int rval = ea->rc;
865 fc_port_t *fcport = ea->fcport;
866 unsigned long flags;
867
868 fcport->flags &= ~FCF_ASYNC_SENT;
869
83548fe2 870 ql_dbg(ql_dbg_disc, vha, 0x20d2,
726b8548
QT		 871 "%s %8phC DS %d LS %d rval %d\n", __func__, fcport->port_name,
872 fcport->disc_state, fcport->fw_login_state, rval);
873
874 if (ea->sp->gen2 != fcport->login_gen) {
875 /* target side must have changed it. */
83548fe2 876 ql_dbg(ql_dbg_disc, vha, 0x20d3,
726b8548
QT		 877 "%s %8phC generation changed rscn %d|%d login %d|%d \n",
878 __func__, fcport->port_name, fcport->last_rscn_gen,
879 fcport->rscn_gen, fcport->last_login_gen,
880 fcport->login_gen);
881 return;
882 } else if (ea->sp->gen1 != fcport->rscn_gen) {
83548fe2 883 ql_dbg(ql_dbg_disc, vha, 0x20d4, "%s %d %8phC post gidpn\n",
726b8548
QT		 884 __func__, __LINE__, fcport->port_name);
885 qla24xx_post_gidpn_work(vha, fcport);
886 return;
887 }
888
889 if (rval != QLA_SUCCESS) {
83548fe2 890 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
726b8548
QT		 891 __func__, __LINE__, fcport->port_name);
892 qlt_schedule_sess_for_deletion_lock(fcport);
893 return;
894 }
895
896 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
897 ea->fcport->login_gen++;
898 ea->fcport->deleted = 0;
899 ea->fcport->logout_on_delete = 1;
900
901 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
902 vha->fcport_count++;
903 ea->fcport->login_succ = 1;
904
905 if (!IS_IIDMA_CAPABLE(vha->hw) ||
906 !vha->hw->flags.gpsc_supported) {
83548fe2 907 ql_dbg(ql_dbg_disc, vha, 0x20d6,
726b8548
QT		 908 "%s %d %8phC post upd_fcport fcp_cnt %d\n",
909 __func__, __LINE__, fcport->port_name,
910 vha->fcport_count);
911
912 qla24xx_post_upd_fcport_work(vha, fcport);
913 } else {
83548fe2 914 ql_dbg(ql_dbg_disc, vha, 0x20d7,
726b8548
QT		 915 "%s %d %8phC post gpsc fcp_cnt %d\n",
916 __func__, __LINE__, fcport->port_name,
917 vha->fcport_count);
918
919 qla24xx_post_gpsc_work(vha, fcport);
920 }
921 }
922 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
923} /* gpdb event */
924
925int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
926{
927 if (fcport->login_retry == 0)
928 return 0;
929
930 if (fcport->scan_state != QLA_FCPORT_FOUND)
931 return 0;
932
83548fe2 933 ql_dbg(ql_dbg_disc, vha, 0x20d8,
726b8548
QT		 934 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d|%d retry %d lid %d\n",
935 __func__, fcport->port_name, fcport->disc_state,
936 fcport->fw_login_state, fcport->login_pause, fcport->flags,
937 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
938 fcport->last_login_gen, fcport->login_gen, fcport->login_retry,
939 fcport->loop_id);
940
941 fcport->login_retry--;
942
943 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 944 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
945 return 0;
946
5b33469a
QT		 947 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
948 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
949 return 0;
950 }
951
726b8548
QT		 952 /* for pure Target Mode. Login will not be initiated */
953 if (vha->host->active_mode == MODE_TARGET)
954 return 0;
955
956 if (fcport->flags & FCF_ASYNC_SENT) {
957 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
958 return 0;
959 }
960
961 switch (fcport->disc_state) {
962 case DSC_DELETED:
963 if (fcport->loop_id == FC_NO_LOOP_ID) {
83548fe2
QT		 964 ql_dbg(ql_dbg_disc, vha, 0x20bd,
965 "%s %d %8phC post gnl\n",
966 __func__, __LINE__, fcport->port_name);
726b8548
QT		 967 qla24xx_async_gnl(vha, fcport);
968 } else {
83548fe2
QT		 969 ql_dbg(ql_dbg_disc, vha, 0x20bf,
970 "%s %d %8phC post login\n",
971 __func__, __LINE__, fcport->port_name);
726b8548
QT		 972 fcport->disc_state = DSC_LOGIN_PEND;
973 qla2x00_post_async_login_work(vha, fcport, NULL);
974 }
975 break;
976
977 case DSC_GNL:
978 if (fcport->login_pause) {
979 fcport->last_rscn_gen = fcport->rscn_gen;
980 fcport->last_login_gen = fcport->login_gen;
981 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
982 break;
983 }
984
985 if (fcport->flags & FCF_FCP2_DEVICE) {
986 u8 opt = PDO_FORCE_ADISC;
987
83548fe2
QT		 988 ql_dbg(ql_dbg_disc, vha, 0x20c9,
989 "%s %d %8phC post gpdb\n",
990 __func__, __LINE__, fcport->port_name);
726b8548
QT		 991
992 fcport->disc_state = DSC_GPDB;
993 qla24xx_post_gpdb_work(vha, fcport, opt);
994 } else {
83548fe2
QT		 995 ql_dbg(ql_dbg_disc, vha, 0x20cf,
996 "%s %d %8phC post login\n",
997 __func__, __LINE__, fcport->port_name);
726b8548
QT		 998 fcport->disc_state = DSC_LOGIN_PEND;
999 qla2x00_post_async_login_work(vha, fcport, NULL);
1000 }
1001
1002 break;
1003
1004 case DSC_LOGIN_FAILED:
83548fe2
QT		 1005 ql_dbg(ql_dbg_disc, vha, 0x20d0,
1006 "%s %d %8phC post gidpn\n",
1007 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1008
1009 qla24xx_post_gidpn_work(vha, fcport);
1010 break;
1011
1012 case DSC_LOGIN_COMPLETE:
1013 /* recheck login state */
83548fe2
QT		 1014 ql_dbg(ql_dbg_disc, vha, 0x20d1,
1015 "%s %d %8phC post gpdb\n",
1016 __func__, __LINE__, fcport->port_name);
726b8548
QT		 1017
1018 qla24xx_post_gpdb_work(vha, fcport, PDO_FORCE_ADISC);
1019 break;
1020
1021 default:
1022 break;
1023 }
1024
1025 return 0;
1026}
1027
1028static
1029void qla24xx_handle_rscn_event(fc_port_t *fcport, struct event_arg *ea)
1030{
1031 fcport->rscn_gen++;
1032
83548fe2
QT		 1033 ql_dbg(ql_dbg_disc, fcport->vha, 0x210c,
1034 "%s %8phC DS %d LS %d\n",
1035 __func__, fcport->port_name, fcport->disc_state,
1036 fcport->fw_login_state);
726b8548
QT		 1037
1038 if (fcport->flags & FCF_ASYNC_SENT)
1039 return;
1040
1041 switch (fcport->disc_state) {
1042 case DSC_DELETED:
1043 case DSC_LOGIN_COMPLETE:
1044 qla24xx_post_gidpn_work(fcport->vha, fcport);
1045 break;
1046
1047 default:
1048 break;
1049 }
1050}
1051
1052int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1053 u8 *port_name, void *pla)
1054{
1055 struct qla_work_evt *e;
1056 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1057 if (!e)
1058 return QLA_FUNCTION_FAILED;
1059
1060 e->u.new_sess.id = *id;
1061 e->u.new_sess.pla = pla;
1062 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1063
1064 return qla2x00_post_work(vha, e);
1065}
1066
1067static
1068int qla24xx_handle_delete_done_event(scsi_qla_host_t *vha,
1069 struct event_arg *ea)
1070{
1071 fc_port_t *fcport = ea->fcport;
1072
1073 if (test_bit(UNLOADING, &vha->dpc_flags))
1074 return 0;
1075
1076 switch (vha->host->active_mode) {
1077 case MODE_INITIATOR:
1078 case MODE_DUAL:
1079 if (fcport->scan_state == QLA_FCPORT_FOUND)
1080 qla24xx_fcport_handle_login(vha, fcport);
1081 break;
1082
1083 case MODE_TARGET:
1084 default:
1085 /* no-op */
1086 break;
1087 }
1088
1089 return 0;
1090}
1091
1092static
1093void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1094 struct event_arg *ea)
1095{
1096 fc_port_t *fcport = ea->fcport;
1097
1098 if (fcport->scan_state != QLA_FCPORT_FOUND) {
1099 fcport->login_retry++;
1100 return;
1101 }
1102
83548fe2
QT		 1103 ql_dbg(ql_dbg_disc, vha, 0x2102,
1104 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1105 __func__, fcport->port_name, fcport->disc_state,
1106 fcport->fw_login_state, fcport->login_pause,
1107 fcport->deleted, fcport->conflict,
1108 fcport->last_rscn_gen, fcport->rscn_gen,
1109 fcport->last_login_gen, fcport->login_gen,
1110 fcport->flags);
726b8548
QT		 1111
1112 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
726b8548
QT		 1113 (fcport->fw_login_state == DSC_LS_PRLI_PEND))
1114 return;
1115
5b33469a
QT		 1116 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) {
1117 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline))
1118 return;
1119 }
1120
726b8548
QT		 1121 if (fcport->flags & FCF_ASYNC_SENT) {
1122 fcport->login_retry++;
1123 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1124 return;
1125 }
1126
1127 if (fcport->disc_state == DSC_DELETE_PEND) {
1128 fcport->login_retry++;
1129 return;
1130 }
1131
1132 if (fcport->last_rscn_gen != fcport->rscn_gen) {
83548fe2 1133 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gidpn\n",
726b8548
QT		 1134 __func__, __LINE__, fcport->port_name);
1135
1136 qla24xx_async_gidpn(vha, fcport);
1137 return;
1138 }
1139
1140 qla24xx_fcport_handle_login(vha, fcport);
1141}
1142
41dc529a 1143void qla2x00_fcport_event_handler(scsi_qla_host_t *vha, struct event_arg *ea)
726b8548 1144{
41dc529a
QT		 1145 fc_port_t *fcport, *f, *tf;
1146 uint32_t id = 0, mask, rid;
726b8548
QT		 1147 int rc;
1148
b98ae0d7
QT		 1149 switch (ea->event) {
1150 case FCME_RELOGIN:
1151 case FCME_RSCN:
1152 case FCME_GIDPN_DONE:
1153 case FCME_GPSC_DONE:
1154 case FCME_GPNID_DONE:
1155 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
1156 test_bit(LOOP_RESYNC_ACTIVE, &vha->dpc_flags))
1157 return;
1158 break;
1159 default:
1160 break;
1161 }
1162
726b8548
QT		 1163 switch (ea->event) {
1164 case FCME_RELOGIN:
1165 if (test_bit(UNLOADING, &vha->dpc_flags))
1166 return;
5ff1d584 1167
726b8548
QT		 1168 qla24xx_handle_relogin_event(vha, ea);
1169 break;
1170 case FCME_RSCN:
1171 if (test_bit(UNLOADING, &vha->dpc_flags))
1172 return;
41dc529a
QT		 1173 switch (ea->id.b.rsvd_1) {
1174 case RSCN_PORT_ADDR:
1175 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1176 if (!fcport) {
1177 /* cable moved */
1178 rc = qla24xx_post_gpnid_work(vha, &ea->id);
1179 if (rc) {
83548fe2
QT		 1180 ql_log(ql_log_warn, vha, 0xd044,
1181 "RSCN GPNID work failed %02x%02x%02x\n",
1182 ea->id.b.domain, ea->id.b.area,
1183 ea->id.b.al_pa);
41dc529a
QT		 1184 }
1185 } else {
1186 ea->fcport = fcport;
1187 qla24xx_handle_rscn_event(fcport, ea);
1188 }
1189 break;
1190 case RSCN_AREA_ADDR:
1191 case RSCN_DOM_ADDR:
1192 if (ea->id.b.rsvd_1 == RSCN_AREA_ADDR) {
1193 mask = 0xffff00;
83548fe2
QT		 1194 ql_dbg(ql_dbg_async, vha, 0x5044,
1195 "RSCN: Area 0x%06x was affected\n",
1196 ea->id.b24);
41dc529a
QT		 1197 } else {
1198 mask = 0xff0000;
83548fe2
QT		 1199 ql_dbg(ql_dbg_async, vha, 0x507a,
1200 "RSCN: Domain 0x%06x was affected\n",
1201 ea->id.b24);
41dc529a 1202 }
726b8548 1203
41dc529a
QT		 1204 rid = ea->id.b24 & mask;
1205 list_for_each_entry_safe(f, tf, &vha->vp_fcports,
1206 list) {
1207 id = f->d_id.b24 & mask;
1208 if (rid == id) {
1209 ea->fcport = f;
1210 qla24xx_handle_rscn_event(f, ea);
1211 }
726b8548 1212 }
41dc529a
QT		 1213 break;
1214 case RSCN_FAB_ADDR:
1215 default:
83548fe2
QT		 1216 ql_log(ql_log_warn, vha, 0xd045,
1217 "RSCN: Fabric was affected. Addr format %d\n",
1218 ea->id.b.rsvd_1);
41dc529a
QT		 1219 qla2x00_mark_all_devices_lost(vha, 1);
1220 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1221 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
726b8548
QT		 1222 }
1223 break;
1224 case FCME_GIDPN_DONE:
1225 qla24xx_handle_gidpn_event(vha, ea);
1226 break;
1227 case FCME_GNL_DONE:
1228 qla24xx_handle_gnl_done_event(vha, ea);
1229 break;
1230 case FCME_GPSC_DONE:
1231 qla24xx_post_upd_fcport_work(vha, ea->fcport);
1232 break;
1233 case FCME_PLOGI_DONE: /* Initiator side sent LLIOCB */
1234 qla24xx_handle_plogi_done_event(vha, ea);
1235 break;
a5d42f4c
DG		 1236 case FCME_PRLI_DONE:
1237 qla24xx_handle_prli_done_event(vha, ea);
1238 break;
726b8548
QT		 1239 case FCME_GPDB_DONE:
1240 qla24xx_handle_gpdb_event(vha, ea);
1241 break;
1242 case FCME_GPNID_DONE:
1243 qla24xx_handle_gpnid_event(vha, ea);
1244 break;
d3bae931
DG		 1245 case FCME_GFFID_DONE:
1246 qla24xx_handle_gffid_event(vha, ea);
1247 break;
726b8548
QT		 1248 case FCME_DELETE_DONE:
1249 qla24xx_handle_delete_done_event(vha, ea);
1250 break;
1251 default:
1252 BUG_ON(1);
1253 break;
1254 }
5ff1d584
AV		 1255}
1256
3822263e 1257static void
faef62d1 1258qla2x00_tmf_iocb_timeout(void *data)
3822263e 1259{
25ff6af1 1260 srb_t *sp = data;
faef62d1 1261 struct srb_iocb *tmf = &sp->u.iocb_cmd;
3822263e 1262
faef62d1
AB		 1263 tmf->u.tmf.comp_status = CS_TIMEOUT;
1264 complete(&tmf->u.tmf.comp);
1265}
9ba56b95 1266
faef62d1 1267static void
25ff6af1 1268qla2x00_tmf_sp_done(void *ptr, int res)
faef62d1 1269{
25ff6af1 1270 srb_t *sp = ptr;
faef62d1 1271 struct srb_iocb *tmf = &sp->u.iocb_cmd;
25ff6af1 1272
faef62d1 1273 complete(&tmf->u.tmf.comp);
3822263e
MI		 1274}
1275
1276int
faef62d1 1277qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
3822263e
MI		 1278 uint32_t tag)
1279{
1280 struct scsi_qla_host *vha = fcport->vha;
faef62d1 1281 struct srb_iocb *tm_iocb;
3822263e 1282 srb_t *sp;
faef62d1 1283 int rval = QLA_FUNCTION_FAILED;
3822263e 1284
9ba56b95 1285 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
3822263e
MI		 1286 if (!sp)
1287 goto done;
1288
faef62d1 1289 tm_iocb = &sp->u.iocb_cmd;
9ba56b95
GM		 1290 sp->type = SRB_TM_CMD;
1291 sp->name = "tmf";
faef62d1
AB		 1292 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1293 tm_iocb->u.tmf.flags = flags;
1294 tm_iocb->u.tmf.lun = lun;
1295 tm_iocb->u.tmf.data = tag;
1296 sp->done = qla2x00_tmf_sp_done;
1297 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1298 init_completion(&tm_iocb->u.tmf.comp);
3822263e
MI		 1299
1300 rval = qla2x00_start_sp(sp);
1301 if (rval != QLA_SUCCESS)
1302 goto done_free_sp;
1303
7c3df132 1304 ql_dbg(ql_dbg_taskm, vha, 0x802f,
cfb0919c
CD		 1305 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1306 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1307 fcport->d_id.b.area, fcport->d_id.b.al_pa);
faef62d1
AB		 1308
1309 wait_for_completion(&tm_iocb->u.tmf.comp);
1310
1311 rval = tm_iocb->u.tmf.comp_status == CS_COMPLETE ?
1312 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1313
1314 if ((rval != QLA_SUCCESS) || tm_iocb->u.tmf.data) {
1315 ql_dbg(ql_dbg_taskm, vha, 0x8030,
1316 "TM IOCB failed (%x).\n", rval);
1317 }
1318
1319 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1320 flags = tm_iocb->u.tmf.flags;
1321 lun = (uint16_t)tm_iocb->u.tmf.lun;
1322
1323 /* Issue Marker IOCB */
1324 qla2x00_marker(vha, vha->hw->req_q_map[0],
1325 vha->hw->rsp_q_map[0], sp->fcport->loop_id, lun,
1326 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1327 }
3822263e
MI		 1328
1329done_free_sp:
25ff6af1 1330 sp->free(sp);
3822263e
MI		 1331done:
1332 return rval;
1333}
1334
4440e46d
AB		 1335static void
1336qla24xx_abort_iocb_timeout(void *data)
1337{
25ff6af1 1338 srb_t *sp = data;
4440e46d
AB		 1339 struct srb_iocb *abt = &sp->u.iocb_cmd;
1340
1341 abt->u.abt.comp_status = CS_TIMEOUT;
1342 complete(&abt->u.abt.comp);
1343}
1344
1345static void
25ff6af1 1346qla24xx_abort_sp_done(void *ptr, int res)
4440e46d 1347{
25ff6af1 1348 srb_t *sp = ptr;
4440e46d
AB		 1349 struct srb_iocb *abt = &sp->u.iocb_cmd;
1350
1351 complete(&abt->u.abt.comp);
1352}
1353
15f30a57 1354int
4440e46d
AB		 1355qla24xx_async_abort_cmd(srb_t *cmd_sp)
1356{
25ff6af1 1357 scsi_qla_host_t *vha = cmd_sp->vha;
4440e46d
AB		 1358 fc_port_t *fcport = cmd_sp->fcport;
1359 struct srb_iocb *abt_iocb;
1360 srb_t *sp;
1361 int rval = QLA_FUNCTION_FAILED;
1362
1363 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1364 if (!sp)
1365 goto done;
1366
1367 abt_iocb = &sp->u.iocb_cmd;
1368 sp->type = SRB_ABT_CMD;
1369 sp->name = "abort";
1370 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1371 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
1372 sp->done = qla24xx_abort_sp_done;
1373 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
1374 init_completion(&abt_iocb->u.abt.comp);
1375
1376 rval = qla2x00_start_sp(sp);
1377 if (rval != QLA_SUCCESS)
1378 goto done_free_sp;
1379
1380 ql_dbg(ql_dbg_async, vha, 0x507c,
1381 "Abort command issued - hdl=%x, target_id=%x\n",
1382 cmd_sp->handle, fcport->tgt_id);
1383
1384 wait_for_completion(&abt_iocb->u.abt.comp);
1385
1386 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
1387 QLA_SUCCESS : QLA_FUNCTION_FAILED;
1388
1389done_free_sp:
25ff6af1 1390 sp->free(sp);
4440e46d
AB		 1391done:
1392 return rval;
1393}
1394
1395int
1396qla24xx_async_abort_command(srb_t *sp)
1397{
1398 unsigned long flags = 0;
1399
1400 uint32_t handle;
1401 fc_port_t *fcport = sp->fcport;
1402 struct scsi_qla_host *vha = fcport->vha;
1403 struct qla_hw_data *ha = vha->hw;
1404 struct req_que *req = vha->req;
1405
1406 spin_lock_irqsave(&ha->hardware_lock, flags);
1407 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1408 if (req->outstanding_cmds[handle] == sp)
1409 break;
1410 }
1411 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1412 if (handle == req->num_outstanding_cmds) {
1413 /* Command not found. */
1414 return QLA_FUNCTION_FAILED;
1415 }
1416 if (sp->type == SRB_FXIOCB_DCMD)
1417 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1418 FXDISC_ABORT_IOCTL);
1419
1420 return qla24xx_async_abort_cmd(sp);
1421}
1422
a5d42f4c
DG		 1423static void
1424qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1425{
1426 switch (ea->data[0]) {
1427 case MBS_COMMAND_COMPLETE:
1428 ql_dbg(ql_dbg_disc, vha, 0x2118,
1429 "%s %d %8phC post gpdb\n",
1430 __func__, __LINE__, ea->fcport->port_name);
1431
1432 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1433 ea->fcport->logout_on_delete = 1;
1434 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1435 break;
1436 default:
1437 ql_dbg(ql_dbg_disc, vha, 0x2119,
1438 "%s %d %8phC unhandle event of %x\n",
1439 __func__, __LINE__, ea->fcport->port_name, ea->data[0]);
1440 break;
1441 }
1442}
1443
726b8548
QT		 1444static void
1445qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
ac280b67 1446{
726b8548 1447 port_id_t cid; /* conflict Nport id */
ac280b67 1448
726b8548 1449 switch (ea->data[0]) {
ac280b67 1450 case MBS_COMMAND_COMPLETE:
a4f92a32
AV		 1451 /*
1452 * Driver must validate login state - If PRLI not complete,
1453 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI
1454 * requests.
1455 */
a5d42f4c
DG		 1456 if (ea->fcport->fc4f_nvme) {
1457 ql_dbg(ql_dbg_disc, vha, 0x2117,
1458 "%s %d %8phC post prli\n",
1459 __func__, __LINE__, ea->fcport->port_name);
1460 qla24xx_post_prli_work(vha, ea->fcport);
1461 } else {
1462 ql_dbg(ql_dbg_disc, vha, 0x20ea,
1463 "%s %d %8phC post gpdb\n",
1464 __func__, __LINE__, ea->fcport->port_name);
1465 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1466 ea->fcport->logout_on_delete = 1;
3515832c 1467 ea->fcport->send_els_logo = 0;
a5d42f4c
DG		 1468 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1469 }
ac280b67
AV		 1470 break;
1471 case MBS_COMMAND_ERROR:
83548fe2 1472 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
726b8548
QT		 1473 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
1474
1475 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1476 ea->fcport->disc_state = DSC_LOGIN_FAILED;
1477 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
ac280b67
AV		 1478 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1479 else
726b8548 1480 qla2x00_mark_device_lost(vha, ea->fcport, 1, 0);
ac280b67
AV		 1481 break;
1482 case MBS_LOOP_ID_USED:
726b8548
QT		 1483 /* data[1] = IO PARAM 1 = nport ID */
1484 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
1485 cid.b.area = (ea->iop[1] >> 8) & 0xff;
1486 cid.b.al_pa = ea->iop[1] & 0xff;
1487 cid.b.rsvd_1 = 0;
1488
83548fe2
QT		 1489 ql_dbg(ql_dbg_disc, vha, 0x20ec,
1490 "%s %d %8phC LoopID 0x%x in use post gnl\n",
1491 __func__, __LINE__, ea->fcport->port_name,
1492 ea->fcport->loop_id);
726b8548
QT		 1493
1494 if (IS_SW_RESV_ADDR(cid)) {
1495 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
1496 ea->fcport->loop_id = FC_NO_LOOP_ID;
1497 } else {
1498 qla2x00_clear_loop_id(ea->fcport);
ac280b67 1499 }
726b8548
QT		 1500 qla24xx_post_gnl_work(vha, ea->fcport);
1501 break;
1502 case MBS_PORT_ID_USED:
83548fe2
QT		 1503 ql_dbg(ql_dbg_disc, vha, 0x20ed,
1504 "%s %d %8phC NPortId %02x%02x%02x inuse post gidpn\n",
1505 __func__, __LINE__, ea->fcport->port_name,
1506 ea->fcport->d_id.b.domain, ea->fcport->d_id.b.area,
1507 ea->fcport->d_id.b.al_pa);
726b8548
QT		 1508
1509 qla2x00_clear_loop_id(ea->fcport);
1510 qla24xx_post_gidpn_work(vha, ea->fcport);
ac280b67
AV		 1511 break;
1512 }
4916392b 1513 return;
ac280b67
AV		 1514}
1515
4916392b 1516void
ac280b67
AV		 1517qla2x00_async_logout_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1518 uint16_t *data)
1519{
726b8548 1520 qla2x00_mark_device_lost(vha, fcport, 1, 0);
a6ca8878 1521 qlt_logo_completion_handler(fcport, data[0]);
726b8548 1522 fcport->login_gen++;
4916392b 1523 return;
ac280b67
AV		 1524}
1525
4916392b 1526void
5ff1d584
AV		 1527qla2x00_async_adisc_done(struct scsi_qla_host *vha, fc_port_t *fcport,
1528 uint16_t *data)
1529{
1530 if (data[0] == MBS_COMMAND_COMPLETE) {
1531 qla2x00_update_fcport(vha, fcport);
1532
4916392b 1533 return;
5ff1d584
AV		 1534 }
1535
1536 /* Retry login. */
1537 fcport->flags &= ~FCF_ASYNC_SENT;
1538 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
1539 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1540 else
80d79440 1541 qla2x00_mark_device_lost(vha, fcport, 1, 0);
5ff1d584 1542
4916392b 1543 return;
5ff1d584
AV		 1544}
1545
1da177e4
LT		 1546/****************************************************************************/
1547/* QLogic ISP2x00 Hardware Support Functions. */
1548/****************************************************************************/
1549
fa492630 1550static int
7d613ac6
SV		 1551qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
1552{
1553 int rval = QLA_SUCCESS;
1554 struct qla_hw_data *ha = vha->hw;
1555 uint32_t idc_major_ver, idc_minor_ver;
711aa7f7 1556 uint16_t config[4];
7d613ac6
SV		 1557
1558 qla83xx_idc_lock(vha, 0);
1559
1560 /* SV: TODO: Assign initialization timeout from
1561 * flash-info / other param
1562 */
1563 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
1564 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
1565
1566 /* Set our fcoe function presence */
1567 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
1568 ql_dbg(ql_dbg_p3p, vha, 0xb077,
1569 "Error while setting DRV-Presence.\n");
1570 rval = QLA_FUNCTION_FAILED;
1571 goto exit;
1572 }
1573
1574 /* Decide the reset ownership */
1575 qla83xx_reset_ownership(vha);
1576
1577 /*
1578 * On first protocol driver load:
1579 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery
1580 * register.
1581 * Others: Check compatibility with current IDC Major version.
1582 */
1583 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
1584 if (ha->flags.nic_core_reset_owner) {
1585 /* Set IDC Major version */
1586 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
1587 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
1588
1589 /* Clearing IDC-Lock-Recovery register */
1590 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
1591 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
1592 /*
1593 * Clear further IDC participation if we are not compatible with
1594 * the current IDC Major Version.
1595 */
1596 ql_log(ql_log_warn, vha, 0xb07d,
1597 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
1598 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
1599 __qla83xx_clear_drv_presence(vha);
1600 rval = QLA_FUNCTION_FAILED;
1601 goto exit;
1602 }
1603 /* Each function sets its supported Minor version. */
1604 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
1605 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
1606 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
1607
711aa7f7
SK		 1608 if (ha->flags.nic_core_reset_owner) {
1609 memset(config, 0, sizeof(config));
1610 if (!qla81xx_get_port_config(vha, config))
1611 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
1612 QLA8XXX_DEV_READY);
1613 }
1614
7d613ac6
SV		 1615 rval = qla83xx_idc_state_handler(vha);
1616
1617exit:
1618 qla83xx_idc_unlock(vha, 0);
1619
1620 return rval;
1621}
1622
1da177e4
LT		 1623/*
1624* qla2x00_initialize_adapter
1625* Initialize board.
1626*
1627* Input:
1628* ha = adapter block pointer.
1629*
1630* Returns:
1631* 0 = success
1632*/
1633int
e315cd28 1634qla2x00_initialize_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 1635{
1636 int rval;
e315cd28 1637 struct qla_hw_data *ha = vha->hw;
73208dfd 1638 struct req_que *req = ha->req_q_map[0];
2533cf67 1639
fc90adaf
JC		 1640 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
1641 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
1642
1da177e4 1643 /* Clear adapter flags. */
e315cd28 1644 vha->flags.online = 0;
2533cf67 1645 ha->flags.chip_reset_done = 0;
e315cd28 1646 vha->flags.reset_active = 0;
85880801
AV		 1647 ha->flags.pci_channel_io_perm_failure = 0;
1648 ha->flags.eeh_busy = 0;
fabbb8df 1649 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
e315cd28
AC		 1650 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1651 atomic_set(&vha->loop_state, LOOP_DOWN);
1652 vha->device_flags = DFLG_NO_CABLE;
1653 vha->dpc_flags = 0;
1654 vha->flags.management_server_logged_in = 0;
1655 vha->marker_needed = 0;
1da177e4
LT		 1656 ha->isp_abort_cnt = 0;
1657 ha->beacon_blink_led = 0;
1658
73208dfd
AC		 1659 set_bit(0, ha->req_qid_map);
1660 set_bit(0, ha->rsp_qid_map);
1661
cfb0919c 1662 ql_dbg(ql_dbg_init, vha, 0x0040,
7c3df132 1663 "Configuring PCI space...\n");
e315cd28 1664 rval = ha->isp_ops->pci_config(vha);
1da177e4 1665 if (rval) {
7c3df132
SK		 1666 ql_log(ql_log_warn, vha, 0x0044,
1667 "Unable to configure PCI space.\n");
1da177e4
LT		 1668 return (rval);
1669 }
1670
e315cd28 1671 ha->isp_ops->reset_chip(vha);
1da177e4 1672
e315cd28 1673 rval = qla2xxx_get_flash_info(vha);
c00d8994 1674 if (rval) {
7c3df132
SK		 1675 ql_log(ql_log_fatal, vha, 0x004f,
1676 "Unable to validate FLASH data.\n");
7ec0effd
AD		 1677 return rval;
1678 }
1679
1680 if (IS_QLA8044(ha)) {
1681 qla8044_read_reset_template(vha);
1682
1683 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0.
1684 * If DONRESET_BIT0 is set, drivers should not set dev_state
1685 * to NEED_RESET. But if NEED_RESET is set, drivers should
1686 * should honor the reset. */
1687 if (ql2xdontresethba == 1)
1688 qla8044_set_idc_dontreset(vha);
c00d8994
AV		 1689 }
1690
73208dfd 1691 ha->isp_ops->get_flash_version(vha, req->ring);
cfb0919c 1692 ql_dbg(ql_dbg_init, vha, 0x0061,
7c3df132 1693 "Configure NVRAM parameters...\n");
0107109e 1694
e315cd28 1695 ha->isp_ops->nvram_config(vha);
1da177e4 1696
d4c760c2
AV		 1697 if (ha->flags.disable_serdes) {
1698 /* Mask HBA via NVRAM settings? */
7c3df132 1699 ql_log(ql_log_info, vha, 0x0077,
7b833558 1700 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
d4c760c2
AV		 1701 return QLA_FUNCTION_FAILED;
1702 }
1703
cfb0919c 1704 ql_dbg(ql_dbg_init, vha, 0x0078,
7c3df132 1705 "Verifying loaded RISC code...\n");
1da177e4 1706
e315cd28
AC		 1707 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
1708 rval = ha->isp_ops->chip_diag(vha);
d19044c3
AV		 1709 if (rval)
1710 return (rval);
e315cd28 1711 rval = qla2x00_setup_chip(vha);
d19044c3
AV		 1712 if (rval)
1713 return (rval);
1da177e4 1714 }
a9083016 1715
4d4df193 1716 if (IS_QLA84XX(ha)) {
e315cd28 1717 ha->cs84xx = qla84xx_get_chip(vha);
4d4df193 1718 if (!ha->cs84xx) {
7c3df132 1719 ql_log(ql_log_warn, vha, 0x00d0,
4d4df193
HK		 1720 "Unable to configure ISP84XX.\n");
1721 return QLA_FUNCTION_FAILED;
1722 }
1723 }
2d70c103 1724
ead03855 1725 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2d70c103
NB		 1726 rval = qla2x00_init_rings(vha);
1727
2533cf67 1728 ha->flags.chip_reset_done = 1;
1da177e4 1729
9a069e19 1730 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
6c452a45 1731 /* Issue verify 84xx FW IOCB to complete 84xx initialization */
9a069e19
GM		 1732 rval = qla84xx_init_chip(vha);
1733 if (rval != QLA_SUCCESS) {
7c3df132
SK		 1734 ql_log(ql_log_warn, vha, 0x00d4,
1735 "Unable to initialize ISP84XX.\n");
8d2b21db 1736 qla84xx_put_chip(vha);
9a069e19
GM		 1737 }
1738 }
1739
7d613ac6
SV		 1740 /* Load the NIC Core f/w if we are the first protocol driver. */
1741 if (IS_QLA8031(ha)) {
1742 rval = qla83xx_nic_core_fw_load(vha);
1743 if (rval)
1744 ql_log(ql_log_warn, vha, 0x0124,
1745 "Error in initializing NIC Core f/w.\n");
1746 }
1747
2f0f3f4f
MI		 1748 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
1749 qla24xx_read_fcp_prio_cfg(vha);
09ff701a 1750
c46e65c7
JC		 1751 if (IS_P3P_TYPE(ha))
1752 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
1753 else
1754 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
1755
1da177e4
LT		 1756 return (rval);
1757}
1758
1759/**
abbd8870 1760 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers.
1da177e4
LT		 1761 * @ha: HA context
1762 *
1763 * Returns 0 on success.
1764 */
abbd8870 1765int
e315cd28 1766qla2100_pci_config(scsi_qla_host_t *vha)
1da177e4 1767{
a157b101 1768 uint16_t w;
abbd8870 1769 unsigned long flags;
e315cd28 1770 struct qla_hw_data *ha = vha->hw;
3d71644c 1771 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1772
1da177e4 1773 pci_set_master(ha->pdev);
af6177d8 1774 pci_try_set_mwi(ha->pdev);
1da177e4 1775
1da177e4 1776 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1777 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
abbd8870
AV		 1778 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1779
737faece 1780 pci_disable_rom(ha->pdev);
1da177e4
LT		 1781
1782 /* Get PCI bus information. */
1783 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1784 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
1da177e4
LT		 1785 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1786
abbd8870
AV		 1787 return QLA_SUCCESS;
1788}
1da177e4 1789
abbd8870
AV		 1790/**
1791 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers.
1792 * @ha: HA context
1793 *
1794 * Returns 0 on success.
1795 */
1796int
e315cd28 1797qla2300_pci_config(scsi_qla_host_t *vha)
abbd8870 1798{
a157b101 1799 uint16_t w;
abbd8870
AV		 1800 unsigned long flags = 0;
1801 uint32_t cnt;
e315cd28 1802 struct qla_hw_data *ha = vha->hw;
3d71644c 1803 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1804
abbd8870 1805 pci_set_master(ha->pdev);
af6177d8 1806 pci_try_set_mwi(ha->pdev);
1da177e4 1807
abbd8870 1808 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1809 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1da177e4 1810
abbd8870
AV		 1811 if (IS_QLA2322(ha) || IS_QLA6322(ha))
1812 w &= ~PCI_COMMAND_INTX_DISABLE;
a157b101 1813 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1da177e4 1814
abbd8870
AV		 1815 /*
1816 * If this is a 2300 card and not 2312, reset the
1817 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately,
1818 * the 2310 also reports itself as a 2300 so we need to get the
1819 * fb revision level -- a 6 indicates it really is a 2300 and
1820 * not a 2310.
1821 */
1822 if (IS_QLA2300(ha)) {
1823 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1824
abbd8870 1825 /* Pause RISC. */
3d71644c 1826 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
abbd8870 1827 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1828 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
abbd8870 1829 break;
1da177e4 1830
abbd8870
AV		 1831 udelay(10);
1832 }
1da177e4 1833
abbd8870 1834 /* Select FPM registers. */
3d71644c
AV		 1835 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1836 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1837
1838 /* Get the fb rev level */
3d71644c 1839 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
abbd8870
AV		 1840
1841 if (ha->fb_rev == FPM_2300)
a157b101 1842 pci_clear_mwi(ha->pdev);
abbd8870
AV		 1843
1844 /* Deselect FPM registers. */
3d71644c
AV		 1845 WRT_REG_WORD(&reg->ctrl_status, 0x0);
1846 RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1847
1848 /* Release RISC module. */
3d71644c 1849 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
abbd8870 1850 for (cnt = 0; cnt < 30000; cnt++) {
3d71644c 1851 if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0)
abbd8870
AV		 1852 break;
1853
1854 udelay(10);
1da177e4 1855 }
1da177e4 1856
abbd8870
AV		 1857 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1858 }
1da177e4 1859
abbd8870
AV		 1860 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1861
737faece 1862 pci_disable_rom(ha->pdev);
1da177e4 1863
abbd8870
AV		 1864 /* Get PCI bus information. */
1865 spin_lock_irqsave(&ha->hardware_lock, flags);
3d71644c 1866 ha->pci_attr = RD_REG_WORD(&reg->ctrl_status);
abbd8870
AV		 1867 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1868
1869 return QLA_SUCCESS;
1da177e4
LT		 1870}
1871
0107109e
AV		 1872/**
1873 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers.
1874 * @ha: HA context
1875 *
1876 * Returns 0 on success.
1877 */
1878int
e315cd28 1879qla24xx_pci_config(scsi_qla_host_t *vha)
0107109e 1880{
a157b101 1881 uint16_t w;
0107109e 1882 unsigned long flags = 0;
e315cd28 1883 struct qla_hw_data *ha = vha->hw;
0107109e 1884 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
0107109e
AV		 1885
1886 pci_set_master(ha->pdev);
af6177d8 1887 pci_try_set_mwi(ha->pdev);
0107109e
AV		 1888
1889 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
a157b101 1890 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
0107109e
AV		 1891 w &= ~PCI_COMMAND_INTX_DISABLE;
1892 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1893
1894 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
1895
1896 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */
f85ec187
AV		 1897 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
1898 pcix_set_mmrbc(ha->pdev, 2048);
0107109e
AV		 1899
1900 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1901 if (pci_is_pcie(ha->pdev))
5ffd3a52 1902 pcie_set_readrq(ha->pdev, 4096);
0107109e 1903
737faece 1904 pci_disable_rom(ha->pdev);
0107109e 1905
44c10138 1906 ha->chip_revision = ha->pdev->revision;
a8488abe 1907
0107109e
AV		 1908 /* Get PCI bus information. */
1909 spin_lock_irqsave(&ha->hardware_lock, flags);
1910 ha->pci_attr = RD_REG_DWORD(&reg->ctrl_status);
1911 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1912
1913 return QLA_SUCCESS;
1914}
1915
c3a2f0df
AV		 1916/**
1917 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers.
1918 * @ha: HA context
1919 *
1920 * Returns 0 on success.
1921 */
1922int
e315cd28 1923qla25xx_pci_config(scsi_qla_host_t *vha)
c3a2f0df
AV		 1924{
1925 uint16_t w;
e315cd28 1926 struct qla_hw_data *ha = vha->hw;
c3a2f0df
AV		 1927
1928 pci_set_master(ha->pdev);
1929 pci_try_set_mwi(ha->pdev);
1930
1931 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
1932 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
1933 w &= ~PCI_COMMAND_INTX_DISABLE;
1934 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
1935
1936 /* PCIe -- adjust Maximum Read Request Size (2048). */
e67f1321 1937 if (pci_is_pcie(ha->pdev))
5ffd3a52 1938 pcie_set_readrq(ha->pdev, 4096);
c3a2f0df 1939
737faece 1940 pci_disable_rom(ha->pdev);
c3a2f0df
AV		 1941
1942 ha->chip_revision = ha->pdev->revision;
1943
1944 return QLA_SUCCESS;
1945}
1946
1da177e4
LT		 1947/**
1948 * qla2x00_isp_firmware() - Choose firmware image.
1949 * @ha: HA context
1950 *
1951 * Returns 0 on success.
1952 */
1953static int
e315cd28 1954qla2x00_isp_firmware(scsi_qla_host_t *vha)
1da177e4
LT		 1955{
1956 int rval;
42e421b1
AV		 1957 uint16_t loop_id, topo, sw_cap;
1958 uint8_t domain, area, al_pa;
e315cd28 1959 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 1960
1961 /* Assume loading risc code */
fa2a1ce5 1962 rval = QLA_FUNCTION_FAILED;
1da177e4
LT		 1963
1964 if (ha->flags.disable_risc_code_load) {
7c3df132 1965 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
1da177e4
LT		 1966
1967 /* Verify checksum of loaded RISC code. */
e315cd28 1968 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
42e421b1
AV		 1969 if (rval == QLA_SUCCESS) {
1970 /* And, verify we are not in ROM code. */
e315cd28 1971 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
42e421b1
AV		 1972 &area, &domain, &topo, &sw_cap);
1973 }
1da177e4
LT		 1974 }
1975
7c3df132
SK		 1976 if (rval)
1977 ql_dbg(ql_dbg_init, vha, 0x007a,
1978 "**** Load RISC code ****.\n");
1da177e4
LT		 1979
1980 return (rval);
1981}
1982
1983/**
1984 * qla2x00_reset_chip() - Reset ISP chip.
1985 * @ha: HA context
1986 *
1987 * Returns 0 on success.
1988 */
abbd8870 1989void
e315cd28 1990qla2x00_reset_chip(scsi_qla_host_t *vha)
1da177e4
LT		 1991{
1992 unsigned long flags = 0;
e315cd28 1993 struct qla_hw_data *ha = vha->hw;
3d71644c 1994 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 1995 uint32_t cnt;
1da177e4
LT		 1996 uint16_t cmd;
1997
85880801
AV		 1998 if (unlikely(pci_channel_offline(ha->pdev)))
1999 return;
2000
fd34f556 2001 ha->isp_ops->disable_intrs(ha);
1da177e4
LT		 2002
2003 spin_lock_irqsave(&ha->hardware_lock, flags);
2004
2005 /* Turn off master enable */
2006 cmd = 0;
2007 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2008 cmd &= ~PCI_COMMAND_MASTER;
2009 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2010
2011 if (!IS_QLA2100(ha)) {
2012 /* Pause RISC. */
2013 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
2014 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2015 for (cnt = 0; cnt < 30000; cnt++) {
2016 if ((RD_REG_WORD(&reg->hccr) &
2017 HCCR_RISC_PAUSE) != 0)
2018 break;
2019 udelay(100);
2020 }
2021 } else {
2022 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2023 udelay(10);
2024 }
2025
2026 /* Select FPM registers. */
2027 WRT_REG_WORD(&reg->ctrl_status, 0x20);
2028 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2029
2030 /* FPM Soft Reset. */
2031 WRT_REG_WORD(&reg->fpm_diag_config, 0x100);
2032 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2033
2034 /* Toggle Fpm Reset. */
2035 if (!IS_QLA2200(ha)) {
2036 WRT_REG_WORD(&reg->fpm_diag_config, 0x0);
2037 RD_REG_WORD(&reg->fpm_diag_config); /* PCI Posting. */
2038 }
2039
2040 /* Select frame buffer registers. */
2041 WRT_REG_WORD(&reg->ctrl_status, 0x10);
2042 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2043
2044 /* Reset frame buffer FIFOs. */
2045 if (IS_QLA2200(ha)) {
2046 WRT_FB_CMD_REG(ha, reg, 0xa000);
2047 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */
2048 } else {
2049 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2050
2051 /* Read back fb_cmd until zero or 3 seconds max */
2052 for (cnt = 0; cnt < 3000; cnt++) {
2053 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2054 break;
2055 udelay(100);
2056 }
2057 }
2058
2059 /* Select RISC module registers. */
2060 WRT_REG_WORD(&reg->ctrl_status, 0);
2061 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
2062
2063 /* Reset RISC processor. */
2064 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2065 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2066
2067 /* Release RISC processor. */
2068 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2069 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2070 }
2071
2072 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
2073 WRT_REG_WORD(&reg->hccr, HCCR_CLR_HOST_INT);
2074
2075 /* Reset ISP chip. */
2076 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2077
2078 /* Wait for RISC to recover from reset. */
2079 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2080 /*
2081 * It is necessary to for a delay here since the card doesn't
2082 * respond to PCI reads during a reset. On some architectures
2083 * this will result in an MCA.
2084 */
2085 udelay(20);
2086 for (cnt = 30000; cnt; cnt--) {
2087 if ((RD_REG_WORD(&reg->ctrl_status) &
2088 CSR_ISP_SOFT_RESET) == 0)
2089 break;
2090 udelay(100);
2091 }
2092 } else
2093 udelay(10);
2094
2095 /* Reset RISC processor. */
2096 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2097
2098 WRT_REG_WORD(&reg->semaphore, 0);
2099
2100 /* Release RISC processor. */
2101 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2102 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2103
2104 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2105 for (cnt = 0; cnt < 30000; cnt++) {
ffb39f03 2106 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
1da177e4 2107 break;
1da177e4
LT		 2108
2109 udelay(100);
2110 }
2111 } else
2112 udelay(100);
2113
2114 /* Turn on master enable */
2115 cmd |= PCI_COMMAND_MASTER;
2116 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2117
2118 /* Disable RISC pause on FPM parity error. */
2119 if (!IS_QLA2100(ha)) {
2120 WRT_REG_WORD(&reg->hccr, HCCR_DISABLE_PARITY_PAUSE);
2121 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
2122 }
2123
2124 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2125}
2126
b1d46989
MI		 2127/**
2128 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC.
2129 *
2130 * Returns 0 on success.
2131 */
fa492630 2132static int
b1d46989
MI		 2133qla81xx_reset_mpi(scsi_qla_host_t *vha)
2134{
2135 uint16_t mb[4] = {0x1010, 0, 1, 0};
2136
6246b8a1
GM		 2137 if (!IS_QLA81XX(vha->hw))
2138 return QLA_SUCCESS;
2139
b1d46989
MI		 2140 return qla81xx_write_mpi_register(vha, mb);
2141}
2142
0107109e 2143/**
88c26663 2144 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC.
0107109e
AV		 2145 * @ha: HA context
2146 *
2147 * Returns 0 on success.
2148 */
d14e72fb 2149static inline int
e315cd28 2150qla24xx_reset_risc(scsi_qla_host_t *vha)
0107109e
AV		 2151{
2152 unsigned long flags = 0;
e315cd28 2153 struct qla_hw_data *ha = vha->hw;
0107109e 2154 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
52c82823 2155 uint32_t cnt;
335a1cc9 2156 uint16_t wd;
b1d46989 2157 static int abts_cnt; /* ISP abort retry counts */
d14e72fb 2158 int rval = QLA_SUCCESS;
0107109e 2159
0107109e
AV		 2160 spin_lock_irqsave(&ha->hardware_lock, flags);
2161
2162 /* Reset RISC. */
2163 WRT_REG_DWORD(&reg->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2164 for (cnt = 0; cnt < 30000; cnt++) {
2165 if ((RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2166 break;
2167
2168 udelay(10);
2169 }
2170
d14e72fb
HM		 2171 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE))
2172 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2173
2174 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2175 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2176 RD_REG_DWORD(&reg->hccr),
2177 RD_REG_DWORD(&reg->ctrl_status),
2178 (RD_REG_DWORD(&reg->ctrl_status) & CSRX_DMA_ACTIVE));
2179
0107109e
AV		 2180 WRT_REG_DWORD(&reg->ctrl_status,
2181 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
335a1cc9 2182 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
88c26663 2183
335a1cc9 2184 udelay(100);
d14e72fb 2185
88c26663 2186 /* Wait for firmware to complete NVRAM accesses. */
52c82823 2187 RD_REG_WORD(&reg->mailbox0);
d14e72fb
HM		 2188 for (cnt = 10000; RD_REG_WORD(&reg->mailbox0) != 0 &&
2189 rval == QLA_SUCCESS; cnt--) {
88c26663 2190 barrier();
d14e72fb
HM		 2191 if (cnt)
2192 udelay(5);
2193 else
2194 rval = QLA_FUNCTION_TIMEOUT;
88c26663
AV		 2195 }
2196
d14e72fb
HM		 2197 if (rval == QLA_SUCCESS)
2198 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2199
2200 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2201 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2202 RD_REG_DWORD(&reg->hccr),
2203 RD_REG_DWORD(&reg->mailbox0));
2204
335a1cc9 2205 /* Wait for soft-reset to complete. */
52c82823 2206 RD_REG_DWORD(&reg->ctrl_status);
200ffb15 2207 for (cnt = 0; cnt < 60; cnt++) {
0107109e 2208 barrier();
d14e72fb
HM		 2209 if ((RD_REG_DWORD(&reg->ctrl_status) &
2210 CSRX_ISP_SOFT_RESET) == 0)
2211 break;
2212
2213 udelay(5);
0107109e 2214 }
d14e72fb
HM		 2215 if (!(RD_REG_DWORD(&reg->ctrl_status) & CSRX_ISP_SOFT_RESET))
2216 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2217
2218 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2219 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2220 RD_REG_DWORD(&reg->hccr),
2221 RD_REG_DWORD(&reg->ctrl_status));
0107109e 2222
b1d46989
MI		 2223 /* If required, do an MPI FW reset now */
2224 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2225 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2226 if (++abts_cnt < 5) {
2227 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2228 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2229 } else {
2230 /*
2231 * We exhausted the ISP abort retries. We have to
2232 * set the board offline.
2233 */
2234 abts_cnt = 0;
2235 vha->flags.online = 0;
2236 }
2237 }
2238 }
2239
0107109e
AV		 2240 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
2241 RD_REG_DWORD(&reg->hccr);
2242
2243 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
2244 RD_REG_DWORD(&reg->hccr);
2245
2246 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
2247 RD_REG_DWORD(&reg->hccr);
2248
52c82823 2249 RD_REG_WORD(&reg->mailbox0);
200ffb15 2250 for (cnt = 60; RD_REG_WORD(&reg->mailbox0) != 0 &&
d14e72fb 2251 rval == QLA_SUCCESS; cnt--) {
0107109e 2252 barrier();
d14e72fb
HM		 2253 if (cnt)
2254 udelay(5);
2255 else
2256 rval = QLA_FUNCTION_TIMEOUT;
0107109e 2257 }
d14e72fb
HM		 2258 if (rval == QLA_SUCCESS)
2259 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2260
2261 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2262 "Host Risc 0x%x, mailbox0 0x%x\n",
2263 RD_REG_DWORD(&reg->hccr),
2264 RD_REG_WORD(&reg->mailbox0));
0107109e
AV		 2265
2266 spin_unlock_irqrestore(&ha->hardware_lock, flags);
124f85e6 2267
d14e72fb
HM		 2268 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2269 "Driver in %s mode\n",
2270 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2271
124f85e6
AV		 2272 if (IS_NOPOLLING_TYPE(ha))
2273 ha->isp_ops->enable_intrs(ha);
d14e72fb
HM		 2274
2275 return rval;
0107109e
AV		 2276}
2277
4ea2c9c7
JC		 2278static void
2279qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2280{
2281 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2282
2283 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2284 *data = RD_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET);
2285
2286}
2287
2288static void
2289qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2290{
2291 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2292
2293 WRT_REG_DWORD(&reg->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2294 WRT_REG_DWORD(&reg->iobase_window + RISC_REGISTER_WINDOW_OFFET, data);
2295}
2296
2297static void
2298qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2299{
4ea2c9c7
JC		 2300 uint32_t wd32 = 0;
2301 uint delta_msec = 100;
2302 uint elapsed_msec = 0;
2303 uint timeout_msec;
2304 ulong n;
2305
cc790764
JC		 2306 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2307 vha->hw->pdev->subsystem_device != 0x0240)
4ea2c9c7
JC		 2308 return;
2309
8dd7e3a5
JC		 2310 WRT_REG_DWORD(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2311 udelay(100);
2312
4ea2c9c7
JC		 2313attempt:
2314 timeout_msec = TIMEOUT_SEMAPHORE;
2315 n = timeout_msec / delta_msec;
2316 while (n--) {
2317 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
2318 qla25xx_read_risc_sema_reg(vha, &wd32);
2319 if (wd32 & RISC_SEMAPHORE)
2320 break;
2321 msleep(delta_msec);
2322 elapsed_msec += delta_msec;
2323 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2324 goto force;
2325 }
2326
2327 if (!(wd32 & RISC_SEMAPHORE))
2328 goto force;
2329
2330 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2331 goto acquired;
2332
2333 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
2334 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
2335 n = timeout_msec / delta_msec;
2336 while (n--) {
2337 qla25xx_read_risc_sema_reg(vha, &wd32);
2338 if (!(wd32 & RISC_SEMAPHORE_FORCE))
2339 break;
2340 msleep(delta_msec);
2341 elapsed_msec += delta_msec;
2342 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
2343 goto force;
2344 }
2345
2346 if (wd32 & RISC_SEMAPHORE_FORCE)
2347 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
2348
2349 goto attempt;
2350
2351force:
2352 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
2353
2354acquired:
2355 return;
2356}
2357
88c26663
AV		 2358/**
2359 * qla24xx_reset_chip() - Reset ISP24xx chip.
2360 * @ha: HA context
2361 *
2362 * Returns 0 on success.
2363 */
2364void
e315cd28 2365qla24xx_reset_chip(scsi_qla_host_t *vha)
88c26663 2366{
e315cd28 2367 struct qla_hw_data *ha = vha->hw;
85880801
AV		 2368
2369 if (pci_channel_offline(ha->pdev) &&
2370 ha->flags.pci_channel_io_perm_failure) {
2371 return;
2372 }
2373
fd34f556 2374 ha->isp_ops->disable_intrs(ha);
88c26663 2375
4ea2c9c7
JC		 2376 qla25xx_manipulate_risc_semaphore(vha);
2377
88c26663 2378 /* Perform RISC reset. */
e315cd28 2379 qla24xx_reset_risc(vha);
88c26663
AV		 2380}
2381
1da177e4
LT		 2382/**
2383 * qla2x00_chip_diag() - Test chip for proper operation.
2384 * @ha: HA context
2385 *
2386 * Returns 0 on success.
2387 */
abbd8870 2388int
e315cd28 2389qla2x00_chip_diag(scsi_qla_host_t *vha)
1da177e4
LT		 2390{
2391 int rval;
e315cd28 2392 struct qla_hw_data *ha = vha->hw;
3d71644c 2393 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 2394 unsigned long flags = 0;
2395 uint16_t data;
2396 uint32_t cnt;
2397 uint16_t mb[5];
73208dfd 2398 struct req_que *req = ha->req_q_map[0];
1da177e4
LT		 2399
2400 /* Assume a failed state */
2401 rval = QLA_FUNCTION_FAILED;
2402
7c3df132
SK		 2403 ql_dbg(ql_dbg_init, vha, 0x007b,
2404 "Testing device at %lx.\n", (u_long)&reg->flash_address);
1da177e4
LT		 2405
2406 spin_lock_irqsave(&ha->hardware_lock, flags);
2407
2408 /* Reset ISP chip. */
2409 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
2410
2411 /*
2412 * We need to have a delay here since the card will not respond while
2413 * in reset causing an MCA on some architectures.
2414 */
2415 udelay(20);
2416 data = qla2x00_debounce_register(&reg->ctrl_status);
2417 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
2418 udelay(5);
2419 data = RD_REG_WORD(&reg->ctrl_status);
2420 barrier();
2421 }
2422
2423 if (!cnt)
2424 goto chip_diag_failed;
2425
7c3df132
SK		 2426 ql_dbg(ql_dbg_init, vha, 0x007c,
2427 "Reset register cleared by chip reset.\n");
1da177e4
LT		 2428
2429 /* Reset RISC processor. */
2430 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
2431 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
2432
2433 /* Workaround for QLA2312 PCI parity error */
2434 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2435 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
2436 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
2437 udelay(5);
2438 data = RD_MAILBOX_REG(ha, reg, 0);
fa2a1ce5 2439 barrier();
1da177e4
LT		 2440 }
2441 } else
2442 udelay(10);
2443
2444 if (!cnt)
2445 goto chip_diag_failed;
2446
2447 /* Check product ID of chip */
5a68a1c2 2448 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
1da177e4
LT		 2449
2450 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
2451 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
2452 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
2453 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
2454 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
2455 mb[3] != PROD_ID_3) {
7c3df132
SK		 2456 ql_log(ql_log_warn, vha, 0x0062,
2457 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
2458 mb[1], mb[2], mb[3]);
1da177e4
LT		 2459
2460 goto chip_diag_failed;
2461 }
2462 ha->product_id[0] = mb[1];
2463 ha->product_id[1] = mb[2];
2464 ha->product_id[2] = mb[3];
2465 ha->product_id[3] = mb[4];
2466
2467 /* Adjust fw RISC transfer size */
73208dfd 2468 if (req->length > 1024)
1da177e4
LT		 2469 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
2470 else
2471 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
73208dfd 2472 req->length;
1da177e4
LT		 2473
2474 if (IS_QLA2200(ha) &&
2475 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
2476 /* Limit firmware transfer size with a 2200A */
7c3df132 2477 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
1da177e4 2478
ea5b6382 2479 ha->device_type |= DT_ISP2200A;
1da177e4
LT		 2480 ha->fw_transfer_size = 128;
2481 }
2482
2483 /* Wrap Incoming Mailboxes Test. */
2484 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2485
7c3df132 2486 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
e315cd28 2487 rval = qla2x00_mbx_reg_test(vha);
7c3df132
SK		 2488 if (rval)
2489 ql_log(ql_log_warn, vha, 0x0080,
2490 "Failed mailbox send register test.\n");
2491 else
1da177e4
LT		 2492 /* Flag a successful rval */
2493 rval = QLA_SUCCESS;
1da177e4
LT		 2494 spin_lock_irqsave(&ha->hardware_lock, flags);
2495
2496chip_diag_failed:
2497 if (rval)
7c3df132
SK		 2498 ql_log(ql_log_info, vha, 0x0081,
2499 "Chip diagnostics **** FAILED ****.\n");
1da177e4
LT		 2500
2501 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2502
2503 return (rval);
2504}
2505
0107109e
AV		 2506/**
2507 * qla24xx_chip_diag() - Test ISP24xx for proper operation.
2508 * @ha: HA context
2509 *
2510 * Returns 0 on success.
2511 */
2512int
e315cd28 2513qla24xx_chip_diag(scsi_qla_host_t *vha)
0107109e
AV		 2514{
2515 int rval;
e315cd28 2516 struct qla_hw_data *ha = vha->hw;
73208dfd 2517 struct req_que *req = ha->req_q_map[0];
0107109e 2518
7ec0effd 2519 if (IS_P3P_TYPE(ha))
a9083016
GM		 2520 return QLA_SUCCESS;
2521
73208dfd 2522 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
0107109e 2523
e315cd28 2524 rval = qla2x00_mbx_reg_test(vha);
0107109e 2525 if (rval) {
7c3df132
SK		 2526 ql_log(ql_log_warn, vha, 0x0082,
2527 "Failed mailbox send register test.\n");
0107109e
AV		 2528 } else {
2529 /* Flag a successful rval */
2530 rval = QLA_SUCCESS;
2531 }
2532
2533 return rval;
2534}
2535
a7a167bf 2536void
e315cd28 2537qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
0107109e 2538{
a7a167bf
AV		 2539 int rval;
2540 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
73208dfd 2541 eft_size, fce_size, mq_size;
df613b96
AV		 2542 dma_addr_t tc_dma;
2543 void *tc;
e315cd28 2544 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 2545 struct req_que *req = ha->req_q_map[0];
2546 struct rsp_que *rsp = ha->rsp_q_map[0];
a7a167bf
AV		 2547
2548 if (ha->fw_dump) {
7c3df132
SK		 2549 ql_dbg(ql_dbg_init, vha, 0x00bd,
2550 "Firmware dump already allocated.\n");
a7a167bf
AV		 2551 return;
2552 }
d4e3e04d 2553
0107109e 2554 ha->fw_dumped = 0;
61f098dd 2555 ha->fw_dump_cap_flags = 0;
f73cb695
CD		 2556 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
2557 req_q_size = rsp_q_size = 0;
2558
2559 if (IS_QLA27XX(ha))
2560 goto try_fce;
2561
d4e3e04d 2562 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
a7a167bf 2563 fixed_size = sizeof(struct qla2100_fw_dump);
d4e3e04d 2564 } else if (IS_QLA23XX(ha)) {
a7a167bf
AV		 2565 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
2566 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
2567 sizeof(uint16_t);
e428924c 2568 } else if (IS_FWI2_CAPABLE(ha)) {
b20f02e1 2569 if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
6246b8a1
GM		 2570 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
2571 else if (IS_QLA81XX(ha))
3a03eb79
AV		 2572 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
2573 else if (IS_QLA25XX(ha))
2574 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
2575 else
2576 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
f73cb695 2577
a7a167bf
AV		 2578 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
2579 sizeof(uint32_t);
050c9bb1 2580 if (ha->mqenable) {
b20f02e1 2581 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
6246b8a1 2582 mq_size = sizeof(struct qla2xxx_mq_chain);
050c9bb1
GM		 2583 /*
2584 * Allocate maximum buffer size for all queues.
2585 * Resizing must be done at end-of-dump processing.
2586 */
2587 mq_size += ha->max_req_queues *
2588 (req->length * sizeof(request_t));
2589 mq_size += ha->max_rsp_queues *
2590 (rsp->length * sizeof(response_t));
2591 }
00876ae8 2592 if (ha->tgt.atio_ring)
2d70c103 2593 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
df613b96 2594 /* Allocate memory for Fibre Channel Event Buffer. */
f73cb695
CD		 2595 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
2596 !IS_QLA27XX(ha))
436a7b11 2597 goto try_eft;
df613b96 2598
f73cb695
CD		 2599try_fce:
2600 if (ha->fce)
2601 dma_free_coherent(&ha->pdev->dev,
2602 FCE_SIZE, ha->fce, ha->fce_dma);
2603
2604 /* Allocate memory for Fibre Channel Event Buffer. */
0ea85b50
JP		 2605 tc = dma_zalloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
2606 GFP_KERNEL);
df613b96 2607 if (!tc) {
7c3df132
SK		 2608 ql_log(ql_log_warn, vha, 0x00be,
2609 "Unable to allocate (%d KB) for FCE.\n",
2610 FCE_SIZE / 1024);
17d98630 2611 goto try_eft;
df613b96
AV		 2612 }
2613
e315cd28 2614 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
df613b96
AV		 2615 ha->fce_mb, &ha->fce_bufs);
2616 if (rval) {
7c3df132
SK		 2617 ql_log(ql_log_warn, vha, 0x00bf,
2618 "Unable to initialize FCE (%d).\n", rval);
df613b96
AV		 2619 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc,
2620 tc_dma);
2621 ha->flags.fce_enabled = 0;
17d98630 2622 goto try_eft;
df613b96 2623 }
cfb0919c 2624 ql_dbg(ql_dbg_init, vha, 0x00c0,
7c3df132 2625 "Allocate (%d KB) for FCE...\n", FCE_SIZE / 1024);
df613b96 2626
7d9dade3 2627 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
df613b96
AV		 2628 ha->flags.fce_enabled = 1;
2629 ha->fce_dma = tc_dma;
2630 ha->fce = tc;
f73cb695 2631
436a7b11 2632try_eft:
f73cb695
CD		 2633 if (ha->eft)
2634 dma_free_coherent(&ha->pdev->dev,
2635 EFT_SIZE, ha->eft, ha->eft_dma);
2636
436a7b11 2637 /* Allocate memory for Extended Trace Buffer. */
0ea85b50
JP		 2638 tc = dma_zalloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
2639 GFP_KERNEL);
436a7b11 2640 if (!tc) {
7c3df132
SK		 2641 ql_log(ql_log_warn, vha, 0x00c1,
2642 "Unable to allocate (%d KB) for EFT.\n",
2643 EFT_SIZE / 1024);
436a7b11
AV		 2644 goto cont_alloc;
2645 }
2646
e315cd28 2647 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
436a7b11 2648 if (rval) {
7c3df132
SK		 2649 ql_log(ql_log_warn, vha, 0x00c2,
2650 "Unable to initialize EFT (%d).\n", rval);
436a7b11
AV		 2651 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc,
2652 tc_dma);
2653 goto cont_alloc;
2654 }
cfb0919c 2655 ql_dbg(ql_dbg_init, vha, 0x00c3,
7c3df132 2656 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
436a7b11
AV		 2657
2658 eft_size = EFT_SIZE;
2659 ha->eft_dma = tc_dma;
2660 ha->eft = tc;
d4e3e04d 2661 }
f73cb695 2662
a7a167bf 2663cont_alloc:
f73cb695
CD		 2664 if (IS_QLA27XX(ha)) {
2665 if (!ha->fw_dump_template) {
2666 ql_log(ql_log_warn, vha, 0x00ba,
2667 "Failed missing fwdump template\n");
2668 return;
2669 }
2670 dump_size = qla27xx_fwdt_calculate_dump_size(vha);
2671 ql_dbg(ql_dbg_init, vha, 0x00fa,
2672 "-> allocating fwdump (%x bytes)...\n", dump_size);
2673 goto allocate;
2674 }
2675
73208dfd
AC		 2676 req_q_size = req->length * sizeof(request_t);
2677 rsp_q_size = rsp->length * sizeof(response_t);
a7a167bf 2678 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
2afa19a9 2679 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size + eft_size;
bb99de67
AV		 2680 ha->chain_offset = dump_size;
2681 dump_size += mq_size + fce_size;
d4e3e04d 2682
b945e777
QT		 2683 if (ha->exchoffld_buf)
2684 dump_size += sizeof(struct qla2xxx_offld_chain) +
2685 ha->exchoffld_size;
2686 if (ha->exlogin_buf)
2687 dump_size += sizeof(struct qla2xxx_offld_chain) +
2688 ha->exlogin_size;
2689
f73cb695 2690allocate:
d4e3e04d 2691 ha->fw_dump = vmalloc(dump_size);
a7a167bf 2692 if (!ha->fw_dump) {
7c3df132
SK		 2693 ql_log(ql_log_warn, vha, 0x00c4,
2694 "Unable to allocate (%d KB) for firmware dump.\n",
2695 dump_size / 1024);
a7a167bf 2696
e30d1756
MI		 2697 if (ha->fce) {
2698 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce,
2699 ha->fce_dma);
2700 ha->fce = NULL;
2701 ha->fce_dma = 0;
2702 }
2703
a7a167bf
AV		 2704 if (ha->eft) {
2705 dma_free_coherent(&ha->pdev->dev, eft_size, ha->eft,
2706 ha->eft_dma);
2707 ha->eft = NULL;
2708 ha->eft_dma = 0;
2709 }
2710 return;
2711 }
f73cb695 2712 ha->fw_dump_len = dump_size;
cfb0919c 2713 ql_dbg(ql_dbg_init, vha, 0x00c5,
7c3df132 2714 "Allocated (%d KB) for firmware dump.\n", dump_size / 1024);
a7a167bf 2715
f73cb695
CD		 2716 if (IS_QLA27XX(ha))
2717 return;
2718
a7a167bf
AV		 2719 ha->fw_dump->signature[0] = 'Q';
2720 ha->fw_dump->signature[1] = 'L';
2721 ha->fw_dump->signature[2] = 'G';
2722 ha->fw_dump->signature[3] = 'C';
ad950360 2723 ha->fw_dump->version = htonl(1);
a7a167bf
AV		 2724
2725 ha->fw_dump->fixed_size = htonl(fixed_size);
2726 ha->fw_dump->mem_size = htonl(mem_size);
2727 ha->fw_dump->req_q_size = htonl(req_q_size);
2728 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
2729
2730 ha->fw_dump->eft_size = htonl(eft_size);
2731 ha->fw_dump->eft_addr_l = htonl(LSD(ha->eft_dma));
2732 ha->fw_dump->eft_addr_h = htonl(MSD(ha->eft_dma));
2733
2734 ha->fw_dump->header_size =
2735 htonl(offsetof(struct qla2xxx_fw_dump, isp));
0107109e
AV		 2736}
2737
18e7555a
AV		 2738static int
2739qla81xx_mpi_sync(scsi_qla_host_t *vha)
2740{
2741#define MPS_MASK 0xe0
2742 int rval;
2743 uint16_t dc;
2744 uint32_t dw;
18e7555a
AV		 2745
2746 if (!IS_QLA81XX(vha->hw))
2747 return QLA_SUCCESS;
2748
2749 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
2750 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2751 ql_log(ql_log_warn, vha, 0x0105,
2752 "Unable to acquire semaphore.\n");
18e7555a
AV		 2753 goto done;
2754 }
2755
2756 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
2757 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
2758 if (rval != QLA_SUCCESS) {
7c3df132 2759 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
18e7555a
AV		 2760 goto done_release;
2761 }
2762
2763 dc &= MPS_MASK;
2764 if (dc == (dw & MPS_MASK))
2765 goto done_release;
2766
2767 dw &= ~MPS_MASK;
2768 dw |= dc;
2769 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
2770 if (rval != QLA_SUCCESS) {
7c3df132 2771 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
18e7555a
AV		 2772 }
2773
2774done_release:
2775 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
2776 if (rval != QLA_SUCCESS) {
7c3df132
SK		 2777 ql_log(ql_log_warn, vha, 0x006d,
2778 "Unable to release semaphore.\n");
18e7555a
AV		 2779 }
2780
2781done:
2782 return rval;
2783}
2784
8d93f550
CD		 2785int
2786qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
2787{
2788 /* Don't try to reallocate the array */
2789 if (req->outstanding_cmds)
2790 return QLA_SUCCESS;
2791
d7459527 2792 if (!IS_FWI2_CAPABLE(ha))
8d93f550
CD		 2793 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
2794 else {
03e8c680
QT		 2795 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
2796 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
8d93f550 2797 else
03e8c680 2798 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
8d93f550
CD		 2799 }
2800
2801 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2802 req->num_outstanding_cmds, GFP_KERNEL);
2803
2804 if (!req->outstanding_cmds) {
2805 /*
2806 * Try to allocate a minimal size just so we can get through
2807 * initialization.
2808 */
2809 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
2810 req->outstanding_cmds = kzalloc(sizeof(srb_t *) *
2811 req->num_outstanding_cmds, GFP_KERNEL);
2812
2813 if (!req->outstanding_cmds) {
2814 ql_log(ql_log_fatal, NULL, 0x0126,
2815 "Failed to allocate memory for "
2816 "outstanding_cmds for req_que %p.\n", req);
2817 req->num_outstanding_cmds = 0;
2818 return QLA_FUNCTION_FAILED;
2819 }
2820 }
2821
2822 return QLA_SUCCESS;
2823}
2824
e4e3a2ce
QT		 2825#define PRINT_FIELD(_field, _flag, _str) { \
2826 if (a0->_field & _flag) {\
2827 if (p) {\
2828 strcat(ptr, "|");\
2829 ptr++;\
2830 leftover--;\
2831 } \
2832 len = snprintf(ptr, leftover, "%s", _str); \
2833 p = 1;\
2834 leftover -= len;\
2835 ptr += len; \
2836 } \
2837}
2838
2839static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
2840{
2841#define STR_LEN 64
2842 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
2843 u8 str[STR_LEN], *ptr, p;
2844 int leftover, len;
2845
2846 memset(str, 0, STR_LEN);
2847 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
2848 ql_dbg(ql_dbg_init, vha, 0x015a,
2849 "SFP MFG Name: %s\n", str);
2850
2851 memset(str, 0, STR_LEN);
2852 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
2853 ql_dbg(ql_dbg_init, vha, 0x015c,
2854 "SFP Part Name: %s\n", str);
2855
2856 /* media */
2857 memset(str, 0, STR_LEN);
2858 ptr = str;
2859 leftover = STR_LEN;
2860 p = len = 0;
2861 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
2862 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
2863 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
2864 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
2865 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
2866 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
2867 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
2868 ql_dbg(ql_dbg_init, vha, 0x0160,
2869 "SFP Media: %s\n", str);
2870
2871 /* link length */
2872 memset(str, 0, STR_LEN);
2873 ptr = str;
2874 leftover = STR_LEN;
2875 p = len = 0;
2876 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
2877 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
2878 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
2879 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
2880 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
2881 ql_dbg(ql_dbg_init, vha, 0x0196,
2882 "SFP Link Length: %s\n", str);
2883
2884 memset(str, 0, STR_LEN);
2885 ptr = str;
2886 leftover = STR_LEN;
2887 p = len = 0;
2888 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
2889 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
2890 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
2891 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
2892 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
2893 ql_dbg(ql_dbg_init, vha, 0x016e,
2894 "SFP FC Link Tech: %s\n", str);
2895
2896 if (a0->length_km)
2897 ql_dbg(ql_dbg_init, vha, 0x016f,
2898 "SFP Distant: %d km\n", a0->length_km);
2899 if (a0->length_100m)
2900 ql_dbg(ql_dbg_init, vha, 0x0170,
2901 "SFP Distant: %d m\n", a0->length_100m*100);
2902 if (a0->length_50um_10m)
2903 ql_dbg(ql_dbg_init, vha, 0x0189,
2904 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
2905 if (a0->length_62um_10m)
2906 ql_dbg(ql_dbg_init, vha, 0x018a,
2907 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
2908 if (a0->length_om4_10m)
2909 ql_dbg(ql_dbg_init, vha, 0x0194,
2910 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
2911 if (a0->length_om3_10m)
2912 ql_dbg(ql_dbg_init, vha, 0x0195,
2913 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
2914}
2915
2916
2917/*
2918 * Return Code:
2919 * QLA_SUCCESS: no action
2920 * QLA_INTERFACE_ERROR: SFP is not there.
2921 * QLA_FUNCTION_FAILED: detected New SFP
2922 */
2923int
2924qla24xx_detect_sfp(scsi_qla_host_t *vha)
2925{
2926 int rc = QLA_SUCCESS;
2927 struct sff_8247_a0 *a;
2928 struct qla_hw_data *ha = vha->hw;
2929
2930 if (!AUTO_DETECT_SFP_SUPPORT(vha))
2931 goto out;
2932
2933 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
2934 if (rc)
2935 goto out;
2936
2937 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
2938 qla2xxx_print_sfp_info(vha);
2939
2940 if (a->fc_ll_cc7 & FC_LL_VL || a->fc_ll_cc7 & FC_LL_L) {
2941 /* long range */
2942 ha->flags.detected_lr_sfp = 1;
2943
2944 if (a->length_km > 5 || a->length_100m > 50)
2945 ha->long_range_distance = LR_DISTANCE_10K;
2946 else
2947 ha->long_range_distance = LR_DISTANCE_5K;
2948
2949 if (ha->flags.detected_lr_sfp != ha->flags.using_lr_setting)
2950 ql_dbg(ql_dbg_async, vha, 0x507b,
2951 "Detected Long Range SFP.\n");
2952 } else {
2953 /* short range */
2954 ha->flags.detected_lr_sfp = 0;
2955 if (ha->flags.using_lr_setting)
2956 ql_dbg(ql_dbg_async, vha, 0x5084,
2957 "Detected Short Range SFP.\n");
2958 }
2959
2960 if (!vha->flags.init_done)
2961 rc = QLA_SUCCESS;
2962out:
2963 return rc;
2964}
2965
1da177e4
LT		 2966/**
2967 * qla2x00_setup_chip() - Load and start RISC firmware.
2968 * @ha: HA context
2969 *
2970 * Returns 0 on success.
2971 */
2972static int
e315cd28 2973qla2x00_setup_chip(scsi_qla_host_t *vha)
1da177e4 2974{
0107109e
AV		 2975 int rval;
2976 uint32_t srisc_address = 0;
e315cd28 2977 struct qla_hw_data *ha = vha->hw;
3db0652e
AV		 2978 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2979 unsigned long flags;
dda772e8 2980 uint16_t fw_major_version;
3db0652e 2981
7ec0effd 2982 if (IS_P3P_TYPE(ha)) {
a9083016 2983 rval = ha->isp_ops->load_risc(vha, &srisc_address);
14e303d9
AV		 2984 if (rval == QLA_SUCCESS) {
2985 qla2x00_stop_firmware(vha);
a9083016 2986 goto enable_82xx_npiv;
14e303d9 2987 } else
b963752f 2988 goto failed;
a9083016
GM		 2989 }
2990
3db0652e
AV		 2991 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
2992 /* Disable SRAM, Instruction RAM and GP RAM parity. */
2993 spin_lock_irqsave(&ha->hardware_lock, flags);
2994 WRT_REG_WORD(&reg->hccr, (HCCR_ENABLE_PARITY + 0x0));
2995 RD_REG_WORD(&reg->hccr);
2996 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2997 }
1da177e4 2998
18e7555a
AV		 2999 qla81xx_mpi_sync(vha);
3000
1da177e4 3001 /* Load firmware sequences */
e315cd28 3002 rval = ha->isp_ops->load_risc(vha, &srisc_address);
0107109e 3003 if (rval == QLA_SUCCESS) {
7c3df132
SK		 3004 ql_dbg(ql_dbg_init, vha, 0x00c9,
3005 "Verifying Checksum of loaded RISC code.\n");
1da177e4 3006
e315cd28 3007 rval = qla2x00_verify_checksum(vha, srisc_address);
1da177e4
LT		 3008 if (rval == QLA_SUCCESS) {
3009 /* Start firmware execution. */
7c3df132
SK		 3010 ql_dbg(ql_dbg_init, vha, 0x00ca,
3011 "Starting firmware.\n");
1da177e4 3012
b0d6cabd
HM		 3013 if (ql2xexlogins)
3014 ha->flags.exlogins_enabled = 1;
3015
99e1b683 3016 if (qla_is_exch_offld_enabled(vha))
2f56a7f1
HM		 3017 ha->flags.exchoffld_enabled = 1;
3018
e315cd28 3019 rval = qla2x00_execute_fw(vha, srisc_address);
1da177e4 3020 /* Retrieve firmware information. */
dda772e8 3021 if (rval == QLA_SUCCESS) {
e4e3a2ce
QT		 3022 qla24xx_detect_sfp(vha);
3023
b0d6cabd
HM		 3024 rval = qla2x00_set_exlogins_buffer(vha);
3025 if (rval != QLA_SUCCESS)
3026 goto failed;
3027
2f56a7f1
HM		 3028 rval = qla2x00_set_exchoffld_buffer(vha);
3029 if (rval != QLA_SUCCESS)
3030 goto failed;
3031
a9083016 3032enable_82xx_npiv:
dda772e8 3033 fw_major_version = ha->fw_major_version;
7ec0effd 3034 if (IS_P3P_TYPE(ha))
3173167f 3035 qla82xx_check_md_needed(vha);
6246b8a1
GM		 3036 else
3037 rval = qla2x00_get_fw_version(vha);
ca9e9c3e
AV		 3038 if (rval != QLA_SUCCESS)
3039 goto failed;
2c3dfe3f 3040 ha->flags.npiv_supported = 0;
e315cd28 3041 if (IS_QLA2XXX_MIDTYPE(ha) &&
946fb891 3042 (ha->fw_attributes & BIT_2)) {
2c3dfe3f 3043 ha->flags.npiv_supported = 1;
4d0ea247
SJ		 3044 if ((!ha->max_npiv_vports) ||
3045 ((ha->max_npiv_vports + 1) %
eb66dc60 3046 MIN_MULTI_ID_FABRIC))
4d0ea247 3047 ha->max_npiv_vports =
eb66dc60 3048 MIN_MULTI_ID_FABRIC - 1;
4d0ea247 3049 }
03e8c680 3050 qla2x00_get_resource_cnts(vha);
d743de66 3051
8d93f550
CD		 3052 /*
3053 * Allocate the array of outstanding commands
3054 * now that we know the firmware resources.
3055 */
3056 rval = qla2x00_alloc_outstanding_cmds(ha,
3057 vha->req);
3058 if (rval != QLA_SUCCESS)
3059 goto failed;
3060
be5ea3cf 3061 if (!fw_major_version && ql2xallocfwdump
7ec0effd 3062 && !(IS_P3P_TYPE(ha)))
08de2844 3063 qla2x00_alloc_fw_dump(vha);
3b6e5b9d
CD		 3064 } else {
3065 goto failed;
1da177e4
LT		 3066 }
3067 } else {
7c3df132
SK		 3068 ql_log(ql_log_fatal, vha, 0x00cd,
3069 "ISP Firmware failed checksum.\n");
3070 goto failed;
1da177e4 3071 }
c74d88a4
AV		 3072 } else
3073 goto failed;
1da177e4 3074
3db0652e
AV		 3075 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3076 /* Enable proper parity. */
3077 spin_lock_irqsave(&ha->hardware_lock, flags);
3078 if (IS_QLA2300(ha))
3079 /* SRAM parity */
3080 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x1);
3081 else
3082 /* SRAM, Instruction RAM and GP RAM parity */
3083 WRT_REG_WORD(&reg->hccr, HCCR_ENABLE_PARITY + 0x7);
3084 RD_REG_WORD(&reg->hccr);
3085 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3086 }
3087
f3982d89
CD		 3088 if (IS_QLA27XX(ha))
3089 ha->flags.fac_supported = 1;
3090 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
1d2874de
JC		 3091 uint32_t size;
3092
3093 rval = qla81xx_fac_get_sector_size(vha, &size);
3094 if (rval == QLA_SUCCESS) {
3095 ha->flags.fac_supported = 1;
3096 ha->fdt_block_size = size << 2;
3097 } else {
7c3df132 3098 ql_log(ql_log_warn, vha, 0x00ce,
1d2874de
JC		 3099 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3100 ha->fw_major_version, ha->fw_minor_version,
3101 ha->fw_subminor_version);
1ca60e3b 3102
f73cb695 3103 if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
6246b8a1
GM		 3104 ha->flags.fac_supported = 0;
3105 rval = QLA_SUCCESS;
3106 }
1d2874de
JC		 3107 }
3108 }
ca9e9c3e 3109failed:
1da177e4 3110 if (rval) {
7c3df132
SK		 3111 ql_log(ql_log_fatal, vha, 0x00cf,
3112 "Setup chip ****FAILED****.\n");
1da177e4
LT		 3113 }
3114
3115 return (rval);
3116}
3117
3118/**
3119 * qla2x00_init_response_q_entries() - Initializes response queue entries.
3120 * @ha: HA context
3121 *
3122 * Beginning of request ring has initialization control block already built
3123 * by nvram config routine.
3124 *
3125 * Returns 0 on success.
3126 */
73208dfd
AC		 3127void
3128qla2x00_init_response_q_entries(struct rsp_que *rsp)
1da177e4
LT		 3129{
3130 uint16_t cnt;
3131 response_t *pkt;
3132
2afa19a9
AC		 3133 rsp->ring_ptr = rsp->ring;
3134 rsp->ring_index = 0;
3135 rsp->status_srb = NULL;
e315cd28
AC		 3136 pkt = rsp->ring_ptr;
3137 for (cnt = 0; cnt < rsp->length; cnt++) {
1da177e4
LT		 3138 pkt->signature = RESPONSE_PROCESSED;
3139 pkt++;
3140 }
1da177e4
LT		 3141}
3142
3143/**
3144 * qla2x00_update_fw_options() - Read and process firmware options.
3145 * @ha: HA context
3146 *
3147 * Returns 0 on success.
3148 */
abbd8870 3149void
e315cd28 3150qla2x00_update_fw_options(scsi_qla_host_t *vha)
1da177e4
LT		 3151{
3152 uint16_t swing, emphasis, tx_sens, rx_sens;
e315cd28 3153 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 3154
3155 memset(ha->fw_options, 0, sizeof(ha->fw_options));
e315cd28 3156 qla2x00_get_fw_options(vha, ha->fw_options);
1da177e4
LT		 3157
3158 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3159 return;
3160
3161 /* Serial Link options. */
7c3df132
SK		 3162 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3163 "Serial link options.\n");
3164 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3165 (uint8_t *)&ha->fw_seriallink_options,
3166 sizeof(ha->fw_seriallink_options));
1da177e4
LT		 3167
3168 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3169 if (ha->fw_seriallink_options[3] & BIT_2) {
3170 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3171
3172 /* 1G settings */
3173 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3174 emphasis = (ha->fw_seriallink_options[2] &
3175 (BIT_4 | BIT_3)) >> 3;
3176 tx_sens = ha->fw_seriallink_options[0] &
fa2a1ce5 3177 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3178 rx_sens = (ha->fw_seriallink_options[0] &
3179 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3180 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3181 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3182 if (rx_sens == 0x0)
3183 rx_sens = 0x3;
3184 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3185 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3186 ha->fw_options[10] |= BIT_5 |
3187 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3188 (tx_sens & (BIT_1 | BIT_0));
3189
3190 /* 2G settings */
3191 swing = (ha->fw_seriallink_options[2] &
3192 (BIT_7 | BIT_6 | BIT_5)) >> 5;
3193 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
3194 tx_sens = ha->fw_seriallink_options[1] &
fa2a1ce5 3195 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1da177e4
LT		 3196 rx_sens = (ha->fw_seriallink_options[1] &
3197 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3198 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
3199 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3200 if (rx_sens == 0x0)
3201 rx_sens = 0x3;
3202 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
3203 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3204 ha->fw_options[11] |= BIT_5 |
3205 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3206 (tx_sens & (BIT_1 | BIT_0));
3207 }
3208
3209 /* FCP2 options. */
3210 /* Return command IOCBs without waiting for an ABTS to complete. */
3211 ha->fw_options[3] |= BIT_13;
3212
3213 /* LED scheme. */
3214 if (ha->flags.enable_led_scheme)
3215 ha->fw_options[2] |= BIT_12;
3216
48c02fde
AV		 3217 /* Detect ISP6312. */
3218 if (IS_QLA6312(ha))
3219 ha->fw_options[2] |= BIT_13;
3220
088d09d4
GM		 3221 /* Set Retry FLOGI in case of P2P connection */
3222 if (ha->operating_mode == P2P) {
3223 ha->fw_options[2] |= BIT_3;
3224 ql_dbg(ql_dbg_disc, vha, 0x2100,
3225 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3226 __func__, ha->fw_options[2]);
3227 }
3228
1da177e4 3229 /* Update firmware options. */
e315cd28 3230 qla2x00_set_fw_options(vha, ha->fw_options);
1da177e4
LT		 3231}
3232
0107109e 3233void
e315cd28 3234qla24xx_update_fw_options(scsi_qla_host_t *vha)
0107109e
AV		 3235{
3236 int rval;
e315cd28 3237 struct qla_hw_data *ha = vha->hw;
0107109e 3238
7ec0effd 3239 if (IS_P3P_TYPE(ha))
a9083016
GM		 3240 return;
3241
f198cafa
HM		 3242 /* Hold status IOCBs until ABTS response received. */
3243 if (ql2xfwholdabts)
3244 ha->fw_options[3] |= BIT_12;
3245
088d09d4
GM		 3246 /* Set Retry FLOGI in case of P2P connection */
3247 if (ha->operating_mode == P2P) {
3248 ha->fw_options[2] |= BIT_3;
3249 ql_dbg(ql_dbg_disc, vha, 0x2101,
3250 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
3251 __func__, ha->fw_options[2]);
3252 }
3253
41dc529a 3254 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
3c4810ff
QT		 3255 if (ql2xmvasynctoatio &&
3256 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
41dc529a
QT		 3257 if (qla_tgt_mode_enabled(vha) ||
3258 qla_dual_mode_enabled(vha))
3259 ha->fw_options[2] |= BIT_11;
3260 else
3261 ha->fw_options[2] &= ~BIT_11;
3262 }
3263
f7e761f5
QT		 3264 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3265 /*
3266 * Tell FW to track each exchange to prevent
3267 * driver from using stale exchange.
3268 */
3269 if (qla_tgt_mode_enabled(vha) ||
3270 qla_dual_mode_enabled(vha))
3271 ha->fw_options[2] |= BIT_4;
3272 else
3273 ha->fw_options[2] &= ~BIT_4;
3274 }
3275
83548fe2
QT		 3276 ql_dbg(ql_dbg_init, vha, 0x00e8,
3277 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
3278 __func__, ha->fw_options[1], ha->fw_options[2],
3279 ha->fw_options[3], vha->host->active_mode);
3c4810ff
QT		 3280
3281 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
3282 qla2x00_set_fw_options(vha, ha->fw_options);
41dc529a 3283
0107109e 3284 /* Update Serial Link options. */
f94097ed 3285 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
0107109e
AV		 3286 return;
3287
e315cd28 3288 rval = qla2x00_set_serdes_params(vha,
f94097ed
AV		 3289 le16_to_cpu(ha->fw_seriallink_options24[1]),
3290 le16_to_cpu(ha->fw_seriallink_options24[2]),
3291 le16_to_cpu(ha->fw_seriallink_options24[3]));
0107109e 3292 if (rval != QLA_SUCCESS) {
7c3df132 3293 ql_log(ql_log_warn, vha, 0x0104,
0107109e
AV		 3294 "Unable to update Serial Link options (%x).\n", rval);
3295 }
3296}
3297
abbd8870 3298void
e315cd28 3299qla2x00_config_rings(struct scsi_qla_host *vha)
abbd8870 3300{
e315cd28 3301 struct qla_hw_data *ha = vha->hw;
3d71644c 3302 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
73208dfd
AC		 3303 struct req_que *req = ha->req_q_map[0];
3304 struct rsp_que *rsp = ha->rsp_q_map[0];
abbd8870
AV		 3305
3306 /* Setup ring parameters in initialization control block. */
ad950360
BVA		 3307 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
3308 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3309 ha->init_cb->request_q_length = cpu_to_le16(req->length);
3310 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
3311 ha->init_cb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3312 ha->init_cb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3313 ha->init_cb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3314 ha->init_cb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
abbd8870
AV		 3315
3316 WRT_REG_WORD(ISP_REQ_Q_IN(ha, reg), 0);
3317 WRT_REG_WORD(ISP_REQ_Q_OUT(ha, reg), 0);
3318 WRT_REG_WORD(ISP_RSP_Q_IN(ha, reg), 0);
3319 WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), 0);
3320 RD_REG_WORD(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */
3321}
3322
0107109e 3323void
e315cd28 3324qla24xx_config_rings(struct scsi_qla_host *vha)
0107109e 3325{
e315cd28 3326 struct qla_hw_data *ha = vha->hw;
118e2ef9 3327 device_reg_t *reg = ISP_QUE_REG(ha, 0);
73208dfd
AC		 3328 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
3329 struct qla_msix_entry *msix;
0107109e 3330 struct init_cb_24xx *icb;
73208dfd
AC		 3331 uint16_t rid = 0;
3332 struct req_que *req = ha->req_q_map[0];
3333 struct rsp_que *rsp = ha->rsp_q_map[0];
0107109e 3334
6246b8a1 3335 /* Setup ring parameters in initialization control block. */
0107109e 3336 icb = (struct init_cb_24xx *)ha->init_cb;
ad950360
BVA		 3337 icb->request_q_outpointer = cpu_to_le16(0);
3338 icb->response_q_inpointer = cpu_to_le16(0);
e315cd28
AC		 3339 icb->request_q_length = cpu_to_le16(req->length);
3340 icb->response_q_length = cpu_to_le16(rsp->length);
3341 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
3342 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
3343 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
3344 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
0107109e 3345
2d70c103 3346 /* Setup ATIO queue dma pointers for target mode */
ad950360 3347 icb->atio_q_inpointer = cpu_to_le16(0);
2d70c103
NB		 3348 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
3349 icb->atio_q_address[0] = cpu_to_le32(LSD(ha->tgt.atio_dma));
3350 icb->atio_q_address[1] = cpu_to_le32(MSD(ha->tgt.atio_dma));
3351
7c6300e3 3352 if (IS_SHADOW_REG_CAPABLE(ha))
ad950360 3353 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
7c6300e3 3354
f73cb695 3355 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
ad950360
BVA		 3356 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
3357 icb->rid = cpu_to_le16(rid);
73208dfd
AC		 3358 if (ha->flags.msix_enabled) {
3359 msix = &ha->msix_entries[1];
83548fe2 3360 ql_dbg(ql_dbg_init, vha, 0x0019,
7c3df132
SK		 3361 "Registering vector 0x%x for base que.\n",
3362 msix->entry);
73208dfd
AC		 3363 icb->msix = cpu_to_le16(msix->entry);
3364 }
3365 /* Use alternate PCI bus number */
3366 if (MSB(rid))
ad950360 3367 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
73208dfd
AC		 3368 /* Use alternate PCI devfn */
3369 if (LSB(rid))
ad950360 3370 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
73208dfd 3371
3155754a 3372 /* Use Disable MSIX Handshake mode for capable adapters */
6246b8a1
GM		 3373 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
3374 (ha->flags.msix_enabled)) {
ad950360 3375 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
3155754a 3376 ha->flags.disable_msix_handshake = 1;
7c3df132
SK		 3377 ql_dbg(ql_dbg_init, vha, 0x00fe,
3378 "MSIX Handshake Disable Mode turned on.\n");
3155754a 3379 } else {
ad950360 3380 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
3155754a 3381 }
ad950360 3382 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
73208dfd
AC		 3383
3384 WRT_REG_DWORD(&reg->isp25mq.req_q_in, 0);
3385 WRT_REG_DWORD(&reg->isp25mq.req_q_out, 0);
3386 WRT_REG_DWORD(&reg->isp25mq.rsp_q_in, 0);
3387 WRT_REG_DWORD(&reg->isp25mq.rsp_q_out, 0);
3388 } else {
3389 WRT_REG_DWORD(&reg->isp24.req_q_in, 0);
3390 WRT_REG_DWORD(&reg->isp24.req_q_out, 0);
3391 WRT_REG_DWORD(&reg->isp24.rsp_q_in, 0);
3392 WRT_REG_DWORD(&reg->isp24.rsp_q_out, 0);
3393 }
aa230bc5 3394 qlt_24xx_config_rings(vha);
2d70c103 3395
73208dfd
AC		 3396 /* PCI posting */
3397 RD_REG_DWORD(&ioreg->hccr);
0107109e
AV		 3398}
3399
1da177e4
LT		 3400/**
3401 * qla2x00_init_rings() - Initializes firmware.
3402 * @ha: HA context
3403 *
3404 * Beginning of request ring has initialization control block already built
3405 * by nvram config routine.
3406 *
3407 * Returns 0 on success.
3408 */
8ae6d9c7 3409int
e315cd28 3410qla2x00_init_rings(scsi_qla_host_t *vha)
1da177e4
LT		 3411{
3412 int rval;
3413 unsigned long flags = 0;
29bdccbe 3414 int cnt, que;
e315cd28 3415 struct qla_hw_data *ha = vha->hw;
29bdccbe
AC		 3416 struct req_que *req;
3417 struct rsp_que *rsp;
2c3dfe3f
SJ		 3418 struct mid_init_cb_24xx *mid_init_cb =
3419 (struct mid_init_cb_24xx *) ha->init_cb;
1da177e4
LT		 3420
3421 spin_lock_irqsave(&ha->hardware_lock, flags);
3422
3423 /* Clear outstanding commands array. */
2afa19a9 3424 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 3425 req = ha->req_q_map[que];
cb43285f 3426 if (!req || !test_bit(que, ha->req_qid_map))
29bdccbe 3427 continue;
7c6300e3
JC		 3428 req->out_ptr = (void *)(req->ring + req->length);
3429 *req->out_ptr = 0;
8d93f550 3430 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
29bdccbe 3431 req->outstanding_cmds[cnt] = NULL;
1da177e4 3432
2afa19a9 3433 req->current_outstanding_cmd = 1;
1da177e4 3434
29bdccbe
AC		 3435 /* Initialize firmware. */
3436 req->ring_ptr = req->ring;
3437 req->ring_index = 0;
3438 req->cnt = req->length;
3439 }
1da177e4 3440
2afa19a9 3441 for (que = 0; que < ha->max_rsp_queues; que++) {
29bdccbe 3442 rsp = ha->rsp_q_map[que];
cb43285f 3443 if (!rsp || !test_bit(que, ha->rsp_qid_map))
29bdccbe 3444 continue;
7c6300e3
JC		 3445 rsp->in_ptr = (void *)(rsp->ring + rsp->length);
3446 *rsp->in_ptr = 0;
29bdccbe 3447 /* Initialize response queue entries */
8ae6d9c7
GM		 3448 if (IS_QLAFX00(ha))
3449 qlafx00_init_response_q_entries(rsp);
3450 else
3451 qla2x00_init_response_q_entries(rsp);
29bdccbe 3452 }
1da177e4 3453
2d70c103
NB		 3454 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
3455 ha->tgt.atio_ring_index = 0;
3456 /* Initialize ATIO queue entries */
3457 qlt_init_atio_q_entries(vha);
3458
e315cd28 3459 ha->isp_ops->config_rings(vha);
1da177e4
LT		 3460
3461 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3462
8ae6d9c7
GM		 3463 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
3464
3465 if (IS_QLAFX00(ha)) {
3466 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
3467 goto next_check;
3468 }
3469
1da177e4 3470 /* Update any ISP specific firmware options before initialization. */
e315cd28 3471 ha->isp_ops->update_fw_options(vha);
1da177e4 3472
605aa2bc 3473 if (ha->flags.npiv_supported) {
45980cc2 3474 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
605aa2bc 3475 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
c48339de 3476 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
605aa2bc
LC		 3477 }
3478
24a08138 3479 if (IS_FWI2_CAPABLE(ha)) {
ad950360 3480 mid_init_cb->options = cpu_to_le16(BIT_1);
24a08138 3481 mid_init_cb->init_cb.execution_throttle =
03e8c680 3482 cpu_to_le16(ha->cur_fw_xcb_count);
40f3862b
JC		 3483 ha->flags.dport_enabled =
3484 (mid_init_cb->init_cb.firmware_options_1 & BIT_7) != 0;
3485 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
3486 (ha->flags.dport_enabled) ? "enabled" : "disabled");
3487 /* FA-WWPN Status */
2486c627 3488 ha->flags.fawwpn_enabled =
40f3862b 3489 (mid_init_cb->init_cb.firmware_options_1 & BIT_6) != 0;
83548fe2 3490 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
2486c627 3491 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
24a08138 3492 }
2c3dfe3f 3493
e315cd28 3494 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
8ae6d9c7 3495next_check:
1da177e4 3496 if (rval) {
7c3df132
SK		 3497 ql_log(ql_log_fatal, vha, 0x00d2,
3498 "Init Firmware **** FAILED ****.\n");
1da177e4 3499 } else {
7c3df132
SK		 3500 ql_dbg(ql_dbg_init, vha, 0x00d3,
3501 "Init Firmware -- success.\n");
4b60c827 3502 QLA_FW_STARTED(ha);
1da177e4
LT		 3503 }
3504
3505 return (rval);
3506}
3507
3508/**
3509 * qla2x00_fw_ready() - Waits for firmware ready.
3510 * @ha: HA context
3511 *
3512 * Returns 0 on success.
3513 */
3514static int
e315cd28 3515qla2x00_fw_ready(scsi_qla_host_t *vha)
1da177e4
LT		 3516{
3517 int rval;
4d4df193 3518 unsigned long wtime, mtime, cs84xx_time;
1da177e4
LT		 3519 uint16_t min_wait; /* Minimum wait time if loop is down */
3520 uint16_t wait_time; /* Wait time if loop is coming ready */
b5a340dd 3521 uint16_t state[6];
e315cd28 3522 struct qla_hw_data *ha = vha->hw;
1da177e4 3523
8ae6d9c7
GM		 3524 if (IS_QLAFX00(vha->hw))
3525 return qlafx00_fw_ready(vha);
3526
1da177e4
LT		 3527 rval = QLA_SUCCESS;
3528
33461491
CD		 3529 /* Time to wait for loop down */
3530 if (IS_P3P_TYPE(ha))
3531 min_wait = 30;
3532 else
3533 min_wait = 20;
1da177e4
LT		 3534
3535 /*
3536 * Firmware should take at most one RATOV to login, plus 5 seconds for
3537 * our own processing.
3538 */
3539 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
3540 wait_time = min_wait;
3541 }
3542
3543 /* Min wait time if loop down */
3544 mtime = jiffies + (min_wait * HZ);
3545
3546 /* wait time before firmware ready */
3547 wtime = jiffies + (wait_time * HZ);
3548
3549 /* Wait for ISP to finish LIP */
e315cd28 3550 if (!vha->flags.init_done)
7c3df132
SK		 3551 ql_log(ql_log_info, vha, 0x801e,
3552 "Waiting for LIP to complete.\n");
1da177e4
LT		 3553
3554 do {
5b939038 3555 memset(state, -1, sizeof(state));
e315cd28 3556 rval = qla2x00_get_firmware_state(vha, state);
1da177e4 3557 if (rval == QLA_SUCCESS) {
4d4df193 3558 if (state[0] < FSTATE_LOSS_OF_SYNC) {
e315cd28 3559 vha->device_flags &= ~DFLG_NO_CABLE;
1da177e4 3560 }
4d4df193 3561 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
7c3df132
SK		 3562 ql_dbg(ql_dbg_taskm, vha, 0x801f,
3563 "fw_state=%x 84xx=%x.\n", state[0],
3564 state[2]);
4d4df193
HK		 3565 if ((state[2] & FSTATE_LOGGED_IN) &&
3566 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
7c3df132
SK		 3567 ql_dbg(ql_dbg_taskm, vha, 0x8028,
3568 "Sending verify iocb.\n");
4d4df193
HK		 3569
3570 cs84xx_time = jiffies;
e315cd28 3571 rval = qla84xx_init_chip(vha);
7c3df132
SK		 3572 if (rval != QLA_SUCCESS) {
3573 ql_log(ql_log_warn,
cfb0919c 3574 vha, 0x8007,
7c3df132 3575 "Init chip failed.\n");
4d4df193 3576 break;
7c3df132 3577 }
4d4df193
HK		 3578
3579 /* Add time taken to initialize. */
3580 cs84xx_time = jiffies - cs84xx_time;
3581 wtime += cs84xx_time;
3582 mtime += cs84xx_time;
cfb0919c 3583 ql_dbg(ql_dbg_taskm, vha, 0x8008,
7c3df132
SK		 3584 "Increasing wait time by %ld. "
3585 "New time %ld.\n", cs84xx_time,
3586 wtime);
4d4df193
HK		 3587 }
3588 } else if (state[0] == FSTATE_READY) {
7c3df132
SK		 3589 ql_dbg(ql_dbg_taskm, vha, 0x8037,
3590 "F/W Ready - OK.\n");
1da177e4 3591
e315cd28 3592 qla2x00_get_retry_cnt(vha, &ha->retry_count,
1da177e4
LT		 3593 &ha->login_timeout, &ha->r_a_tov);
3594
3595 rval = QLA_SUCCESS;
3596 break;
3597 }
3598
3599 rval = QLA_FUNCTION_FAILED;
3600
e315cd28 3601 if (atomic_read(&vha->loop_down_timer) &&
4d4df193 3602 state[0] != FSTATE_READY) {
1da177e4 3603 /* Loop down. Timeout on min_wait for states
fa2a1ce5
AV		 3604 * other than Wait for Login.
3605 */
1da177e4 3606 if (time_after_eq(jiffies, mtime)) {
7c3df132 3607 ql_log(ql_log_info, vha, 0x8038,
1da177e4
LT		 3608 "Cable is unplugged...\n");
3609
e315cd28 3610 vha->device_flags |= DFLG_NO_CABLE;
1da177e4
LT		 3611 break;
3612 }
3613 }
3614 } else {
3615 /* Mailbox cmd failed. Timeout on min_wait. */
cdbb0a4f 3616 if (time_after_eq(jiffies, mtime) ||
7190575f 3617 ha->flags.isp82xx_fw_hung)
1da177e4
LT		 3618 break;
3619 }
3620
3621 if (time_after_eq(jiffies, wtime))
3622 break;
3623
3624 /* Delay for a while */
3625 msleep(500);
1da177e4
LT		 3626 } while (1);
3627
7c3df132 3628 ql_dbg(ql_dbg_taskm, vha, 0x803a,
b5a340dd
JC		 3629 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
3630 state[1], state[2], state[3], state[4], state[5], jiffies);
1da177e4 3631
cfb0919c 3632 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132
SK		 3633 ql_log(ql_log_warn, vha, 0x803b,
3634 "Firmware ready **** FAILED ****.\n");
1da177e4
LT		 3635 }
3636
3637 return (rval);
3638}
3639
3640/*
3641* qla2x00_configure_hba
3642* Setup adapter context.
3643*
3644* Input:
3645* ha = adapter state pointer.
3646*
3647* Returns:
3648* 0 = success
3649*
3650* Context:
3651* Kernel context.
3652*/
3653static int
e315cd28 3654qla2x00_configure_hba(scsi_qla_host_t *vha)
1da177e4
LT		 3655{
3656 int rval;
3657 uint16_t loop_id;
3658 uint16_t topo;
2c3dfe3f 3659 uint16_t sw_cap;
1da177e4
LT		 3660 uint8_t al_pa;
3661 uint8_t area;
3662 uint8_t domain;
3663 char connect_type[22];
e315cd28 3664 struct qla_hw_data *ha = vha->hw;
61e1b269 3665 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
482c9dc7 3666 port_id_t id;
1da177e4
LT		 3667
3668 /* Get host addresses. */
e315cd28 3669 rval = qla2x00_get_adapter_id(vha,
2c3dfe3f 3670 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
1da177e4 3671 if (rval != QLA_SUCCESS) {
e315cd28 3672 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
6246b8a1 3673 IS_CNA_CAPABLE(ha) ||
33135aa2 3674 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
7c3df132
SK		 3675 ql_dbg(ql_dbg_disc, vha, 0x2008,
3676 "Loop is in a transition state.\n");
33135aa2 3677 } else {
7c3df132
SK		 3678 ql_log(ql_log_warn, vha, 0x2009,
3679 "Unable to get host loop ID.\n");
61e1b269
JC		 3680 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
3681 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
3682 ql_log(ql_log_warn, vha, 0x1151,
3683 "Doing link init.\n");
3684 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
3685 return rval;
3686 }
e315cd28 3687 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
33135aa2 3688 }
1da177e4
LT		 3689 return (rval);
3690 }
3691
3692 if (topo == 4) {
7c3df132
SK		 3693 ql_log(ql_log_info, vha, 0x200a,
3694 "Cannot get topology - retrying.\n");
1da177e4
LT		 3695 return (QLA_FUNCTION_FAILED);
3696 }
3697
e315cd28 3698 vha->loop_id = loop_id;
1da177e4
LT		 3699
3700 /* initialize */
3701 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
3702 ha->operating_mode = LOOP;
2c3dfe3f 3703 ha->switch_cap = 0;
1da177e4
LT		 3704
3705 switch (topo) {
3706 case 0:
7c3df132 3707 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
1da177e4
LT		 3708 ha->current_topology = ISP_CFG_NL;
3709 strcpy(connect_type, "(Loop)");
3710 break;
3711
3712 case 1:
7c3df132 3713 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
2c3dfe3f 3714 ha->switch_cap = sw_cap;
1da177e4
LT		 3715 ha->current_topology = ISP_CFG_FL;
3716 strcpy(connect_type, "(FL_Port)");
3717 break;
3718
3719 case 2:
7c3df132 3720 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
1da177e4
LT		 3721 ha->operating_mode = P2P;
3722 ha->current_topology = ISP_CFG_N;
3723 strcpy(connect_type, "(N_Port-to-N_Port)");
3724 break;
3725
3726 case 3:
7c3df132 3727 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
2c3dfe3f 3728 ha->switch_cap = sw_cap;
1da177e4
LT		 3729 ha->operating_mode = P2P;
3730 ha->current_topology = ISP_CFG_F;
3731 strcpy(connect_type, "(F_Port)");
3732 break;
3733
3734 default:
7c3df132
SK		 3735 ql_dbg(ql_dbg_disc, vha, 0x200f,
3736 "HBA in unknown topology %x, using NL.\n", topo);
1da177e4
LT		 3737 ha->current_topology = ISP_CFG_NL;
3738 strcpy(connect_type, "(Loop)");
3739 break;
3740 }
3741
3742 /* Save Host port and loop ID. */
3743 /* byte order - Big Endian */
482c9dc7
QT		 3744 id.b.domain = domain;
3745 id.b.area = area;
3746 id.b.al_pa = al_pa;
3747 id.b.rsvd_1 = 0;
3748 qlt_update_host_map(vha, id);
2d70c103 3749
e315cd28 3750 if (!vha->flags.init_done)
7c3df132
SK		 3751 ql_log(ql_log_info, vha, 0x2010,
3752 "Topology - %s, Host Loop address 0x%x.\n",
e315cd28 3753 connect_type, vha->loop_id);
1da177e4 3754
1da177e4
LT		 3755 return(rval);
3756}
3757
a9083016 3758inline void
e315cd28
AC		 3759qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
3760 char *def)
9bb9fcf2
AV		 3761{
3762 char *st, *en;
3763 uint16_t index;
e315cd28 3764 struct qla_hw_data *ha = vha->hw;
ab671149 3765 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
6246b8a1 3766 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
9bb9fcf2
AV		 3767
3768 if (memcmp(model, BINZERO, len) != 0) {
3769 strncpy(ha->model_number, model, len);
3770 st = en = ha->model_number;
3771 en += len - 1;
3772 while (en > st) {
3773 if (*en != 0x20 && *en != 0x00)
3774 break;
3775 *en-- = '\0';
3776 }
3777
3778 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3779 if (use_tbl &&
3780 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2 3781 index < QLA_MODEL_NAMES)
1ee27146
JC		 3782 strncpy(ha->model_desc,
3783 qla2x00_model_name[index * 2 + 1],
3784 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3785 } else {
3786 index = (ha->pdev->subsystem_device & 0xff);
7d0dba17
AV		 3787 if (use_tbl &&
3788 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
9bb9fcf2
AV		 3789 index < QLA_MODEL_NAMES) {
3790 strcpy(ha->model_number,
3791 qla2x00_model_name[index * 2]);
1ee27146
JC		 3792 strncpy(ha->model_desc,
3793 qla2x00_model_name[index * 2 + 1],
3794 sizeof(ha->model_desc) - 1);
9bb9fcf2
AV		 3795 } else {
3796 strcpy(ha->model_number, def);
3797 }
3798 }
1ee27146 3799 if (IS_FWI2_CAPABLE(ha))
e315cd28 3800 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
1ee27146 3801 sizeof(ha->model_desc));
9bb9fcf2
AV		 3802}
3803
4e08df3f
DM		 3804/* On sparc systems, obtain port and node WWN from firmware
3805 * properties.
3806 */
e315cd28 3807static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4e08df3f
DM		 3808{
3809#ifdef CONFIG_SPARC
e315cd28 3810 struct qla_hw_data *ha = vha->hw;
4e08df3f 3811 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 3812 struct device_node *dp = pci_device_to_OF_node(pdev);
3813 const u8 *val;
4e08df3f
DM		 3814 int len;
3815
3816 val = of_get_property(dp, "port-wwn", &len);
3817 if (val && len >= WWN_SIZE)
3818 memcpy(nv->port_name, val, WWN_SIZE);
3819
3820 val = of_get_property(dp, "node-wwn", &len);
3821 if (val && len >= WWN_SIZE)
3822 memcpy(nv->node_name, val, WWN_SIZE);
3823#endif
3824}
3825
1da177e4
LT		 3826/*
3827* NVRAM configuration for ISP 2xxx
3828*
3829* Input:
3830* ha = adapter block pointer.
3831*
3832* Output:
3833* initialization control block in response_ring
3834* host adapters parameters in host adapter block
3835*
3836* Returns:
3837* 0 = success.
3838*/
abbd8870 3839int
e315cd28 3840qla2x00_nvram_config(scsi_qla_host_t *vha)
1da177e4 3841{
4e08df3f 3842 int rval;
0107109e
AV		 3843 uint8_t chksum = 0;
3844 uint16_t cnt;
3845 uint8_t *dptr1, *dptr2;
e315cd28 3846 struct qla_hw_data *ha = vha->hw;
0107109e 3847 init_cb_t *icb = ha->init_cb;
281afe19
SJ		 3848 nvram_t *nv = ha->nvram;
3849 uint8_t *ptr = ha->nvram;
3d71644c 3850 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 3851
4e08df3f
DM		 3852 rval = QLA_SUCCESS;
3853
1da177e4 3854 /* Determine NVRAM starting address. */
0107109e 3855 ha->nvram_size = sizeof(nvram_t);
1da177e4
LT		 3856 ha->nvram_base = 0;
3857 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
3858 if ((RD_REG_WORD(&reg->ctrl_status) >> 14) == 1)
3859 ha->nvram_base = 0x80;
3860
3861 /* Get NVRAM data and calculate checksum. */
e315cd28 3862 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
0107109e
AV		 3863 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
3864 chksum += *ptr++;
1da177e4 3865
7c3df132
SK		 3866 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
3867 "Contents of NVRAM.\n");
3868 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
3869 (uint8_t *)nv, ha->nvram_size);
1da177e4
LT		 3870
3871 /* Bad NVRAM data, set defaults parameters. */
3872 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' ||
3873 nv->id[2] != 'P' || nv->id[3] != ' ' || nv->nvram_version < 1) {
3874 /* Reset NVRAM data. */
7c3df132 3875 ql_log(ql_log_warn, vha, 0x0064,
9e336520 3876 "Inconsistent NVRAM "
7c3df132
SK		 3877 "detected: checksum=0x%x id=%c version=0x%x.\n",
3878 chksum, nv->id[0], nv->nvram_version);
3879 ql_log(ql_log_warn, vha, 0x0065,
3880 "Falling back to "
3881 "functioning (yet invalid -- WWPN) defaults.\n");
4e08df3f
DM		 3882
3883 /*
3884 * Set default initialization control block.
3885 */
3886 memset(nv, 0, ha->nvram_size);
3887 nv->parameter_block_version = ICB_VERSION;
3888
3889 if (IS_QLA23XX(ha)) {
3890 nv->firmware_options[0] = BIT_2 | BIT_1;
3891 nv->firmware_options[1] = BIT_7 | BIT_5;
3892 nv->add_firmware_options[0] = BIT_5;
3893 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3894 nv->frame_payload_size = 2048;
4e08df3f
DM		 3895 nv->special_options[1] = BIT_7;
3896 } else if (IS_QLA2200(ha)) {
3897 nv->firmware_options[0] = BIT_2 | BIT_1;
3898 nv->firmware_options[1] = BIT_7 | BIT_5;
3899 nv->add_firmware_options[0] = BIT_5;
3900 nv->add_firmware_options[1] = BIT_5 | BIT_4;
98aee70d 3901 nv->frame_payload_size = 1024;
4e08df3f
DM		 3902 } else if (IS_QLA2100(ha)) {
3903 nv->firmware_options[0] = BIT_3 | BIT_1;
3904 nv->firmware_options[1] = BIT_5;
98aee70d 3905 nv->frame_payload_size = 1024;
4e08df3f
DM		 3906 }
3907
ad950360
BVA		 3908 nv->max_iocb_allocation = cpu_to_le16(256);
3909 nv->execution_throttle = cpu_to_le16(16);
4e08df3f
DM		 3910 nv->retry_count = 8;
3911 nv->retry_delay = 1;
3912
3913 nv->port_name[0] = 33;
3914 nv->port_name[3] = 224;
3915 nv->port_name[4] = 139;
3916
e315cd28 3917 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4e08df3f
DM		 3918
3919 nv->login_timeout = 4;
3920
3921 /*
3922 * Set default host adapter parameters
3923 */
3924 nv->host_p[1] = BIT_2;
3925 nv->reset_delay = 5;
3926 nv->port_down_retry_count = 8;
ad950360 3927 nv->max_luns_per_target = cpu_to_le16(8);
4e08df3f
DM		 3928 nv->link_down_timeout = 60;
3929
3930 rval = 1;
1da177e4
LT		 3931 }
3932
3933#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_SGI_SN2)
3934 /*
3935 * The SN2 does not provide BIOS emulation which means you can't change
3936 * potentially bogus BIOS settings. Force the use of default settings
3937 * for link rate and frame size. Hope that the rest of the settings
3938 * are valid.
3939 */
3940 if (ia64_platform_is("sn2")) {
98aee70d 3941 nv->frame_payload_size = 2048;
1da177e4
LT		 3942 if (IS_QLA23XX(ha))
3943 nv->special_options[1] = BIT_7;
3944 }
3945#endif
3946
3947 /* Reset Initialization control block */
0107109e 3948 memset(icb, 0, ha->init_cb_size);
1da177e4
LT		 3949
3950 /*
3951 * Setup driver NVRAM options.
3952 */
3953 nv->firmware_options[0] |= (BIT_6 | BIT_1);
3954 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
3955 nv->firmware_options[1] |= (BIT_5 | BIT_0);
3956 nv->firmware_options[1] &= ~BIT_4;
3957
3958 if (IS_QLA23XX(ha)) {
3959 nv->firmware_options[0] |= BIT_2;
3960 nv->firmware_options[0] &= ~BIT_3;
2d70c103 3961 nv->special_options[0] &= ~BIT_6;
0107109e 3962 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
1da177e4
LT		 3963
3964 if (IS_QLA2300(ha)) {
3965 if (ha->fb_rev == FPM_2310) {
3966 strcpy(ha->model_number, "QLA2310");
3967 } else {
3968 strcpy(ha->model_number, "QLA2300");
3969 }
3970 } else {
e315cd28 3971 qla2x00_set_model_info(vha, nv->model_number,
9bb9fcf2 3972 sizeof(nv->model_number), "QLA23xx");
1da177e4
LT		 3973 }
3974 } else if (IS_QLA2200(ha)) {
3975 nv->firmware_options[0] |= BIT_2;
3976 /*
3977 * 'Point-to-point preferred, else loop' is not a safe
3978 * connection mode setting.
3979 */
3980 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
3981 (BIT_5 | BIT_4)) {
3982 /* Force 'loop preferred, else point-to-point'. */
3983 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
3984 nv->add_firmware_options[0] |= BIT_5;
3985 }
3986 strcpy(ha->model_number, "QLA22xx");
3987 } else /*if (IS_QLA2100(ha))*/ {
3988 strcpy(ha->model_number, "QLA2100");
3989 }
3990
3991 /*
3992 * Copy over NVRAM RISC parameter block to initialization control block.
3993 */
3994 dptr1 = (uint8_t *)icb;
3995 dptr2 = (uint8_t *)&nv->parameter_block_version;
3996 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
3997 while (cnt--)
3998 *dptr1++ = *dptr2++;
3999
4000 /* Copy 2nd half. */
4001 dptr1 = (uint8_t *)icb->add_firmware_options;
4002 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4003 while (cnt--)
4004 *dptr1++ = *dptr2++;
4005
5341e868
AV		 4006 /* Use alternate WWN? */
4007 if (nv->host_p[1] & BIT_7) {
4008 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4009 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4010 }
4011
1da177e4
LT		 4012 /* Prepare nodename */
4013 if ((icb->firmware_options[1] & BIT_6) == 0) {
4014 /*
4015 * Firmware will apply the following mask if the nodename was
4016 * not provided.
4017 */
4018 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4019 icb->node_name[0] &= 0xF0;
4020 }
4021
4022 /*
4023 * Set host adapter parameters.
4024 */
3ce8866c
SK		 4025
4026 /*
4027 * BIT_7 in the host-parameters section allows for modification to
4028 * internal driver logging.
4029 */
0181944f 4030 if (nv->host_p[0] & BIT_7)
cfb0919c 4031 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
1da177e4
LT		 4032 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4033 /* Always load RISC code on non ISP2[12]00 chips. */
4034 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4035 ha->flags.disable_risc_code_load = 0;
4036 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4037 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4038 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
06c22bd1 4039 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
d4c760c2 4040 ha->flags.disable_serdes = 0;
1da177e4
LT		 4041
4042 ha->operating_mode =
4043 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4044
4045 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4046 sizeof(ha->fw_seriallink_options));
4047
4048 /* save HBA serial number */
4049 ha->serial0 = icb->port_name[5];
4050 ha->serial1 = icb->port_name[6];
4051 ha->serial2 = icb->port_name[7];
e315cd28
AC		 4052 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4053 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
1da177e4 4054
ad950360 4055 icb->execution_throttle = cpu_to_le16(0xFFFF);
1da177e4
LT		 4056
4057 ha->retry_count = nv->retry_count;
4058
4059 /* Set minimum login_timeout to 4 seconds. */
5b91490e 4060 if (nv->login_timeout != ql2xlogintimeout)
1da177e4
LT		 4061 nv->login_timeout = ql2xlogintimeout;
4062 if (nv->login_timeout < 4)
4063 nv->login_timeout = 4;
4064 ha->login_timeout = nv->login_timeout;
1da177e4 4065
00a537b8
AV		 4066 /* Set minimum RATOV to 100 tenths of a second. */
4067 ha->r_a_tov = 100;
1da177e4 4068
1da177e4
LT		 4069 ha->loop_reset_delay = nv->reset_delay;
4070
1da177e4
LT		 4071 /* Link Down Timeout = 0:
4072 *
4073 * When Port Down timer expires we will start returning
4074 * I/O's to OS with "DID_NO_CONNECT".
4075 *
4076 * Link Down Timeout != 0:
4077 *
4078 * The driver waits for the link to come up after link down
4079 * before returning I/Os to OS with "DID_NO_CONNECT".
fa2a1ce5 4080 */
1da177e4
LT		 4081 if (nv->link_down_timeout == 0) {
4082 ha->loop_down_abort_time =
354d6b21 4083 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
1da177e4
LT		 4084 } else {
4085 ha->link_down_timeout = nv->link_down_timeout;
4086 ha->loop_down_abort_time =
4087 (LOOP_DOWN_TIME - ha->link_down_timeout);
fa2a1ce5 4088 }
1da177e4 4089
1da177e4
LT		 4090 /*
4091 * Need enough time to try and get the port back.
4092 */
4093 ha->port_down_retry_count = nv->port_down_retry_count;
4094 if (qlport_down_retry)
4095 ha->port_down_retry_count = qlport_down_retry;
4096 /* Set login_retry_count */
4097 ha->login_retry_count = nv->retry_count;
4098 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4099 ha->port_down_retry_count > 3)
4100 ha->login_retry_count = ha->port_down_retry_count;
4101 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4102 ha->login_retry_count = ha->port_down_retry_count;
4103 if (ql2xloginretrycount)
4104 ha->login_retry_count = ql2xloginretrycount;
4105
ad950360 4106 icb->lun_enables = cpu_to_le16(0);
1da177e4
LT		 4107 icb->command_resource_count = 0;
4108 icb->immediate_notify_resource_count = 0;
ad950360 4109 icb->timeout = cpu_to_le16(0);
1da177e4
LT		 4110
4111 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4112 /* Enable RIO */
4113 icb->firmware_options[0] &= ~BIT_3;
4114 icb->add_firmware_options[0] &=
4115 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4116 icb->add_firmware_options[0] |= BIT_2;
4117 icb->response_accumulation_timer = 3;
4118 icb->interrupt_delay_timer = 5;
4119
e315cd28 4120 vha->flags.process_response_queue = 1;
1da177e4 4121 } else {
4fdfefe5 4122 /* Enable ZIO. */
e315cd28 4123 if (!vha->flags.init_done) {
4fdfefe5
AV		 4124 ha->zio_mode = icb->add_firmware_options[0] &
4125 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4126 ha->zio_timer = icb->interrupt_delay_timer ?
4127 icb->interrupt_delay_timer: 2;
4128 }
1da177e4
LT		 4129 icb->add_firmware_options[0] &=
4130 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
e315cd28 4131 vha->flags.process_response_queue = 0;
4fdfefe5 4132 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 4133 ha->zio_mode = QLA_ZIO_MODE_6;
4134
7c3df132 4135 ql_log(ql_log_info, vha, 0x0068,
4fdfefe5
AV		 4136 "ZIO mode %d enabled; timer delay (%d us).\n",
4137 ha->zio_mode, ha->zio_timer * 100);
1da177e4 4138
4fdfefe5
AV		 4139 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4140 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
e315cd28 4141 vha->flags.process_response_queue = 1;
1da177e4
LT		 4142 }
4143 }
4144
4e08df3f 4145 if (rval) {
7c3df132
SK		 4146 ql_log(ql_log_warn, vha, 0x0069,
4147 "NVRAM configuration failed.\n");
4e08df3f
DM		 4148 }
4149 return (rval);
1da177e4
LT		 4150}
4151
19a7b4ae
JSEC		 4152static void
4153qla2x00_rport_del(void *data)
4154{
4155 fc_port_t *fcport = data;
d97994dc 4156 struct fc_rport *rport;
044d78e1 4157 unsigned long flags;
d97994dc 4158
044d78e1 4159 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
ac280b67 4160 rport = fcport->drport ? fcport->drport: fcport->rport;
d97994dc 4161 fcport->drport = NULL;
044d78e1 4162 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
726b8548 4163 if (rport) {
83548fe2
QT		 4164 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4165 "%s %8phN. rport %p roles %x\n",
4166 __func__, fcport->port_name, rport,
4167 rport->roles);
726b8548 4168
d97994dc 4169 fc_remote_port_delete(rport);
726b8548 4170 }
19a7b4ae
JSEC		 4171}
4172
1da177e4
LT		 4173/**
4174 * qla2x00_alloc_fcport() - Allocate a generic fcport.
4175 * @ha: HA context
4176 * @flags: allocation flags
4177 *
4178 * Returns a pointer to the allocated fcport, or NULL, if none available.
4179 */
9a069e19 4180fc_port_t *
e315cd28 4181qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
1da177e4
LT		 4182{
4183 fc_port_t *fcport;
4184
bbfbbbc1
MK		 4185 fcport = kzalloc(sizeof(fc_port_t), flags);
4186 if (!fcport)
4187 return NULL;
1da177e4
LT		 4188
4189 /* Setup fcport template structure. */
e315cd28 4190 fcport->vha = vha;
1da177e4
LT		 4191 fcport->port_type = FCT_UNKNOWN;
4192 fcport->loop_id = FC_NO_LOOP_ID;
ec426e10 4193 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
ad3e0eda 4194 fcport->supported_classes = FC_COS_UNSPECIFIED;
1da177e4 4195
726b8548
QT		 4196 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
4197 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
6cb3216a 4198 flags);
726b8548
QT		 4199 fcport->disc_state = DSC_DELETED;
4200 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
4201 fcport->deleted = QLA_SESS_DELETED;
4202 fcport->login_retry = vha->hw->login_retry_count;
4203 fcport->login_retry = 5;
4204 fcport->logout_on_delete = 1;
4205
4206 if (!fcport->ct_desc.ct_sns) {
83548fe2 4207 ql_log(ql_log_warn, vha, 0xd049,
726b8548
QT		 4208 "Failed to allocate ct_sns request.\n");
4209 kfree(fcport);
4210 fcport = NULL;
4211 }
4212 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
4213 INIT_LIST_HEAD(&fcport->gnl_entry);
4214 INIT_LIST_HEAD(&fcport->list);
4215
bbfbbbc1 4216 return fcport;
1da177e4
LT		 4217}
4218
726b8548
QT		 4219void
4220qla2x00_free_fcport(fc_port_t *fcport)
4221{
4222 if (fcport->ct_desc.ct_sns) {
4223 dma_free_coherent(&fcport->vha->hw->pdev->dev,
4224 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
4225 fcport->ct_desc.ct_sns_dma);
4226
4227 fcport->ct_desc.ct_sns = NULL;
4228 }
4229 kfree(fcport);
4230}
4231
1da177e4
LT		 4232/*
4233 * qla2x00_configure_loop
4234 * Updates Fibre Channel Device Database with what is actually on loop.
4235 *
4236 * Input:
4237 * ha = adapter block pointer.
4238 *
4239 * Returns:
4240 * 0 = success.
4241 * 1 = error.
4242 * 2 = database was full and device was not configured.
4243 */
4244static int
e315cd28 4245qla2x00_configure_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4246{
4247 int rval;
4248 unsigned long flags, save_flags;
e315cd28 4249 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 4250 rval = QLA_SUCCESS;
4251
4252 /* Get Initiator ID */
e315cd28
AC		 4253 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
4254 rval = qla2x00_configure_hba(vha);
1da177e4 4255 if (rval != QLA_SUCCESS) {
7c3df132
SK		 4256 ql_dbg(ql_dbg_disc, vha, 0x2013,
4257 "Unable to configure HBA.\n");
1da177e4
LT		 4258 return (rval);
4259 }
4260 }
4261
e315cd28 4262 save_flags = flags = vha->dpc_flags;
7c3df132
SK		 4263 ql_dbg(ql_dbg_disc, vha, 0x2014,
4264 "Configure loop -- dpc flags = 0x%lx.\n", flags);
1da177e4
LT		 4265
4266 /*
4267 * If we have both an RSCN and PORT UPDATE pending then handle them
4268 * both at the same time.
4269 */
e315cd28
AC		 4270 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
4271 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
1da177e4 4272
3064ff39
MH		 4273 qla2x00_get_data_rate(vha);
4274
1da177e4
LT		 4275 /* Determine what we need to do */
4276 if (ha->current_topology == ISP_CFG_FL &&
4277 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4278
1da177e4
LT		 4279 set_bit(RSCN_UPDATE, &flags);
4280
4281 } else if (ha->current_topology == ISP_CFG_F &&
4282 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
4283
1da177e4
LT		 4284 set_bit(RSCN_UPDATE, &flags);
4285 clear_bit(LOCAL_LOOP_UPDATE, &flags);
21333b48
AV		 4286
4287 } else if (ha->current_topology == ISP_CFG_N) {
4288 clear_bit(RSCN_UPDATE, &flags);
41dc529a
QT		 4289 } else if (ha->current_topology == ISP_CFG_NL) {
4290 clear_bit(RSCN_UPDATE, &flags);
4291 set_bit(LOCAL_LOOP_UPDATE, &flags);
e315cd28 4292 } else if (!vha->flags.online ||
1da177e4 4293 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
1da177e4
LT		 4294 set_bit(RSCN_UPDATE, &flags);
4295 set_bit(LOCAL_LOOP_UPDATE, &flags);
4296 }
4297
4298 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
7c3df132
SK		 4299 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
4300 ql_dbg(ql_dbg_disc, vha, 0x2015,
4301 "Loop resync needed, failing.\n");
1da177e4 4302 rval = QLA_FUNCTION_FAILED;
642ef983 4303 } else
e315cd28 4304 rval = qla2x00_configure_local_loop(vha);
1da177e4
LT		 4305 }
4306
4307 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
7c3df132 4308 if (LOOP_TRANSITION(vha)) {
83548fe2 4309 ql_dbg(ql_dbg_disc, vha, 0x2099,
7c3df132 4310 "Needs RSCN update and loop transition.\n");
1da177e4 4311 rval = QLA_FUNCTION_FAILED;
7c3df132 4312 }
e315cd28
AC		 4313 else
4314 rval = qla2x00_configure_fabric(vha);
1da177e4
LT		 4315 }
4316
4317 if (rval == QLA_SUCCESS) {
e315cd28
AC		 4318 if (atomic_read(&vha->loop_down_timer) ||
4319 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4
LT		 4320 rval = QLA_FUNCTION_FAILED;
4321 } else {
e315cd28 4322 atomic_set(&vha->loop_state, LOOP_READY);
7c3df132
SK		 4323 ql_dbg(ql_dbg_disc, vha, 0x2069,
4324 "LOOP READY.\n");
ec7193e2 4325 ha->flags.fw_init_done = 1;
3bb67df5
DKU		 4326
4327 /*
4328 * Process any ATIO queue entries that came in
4329 * while we weren't online.
4330 */
ead03855
QT		 4331 if (qla_tgt_mode_enabled(vha) ||
4332 qla_dual_mode_enabled(vha)) {
3bb67df5
DKU		 4333 if (IS_QLA27XX(ha) || IS_QLA83XX(ha)) {
4334 spin_lock_irqsave(&ha->tgt.atio_lock,
4335 flags);
4336 qlt_24xx_process_atio_queue(vha, 0);
4337 spin_unlock_irqrestore(
4338 &ha->tgt.atio_lock, flags);
4339 } else {
4340 spin_lock_irqsave(&ha->hardware_lock,
4341 flags);
4342 qlt_24xx_process_atio_queue(vha, 1);
4343 spin_unlock_irqrestore(
4344 &ha->hardware_lock, flags);
4345 }
4346 }
1da177e4
LT		 4347 }
4348 }
4349
4350 if (rval) {
7c3df132
SK		 4351 ql_dbg(ql_dbg_disc, vha, 0x206a,
4352 "%s *** FAILED ***.\n", __func__);
1da177e4 4353 } else {
7c3df132
SK		 4354 ql_dbg(ql_dbg_disc, vha, 0x206b,
4355 "%s: exiting normally.\n", __func__);
1da177e4
LT		 4356 }
4357
cc3ef7bc 4358 /* Restore state if a resync event occurred during processing */
e315cd28 4359 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
1da177e4 4360 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
e315cd28 4361 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
f4658b6c 4362 if (test_bit(RSCN_UPDATE, &save_flags)) {
e315cd28 4363 set_bit(RSCN_UPDATE, &vha->dpc_flags);
f4658b6c 4364 }
1da177e4
LT		 4365 }
4366
4367 return (rval);
4368}
4369
4370
4371
4372/*
4373 * qla2x00_configure_local_loop
4374 * Updates Fibre Channel Device Database with local loop devices.
4375 *
4376 * Input:
4377 * ha = adapter block pointer.
4378 *
4379 * Returns:
4380 * 0 = success.
4381 */
4382static int
e315cd28 4383qla2x00_configure_local_loop(scsi_qla_host_t *vha)
1da177e4
LT		 4384{
4385 int rval, rval2;
4386 int found_devs;
4387 int found;
4388 fc_port_t *fcport, *new_fcport;
4389
4390 uint16_t index;
4391 uint16_t entries;
4392 char *id_iter;
4393 uint16_t loop_id;
4394 uint8_t domain, area, al_pa;
e315cd28 4395 struct qla_hw_data *ha = vha->hw;
41dc529a 4396 unsigned long flags;
1da177e4
LT		 4397
4398 found_devs = 0;
4399 new_fcport = NULL;
642ef983 4400 entries = MAX_FIBRE_DEVICES_LOOP;
1da177e4 4401
1da177e4 4402 /* Get list of logged in devices. */
642ef983 4403 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
e315cd28 4404 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
1da177e4
LT		 4405 &entries);
4406 if (rval != QLA_SUCCESS)
4407 goto cleanup_allocation;
4408
83548fe2 4409 ql_dbg(ql_dbg_disc, vha, 0x2011,
7c3df132
SK		 4410 "Entries in ID list (%d).\n", entries);
4411 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
4412 (uint8_t *)ha->gid_list,
4413 entries * sizeof(struct gid_list_info));
1da177e4
LT		 4414
4415 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4416 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4417 if (new_fcport == NULL) {
83548fe2 4418 ql_log(ql_log_warn, vha, 0x2012,
7c3df132 4419 "Memory allocation failed for fcport.\n");
1da177e4
LT		 4420 rval = QLA_MEMORY_ALLOC_FAILED;
4421 goto cleanup_allocation;
4422 }
4423 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4424
4425 /*
4426 * Mark local devices that were present with FCF_DEVICE_LOST for now.
4427 */
e315cd28 4428 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4429 if (atomic_read(&fcport->state) == FCS_ONLINE &&
4430 fcport->port_type != FCT_BROADCAST &&
4431 (fcport->flags & FCF_FABRIC_DEVICE) == 0) {
4432
83548fe2 4433 ql_dbg(ql_dbg_disc, vha, 0x2096,
7c3df132
SK		 4434 "Marking port lost loop_id=0x%04x.\n",
4435 fcport->loop_id);
1da177e4 4436
41dc529a 4437 qla2x00_mark_device_lost(vha, fcport, 0, 0);
1da177e4
LT		 4438 }
4439 }
4440
4441 /* Add devices to port list. */
4442 id_iter = (char *)ha->gid_list;
4443 for (index = 0; index < entries; index++) {
4444 domain = ((struct gid_list_info *)id_iter)->domain;
4445 area = ((struct gid_list_info *)id_iter)->area;
4446 al_pa = ((struct gid_list_info *)id_iter)->al_pa;
abbd8870 4447 if (IS_QLA2100(ha) || IS_QLA2200(ha))
1da177e4
LT		 4448 loop_id = (uint16_t)
4449 ((struct gid_list_info *)id_iter)->loop_id_2100;
abbd8870 4450 else
1da177e4
LT		 4451 loop_id = le16_to_cpu(
4452 ((struct gid_list_info *)id_iter)->loop_id);
abbd8870 4453 id_iter += ha->gid_list_info_size;
1da177e4
LT		 4454
4455 /* Bypass reserved domain fields. */
4456 if ((domain & 0xf0) == 0xf0)
4457 continue;
4458
4459 /* Bypass if not same domain and area of adapter. */
f7d289f6 4460 if (area && domain &&
e315cd28 4461 (area != vha->d_id.b.area || domain != vha->d_id.b.domain))
1da177e4
LT		 4462 continue;
4463
4464 /* Bypass invalid local loop ID. */
4465 if (loop_id > LAST_LOCAL_LOOP_ID)
4466 continue;
4467
41dc529a 4468 memset(new_fcport->port_name, 0, WWN_SIZE);
370d550e 4469
1da177e4
LT		 4470 /* Fill in member data. */
4471 new_fcport->d_id.b.domain = domain;
4472 new_fcport->d_id.b.area = area;
4473 new_fcport->d_id.b.al_pa = al_pa;
4474 new_fcport->loop_id = loop_id;
41dc529a 4475
e315cd28 4476 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
1da177e4 4477 if (rval2 != QLA_SUCCESS) {
83548fe2 4478 ql_dbg(ql_dbg_disc, vha, 0x2097,
7c3df132
SK		 4479 "Failed to retrieve fcport information "
4480 "-- get_port_database=%x, loop_id=0x%04x.\n",
4481 rval2, new_fcport->loop_id);
83548fe2 4482 ql_dbg(ql_dbg_disc, vha, 0x2105,
7c3df132 4483 "Scheduling resync.\n");
e315cd28 4484 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 4485 continue;
4486 }
4487
41dc529a 4488 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4489 /* Check for matching device in port list. */
4490 found = 0;
4491 fcport = NULL;
e315cd28 4492 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 4493 if (memcmp(new_fcport->port_name, fcport->port_name,
4494 WWN_SIZE))
4495 continue;
4496
ddb9b126 4497 fcport->flags &= ~FCF_FABRIC_DEVICE;
1da177e4
LT		 4498 fcport->loop_id = new_fcport->loop_id;
4499 fcport->port_type = new_fcport->port_type;
4500 fcport->d_id.b24 = new_fcport->d_id.b24;
4501 memcpy(fcport->node_name, new_fcport->node_name,
4502 WWN_SIZE);
4503
41dc529a
QT		 4504 if (!fcport->login_succ) {
4505 vha->fcport_count++;
4506 fcport->login_succ = 1;
4507 fcport->disc_state = DSC_LOGIN_COMPLETE;
4508 }
4509
1da177e4
LT		 4510 found++;
4511 break;
4512 }
4513
4514 if (!found) {
4515 /* New device, add to fcports list. */
e315cd28 4516 list_add_tail(&new_fcport->list, &vha->vp_fcports);
1da177e4
LT		 4517
4518 /* Allocate a new replacement fcport. */
4519 fcport = new_fcport;
41dc529a
QT		 4520 if (!fcport->login_succ) {
4521 vha->fcport_count++;
4522 fcport->login_succ = 1;
4523 fcport->disc_state = DSC_LOGIN_COMPLETE;
4524 }
4525
4526 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4527
e315cd28 4528 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
41dc529a 4529
1da177e4 4530 if (new_fcport == NULL) {
83548fe2 4531 ql_log(ql_log_warn, vha, 0xd031,
7c3df132 4532 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4533 rval = QLA_MEMORY_ALLOC_FAILED;
4534 goto cleanup_allocation;
4535 }
41dc529a 4536 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1da177e4
LT		 4537 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
4538 }
4539
41dc529a
QT		 4540 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4541
d8b45213 4542 /* Base iIDMA settings on HBA port speed. */
a3cbdfad 4543 fcport->fp_speed = ha->link_data_rate;
d8b45213 4544
e315cd28 4545 qla2x00_update_fcport(vha, fcport);
1da177e4
LT		 4546
4547 found_devs++;
4548 }
4549
4550cleanup_allocation:
c9475cb0 4551 kfree(new_fcport);
1da177e4
LT		 4552
4553 if (rval != QLA_SUCCESS) {
83548fe2 4554 ql_dbg(ql_dbg_disc, vha, 0x2098,
7c3df132 4555 "Configure local loop error exit: rval=%x.\n", rval);
1da177e4
LT		 4556 }
4557
1da177e4
LT		 4558 return (rval);
4559}
4560
d8b45213 4561static void
e315cd28 4562qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
d8b45213 4563{
d8b45213 4564 int rval;
93f2bd67 4565 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 4566 struct qla_hw_data *ha = vha->hw;
d8b45213 4567
c76f2c01 4568 if (!IS_IIDMA_CAPABLE(ha))
d8b45213
AV		 4569 return;
4570
c9afb9a2
GM		 4571 if (atomic_read(&fcport->state) != FCS_ONLINE)
4572 return;
4573
39bd9622
AV		 4574 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
4575 fcport->fp_speed > ha->link_data_rate)
d8b45213
AV		 4576 return;
4577
e315cd28 4578 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
a3cbdfad 4579 mb);
d8b45213 4580 if (rval != QLA_SUCCESS) {
7c3df132 4581 ql_dbg(ql_dbg_disc, vha, 0x2004,
7b833558
OK		 4582 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
4583 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
d8b45213 4584 } else {
7c3df132 4585 ql_dbg(ql_dbg_disc, vha, 0x2005,
7b833558 4586 "iIDMA adjusted to %s GB/s on %8phN.\n",
d0297c9a 4587 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
7b833558 4588 fcport->port_name);
d8b45213
AV		 4589 }
4590}
4591
726b8548 4592/* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/
23be331d 4593static void
e315cd28 4594qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
8482e118
AV		 4595{
4596 struct fc_rport_identifiers rport_ids;
bdf79621 4597 struct fc_rport *rport;
044d78e1 4598 unsigned long flags;
8482e118 4599
f8b02a85
AV		 4600 rport_ids.node_name = wwn_to_u64(fcport->node_name);
4601 rport_ids.port_name = wwn_to_u64(fcport->port_name);
8482e118
AV		 4602 rport_ids.port_id = fcport->d_id.b.domain << 16 |
4603 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
77d74143 4604 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
e315cd28 4605 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
77d74143 4606 if (!rport) {
7c3df132
SK		 4607 ql_log(ql_log_warn, vha, 0x2006,
4608 "Unable to allocate fc remote port.\n");
77d74143
AV		 4609 return;
4610 }
2d70c103 4611
044d78e1 4612 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
19a7b4ae 4613 *((fc_port_t **)rport->dd_data) = fcport;
044d78e1 4614 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
d97994dc 4615
ad3e0eda 4616 rport->supported_classes = fcport->supported_classes;
77d74143 4617
8482e118
AV		 4618 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
4619 if (fcport->port_type == FCT_INITIATOR)
4620 rport_ids.roles |= FC_RPORT_ROLE_FCP_INITIATOR;
4621 if (fcport->port_type == FCT_TARGET)
4622 rport_ids.roles |= FC_RPORT_ROLE_FCP_TARGET;
726b8548 4623
83548fe2
QT		 4624 ql_dbg(ql_dbg_disc, vha, 0x20ee,
4625 "%s %8phN. rport %p is %s mode\n",
4626 __func__, fcport->port_name, rport,
4627 (fcport->port_type == FCT_TARGET) ? "tgt" : "ini");
726b8548 4628
77d74143 4629 fc_remote_port_rolechg(rport, rport_ids.roles);
1da177e4
LT		 4630}
4631
23be331d
AB		 4632/*
4633 * qla2x00_update_fcport
4634 * Updates device on list.
4635 *
4636 * Input:
4637 * ha = adapter block pointer.
4638 * fcport = port structure pointer.
4639 *
4640 * Return:
4641 * 0 - Success
4642 * BIT_0 - error
4643 *
4644 * Context:
4645 * Kernel context.
4646 */
4647void
e315cd28 4648qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
23be331d 4649{
e315cd28 4650 fcport->vha = vha;
8ae6d9c7 4651
726b8548
QT		 4652 if (IS_SW_RESV_ADDR(fcport->d_id))
4653 return;
4654
83548fe2 4655 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
726b8548
QT		 4656 __func__, fcport->port_name);
4657
8ae6d9c7
GM		 4658 if (IS_QLAFX00(vha->hw)) {
4659 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
d20ed91b 4660 goto reg_port;
8ae6d9c7 4661 }
23be331d 4662 fcport->login_retry = 0;
5ff1d584 4663 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
726b8548
QT		 4664 fcport->disc_state = DSC_LOGIN_COMPLETE;
4665 fcport->deleted = 0;
4666 fcport->logout_on_delete = 1;
23be331d 4667
e84067d7
DG		 4668 if (fcport->fc4f_nvme) {
4669 qla_nvme_register_remote(vha, fcport);
4670 return;
4671 }
4672
1f93da52 4673 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
e315cd28 4674 qla2x00_iidma_fcport(vha, fcport);
21090cbe 4675 qla24xx_update_fcport_fcp_prio(vha, fcport);
d20ed91b
AP		 4676
4677reg_port:
726b8548
QT		 4678 switch (vha->host->active_mode) {
4679 case MODE_INITIATOR:
d20ed91b 4680 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4681 break;
4682 case MODE_TARGET:
4683 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4684 !vha->vha_tgt.qla_tgt->tgt_stopped)
4685 qlt_fc_port_added(vha, fcport);
4686 break;
4687 case MODE_DUAL:
d20ed91b 4688 qla2x00_reg_remote_port(vha, fcport);
726b8548
QT		 4689 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
4690 !vha->vha_tgt.qla_tgt->tgt_stopped)
4691 qlt_fc_port_added(vha, fcport);
4692 break;
4693 default:
4694 break;
d20ed91b 4695 }
23be331d
AB		 4696}
4697
1da177e4
LT		 4698/*
4699 * qla2x00_configure_fabric
4700 * Setup SNS devices with loop ID's.
4701 *
4702 * Input:
4703 * ha = adapter block pointer.
4704 *
4705 * Returns:
4706 * 0 = success.
4707 * BIT_0 = error
4708 */
4709static int
e315cd28 4710qla2x00_configure_fabric(scsi_qla_host_t *vha)
1da177e4 4711{
b3b02e6e 4712 int rval;
726b8548 4713 fc_port_t *fcport;
1da177e4 4714 uint16_t mb[MAILBOX_REGISTER_COUNT];
0107109e 4715 uint16_t loop_id;
1da177e4 4716 LIST_HEAD(new_fcports);
e315cd28 4717 struct qla_hw_data *ha = vha->hw;
df673274 4718 int discovery_gen;
1da177e4
LT		 4719
4720 /* If FL port exists, then SNS is present */
e428924c 4721 if (IS_FWI2_CAPABLE(ha))
0107109e
AV		 4722 loop_id = NPH_F_PORT;
4723 else
4724 loop_id = SNS_FL_PORT;
e315cd28 4725 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
1da177e4 4726 if (rval != QLA_SUCCESS) {
83548fe2 4727 ql_dbg(ql_dbg_disc, vha, 0x20a0,
7c3df132 4728 "MBX_GET_PORT_NAME failed, No FL Port.\n");
1da177e4 4729
e315cd28 4730 vha->device_flags &= ~SWITCH_FOUND;
1da177e4
LT		 4731 return (QLA_SUCCESS);
4732 }
e315cd28 4733 vha->device_flags |= SWITCH_FOUND;
1da177e4 4734
41dc529a
QT		 4735
4736 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
4737 rval = qla2x00_send_change_request(vha, 0x3, 0);
4738 if (rval != QLA_SUCCESS)
4739 ql_log(ql_log_warn, vha, 0x121,
4740 "Failed to enable receiving of RSCN requests: 0x%x.\n",
4741 rval);
4742 }
4743
4744
1da177e4 4745 do {
726b8548
QT		 4746 qla2x00_mgmt_svr_login(vha);
4747
cca5335c
AV		 4748 /* FDMI support. */
4749 if (ql2xfdmienable &&
e315cd28
AC		 4750 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
4751 qla2x00_fdmi_register(vha);
cca5335c 4752
1da177e4 4753 /* Ensure we are logged into the SNS. */
a14c7711 4754 loop_id = NPH_SNS_LID(ha);
0b91d116
CD		 4755 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
4756 0xfc, mb, BIT_1|BIT_0);
a14c7711
JC		 4757 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
4758 ql_dbg(ql_dbg_disc, vha, 0x20a1,
4759 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
4760 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
0b91d116 4761 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
e452ceb6 4762 return rval;
0b91d116 4763 }
e315cd28
AC		 4764 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
4765 if (qla2x00_rft_id(vha)) {
1da177e4 4766 /* EMPTY */
83548fe2 4767 ql_dbg(ql_dbg_disc, vha, 0x20a2,
7c3df132 4768 "Register FC-4 TYPE failed.\n");
b98ae0d7
QT		 4769 if (test_bit(LOOP_RESYNC_NEEDED,
4770 &vha->dpc_flags))
4771 break;
1da177e4 4772 }
d3bae931 4773 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
1da177e4 4774 /* EMPTY */
83548fe2 4775 ql_dbg(ql_dbg_disc, vha, 0x209a,
7c3df132 4776 "Register FC-4 Features failed.\n");
b98ae0d7
QT		 4777 if (test_bit(LOOP_RESYNC_NEEDED,
4778 &vha->dpc_flags))
4779 break;
1da177e4 4780 }
d3bae931
DG		 4781 if (vha->flags.nvme_enabled) {
4782 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
4783 ql_dbg(ql_dbg_disc, vha, 0x2049,
4784 "Register NVME FC Type Features failed.\n");
4785 }
4786 }
e315cd28 4787 if (qla2x00_rnn_id(vha)) {
1da177e4 4788 /* EMPTY */
83548fe2 4789 ql_dbg(ql_dbg_disc, vha, 0x2104,
7c3df132 4790 "Register Node Name failed.\n");
b98ae0d7
QT		 4791 if (test_bit(LOOP_RESYNC_NEEDED,
4792 &vha->dpc_flags))
4793 break;
e315cd28 4794 } else if (qla2x00_rsnn_nn(vha)) {
1da177e4 4795 /* EMPTY */
83548fe2 4796 ql_dbg(ql_dbg_disc, vha, 0x209b,
0bf0efa1 4797 "Register Symbolic Node Name failed.\n");
b98ae0d7
QT		 4798 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4799 break;
1da177e4
LT		 4800 }
4801 }
4802
827210ba
JC		 4803 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4804 fcport->scan_state = QLA_FCPORT_SCAN;
4805 }
4806
df673274
AP		 4807 /* Mark the time right before querying FW for connected ports.
4808 * This process is long, asynchronous and by the time it's done,
4809 * collected information might not be accurate anymore. E.g.
4810 * disconnected port might have re-connected and a brand new
4811 * session has been created. In this case session's generation
4812 * will be newer than discovery_gen. */
4813 qlt_do_generation_tick(vha, &discovery_gen);
4814
726b8548 4815 rval = qla2x00_find_all_fabric_devs(vha);
1da177e4
LT		 4816 if (rval != QLA_SUCCESS)
4817 break;
1da177e4
LT		 4818 } while (0);
4819
e84067d7
DG		 4820 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
4821 qla_nvme_register_hba(vha);
4822
726b8548 4823 if (rval)
7c3df132
SK		 4824 ql_dbg(ql_dbg_disc, vha, 0x2068,
4825 "Configure fabric error exit rval=%d.\n", rval);
1da177e4
LT		 4826
4827 return (rval);
4828}
4829
1da177e4
LT		 4830/*
4831 * qla2x00_find_all_fabric_devs
4832 *
4833 * Input:
4834 * ha = adapter block pointer.
4835 * dev = database device entry pointer.
4836 *
4837 * Returns:
4838 * 0 = success.
4839 *
4840 * Context:
4841 * Kernel context.
4842 */
4843static int
726b8548 4844qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
1da177e4
LT		 4845{
4846 int rval;
4847 uint16_t loop_id;
726b8548 4848 fc_port_t *fcport, *new_fcport;
1da177e4
LT		 4849 int found;
4850
4851 sw_info_t *swl;
4852 int swl_idx;
4853 int first_dev, last_dev;
1516ef44 4854 port_id_t wrap = {}, nxt_d_id;
e315cd28 4855 struct qla_hw_data *ha = vha->hw;
bb4cf5b7 4856 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
726b8548 4857 unsigned long flags;
1da177e4
LT		 4858
4859 rval = QLA_SUCCESS;
4860
4861 /* Try GID_PT to get device list, else GAN. */
7a67735b 4862 if (!ha->swl)
642ef983 4863 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
7a67735b
AV		 4864 GFP_KERNEL);
4865 swl = ha->swl;
bbfbbbc1 4866 if (!swl) {
1da177e4 4867 /*EMPTY*/
83548fe2 4868 ql_dbg(ql_dbg_disc, vha, 0x209c,
7c3df132 4869 "GID_PT allocations failed, fallback on GA_NXT.\n");
1da177e4 4870 } else {
642ef983 4871 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
e315cd28 4872 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
1da177e4 4873 swl = NULL;
b98ae0d7
QT		 4874 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4875 return rval;
e315cd28 4876 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4877 swl = NULL;
b98ae0d7
QT		 4878 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4879 return rval;
e315cd28 4880 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
1da177e4 4881 swl = NULL;
b98ae0d7
QT		 4882 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4883 return rval;
726b8548
QT		 4884 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
4885 swl = NULL;
b98ae0d7
QT		 4886 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4887 return rval;
1da177e4 4888 }
e8c72ba5
CD		 4889
4890 /* If other queries succeeded probe for FC-4 type */
b98ae0d7 4891 if (swl) {
e8c72ba5 4892 qla2x00_gff_id(vha, swl);
b98ae0d7
QT		 4893 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4894 return rval;
4895 }
1da177e4
LT		 4896 }
4897 swl_idx = 0;
4898
4899 /* Allocate temporary fcport for any new fcports discovered. */
e315cd28 4900 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 4901 if (new_fcport == NULL) {
83548fe2 4902 ql_log(ql_log_warn, vha, 0x209d,
7c3df132 4903 "Failed to allocate memory for fcport.\n");
1da177e4
LT		 4904 return (QLA_MEMORY_ALLOC_FAILED);
4905 }
4906 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
1da177e4
LT		 4907 /* Set start port ID scan at adapter ID. */
4908 first_dev = 1;
4909 last_dev = 0;
4910
4911 /* Starting free loop ID. */
e315cd28
AC		 4912 loop_id = ha->min_external_loopid;
4913 for (; loop_id <= ha->max_loop_id; loop_id++) {
4914 if (qla2x00_is_reserved_id(vha, loop_id))
1da177e4
LT		 4915 continue;
4916
3a6478df
GM		 4917 if (ha->current_topology == ISP_CFG_FL &&
4918 (atomic_read(&vha->loop_down_timer) ||
4919 LOOP_TRANSITION(vha))) {
bb2d52b2
AV		 4920 atomic_set(&vha->loop_down_timer, 0);
4921 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
4922 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
1da177e4 4923 break;
bb2d52b2 4924 }
1da177e4
LT		 4925
4926 if (swl != NULL) {
4927 if (last_dev) {
4928 wrap.b24 = new_fcport->d_id.b24;
4929 } else {
4930 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
4931 memcpy(new_fcport->node_name,
4932 swl[swl_idx].node_name, WWN_SIZE);
4933 memcpy(new_fcport->port_name,
4934 swl[swl_idx].port_name, WWN_SIZE);
d8b45213
AV		 4935 memcpy(new_fcport->fabric_port_name,
4936 swl[swl_idx].fabric_port_name, WWN_SIZE);
4937 new_fcport->fp_speed = swl[swl_idx].fp_speed;
e8c72ba5 4938 new_fcport->fc4_type = swl[swl_idx].fc4_type;
1da177e4 4939
a5d42f4c 4940 new_fcport->nvme_flag = 0;
1a28faa0 4941 new_fcport->fc4f_nvme = 0;
a5d42f4c
DG		 4942 if (vha->flags.nvme_enabled &&
4943 swl[swl_idx].fc4f_nvme) {
4944 new_fcport->fc4f_nvme =
4945 swl[swl_idx].fc4f_nvme;
4946 ql_log(ql_log_info, vha, 0x2131,
4947 "FOUND: NVME port %8phC as FC Type 28h\n",
4948 new_fcport->port_name);
4949 }
4950
1da177e4
LT		 4951 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
4952 last_dev = 1;
4953 }
4954 swl_idx++;
4955 }
4956 } else {
4957 /* Send GA_NXT to the switch */
e315cd28 4958 rval = qla2x00_ga_nxt(vha, new_fcport);
1da177e4 4959 if (rval != QLA_SUCCESS) {
83548fe2 4960 ql_log(ql_log_warn, vha, 0x209e,
7c3df132
SK		 4961 "SNS scan failed -- assuming "
4962 "zero-entry result.\n");
1da177e4
LT		 4963 rval = QLA_SUCCESS;
4964 break;
4965 }
4966 }
4967
4968 /* If wrap on switch device list, exit. */
4969 if (first_dev) {
4970 wrap.b24 = new_fcport->d_id.b24;
4971 first_dev = 0;
4972 } else if (new_fcport->d_id.b24 == wrap.b24) {
83548fe2 4973 ql_dbg(ql_dbg_disc, vha, 0x209f,
7c3df132
SK		 4974 "Device wrap (%02x%02x%02x).\n",
4975 new_fcport->d_id.b.domain,
4976 new_fcport->d_id.b.area,
4977 new_fcport->d_id.b.al_pa);
1da177e4
LT		 4978 break;
4979 }
4980
2c3dfe3f 4981 /* Bypass if same physical adapter. */
e315cd28 4982 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
1da177e4
LT		 4983 continue;
4984
2c3dfe3f 4985 /* Bypass virtual ports of the same host. */
bb4cf5b7
CD		 4986 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
4987 continue;
2c3dfe3f 4988
f7d289f6
AV		 4989 /* Bypass if same domain and area of adapter. */
4990 if (((new_fcport->d_id.b24 & 0xffff00) ==
e315cd28 4991 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
f7d289f6
AV		 4992 ISP_CFG_FL)
4993 continue;
4994
1da177e4
LT		 4995 /* Bypass reserved domain fields. */
4996 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
4997 continue;
4998
e8c72ba5 4999 /* Bypass ports whose FCP-4 type is not FCP_SCSI */
4da26e16
CD		 5000 if (ql2xgffidenable &&
5001 (new_fcport->fc4_type != FC4_TYPE_FCP_SCSI &&
5002 new_fcport->fc4_type != FC4_TYPE_UNKNOWN))
e8c72ba5
CD		 5003 continue;
5004
726b8548
QT		 5005 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5006
1da177e4
LT		 5007 /* Locate matching device in database. */
5008 found = 0;
e315cd28 5009 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1da177e4
LT		 5010 if (memcmp(new_fcport->port_name, fcport->port_name,
5011 WWN_SIZE))
5012 continue;
5013
827210ba 5014 fcport->scan_state = QLA_FCPORT_FOUND;
b3b02e6e 5015
1da177e4
LT		 5016 found++;
5017
d8b45213
AV		 5018 /* Update port state. */
5019 memcpy(fcport->fabric_port_name,
5020 new_fcport->fabric_port_name, WWN_SIZE);
5021 fcport->fp_speed = new_fcport->fp_speed;
5022
1da177e4 5023 /*
b2032fd5
RD		 5024 * If address the same and state FCS_ONLINE
5025 * (or in target mode), nothing changed.
1da177e4
LT		 5026 */
5027 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
b2032fd5 5028 (atomic_read(&fcport->state) == FCS_ONLINE ||
726b8548 5029 (vha->host->active_mode == MODE_TARGET))) {
1da177e4
LT		 5030 break;
5031 }
5032
5033 /*
5034 * If device was not a fabric device before.
5035 */
5036 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
5037 fcport->d_id.b24 = new_fcport->d_id.b24;
5f16b331 5038 qla2x00_clear_loop_id(fcport);
1da177e4
LT		 5039 fcport->flags |= (FCF_FABRIC_DEVICE |
5040 FCF_LOGIN_NEEDED);
1da177e4
LT		 5041 break;
5042 }
5043
5044 /*
5045 * Port ID changed or device was marked to be updated;
5046 * Log it out if still logged in and mark it for
5047 * relogin later.
5048 */
726b8548 5049 if (qla_tgt_mode_enabled(base_vha)) {
b2032fd5
RD		 5050 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
5051 "port changed FC ID, %8phC"
5052 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
5053 fcport->port_name,
5054 fcport->d_id.b.domain,
5055 fcport->d_id.b.area,
5056 fcport->d_id.b.al_pa,
5057 fcport->loop_id,
5058 new_fcport->d_id.b.domain,
5059 new_fcport->d_id.b.area,
5060 new_fcport->d_id.b.al_pa);
5061 fcport->d_id.b24 = new_fcport->d_id.b24;
5062 break;
5063 }
5064
1da177e4
LT		 5065 fcport->d_id.b24 = new_fcport->d_id.b24;
5066 fcport->flags |= FCF_LOGIN_NEEDED;
1da177e4
LT		 5067 break;
5068 }
5069
726b8548
QT		 5070 if (found) {
5071 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1da177e4 5072 continue;
726b8548 5073 }
1da177e4 5074 /* If device was not in our fcports list, then add it. */
b2032fd5 5075 new_fcport->scan_state = QLA_FCPORT_FOUND;
726b8548
QT		 5076 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5077
5078 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5079
1da177e4
LT		 5080
5081 /* Allocate a new replacement fcport. */
5082 nxt_d_id.b24 = new_fcport->d_id.b24;
e315cd28 5083 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
1da177e4 5084 if (new_fcport == NULL) {
83548fe2 5085 ql_log(ql_log_warn, vha, 0xd032,
7c3df132 5086 "Memory allocation failed for fcport.\n");
1da177e4
LT		 5087 return (QLA_MEMORY_ALLOC_FAILED);
5088 }
5089 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5090 new_fcport->d_id.b24 = nxt_d_id.b24;
5091 }
5092
726b8548
QT		 5093 qla2x00_free_fcport(new_fcport);
5094
5095 /*
5096 * Logout all previous fabric dev marked lost, except FCP2 devices.
5097 */
5098 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5099 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5100 break;
5101
5102 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0 ||
5103 (fcport->flags & FCF_LOGIN_NEEDED) == 0)
5104 continue;
5105
5106 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5107 if ((qla_dual_mode_enabled(vha) ||
5108 qla_ini_mode_enabled(vha)) &&
5109 atomic_read(&fcport->state) == FCS_ONLINE) {
5110 qla2x00_mark_device_lost(vha, fcport,
5111 ql2xplogiabsentdevice, 0);
5112 if (fcport->loop_id != FC_NO_LOOP_ID &&
5113 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5114 fcport->port_type != FCT_INITIATOR &&
5115 fcport->port_type != FCT_BROADCAST) {
83548fe2 5116 ql_dbg(ql_dbg_disc, vha, 0x20f0,
726b8548
QT		 5117 "%s %d %8phC post del sess\n",
5118 __func__, __LINE__,
5119 fcport->port_name);
5120
5121 qlt_schedule_sess_for_deletion_lock
5122 (fcport);
5123 continue;
5124 }
5125 }
5126 }
1da177e4 5127
726b8548
QT		 5128 if (fcport->scan_state == QLA_FCPORT_FOUND)
5129 qla24xx_fcport_handle_login(vha, fcport);
5130 }
1da177e4
LT		 5131 return (rval);
5132}
5133
5134/*
5135 * qla2x00_find_new_loop_id
5136 * Scan through our port list and find a new usable loop ID.
5137 *
5138 * Input:
5139 * ha: adapter state pointer.
5140 * dev: port structure pointer.
5141 *
5142 * Returns:
5143 * qla2x00 local function return status code.
5144 *
5145 * Context:
5146 * Kernel context.
5147 */
03bcfb57 5148int
e315cd28 5149qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
1da177e4
LT		 5150{
5151 int rval;
e315cd28 5152 struct qla_hw_data *ha = vha->hw;
feafb7b1 5153 unsigned long flags = 0;
1da177e4
LT		 5154
5155 rval = QLA_SUCCESS;
5156
5f16b331 5157 spin_lock_irqsave(&ha->vport_slock, flags);
1da177e4 5158
5f16b331
CD		 5159 dev->loop_id = find_first_zero_bit(ha->loop_id_map,
5160 LOOPID_MAP_SIZE);
5161 if (dev->loop_id >= LOOPID_MAP_SIZE ||
5162 qla2x00_is_reserved_id(vha, dev->loop_id)) {
5163 dev->loop_id = FC_NO_LOOP_ID;
5164 rval = QLA_FUNCTION_FAILED;
5165 } else
5166 set_bit(dev->loop_id, ha->loop_id_map);
1da177e4 5167
5f16b331 5168 spin_unlock_irqrestore(&ha->vport_slock, flags);
1da177e4 5169
5f16b331
CD		 5170 if (rval == QLA_SUCCESS)
5171 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
5172 "Assigning new loopid=%x, portid=%x.\n",
5173 dev->loop_id, dev->d_id.b24);
5174 else
5175 ql_log(ql_log_warn, dev->vha, 0x2087,
5176 "No loop_id's available, portid=%x.\n",
5177 dev->d_id.b24);
1da177e4
LT		 5178
5179 return (rval);
5180}
5181
1da177e4
LT		 5182
5183/*
5184 * qla2x00_fabric_login
5185 * Issue fabric login command.
5186 *
5187 * Input:
5188 * ha = adapter block pointer.
5189 * device = pointer to FC device type structure.
5190 *
5191 * Returns:
5192 * 0 - Login successfully
5193 * 1 - Login failed
5194 * 2 - Initiator device
5195 * 3 - Fatal error
5196 */
5197int
e315cd28 5198qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
1da177e4
LT		 5199 uint16_t *next_loopid)
5200{
5201 int rval;
5202 int retry;
5203 uint16_t tmp_loopid;
5204 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28 5205 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 5206
5207 retry = 0;
5208 tmp_loopid = 0;
5209
5210 for (;;) {
7c3df132
SK		 5211 ql_dbg(ql_dbg_disc, vha, 0x2000,
5212 "Trying Fabric Login w/loop id 0x%04x for port "
5213 "%02x%02x%02x.\n",
5214 fcport->loop_id, fcport->d_id.b.domain,
5215 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5216
5217 /* Login fcport on switch. */
0b91d116 5218 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
1da177e4
LT		 5219 fcport->d_id.b.domain, fcport->d_id.b.area,
5220 fcport->d_id.b.al_pa, mb, BIT_0);
0b91d116
CD		 5221 if (rval != QLA_SUCCESS) {
5222 return rval;
5223 }
1da177e4
LT		 5224 if (mb[0] == MBS_PORT_ID_USED) {
5225 /*
5226 * Device has another loop ID. The firmware team
0107109e
AV		 5227 * recommends the driver perform an implicit login with
5228 * the specified ID again. The ID we just used is save
5229 * here so we return with an ID that can be tried by
5230 * the next login.
1da177e4
LT		 5231 */
5232 retry++;
5233 tmp_loopid = fcport->loop_id;
5234 fcport->loop_id = mb[1];
5235
7c3df132
SK		 5236 ql_dbg(ql_dbg_disc, vha, 0x2001,
5237 "Fabric Login: port in use - next loop "
5238 "id=0x%04x, port id= %02x%02x%02x.\n",
1da177e4 5239 fcport->loop_id, fcport->d_id.b.domain,
7c3df132 5240 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1da177e4
LT		 5241
5242 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
5243 /*
5244 * Login succeeded.
5245 */
5246 if (retry) {
5247 /* A retry occurred before. */
5248 *next_loopid = tmp_loopid;
5249 } else {
5250 /*
5251 * No retry occurred before. Just increment the
5252 * ID value for next login.
5253 */
5254 *next_loopid = (fcport->loop_id + 1);
5255 }
5256
5257 if (mb[1] & BIT_0) {
5258 fcport->port_type = FCT_INITIATOR;
5259 } else {
5260 fcport->port_type = FCT_TARGET;
5261 if (mb[1] & BIT_1) {
8474f3a0 5262 fcport->flags |= FCF_FCP2_DEVICE;
1da177e4
LT		 5263 }
5264 }
5265
ad3e0eda
AV		 5266 if (mb[10] & BIT_0)
5267 fcport->supported_classes |= FC_COS_CLASS2;
5268 if (mb[10] & BIT_1)
5269 fcport->supported_classes |= FC_COS_CLASS3;
5270
2d70c103
NB		 5271 if (IS_FWI2_CAPABLE(ha)) {
5272 if (mb[10] & BIT_7)
5273 fcport->flags |=
5274 FCF_CONF_COMP_SUPPORTED;
5275 }
5276
1da177e4
LT		 5277 rval = QLA_SUCCESS;
5278 break;
5279 } else if (mb[0] == MBS_LOOP_ID_USED) {
5280 /*
5281 * Loop ID already used, try next loop ID.
5282 */
5283 fcport->loop_id++;
e315cd28 5284 rval = qla2x00_find_new_loop_id(vha, fcport);
1da177e4
LT		 5285 if (rval != QLA_SUCCESS) {
5286 /* Ran out of loop IDs to use */
5287 break;
5288 }
5289 } else if (mb[0] == MBS_COMMAND_ERROR) {
5290 /*
5291 * Firmware possibly timed out during login. If NO
5292 * retries are left to do then the device is declared
5293 * dead.
5294 */
5295 *next_loopid = fcport->loop_id;
e315cd28 5296 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5297 fcport->d_id.b.domain, fcport->d_id.b.area,
5298 fcport->d_id.b.al_pa);
e315cd28 5299 qla2x00_mark_device_lost(vha, fcport, 1, 0);
1da177e4
LT		 5300
5301 rval = 1;
5302 break;
5303 } else {
5304 /*
5305 * unrecoverable / not handled error
5306 */
7c3df132
SK		 5307 ql_dbg(ql_dbg_disc, vha, 0x2002,
5308 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
5309 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
5310 fcport->d_id.b.area, fcport->d_id.b.al_pa,
5311 fcport->loop_id, jiffies);
1da177e4
LT		 5312
5313 *next_loopid = fcport->loop_id;
e315cd28 5314 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
1c7c6357
AV		 5315 fcport->d_id.b.domain, fcport->d_id.b.area,
5316 fcport->d_id.b.al_pa);
5f16b331 5317 qla2x00_clear_loop_id(fcport);
0eedfcf0 5318 fcport->login_retry = 0;
1da177e4
LT		 5319
5320 rval = 3;
5321 break;
5322 }
5323 }
5324
5325 return (rval);
5326}
5327
5328/*
5329 * qla2x00_local_device_login
5330 * Issue local device login command.
5331 *
5332 * Input:
5333 * ha = adapter block pointer.
5334 * loop_id = loop id of device to login to.
5335 *
5336 * Returns (Where's the #define!!!!):
5337 * 0 - Login successfully
5338 * 1 - Login failed
5339 * 3 - Fatal error
5340 */
5341int
e315cd28 5342qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
1da177e4
LT		 5343{
5344 int rval;
5345 uint16_t mb[MAILBOX_REGISTER_COUNT];
5346
5347 memset(mb, 0, sizeof(mb));
e315cd28 5348 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
1da177e4
LT		 5349 if (rval == QLA_SUCCESS) {
5350 /* Interrogate mailbox registers for any errors */
5351 if (mb[0] == MBS_COMMAND_ERROR)
5352 rval = 1;
5353 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
5354 /* device not in PCB table */
5355 rval = 3;
5356 }
5357
5358 return (rval);
5359}
5360
5361/*
5362 * qla2x00_loop_resync
5363 * Resync with fibre channel devices.
5364 *
5365 * Input:
5366 * ha = adapter block pointer.
5367 *
5368 * Returns:
5369 * 0 = success
5370 */
5371int
e315cd28 5372qla2x00_loop_resync(scsi_qla_host_t *vha)
1da177e4 5373{
73208dfd 5374 int rval = QLA_SUCCESS;
1da177e4 5375 uint32_t wait_time;
67c2e93a
AC		 5376 struct req_que *req;
5377 struct rsp_que *rsp;
5378
d7459527 5379 req = vha->req;
67c2e93a 5380 rsp = req->rsp;
1da177e4 5381
e315cd28
AC		 5382 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5383 if (vha->flags.online) {
5384 if (!(rval = qla2x00_fw_ready(vha))) {
1da177e4
LT		 5385 /* Wait at most MAX_TARGET RSCNs for a stable link. */
5386 wait_time = 256;
5387 do {
8ae6d9c7
GM		 5388 if (!IS_QLAFX00(vha->hw)) {
5389 /*
5390 * Issue a marker after FW becomes
5391 * ready.
5392 */
5393 qla2x00_marker(vha, req, rsp, 0, 0,
5394 MK_SYNC_ALL);
5395 vha->marker_needed = 0;
5396 }
1da177e4
LT		 5397
5398 /* Remap devices on Loop. */
e315cd28 5399 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4 5400
8ae6d9c7
GM		 5401 if (IS_QLAFX00(vha->hw))
5402 qlafx00_configure_devices(vha);
5403 else
5404 qla2x00_configure_loop(vha);
5405
1da177e4 5406 wait_time--;
e315cd28
AC		 5407 } while (!atomic_read(&vha->loop_down_timer) &&
5408 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
5409 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
5410 &vha->dpc_flags)));
1da177e4 5411 }
1da177e4
LT		 5412 }
5413
e315cd28 5414 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
1da177e4 5415 return (QLA_FUNCTION_FAILED);
1da177e4 5416
e315cd28 5417 if (rval)
7c3df132
SK		 5418 ql_dbg(ql_dbg_disc, vha, 0x206c,
5419 "%s *** FAILED ***.\n", __func__);
1da177e4
LT		 5420
5421 return (rval);
5422}
5423
579d12b5
SK		 5424/*
5425* qla2x00_perform_loop_resync
5426* Description: This function will set the appropriate flags and call
5427* qla2x00_loop_resync. If successful loop will be resynced
5428* Arguments : scsi_qla_host_t pointer
5429* returm : Success or Failure
5430*/
5431
5432int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
5433{
5434 int32_t rval = 0;
5435
5436 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
5437 /*Configure the flags so that resync happens properly*/
5438 atomic_set(&ha->loop_down_timer, 0);
5439 if (!(ha->device_flags & DFLG_NO_CABLE)) {
5440 atomic_set(&ha->loop_state, LOOP_UP);
5441 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
5442 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
5443 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
5444
5445 rval = qla2x00_loop_resync(ha);
5446 } else
5447 atomic_set(&ha->loop_state, LOOP_DEAD);
5448
5449 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
5450 }
5451
5452 return rval;
5453}
5454
d97994dc 5455void
67becc00 5456qla2x00_update_fcports(scsi_qla_host_t *base_vha)
d97994dc
AV		 5457{
5458 fc_port_t *fcport;
feafb7b1
AE		 5459 struct scsi_qla_host *vha;
5460 struct qla_hw_data *ha = base_vha->hw;
5461 unsigned long flags;
d97994dc 5462
feafb7b1 5463 spin_lock_irqsave(&ha->vport_slock, flags);
d97994dc 5464 /* Go with deferred removal of rport references. */
feafb7b1
AE		 5465 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
5466 atomic_inc(&vha->vref_count);
5467 list_for_each_entry(fcport, &vha->vp_fcports, list) {
8ae598d0 5468 if (fcport->drport &&
feafb7b1
AE		 5469 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
5470 spin_unlock_irqrestore(&ha->vport_slock, flags);
67becc00 5471 qla2x00_rport_del(fcport);
df673274 5472
feafb7b1
AE		 5473 spin_lock_irqsave(&ha->vport_slock, flags);
5474 }
5475 }
5476 atomic_dec(&vha->vref_count);
c4a9b538 5477 wake_up(&vha->vref_waitq);
feafb7b1
AE		 5478 }
5479 spin_unlock_irqrestore(&ha->vport_slock, flags);
d97994dc
AV		 5480}
5481
7d613ac6
SV		 5482/* Assumes idc_lock always held on entry */
5483void
5484qla83xx_reset_ownership(scsi_qla_host_t *vha)
5485{
5486 struct qla_hw_data *ha = vha->hw;
5487 uint32_t drv_presence, drv_presence_mask;
5488 uint32_t dev_part_info1, dev_part_info2, class_type;
5489 uint32_t class_type_mask = 0x3;
5490 uint16_t fcoe_other_function = 0xffff, i;
5491
7ec0effd
AD		 5492 if (IS_QLA8044(ha)) {
5493 drv_presence = qla8044_rd_direct(vha,
5494 QLA8044_CRB_DRV_ACTIVE_INDEX);
5495 dev_part_info1 = qla8044_rd_direct(vha,
5496 QLA8044_CRB_DEV_PART_INFO_INDEX);
5497 dev_part_info2 = qla8044_rd_direct(vha,
5498 QLA8044_CRB_DEV_PART_INFO2);
5499 } else {
5500 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5501 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
5502 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
5503 }
7d613ac6
SV		 5504 for (i = 0; i < 8; i++) {
5505 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
5506 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5507 (i != ha->portnum)) {
5508 fcoe_other_function = i;
5509 break;
5510 }
5511 }
5512 if (fcoe_other_function == 0xffff) {
5513 for (i = 0; i < 8; i++) {
5514 class_type = ((dev_part_info2 >> (i * 4)) &
5515 class_type_mask);
5516 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
5517 ((i + 8) != ha->portnum)) {
5518 fcoe_other_function = i + 8;
5519 break;
5520 }
5521 }
5522 }
5523 /*
5524 * Prepare drv-presence mask based on fcoe functions present.
5525 * However consider only valid physical fcoe function numbers (0-15).
5526 */
5527 drv_presence_mask = ~((1 << (ha->portnum)) |
5528 ((fcoe_other_function == 0xffff) ?
5529 0 : (1 << (fcoe_other_function))));
5530
5531 /* We are the reset owner iff:
5532 * - No other protocol drivers present.
5533 * - This is the lowest among fcoe functions. */
5534 if (!(drv_presence & drv_presence_mask) &&
5535 (ha->portnum < fcoe_other_function)) {
5536 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
5537 "This host is Reset owner.\n");
5538 ha->flags.nic_core_reset_owner = 1;
5539 }
5540}
5541
fa492630 5542static int
7d613ac6
SV		 5543__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
5544{
5545 int rval = QLA_SUCCESS;
5546 struct qla_hw_data *ha = vha->hw;
5547 uint32_t drv_ack;
5548
5549 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5550 if (rval == QLA_SUCCESS) {
5551 drv_ack |= (1 << ha->portnum);
5552 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5553 }
5554
5555 return rval;
5556}
5557
fa492630 5558static int
7d613ac6
SV		 5559__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
5560{
5561 int rval = QLA_SUCCESS;
5562 struct qla_hw_data *ha = vha->hw;
5563 uint32_t drv_ack;
5564
5565 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5566 if (rval == QLA_SUCCESS) {
5567 drv_ack &= ~(1 << ha->portnum);
5568 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
5569 }
5570
5571 return rval;
5572}
5573
fa492630 5574static const char *
7d613ac6
SV		 5575qla83xx_dev_state_to_string(uint32_t dev_state)
5576{
5577 switch (dev_state) {
5578 case QLA8XXX_DEV_COLD:
5579 return "COLD/RE-INIT";
5580 case QLA8XXX_DEV_INITIALIZING:
5581 return "INITIALIZING";
5582 case QLA8XXX_DEV_READY:
5583 return "READY";
5584 case QLA8XXX_DEV_NEED_RESET:
5585 return "NEED RESET";
5586 case QLA8XXX_DEV_NEED_QUIESCENT:
5587 return "NEED QUIESCENT";
5588 case QLA8XXX_DEV_FAILED:
5589 return "FAILED";
5590 case QLA8XXX_DEV_QUIESCENT:
5591 return "QUIESCENT";
5592 default:
5593 return "Unknown";
5594 }
5595}
5596
5597/* Assumes idc-lock always held on entry */
5598void
5599qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
5600{
5601 struct qla_hw_data *ha = vha->hw;
5602 uint32_t idc_audit_reg = 0, duration_secs = 0;
5603
5604 switch (audit_type) {
5605 case IDC_AUDIT_TIMESTAMP:
5606 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
5607 idc_audit_reg = (ha->portnum) |
5608 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
5609 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5610 break;
5611
5612 case IDC_AUDIT_COMPLETION:
5613 duration_secs = ((jiffies_to_msecs(jiffies) -
5614 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
5615 idc_audit_reg = (ha->portnum) |
5616 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
5617 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
5618 break;
5619
5620 default:
5621 ql_log(ql_log_warn, vha, 0xb078,
5622 "Invalid audit type specified.\n");
5623 break;
5624 }
5625}
5626
5627/* Assumes idc_lock always held on entry */
fa492630 5628static int
7d613ac6
SV		 5629qla83xx_initiating_reset(scsi_qla_host_t *vha)
5630{
5631 struct qla_hw_data *ha = vha->hw;
5632 uint32_t idc_control, dev_state;
5633
5634 __qla83xx_get_idc_control(vha, &idc_control);
5635 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
5636 ql_log(ql_log_info, vha, 0xb080,
5637 "NIC Core reset has been disabled. idc-control=0x%x\n",
5638 idc_control);
5639 return QLA_FUNCTION_FAILED;
5640 }
5641
5642 /* Set NEED-RESET iff in READY state and we are the reset-owner */
5643 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5644 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
5645 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
5646 QLA8XXX_DEV_NEED_RESET);
5647 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
5648 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
5649 } else {
5650 const char *state = qla83xx_dev_state_to_string(dev_state);
5651 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
5652
5653 /* SV: XXX: Is timeout required here? */
5654 /* Wait for IDC state change READY -> NEED_RESET */
5655 while (dev_state == QLA8XXX_DEV_READY) {
5656 qla83xx_idc_unlock(vha, 0);
5657 msleep(200);
5658 qla83xx_idc_lock(vha, 0);
5659 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5660 }
5661 }
5662
5663 /* Send IDC ack by writing to drv-ack register */
5664 __qla83xx_set_drv_ack(vha);
5665
5666 return QLA_SUCCESS;
5667}
5668
5669int
5670__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
5671{
5672 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5673}
5674
7d613ac6
SV		 5675int
5676__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
5677{
5678 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
5679}
5680
fa492630 5681static int
7d613ac6
SV		 5682qla83xx_check_driver_presence(scsi_qla_host_t *vha)
5683{
5684 uint32_t drv_presence = 0;
5685 struct qla_hw_data *ha = vha->hw;
5686
5687 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5688 if (drv_presence & (1 << ha->portnum))
5689 return QLA_SUCCESS;
5690 else
5691 return QLA_TEST_FAILED;
5692}
5693
5694int
5695qla83xx_nic_core_reset(scsi_qla_host_t *vha)
5696{
5697 int rval = QLA_SUCCESS;
5698 struct qla_hw_data *ha = vha->hw;
5699
5700 ql_dbg(ql_dbg_p3p, vha, 0xb058,
5701 "Entered %s().\n", __func__);
5702
5703 if (vha->device_flags & DFLG_DEV_FAILED) {
5704 ql_log(ql_log_warn, vha, 0xb059,
5705 "Device in unrecoverable FAILED state.\n");
5706 return QLA_FUNCTION_FAILED;
5707 }
5708
5709 qla83xx_idc_lock(vha, 0);
5710
5711 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
5712 ql_log(ql_log_warn, vha, 0xb05a,
5713 "Function=0x%x has been removed from IDC participation.\n",
5714 ha->portnum);
5715 rval = QLA_FUNCTION_FAILED;
5716 goto exit;
5717 }
5718
5719 qla83xx_reset_ownership(vha);
5720
5721 rval = qla83xx_initiating_reset(vha);
5722
5723 /*
5724 * Perform reset if we are the reset-owner,
5725 * else wait till IDC state changes to READY/FAILED.
5726 */
5727 if (rval == QLA_SUCCESS) {
5728 rval = qla83xx_idc_state_handler(vha);
5729
5730 if (rval == QLA_SUCCESS)
5731 ha->flags.nic_core_hung = 0;
5732 __qla83xx_clear_drv_ack(vha);
5733 }
5734
5735exit:
5736 qla83xx_idc_unlock(vha, 0);
5737
5738 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
5739
5740 return rval;
5741}
5742
81178772
SK		 5743int
5744qla2xxx_mctp_dump(scsi_qla_host_t *vha)
5745{
5746 struct qla_hw_data *ha = vha->hw;
5747 int rval = QLA_FUNCTION_FAILED;
5748
5749 if (!IS_MCTP_CAPABLE(ha)) {
5750 /* This message can be removed from the final version */
5751 ql_log(ql_log_info, vha, 0x506d,
5752 "This board is not MCTP capable\n");
5753 return rval;
5754 }
5755
5756 if (!ha->mctp_dump) {
5757 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
5758 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
5759
5760 if (!ha->mctp_dump) {
5761 ql_log(ql_log_warn, vha, 0x506e,
5762 "Failed to allocate memory for mctp dump\n");
5763 return rval;
5764 }
5765 }
5766
5767#define MCTP_DUMP_STR_ADDR 0x00000000
5768 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
5769 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
5770 if (rval != QLA_SUCCESS) {
5771 ql_log(ql_log_warn, vha, 0x506f,
5772 "Failed to capture mctp dump\n");
5773 } else {
5774 ql_log(ql_log_info, vha, 0x5070,
5775 "Mctp dump capture for host (%ld/%p).\n",
5776 vha->host_no, ha->mctp_dump);
5777 ha->mctp_dumped = 1;
5778 }
5779
409ee0fe 5780 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
81178772
SK		 5781 ha->flags.nic_core_reset_hdlr_active = 1;
5782 rval = qla83xx_restart_nic_firmware(vha);
5783 if (rval)
5784 /* NIC Core reset failed. */
5785 ql_log(ql_log_warn, vha, 0x5071,
5786 "Failed to restart nic firmware\n");
5787 else
5788 ql_dbg(ql_dbg_p3p, vha, 0xb084,
5789 "Restarted NIC firmware successfully.\n");
5790 ha->flags.nic_core_reset_hdlr_active = 0;
5791 }
5792
5793 return rval;
5794
5795}
5796
579d12b5 5797/*
8fcd6b8b 5798* qla2x00_quiesce_io
579d12b5
SK		 5799* Description: This function will block the new I/Os
5800* Its not aborting any I/Os as context
5801* is not destroyed during quiescence
5802* Arguments: scsi_qla_host_t
5803* return : void
5804*/
5805void
8fcd6b8b 5806qla2x00_quiesce_io(scsi_qla_host_t *vha)
579d12b5
SK		 5807{
5808 struct qla_hw_data *ha = vha->hw;
5809 struct scsi_qla_host *vp;
5810
8fcd6b8b
CD		 5811 ql_dbg(ql_dbg_dpc, vha, 0x401d,
5812 "Quiescing I/O - ha=%p.\n", ha);
579d12b5
SK		 5813
5814 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
5815 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5816 atomic_set(&vha->loop_state, LOOP_DOWN);
5817 qla2x00_mark_all_devices_lost(vha, 0);
5818 list_for_each_entry(vp, &ha->vp_list, list)
8fcd6b8b 5819 qla2x00_mark_all_devices_lost(vp, 0);
579d12b5
SK		 5820 } else {
5821 if (!atomic_read(&vha->loop_down_timer))
5822 atomic_set(&vha->loop_down_timer,
5823 LOOP_DOWN_TIME);
5824 }
5825 /* Wait for pending cmds to complete */
5826 qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST);
5827}
5828
a9083016
GM		 5829void
5830qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
5831{
5832 struct qla_hw_data *ha = vha->hw;
579d12b5 5833 struct scsi_qla_host *vp;
feafb7b1 5834 unsigned long flags;
6aef87be 5835 fc_port_t *fcport;
7c3f8fd1 5836 u16 i;
a9083016 5837
e46ef004
SK		 5838 /* For ISP82XX, driver waits for completion of the commands.
5839 * online flag should be set.
5840 */
7ec0effd 5841 if (!(IS_P3P_TYPE(ha)))
e46ef004 5842 vha->flags.online = 0;
a9083016
GM		 5843 ha->flags.chip_reset_done = 0;
5844 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2be21fa2 5845 vha->qla_stats.total_isp_aborts++;
a9083016 5846
7c3df132
SK		 5847 ql_log(ql_log_info, vha, 0x00af,
5848 "Performing ISP error recovery - ha=%p.\n", ha);
a9083016 5849
e46ef004
SK		 5850 /* For ISP82XX, reset_chip is just disabling interrupts.
5851 * Driver waits for the completion of the commands.
5852 * the interrupts need to be enabled.
5853 */
7ec0effd 5854 if (!(IS_P3P_TYPE(ha)))
a9083016
GM		 5855 ha->isp_ops->reset_chip(vha);
5856
ec7193e2
QT		 5857 ha->flags.n2n_ae = 0;
5858 ha->flags.lip_ae = 0;
5859 ha->current_topology = 0;
5860 ha->flags.fw_started = 0;
5861 ha->flags.fw_init_done = 0;
7c3f8fd1
QT		 5862 ha->base_qpair->chip_reset++;
5863 for (i = 0; i < ha->max_qpairs; i++) {
5864 if (ha->queue_pair_map[i])
5865 ha->queue_pair_map[i]->chip_reset =
5866 ha->base_qpair->chip_reset;
5867 }
726b8548 5868
a9083016
GM		 5869 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
5870 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
5871 atomic_set(&vha->loop_state, LOOP_DOWN);
5872 qla2x00_mark_all_devices_lost(vha, 0);
feafb7b1
AE		 5873
5874 spin_lock_irqsave(&ha->vport_slock, flags);
579d12b5 5875 list_for_each_entry(vp, &ha->vp_list, list) {
feafb7b1
AE		 5876 atomic_inc(&vp->vref_count);
5877 spin_unlock_irqrestore(&ha->vport_slock, flags);
5878
a9083016 5879 qla2x00_mark_all_devices_lost(vp, 0);
feafb7b1
AE		 5880
5881 spin_lock_irqsave(&ha->vport_slock, flags);
5882 atomic_dec(&vp->vref_count);
5883 }
5884 spin_unlock_irqrestore(&ha->vport_slock, flags);
a9083016
GM		 5885 } else {
5886 if (!atomic_read(&vha->loop_down_timer))
5887 atomic_set(&vha->loop_down_timer,
5888 LOOP_DOWN_TIME);
5889 }
5890
6aef87be
AV		 5891 /* Clear all async request states across all VPs. */
5892 list_for_each_entry(fcport, &vha->vp_fcports, list)
5893 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5894 spin_lock_irqsave(&ha->vport_slock, flags);
5895 list_for_each_entry(vp, &ha->vp_list, list) {
5896 atomic_inc(&vp->vref_count);
5897 spin_unlock_irqrestore(&ha->vport_slock, flags);
5898
5899 list_for_each_entry(fcport, &vp->vp_fcports, list)
5900 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5901
5902 spin_lock_irqsave(&ha->vport_slock, flags);
5903 atomic_dec(&vp->vref_count);
5904 }
5905 spin_unlock_irqrestore(&ha->vport_slock, flags);
5906
bddd2d65
LC		 5907 if (!ha->flags.eeh_busy) {
5908 /* Make sure for ISP 82XX IO DMA is complete */
7ec0effd 5909 if (IS_P3P_TYPE(ha)) {
7190575f 5910 qla82xx_chip_reset_cleanup(vha);
7c3df132
SK		 5911 ql_log(ql_log_info, vha, 0x00b4,
5912 "Done chip reset cleanup.\n");
a9083016 5913
e46ef004
SK		 5914 /* Done waiting for pending commands.
5915 * Reset the online flag.
5916 */
5917 vha->flags.online = 0;
4d78c973 5918 }
a9083016 5919
bddd2d65
LC		 5920 /* Requeue all commands in outstanding command list. */
5921 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
5922 }
b6a029e1
AE		 5923 /* memory barrier */
5924 wmb();
a9083016
GM		 5925}
5926
1da177e4
LT		 5927/*
5928* qla2x00_abort_isp
5929* Resets ISP and aborts all outstanding commands.
5930*
5931* Input:
5932* ha = adapter block pointer.
5933*
5934* Returns:
5935* 0 = success
5936*/
5937int
e315cd28 5938qla2x00_abort_isp(scsi_qla_host_t *vha)
1da177e4 5939{
476e8978 5940 int rval;
1da177e4 5941 uint8_t status = 0;
e315cd28
AC		 5942 struct qla_hw_data *ha = vha->hw;
5943 struct scsi_qla_host *vp;
73208dfd 5944 struct req_que *req = ha->req_q_map[0];
feafb7b1 5945 unsigned long flags;
1da177e4 5946
e315cd28 5947 if (vha->flags.online) {
a9083016 5948 qla2x00_abort_isp_cleanup(vha);
1da177e4 5949
a6171297
SV		 5950 if (IS_QLA8031(ha)) {
5951 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
5952 "Clearing fcoe driver presence.\n");
5953 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
5954 ql_dbg(ql_dbg_p3p, vha, 0xb073,
5955 "Error while clearing DRV-Presence.\n");
5956 }
5957
85880801
AV		 5958 if (unlikely(pci_channel_offline(ha->pdev) &&
5959 ha->flags.pci_channel_io_perm_failure)) {
5960 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
5961 status = 0;
5962 return status;
5963 }
5964
73208dfd 5965 ha->isp_ops->get_flash_version(vha, req->ring);
30c47662 5966
e315cd28 5967 ha->isp_ops->nvram_config(vha);
1da177e4 5968
e315cd28
AC		 5969 if (!qla2x00_restart_isp(vha)) {
5970 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4 5971
e315cd28 5972 if (!atomic_read(&vha->loop_down_timer)) {
1da177e4
LT		 5973 /*
5974 * Issue marker command only when we are going
5975 * to start the I/O .
5976 */
e315cd28 5977 vha->marker_needed = 1;
1da177e4
LT		 5978 }
5979
e315cd28 5980 vha->flags.online = 1;
1da177e4 5981
fd34f556 5982 ha->isp_ops->enable_intrs(ha);
1da177e4 5983
fa2a1ce5 5984 ha->isp_abort_cnt = 0;
e315cd28 5985 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
476e8978 5986
6246b8a1
GM		 5987 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
5988 qla2x00_get_fw_version(vha);
df613b96
AV		 5989 if (ha->fce) {
5990 ha->flags.fce_enabled = 1;
5991 memset(ha->fce, 0,
5992 fce_calc_size(ha->fce_bufs));
e315cd28 5993 rval = qla2x00_enable_fce_trace(vha,
df613b96
AV		 5994 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
5995 &ha->fce_bufs);
5996 if (rval) {
7c3df132 5997 ql_log(ql_log_warn, vha, 0x8033,
df613b96
AV		 5998 "Unable to reinitialize FCE "
5999 "(%d).\n", rval);
6000 ha->flags.fce_enabled = 0;
6001 }
6002 }
436a7b11
AV		 6003
6004 if (ha->eft) {
6005 memset(ha->eft, 0, EFT_SIZE);
e315cd28 6006 rval = qla2x00_enable_eft_trace(vha,
436a7b11
AV		 6007 ha->eft_dma, EFT_NUM_BUFFERS);
6008 if (rval) {
7c3df132 6009 ql_log(ql_log_warn, vha, 0x8034,
436a7b11
AV		 6010 "Unable to reinitialize EFT "
6011 "(%d).\n", rval);
6012 }
6013 }
1da177e4 6014 } else { /* failed the ISP abort */
e315cd28
AC		 6015 vha->flags.online = 1;
6016 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
1da177e4 6017 if (ha->isp_abort_cnt == 0) {
7c3df132
SK		 6018 ql_log(ql_log_fatal, vha, 0x8035,
6019 "ISP error recover failed - "
6020 "board disabled.\n");
fa2a1ce5 6021 /*
1da177e4
LT		 6022 * The next call disables the board
6023 * completely.
6024 */
e315cd28
AC		 6025 ha->isp_ops->reset_adapter(vha);
6026 vha->flags.online = 0;
1da177e4 6027 clear_bit(ISP_ABORT_RETRY,
e315cd28 6028 &vha->dpc_flags);
1da177e4
LT		 6029 status = 0;
6030 } else { /* schedule another ISP abort */
6031 ha->isp_abort_cnt--;
7c3df132
SK		 6032 ql_dbg(ql_dbg_taskm, vha, 0x8020,
6033 "ISP abort - retry remaining %d.\n",
6034 ha->isp_abort_cnt);
1da177e4
LT		 6035 status = 1;
6036 }
6037 } else {
6038 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7c3df132
SK		 6039 ql_dbg(ql_dbg_taskm, vha, 0x8021,
6040 "ISP error recovery - retrying (%d) "
6041 "more times.\n", ha->isp_abort_cnt);
e315cd28 6042 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
1da177e4
LT		 6043 status = 1;
6044 }
6045 }
fa2a1ce5 6046
1da177e4
LT		 6047 }
6048
e315cd28 6049 if (!status) {
7c3df132 6050 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
1608cc4a 6051 qla2x00_configure_hba(vha);
feafb7b1
AE		 6052 spin_lock_irqsave(&ha->vport_slock, flags);
6053 list_for_each_entry(vp, &ha->vp_list, list) {
6054 if (vp->vp_idx) {
6055 atomic_inc(&vp->vref_count);
6056 spin_unlock_irqrestore(&ha->vport_slock, flags);
6057
e315cd28 6058 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 6059
6060 spin_lock_irqsave(&ha->vport_slock, flags);
6061 atomic_dec(&vp->vref_count);
6062 }
e315cd28 6063 }
feafb7b1
AE		 6064 spin_unlock_irqrestore(&ha->vport_slock, flags);
6065
7d613ac6
SV		 6066 if (IS_QLA8031(ha)) {
6067 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
6068 "Setting back fcoe driver presence.\n");
6069 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
6070 ql_dbg(ql_dbg_p3p, vha, 0xb074,
6071 "Error while setting DRV-Presence.\n");
6072 }
e315cd28 6073 } else {
d8424f68
JP		 6074 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
6075 __func__);
1da177e4
LT		 6076 }
6077
6078 return(status);
6079}
6080
6081/*
6082* qla2x00_restart_isp
6083* restarts the ISP after a reset
6084*
6085* Input:
6086* ha = adapter block pointer.
6087*
6088* Returns:
6089* 0 = success
6090*/
6091static int
e315cd28 6092qla2x00_restart_isp(scsi_qla_host_t *vha)
1da177e4 6093{
c6b2fca8 6094 int status = 0;
e315cd28 6095 struct qla_hw_data *ha = vha->hw;
73208dfd
AC		 6096 struct req_que *req = ha->req_q_map[0];
6097 struct rsp_que *rsp = ha->rsp_q_map[0];
1da177e4
LT		 6098
6099 /* If firmware needs to be loaded */
e315cd28
AC		 6100 if (qla2x00_isp_firmware(vha)) {
6101 vha->flags.online = 0;
6102 status = ha->isp_ops->chip_diag(vha);
6103 if (!status)
6104 status = qla2x00_setup_chip(vha);
1da177e4
LT		 6105 }
6106
e315cd28
AC		 6107 if (!status && !(status = qla2x00_init_rings(vha))) {
6108 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
2533cf67 6109 ha->flags.chip_reset_done = 1;
7108b76e 6110
73208dfd
AC		 6111 /* Initialize the queues in use */
6112 qla25xx_init_queues(ha);
6113
e315cd28
AC		 6114 status = qla2x00_fw_ready(vha);
6115 if (!status) {
0107109e 6116 /* Issue a marker after FW becomes ready. */
73208dfd 6117 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
7108b76e 6118 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
1da177e4
LT		 6119 }
6120
6121 /* if no cable then assume it's good */
e315cd28 6122 if ((vha->device_flags & DFLG_NO_CABLE))
1da177e4 6123 status = 0;
1da177e4
LT		 6124 }
6125 return (status);
6126}
6127
73208dfd
AC		 6128static int
6129qla25xx_init_queues(struct qla_hw_data *ha)
6130{
6131 struct rsp_que *rsp = NULL;
6132 struct req_que *req = NULL;
6133 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
6134 int ret = -1;
6135 int i;
6136
2afa19a9 6137 for (i = 1; i < ha->max_rsp_queues; i++) {
73208dfd 6138 rsp = ha->rsp_q_map[i];
cb43285f 6139 if (rsp && test_bit(i, ha->rsp_qid_map)) {
73208dfd 6140 rsp->options &= ~BIT_0;
618a7523 6141 ret = qla25xx_init_rsp_que(base_vha, rsp);
73208dfd 6142 if (ret != QLA_SUCCESS)
7c3df132
SK		 6143 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
6144 "%s Rsp que: %d init failed.\n",
6145 __func__, rsp->id);
73208dfd 6146 else
7c3df132
SK		 6147 ql_dbg(ql_dbg_init, base_vha, 0x0100,
6148 "%s Rsp que: %d inited.\n",
6149 __func__, rsp->id);
73208dfd 6150 }
2afa19a9
AC		 6151 }
6152 for (i = 1; i < ha->max_req_queues; i++) {
73208dfd 6153 req = ha->req_q_map[i];
cb43285f
QT		 6154 if (req && test_bit(i, ha->req_qid_map)) {
6155 /* Clear outstanding commands array. */
73208dfd 6156 req->options &= ~BIT_0;
618a7523 6157 ret = qla25xx_init_req_que(base_vha, req);
73208dfd 6158 if (ret != QLA_SUCCESS)
7c3df132
SK		 6159 ql_dbg(ql_dbg_init, base_vha, 0x0101,
6160 "%s Req que: %d init failed.\n",
6161 __func__, req->id);
73208dfd 6162 else
7c3df132
SK		 6163 ql_dbg(ql_dbg_init, base_vha, 0x0102,
6164 "%s Req que: %d inited.\n",
6165 __func__, req->id);
73208dfd
AC		 6166 }
6167 }
6168 return ret;
6169}
6170
1da177e4
LT		 6171/*
6172* qla2x00_reset_adapter
6173* Reset adapter.
6174*
6175* Input:
6176* ha = adapter block pointer.
6177*/
abbd8870 6178void
e315cd28 6179qla2x00_reset_adapter(scsi_qla_host_t *vha)
1da177e4
LT		 6180{
6181 unsigned long flags = 0;
e315cd28 6182 struct qla_hw_data *ha = vha->hw;
3d71644c 6183 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4 6184
e315cd28 6185 vha->flags.online = 0;
fd34f556 6186 ha->isp_ops->disable_intrs(ha);
1da177e4 6187
1da177e4
LT		 6188 spin_lock_irqsave(&ha->hardware_lock, flags);
6189 WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
6190 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6191 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
6192 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
6193 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6194}
0107109e
AV		 6195
6196void
e315cd28 6197qla24xx_reset_adapter(scsi_qla_host_t *vha)
0107109e
AV		 6198{
6199 unsigned long flags = 0;
e315cd28 6200 struct qla_hw_data *ha = vha->hw;
0107109e
AV		 6201 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
6202
7ec0effd 6203 if (IS_P3P_TYPE(ha))
a9083016
GM		 6204 return;
6205
e315cd28 6206 vha->flags.online = 0;
fd34f556 6207 ha->isp_ops->disable_intrs(ha);
0107109e
AV		 6208
6209 spin_lock_irqsave(&ha->hardware_lock, flags);
6210 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET);
6211 RD_REG_DWORD(&reg->hccr);
6212 WRT_REG_DWORD(&reg->hccr, HCCRX_REL_RISC_PAUSE);
6213 RD_REG_DWORD(&reg->hccr);
6214 spin_unlock_irqrestore(&ha->hardware_lock, flags);
09ff36d3
AV		 6215
6216 if (IS_NOPOLLING_TYPE(ha))
6217 ha->isp_ops->enable_intrs(ha);
0107109e
AV		 6218}
6219
4e08df3f
DM		 6220/* On sparc systems, obtain port and node WWN from firmware
6221 * properties.
6222 */
e315cd28
AC		 6223static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
6224 struct nvram_24xx *nv)
4e08df3f
DM		 6225{
6226#ifdef CONFIG_SPARC
e315cd28 6227 struct qla_hw_data *ha = vha->hw;
4e08df3f 6228 struct pci_dev *pdev = ha->pdev;
15576bc8
DM		 6229 struct device_node *dp = pci_device_to_OF_node(pdev);
6230 const u8 *val;
4e08df3f
DM		 6231 int len;
6232
6233 val = of_get_property(dp, "port-wwn", &len);
6234 if (val && len >= WWN_SIZE)
6235 memcpy(nv->port_name, val, WWN_SIZE);
6236
6237 val = of_get_property(dp, "node-wwn", &len);
6238 if (val && len >= WWN_SIZE)
6239 memcpy(nv->node_name, val, WWN_SIZE);
6240#endif
6241}
6242
0107109e 6243int
e315cd28 6244qla24xx_nvram_config(scsi_qla_host_t *vha)
0107109e 6245{
4e08df3f 6246 int rval;
0107109e
AV		 6247 struct init_cb_24xx *icb;
6248 struct nvram_24xx *nv;
6249 uint32_t *dptr;
6250 uint8_t *dptr1, *dptr2;
6251 uint32_t chksum;
6252 uint16_t cnt;
e315cd28 6253 struct qla_hw_data *ha = vha->hw;
0107109e 6254
4e08df3f 6255 rval = QLA_SUCCESS;
0107109e 6256 icb = (struct init_cb_24xx *)ha->init_cb;
281afe19 6257 nv = ha->nvram;
0107109e
AV		 6258
6259 /* Determine NVRAM starting address. */
f73cb695 6260 if (ha->port_no == 0) {
e5b68a61
AC		 6261 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
6262 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
6263 } else {
0107109e 6264 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
6f641790
AV		 6265 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
6266 }
f73cb695 6267
e5b68a61
AC		 6268 ha->nvram_size = sizeof(struct nvram_24xx);
6269 ha->vpd_size = FA_NVRAM_VPD_SIZE;
0107109e 6270
281afe19
SJ		 6271 /* Get VPD data into cache */
6272 ha->vpd = ha->nvram + VPD_OFFSET;
e315cd28 6273 ha->isp_ops->read_nvram(vha, (uint8_t *)ha->vpd,
281afe19
SJ		 6274 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
6275
6276 /* Get NVRAM data into cache and calculate checksum. */
0107109e 6277 dptr = (uint32_t *)nv;
e315cd28 6278 ha->isp_ops->read_nvram(vha, (uint8_t *)dptr, ha->nvram_base,
0107109e 6279 ha->nvram_size);
da08ef5c
JC		 6280 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
6281 chksum += le32_to_cpu(*dptr);
0107109e 6282
7c3df132
SK		 6283 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
6284 "Contents of NVRAM\n");
6285 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
6286 (uint8_t *)nv, ha->nvram_size);
0107109e
AV		 6287
6288 /* Bad NVRAM data, set defaults parameters. */
6289 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
6290 || nv->id[3] != ' ' ||
ad950360 6291 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
0107109e 6292 /* Reset NVRAM data. */
7c3df132 6293 ql_log(ql_log_warn, vha, 0x006b,
9e336520 6294 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132
SK		 6295 "version=0x%x.\n", chksum, nv->id[0], nv->nvram_version);
6296 ql_log(ql_log_warn, vha, 0x006c,
6297 "Falling back to functioning (yet invalid -- WWPN) "
6298 "defaults.\n");
4e08df3f
DM		 6299
6300 /*
6301 * Set default initialization control block.
6302 */
6303 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 6304 nv->nvram_version = cpu_to_le16(ICB_VERSION);
6305 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 6306 nv->frame_payload_size = 2048;
ad950360
BVA		 6307 nv->execution_throttle = cpu_to_le16(0xFFFF);
6308 nv->exchange_count = cpu_to_le16(0);
6309 nv->hard_address = cpu_to_le16(124);
4e08df3f 6310 nv->port_name[0] = 0x21;
f73cb695 6311 nv->port_name[1] = 0x00 + ha->port_no + 1;
4e08df3f
DM		 6312 nv->port_name[2] = 0x00;
6313 nv->port_name[3] = 0xe0;
6314 nv->port_name[4] = 0x8b;
6315 nv->port_name[5] = 0x1c;
6316 nv->port_name[6] = 0x55;
6317 nv->port_name[7] = 0x86;
6318 nv->node_name[0] = 0x20;
6319 nv->node_name[1] = 0x00;
6320 nv->node_name[2] = 0x00;
6321 nv->node_name[3] = 0xe0;
6322 nv->node_name[4] = 0x8b;
6323 nv->node_name[5] = 0x1c;
6324 nv->node_name[6] = 0x55;
6325 nv->node_name[7] = 0x86;
e315cd28 6326 qla24xx_nvram_wwn_from_ofw(vha, nv);
ad950360
BVA		 6327 nv->login_retry_count = cpu_to_le16(8);
6328 nv->interrupt_delay_timer = cpu_to_le16(0);
6329 nv->login_timeout = cpu_to_le16(0);
4e08df3f 6330 nv->firmware_options_1 =
ad950360
BVA		 6331 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
6332 nv->firmware_options_2 = cpu_to_le32(2 << 4);
6333 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
6334 nv->firmware_options_3 = cpu_to_le32(2 << 13);
6335 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
6336 nv->efi_parameters = cpu_to_le32(0);
4e08df3f 6337 nv->reset_delay = 5;
ad950360
BVA		 6338 nv->max_luns_per_target = cpu_to_le16(128);
6339 nv->port_down_retry_count = cpu_to_le16(30);
6340 nv->link_down_timeout = cpu_to_le16(30);
4e08df3f
DM		 6341
6342 rval = 1;
0107109e
AV		 6343 }
6344
726b8548 6345 if (qla_tgt_mode_enabled(vha)) {
2d70c103 6346 /* Don't enable full login after initial LIP */
ad950360 6347 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
2d70c103 6348 /* Don't enable LIP full login for initiator */
ad950360 6349 nv->host_p &= cpu_to_le32(~BIT_10);
2d70c103
NB		 6350 }
6351
6352 qlt_24xx_config_nvram_stage1(vha, nv);
6353
0107109e 6354 /* Reset Initialization control block */
e315cd28 6355 memset(icb, 0, ha->init_cb_size);
0107109e
AV		 6356
6357 /* Copy 1st segment. */
6358 dptr1 = (uint8_t *)icb;
6359 dptr2 = (uint8_t *)&nv->version;
6360 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
6361 while (cnt--)
6362 *dptr1++ = *dptr2++;
6363
6364 icb->login_retry_count = nv->login_retry_count;
3ea66e28 6365 icb->link_down_on_nos = nv->link_down_on_nos;
0107109e
AV		 6366
6367 /* Copy 2nd segment. */
6368 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
6369 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
6370 cnt = (uint8_t *)&icb->reserved_3 -
6371 (uint8_t *)&icb->interrupt_delay_timer;
6372 while (cnt--)
6373 *dptr1++ = *dptr2++;
6374
6375 /*
6376 * Setup driver NVRAM options.
6377 */
e315cd28 6378 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
9bb9fcf2 6379 "QLA2462");
0107109e 6380
2d70c103
NB		 6381 qlt_24xx_config_nvram_stage2(vha, icb);
6382
ad950360 6383 if (nv->host_p & cpu_to_le32(BIT_15)) {
2d70c103 6384 /* Use alternate WWN? */
5341e868
AV		 6385 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
6386 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
6387 }
6388
0107109e 6389 /* Prepare nodename */
ad950360 6390 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
0107109e
AV		 6391 /*
6392 * Firmware will apply the following mask if the nodename was
6393 * not provided.
6394 */
6395 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
6396 icb->node_name[0] &= 0xF0;
6397 }
6398
6399 /* Set host adapter parameters. */
6400 ha->flags.disable_risc_code_load = 0;
0c8c39af
AV		 6401 ha->flags.enable_lip_reset = 0;
6402 ha->flags.enable_lip_full_login =
6403 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
6404 ha->flags.enable_target_reset =
6405 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
0107109e 6406 ha->flags.enable_led_scheme = 0;
d4c760c2 6407 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
0107109e 6408
fd0e7e4d
AV		 6409 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
6410 (BIT_6 | BIT_5 | BIT_4)) >> 4;
0107109e
AV		 6411
6412 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
6413 sizeof(ha->fw_seriallink_options24));
6414
6415 /* save HBA serial number */
6416 ha->serial0 = icb->port_name[5];
6417 ha->serial1 = icb->port_name[6];
6418 ha->serial2 = icb->port_name[7];
e315cd28
AC		 6419 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
6420 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
0107109e 6421
ad950360 6422 icb->execution_throttle = cpu_to_le16(0xFFFF);
bc8fb3cb 6423
0107109e
AV		 6424 ha->retry_count = le16_to_cpu(nv->login_retry_count);
6425
6426 /* Set minimum login_timeout to 4 seconds. */
6427 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
6428 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
6429 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 6430 nv->login_timeout = cpu_to_le16(4);
0107109e 6431 ha->login_timeout = le16_to_cpu(nv->login_timeout);
0107109e 6432
00a537b8
AV		 6433 /* Set minimum RATOV to 100 tenths of a second. */
6434 ha->r_a_tov = 100;
0107109e
AV		 6435
6436 ha->loop_reset_delay = nv->reset_delay;
6437
6438 /* Link Down Timeout = 0:
6439 *
6440 * When Port Down timer expires we will start returning
6441 * I/O's to OS with "DID_NO_CONNECT".
6442 *
6443 * Link Down Timeout != 0:
6444 *
6445 * The driver waits for the link to come up after link down
6446 * before returning I/Os to OS with "DID_NO_CONNECT".
6447 */
6448 if (le16_to_cpu(nv->link_down_timeout) == 0) {
6449 ha->loop_down_abort_time =
6450 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
6451 } else {
6452 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
6453 ha->loop_down_abort_time =
6454 (LOOP_DOWN_TIME - ha->link_down_timeout);
6455 }
6456
6457 /* Need enough time to try and get the port back. */
6458 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
6459 if (qlport_down_retry)
6460 ha->port_down_retry_count = qlport_down_retry;
6461
6462 /* Set login_retry_count */
6463 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
6464 if (ha->port_down_retry_count ==
6465 le16_to_cpu(nv->port_down_retry_count) &&
6466 ha->port_down_retry_count > 3)
6467 ha->login_retry_count = ha->port_down_retry_count;
6468 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
6469 ha->login_retry_count = ha->port_down_retry_count;
6470 if (ql2xloginretrycount)
6471 ha->login_retry_count = ql2xloginretrycount;
6472
4fdfefe5 6473 /* Enable ZIO. */
e315cd28 6474 if (!vha->flags.init_done) {
4fdfefe5
AV		 6475 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
6476 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
6477 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
6478 le16_to_cpu(icb->interrupt_delay_timer): 2;
6479 }
ad950360 6480 icb->firmware_options_2 &= cpu_to_le32(
4fdfefe5 6481 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
e315cd28 6482 vha->flags.process_response_queue = 0;
4fdfefe5 6483 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4a59f71d
AV		 6484 ha->zio_mode = QLA_ZIO_MODE_6;
6485
7c3df132 6486 ql_log(ql_log_info, vha, 0x006f,
4fdfefe5
AV		 6487 "ZIO mode %d enabled; timer delay (%d us).\n",
6488 ha->zio_mode, ha->zio_timer * 100);
6489
6490 icb->firmware_options_2 |= cpu_to_le32(
6491 (uint32_t)ha->zio_mode);
6492 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
e315cd28 6493 vha->flags.process_response_queue = 1;
4fdfefe5
AV		 6494 }
6495
4e08df3f 6496 if (rval) {
7c3df132
SK		 6497 ql_log(ql_log_warn, vha, 0x0070,
6498 "NVRAM configuration failed.\n");
4e08df3f
DM		 6499 }
6500 return (rval);
0107109e
AV		 6501}
6502
4243c115
SC		 6503uint8_t qla27xx_find_valid_image(struct scsi_qla_host *vha)
6504{
6505 struct qla27xx_image_status pri_image_status, sec_image_status;
6506 uint8_t valid_pri_image, valid_sec_image;
6507 uint32_t *wptr;
6508 uint32_t cnt, chksum, size;
6509 struct qla_hw_data *ha = vha->hw;
6510
6511 valid_pri_image = valid_sec_image = 1;
6512 ha->active_image = 0;
6513 size = sizeof(struct qla27xx_image_status) / sizeof(uint32_t);
6514
6515 if (!ha->flt_region_img_status_pri) {
6516 valid_pri_image = 0;
6517 goto check_sec_image;
6518 }
6519
6520 qla24xx_read_flash_data(vha, (uint32_t *)(&pri_image_status),
6521 ha->flt_region_img_status_pri, size);
6522
6523 if (pri_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6524 ql_dbg(ql_dbg_init, vha, 0x018b,
6525 "Primary image signature (0x%x) not valid\n",
6526 pri_image_status.signature);
6527 valid_pri_image = 0;
6528 goto check_sec_image;
6529 }
6530
6531 wptr = (uint32_t *)(&pri_image_status);
6532 cnt = size;
6533
da08ef5c
JC		 6534 for (chksum = 0; cnt--; wptr++)
6535 chksum += le32_to_cpu(*wptr);
41dc529a 6536
4243c115
SC		 6537 if (chksum) {
6538 ql_dbg(ql_dbg_init, vha, 0x018c,
6539 "Checksum validation failed for primary image (0x%x)\n",
6540 chksum);
6541 valid_pri_image = 0;
6542 }
6543
6544check_sec_image:
6545 if (!ha->flt_region_img_status_sec) {
6546 valid_sec_image = 0;
6547 goto check_valid_image;
6548 }
6549
6550 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
6551 ha->flt_region_img_status_sec, size);
6552
6553 if (sec_image_status.signature != QLA27XX_IMG_STATUS_SIGN) {
6554 ql_dbg(ql_dbg_init, vha, 0x018d,
6555 "Secondary image signature(0x%x) not valid\n",
6556 sec_image_status.signature);
6557 valid_sec_image = 0;
6558 goto check_valid_image;
6559 }
6560
6561 wptr = (uint32_t *)(&sec_image_status);
6562 cnt = size;
da08ef5c
JC		 6563 for (chksum = 0; cnt--; wptr++)
6564 chksum += le32_to_cpu(*wptr);
4243c115
SC		 6565 if (chksum) {
6566 ql_dbg(ql_dbg_init, vha, 0x018e,
6567 "Checksum validation failed for secondary image (0x%x)\n",
6568 chksum);
6569 valid_sec_image = 0;
6570 }
6571
6572check_valid_image:
6573 if (valid_pri_image && (pri_image_status.image_status_mask & 0x1))
6574 ha->active_image = QLA27XX_PRIMARY_IMAGE;
6575 if (valid_sec_image && (sec_image_status.image_status_mask & 0x1)) {
6576 if (!ha->active_image ||
6577 pri_image_status.generation_number <
6578 sec_image_status.generation_number)
6579 ha->active_image = QLA27XX_SECONDARY_IMAGE;
6580 }
6581
6582 ql_dbg(ql_dbg_init, vha, 0x018f, "%s image\n",
6583 ha->active_image == 0 ? "default bootld and fw" :
6584 ha->active_image == 1 ? "primary" :
6585 ha->active_image == 2 ? "secondary" :
6586 "Invalid");
6587
6588 return ha->active_image;
6589}
6590
413975a0 6591static int
cbc8eb67
AV		 6592qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
6593 uint32_t faddr)
d1c61909 6594{
73208dfd 6595 int rval = QLA_SUCCESS;
d1c61909 6596 int segments, fragment;
d1c61909
AV		 6597 uint32_t *dcode, dlen;
6598 uint32_t risc_addr;
6599 uint32_t risc_size;
6600 uint32_t i;
e315cd28 6601 struct qla_hw_data *ha = vha->hw;
73208dfd 6602 struct req_que *req = ha->req_q_map[0];
eaac30be 6603
7c3df132 6604 ql_dbg(ql_dbg_init, vha, 0x008b,
cfb0919c 6605 "FW: Loading firmware from flash (%x).\n", faddr);
eaac30be 6606
d1c61909
AV		 6607 rval = QLA_SUCCESS;
6608
6609 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6610 dcode = (uint32_t *)req->ring;
d1c61909
AV		 6611 *srisc_addr = 0;
6612
4243c115
SC		 6613 if (IS_QLA27XX(ha) &&
6614 qla27xx_find_valid_image(vha) == QLA27XX_SECONDARY_IMAGE)
6615 faddr = ha->flt_region_fw_sec;
6616
d1c61909 6617 /* Validate firmware image by checking version. */
e315cd28 6618 qla24xx_read_flash_data(vha, dcode, faddr + 4, 4);
d1c61909
AV		 6619 for (i = 0; i < 4; i++)
6620 dcode[i] = be32_to_cpu(dcode[i]);
6621 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6622 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6623 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6624 dcode[3] == 0)) {
7c3df132
SK		 6625 ql_log(ql_log_fatal, vha, 0x008c,
6626 "Unable to verify the integrity of flash firmware "
6627 "image.\n");
6628 ql_log(ql_log_fatal, vha, 0x008d,
6629 "Firmware data: %08x %08x %08x %08x.\n",
6630 dcode[0], dcode[1], dcode[2], dcode[3]);
d1c61909
AV		 6631
6632 return QLA_FUNCTION_FAILED;
6633 }
6634
6635 while (segments && rval == QLA_SUCCESS) {
6636 /* Read segment's load information. */
e315cd28 6637 qla24xx_read_flash_data(vha, dcode, faddr, 4);
d1c61909
AV		 6638
6639 risc_addr = be32_to_cpu(dcode[2]);
6640 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6641 risc_size = be32_to_cpu(dcode[3]);
6642
6643 fragment = 0;
6644 while (risc_size > 0 && rval == QLA_SUCCESS) {
6645 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6646 if (dlen > risc_size)
6647 dlen = risc_size;
6648
7c3df132
SK		 6649 ql_dbg(ql_dbg_init, vha, 0x008e,
6650 "Loading risc segment@ risc addr %x "
6651 "number of dwords 0x%x offset 0x%x.\n",
6652 risc_addr, dlen, faddr);
d1c61909 6653
e315cd28 6654 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
d1c61909
AV		 6655 for (i = 0; i < dlen; i++)
6656 dcode[i] = swab32(dcode[i]);
6657
73208dfd 6658 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
d1c61909
AV		 6659 dlen);
6660 if (rval) {
7c3df132
SK		 6661 ql_log(ql_log_fatal, vha, 0x008f,
6662 "Failed to load segment %d of firmware.\n",
6663 fragment);
f261f7af 6664 return QLA_FUNCTION_FAILED;
d1c61909
AV		 6665 }
6666
6667 faddr += dlen;
6668 risc_addr += dlen;
6669 risc_size -= dlen;
6670 fragment++;
6671 }
6672
6673 /* Next segment. */
6674 segments--;
6675 }
6676
f73cb695
CD		 6677 if (!IS_QLA27XX(ha))
6678 return rval;
6679
6680 if (ha->fw_dump_template)
6681 vfree(ha->fw_dump_template);
6682 ha->fw_dump_template = NULL;
6683 ha->fw_dump_template_len = 0;
6684
6685 ql_dbg(ql_dbg_init, vha, 0x0161,
6686 "Loading fwdump template from %x\n", faddr);
6687 qla24xx_read_flash_data(vha, dcode, faddr, 7);
6688 risc_size = be32_to_cpu(dcode[2]);
6689 ql_dbg(ql_dbg_init, vha, 0x0162,
6690 "-> array size %x dwords\n", risc_size);
6691 if (risc_size == 0 || risc_size == ~0)
6692 goto default_template;
6693
6694 dlen = (risc_size - 8) * sizeof(*dcode);
6695 ql_dbg(ql_dbg_init, vha, 0x0163,
6696 "-> template allocating %x bytes...\n", dlen);
6697 ha->fw_dump_template = vmalloc(dlen);
6698 if (!ha->fw_dump_template) {
6699 ql_log(ql_log_warn, vha, 0x0164,
6700 "Failed fwdump template allocate %x bytes.\n", risc_size);
6701 goto default_template;
6702 }
6703
6704 faddr += 7;
6705 risc_size -= 8;
6706 dcode = ha->fw_dump_template;
6707 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
6708 for (i = 0; i < risc_size; i++)
6709 dcode[i] = le32_to_cpu(dcode[i]);
6710
6711 if (!qla27xx_fwdt_template_valid(dcode)) {
6712 ql_log(ql_log_warn, vha, 0x0165,
6713 "Failed fwdump template validate\n");
6714 goto default_template;
6715 }
6716
6717 dlen = qla27xx_fwdt_template_size(dcode);
6718 ql_dbg(ql_dbg_init, vha, 0x0166,
6719 "-> template size %x bytes\n", dlen);
6720 if (dlen > risc_size * sizeof(*dcode)) {
6721 ql_log(ql_log_warn, vha, 0x0167,
4fae52b5 6722 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 6723 (size_t)(dlen - risc_size * sizeof(*dcode)));
f73cb695
CD		 6724 goto default_template;
6725 }
6726 ha->fw_dump_template_len = dlen;
6727 return rval;
6728
6729default_template:
6730 ql_log(ql_log_warn, vha, 0x0168, "Using default fwdump template\n");
6731 if (ha->fw_dump_template)
6732 vfree(ha->fw_dump_template);
6733 ha->fw_dump_template = NULL;
6734 ha->fw_dump_template_len = 0;
6735
6736 dlen = qla27xx_fwdt_template_default_size();
6737 ql_dbg(ql_dbg_init, vha, 0x0169,
6738 "-> template allocating %x bytes...\n", dlen);
6739 ha->fw_dump_template = vmalloc(dlen);
6740 if (!ha->fw_dump_template) {
6741 ql_log(ql_log_warn, vha, 0x016a,
6742 "Failed fwdump template allocate %x bytes.\n", risc_size);
6743 goto failed_template;
6744 }
6745
6746 dcode = ha->fw_dump_template;
6747 risc_size = dlen / sizeof(*dcode);
6748 memcpy(dcode, qla27xx_fwdt_template_default(), dlen);
6749 for (i = 0; i < risc_size; i++)
6750 dcode[i] = be32_to_cpu(dcode[i]);
6751
6752 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
6753 ql_log(ql_log_warn, vha, 0x016b,
6754 "Failed fwdump template validate\n");
6755 goto failed_template;
6756 }
6757
6758 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
6759 ql_dbg(ql_dbg_init, vha, 0x016c,
6760 "-> template size %x bytes\n", dlen);
6761 ha->fw_dump_template_len = dlen;
6762 return rval;
6763
6764failed_template:
6765 ql_log(ql_log_warn, vha, 0x016d, "Failed default fwdump template\n");
6766 if (ha->fw_dump_template)
6767 vfree(ha->fw_dump_template);
6768 ha->fw_dump_template = NULL;
6769 ha->fw_dump_template_len = 0;
d1c61909
AV		 6770 return rval;
6771}
6772
e9454a88 6773#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
d1c61909 6774
0107109e 6775int
e315cd28 6776qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
5433383e
AV		 6777{
6778 int rval;
6779 int i, fragment;
6780 uint16_t *wcode, *fwcode;
6781 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
6782 struct fw_blob *blob;
e315cd28 6783 struct qla_hw_data *ha = vha->hw;
73208dfd 6784 struct req_que *req = ha->req_q_map[0];
5433383e
AV		 6785
6786 /* Load firmware blob. */
e315cd28 6787 blob = qla2x00_request_firmware(vha);
5433383e 6788 if (!blob) {
7c3df132 6789 ql_log(ql_log_info, vha, 0x0083,
94bcf830 6790 "Firmware image unavailable.\n");
7c3df132
SK		 6791 ql_log(ql_log_info, vha, 0x0084,
6792 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
5433383e
AV		 6793 return QLA_FUNCTION_FAILED;
6794 }
6795
6796 rval = QLA_SUCCESS;
6797
73208dfd 6798 wcode = (uint16_t *)req->ring;
5433383e
AV		 6799 *srisc_addr = 0;
6800 fwcode = (uint16_t *)blob->fw->data;
6801 fwclen = 0;
6802
6803 /* Validate firmware image by checking version. */
6804 if (blob->fw->size < 8 * sizeof(uint16_t)) {
7c3df132 6805 ql_log(ql_log_fatal, vha, 0x0085,
5b5e0928 6806 "Unable to verify integrity of firmware image (%zd).\n",
5433383e
AV		 6807 blob->fw->size);
6808 goto fail_fw_integrity;
6809 }
6810 for (i = 0; i < 4; i++)
6811 wcode[i] = be16_to_cpu(fwcode[i + 4]);
6812 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
6813 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
6814 wcode[2] == 0 && wcode[3] == 0)) {
7c3df132
SK		 6815 ql_log(ql_log_fatal, vha, 0x0086,
6816 "Unable to verify integrity of firmware image.\n");
6817 ql_log(ql_log_fatal, vha, 0x0087,
6818 "Firmware data: %04x %04x %04x %04x.\n",
6819 wcode[0], wcode[1], wcode[2], wcode[3]);
5433383e
AV		 6820 goto fail_fw_integrity;
6821 }
6822
6823 seg = blob->segs;
6824 while (*seg && rval == QLA_SUCCESS) {
6825 risc_addr = *seg;
6826 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
6827 risc_size = be16_to_cpu(fwcode[3]);
6828
6829 /* Validate firmware image size. */
6830 fwclen += risc_size * sizeof(uint16_t);
6831 if (blob->fw->size < fwclen) {
7c3df132 6832 ql_log(ql_log_fatal, vha, 0x0088,
5433383e 6833 "Unable to verify integrity of firmware image "
5b5e0928 6834 "(%zd).\n", blob->fw->size);
5433383e
AV		 6835 goto fail_fw_integrity;
6836 }
6837
6838 fragment = 0;
6839 while (risc_size > 0 && rval == QLA_SUCCESS) {
6840 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
6841 if (wlen > risc_size)
6842 wlen = risc_size;
7c3df132
SK		 6843 ql_dbg(ql_dbg_init, vha, 0x0089,
6844 "Loading risc segment@ risc addr %x number of "
6845 "words 0x%x.\n", risc_addr, wlen);
5433383e
AV		 6846
6847 for (i = 0; i < wlen; i++)
6848 wcode[i] = swab16(fwcode[i]);
6849
73208dfd 6850 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
5433383e
AV		 6851 wlen);
6852 if (rval) {
7c3df132
SK		 6853 ql_log(ql_log_fatal, vha, 0x008a,
6854 "Failed to load segment %d of firmware.\n",
6855 fragment);
5433383e
AV		 6856 break;
6857 }
6858
6859 fwcode += wlen;
6860 risc_addr += wlen;
6861 risc_size -= wlen;
6862 fragment++;
6863 }
6864
6865 /* Next segment. */
6866 seg++;
6867 }
6868 return rval;
6869
6870fail_fw_integrity:
6871 return QLA_FUNCTION_FAILED;
6872}
6873
eaac30be
AV		 6874static int
6875qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
0107109e
AV		 6876{
6877 int rval;
6878 int segments, fragment;
6879 uint32_t *dcode, dlen;
6880 uint32_t risc_addr;
6881 uint32_t risc_size;
6882 uint32_t i;
5433383e 6883 struct fw_blob *blob;
f73cb695
CD		 6884 const uint32_t *fwcode;
6885 uint32_t fwclen;
e315cd28 6886 struct qla_hw_data *ha = vha->hw;
73208dfd 6887 struct req_que *req = ha->req_q_map[0];
0107109e 6888
5433383e 6889 /* Load firmware blob. */
e315cd28 6890 blob = qla2x00_request_firmware(vha);
5433383e 6891 if (!blob) {
7c3df132 6892 ql_log(ql_log_warn, vha, 0x0090,
94bcf830 6893 "Firmware image unavailable.\n");
7c3df132
SK		 6894 ql_log(ql_log_warn, vha, 0x0091,
6895 "Firmware images can be retrieved from: "
6896 QLA_FW_URL ".\n");
d1c61909 6897
eaac30be 6898 return QLA_FUNCTION_FAILED;
0107109e
AV		 6899 }
6900
cfb0919c
CD		 6901 ql_dbg(ql_dbg_init, vha, 0x0092,
6902 "FW: Loading via request-firmware.\n");
eaac30be 6903
0107109e
AV		 6904 rval = QLA_SUCCESS;
6905
6906 segments = FA_RISC_CODE_SEGMENTS;
73208dfd 6907 dcode = (uint32_t *)req->ring;
0107109e 6908 *srisc_addr = 0;
5433383e 6909 fwcode = (uint32_t *)blob->fw->data;
0107109e
AV		 6910 fwclen = 0;
6911
6912 /* Validate firmware image by checking version. */
5433383e 6913 if (blob->fw->size < 8 * sizeof(uint32_t)) {
7c3df132 6914 ql_log(ql_log_fatal, vha, 0x0093,
5b5e0928 6915 "Unable to verify integrity of firmware image (%zd).\n",
5433383e 6916 blob->fw->size);
f73cb695 6917 return QLA_FUNCTION_FAILED;
0107109e
AV		 6918 }
6919 for (i = 0; i < 4; i++)
6920 dcode[i] = be32_to_cpu(fwcode[i + 4]);
6921 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
6922 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
6923 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
6924 dcode[3] == 0)) {
7c3df132 6925 ql_log(ql_log_fatal, vha, 0x0094,
5b5e0928 6926 "Unable to verify integrity of firmware image (%zd).\n",
7c3df132
SK		 6927 blob->fw->size);
6928 ql_log(ql_log_fatal, vha, 0x0095,
6929 "Firmware data: %08x %08x %08x %08x.\n",
6930 dcode[0], dcode[1], dcode[2], dcode[3]);
f73cb695 6931 return QLA_FUNCTION_FAILED;
0107109e
AV		 6932 }
6933
6934 while (segments && rval == QLA_SUCCESS) {
6935 risc_addr = be32_to_cpu(fwcode[2]);
6936 *srisc_addr = *srisc_addr == 0 ? risc_addr : *srisc_addr;
6937 risc_size = be32_to_cpu(fwcode[3]);
6938
6939 /* Validate firmware image size. */
6940 fwclen += risc_size * sizeof(uint32_t);
5433383e 6941 if (blob->fw->size < fwclen) {
7c3df132 6942 ql_log(ql_log_fatal, vha, 0x0096,
5433383e 6943 "Unable to verify integrity of firmware image "
5b5e0928 6944 "(%zd).\n", blob->fw->size);
f73cb695 6945 return QLA_FUNCTION_FAILED;
0107109e
AV		 6946 }
6947
6948 fragment = 0;
6949 while (risc_size > 0 && rval == QLA_SUCCESS) {
6950 dlen = (uint32_t)(ha->fw_transfer_size >> 2);
6951 if (dlen > risc_size)
6952 dlen = risc_size;
6953
7c3df132
SK		 6954 ql_dbg(ql_dbg_init, vha, 0x0097,
6955 "Loading risc segment@ risc addr %x "
6956 "number of dwords 0x%x.\n", risc_addr, dlen);
0107109e
AV		 6957
6958 for (i = 0; i < dlen; i++)
6959 dcode[i] = swab32(fwcode[i]);
6960
73208dfd 6961 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
590f98e5 6962 dlen);
0107109e 6963 if (rval) {
7c3df132
SK		 6964 ql_log(ql_log_fatal, vha, 0x0098,
6965 "Failed to load segment %d of firmware.\n",
6966 fragment);
f261f7af 6967 return QLA_FUNCTION_FAILED;
0107109e
AV		 6968 }
6969
6970 fwcode += dlen;
6971 risc_addr += dlen;
6972 risc_size -= dlen;
6973 fragment++;
6974 }
6975
6976 /* Next segment. */
6977 segments--;
6978 }
f73cb695
CD		 6979
6980 if (!IS_QLA27XX(ha))
6981 return rval;
6982
6983 if (ha->fw_dump_template)
6984 vfree(ha->fw_dump_template);
6985 ha->fw_dump_template = NULL;
6986 ha->fw_dump_template_len = 0;
6987
6988 ql_dbg(ql_dbg_init, vha, 0x171,
97ea702b
CD		 6989 "Loading fwdump template from %x\n",
6990 (uint32_t)((void *)fwcode - (void *)blob->fw->data));
f73cb695
CD		 6991 risc_size = be32_to_cpu(fwcode[2]);
6992 ql_dbg(ql_dbg_init, vha, 0x172,
6993 "-> array size %x dwords\n", risc_size);
6994 if (risc_size == 0 || risc_size == ~0)
6995 goto default_template;
6996
6997 dlen = (risc_size - 8) * sizeof(*fwcode);
6998 ql_dbg(ql_dbg_init, vha, 0x0173,
6999 "-> template allocating %x bytes...\n", dlen);
7000 ha->fw_dump_template = vmalloc(dlen);
7001 if (!ha->fw_dump_template) {
7002 ql_log(ql_log_warn, vha, 0x0174,
7003 "Failed fwdump template allocate %x bytes.\n", risc_size);
7004 goto default_template;
7005 }
7006
7007 fwcode += 7;
7008 risc_size -= 8;
7009 dcode = ha->fw_dump_template;
7010 for (i = 0; i < risc_size; i++)
7011 dcode[i] = le32_to_cpu(fwcode[i]);
7012
7013 if (!qla27xx_fwdt_template_valid(dcode)) {
7014 ql_log(ql_log_warn, vha, 0x0175,
7015 "Failed fwdump template validate\n");
7016 goto default_template;
7017 }
7018
7019 dlen = qla27xx_fwdt_template_size(dcode);
7020 ql_dbg(ql_dbg_init, vha, 0x0176,
7021 "-> template size %x bytes\n", dlen);
7022 if (dlen > risc_size * sizeof(*fwcode)) {
7023 ql_log(ql_log_warn, vha, 0x0177,
4fae52b5 7024 "Failed fwdump template exceeds array by %zx bytes\n",
383a298b 7025 (size_t)(dlen - risc_size * sizeof(*fwcode)));
f73cb695
CD		 7026 goto default_template;
7027 }
7028 ha->fw_dump_template_len = dlen;
0107109e
AV		 7029 return rval;
7030
f73cb695
CD		 7031default_template:
7032 ql_log(ql_log_warn, vha, 0x0178, "Using default fwdump template\n");
7033 if (ha->fw_dump_template)
7034 vfree(ha->fw_dump_template);
7035 ha->fw_dump_template = NULL;
7036 ha->fw_dump_template_len = 0;
7037
7038 dlen = qla27xx_fwdt_template_default_size();
7039 ql_dbg(ql_dbg_init, vha, 0x0179,
7040 "-> template allocating %x bytes...\n", dlen);
7041 ha->fw_dump_template = vmalloc(dlen);
7042 if (!ha->fw_dump_template) {
7043 ql_log(ql_log_warn, vha, 0x017a,
7044 "Failed fwdump template allocate %x bytes.\n", risc_size);
7045 goto failed_template;
7046 }
7047
7048 dcode = ha->fw_dump_template;
7049 risc_size = dlen / sizeof(*fwcode);
7050 fwcode = qla27xx_fwdt_template_default();
7051 for (i = 0; i < risc_size; i++)
7052 dcode[i] = be32_to_cpu(fwcode[i]);
7053
7054 if (!qla27xx_fwdt_template_valid(ha->fw_dump_template)) {
7055 ql_log(ql_log_warn, vha, 0x017b,
7056 "Failed fwdump template validate\n");
7057 goto failed_template;
7058 }
7059
7060 dlen = qla27xx_fwdt_template_size(ha->fw_dump_template);
7061 ql_dbg(ql_dbg_init, vha, 0x017c,
7062 "-> template size %x bytes\n", dlen);
7063 ha->fw_dump_template_len = dlen;
7064 return rval;
7065
7066failed_template:
7067 ql_log(ql_log_warn, vha, 0x017d, "Failed default fwdump template\n");
7068 if (ha->fw_dump_template)
7069 vfree(ha->fw_dump_template);
7070 ha->fw_dump_template = NULL;
7071 ha->fw_dump_template_len = 0;
7072 return rval;
0107109e 7073}
18c6c127 7074
eaac30be
AV		 7075int
7076qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7077{
7078 int rval;
7079
e337d907
AV		 7080 if (ql2xfwloadbin == 1)
7081 return qla81xx_load_risc(vha, srisc_addr);
7082
eaac30be
AV		 7083 /*
7084 * FW Load priority:
7085 * 1) Firmware via request-firmware interface (.bin file).
7086 * 2) Firmware residing in flash.
7087 */
7088 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7089 if (rval == QLA_SUCCESS)
7090 return rval;
7091
cbc8eb67
AV		 7092 return qla24xx_load_risc_flash(vha, srisc_addr,
7093 vha->hw->flt_region_fw);
eaac30be
AV		 7094}
7095
7096int
7097qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
7098{
7099 int rval;
cbc8eb67 7100 struct qla_hw_data *ha = vha->hw;
eaac30be 7101
e337d907 7102 if (ql2xfwloadbin == 2)
cbc8eb67 7103 goto try_blob_fw;
e337d907 7104
eaac30be
AV		 7105 /*
7106 * FW Load priority:
7107 * 1) Firmware residing in flash.
7108 * 2) Firmware via request-firmware interface (.bin file).
cbc8eb67 7109 * 3) Golden-Firmware residing in flash -- limited operation.
eaac30be 7110 */
cbc8eb67 7111 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
eaac30be
AV		 7112 if (rval == QLA_SUCCESS)
7113 return rval;
7114
cbc8eb67
AV		 7115try_blob_fw:
7116 rval = qla24xx_load_risc_blob(vha, srisc_addr);
7117 if (rval == QLA_SUCCESS || !ha->flt_region_gold_fw)
7118 return rval;
7119
7c3df132
SK		 7120 ql_log(ql_log_info, vha, 0x0099,
7121 "Attempting to fallback to golden firmware.\n");
cbc8eb67
AV		 7122 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
7123 if (rval != QLA_SUCCESS)
7124 return rval;
7125
7c3df132 7126 ql_log(ql_log_info, vha, 0x009a, "Update operational firmware.\n");
cbc8eb67 7127 ha->flags.running_gold_fw = 1;
cbc8eb67 7128 return rval;
eaac30be
AV		 7129}
7130
18c6c127 7131void
e315cd28 7132qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
18c6c127
AV		 7133{
7134 int ret, retries;
e315cd28 7135 struct qla_hw_data *ha = vha->hw;
18c6c127 7136
85880801
AV		 7137 if (ha->flags.pci_channel_io_perm_failure)
7138 return;
e428924c 7139 if (!IS_FWI2_CAPABLE(ha))
18c6c127 7140 return;
75edf81d
AV		 7141 if (!ha->fw_major_version)
7142 return;
ec7193e2
QT		 7143 if (!ha->flags.fw_started)
7144 return;
18c6c127 7145
e315cd28 7146 ret = qla2x00_stop_firmware(vha);
7c7f1f29 7147 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
b469a7cb 7148 ret != QLA_INVALID_COMMAND && retries ; retries--) {
e315cd28
AC		 7149 ha->isp_ops->reset_chip(vha);
7150 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
18c6c127 7151 continue;
e315cd28 7152 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
18c6c127 7153 continue;
7c3df132
SK		 7154 ql_log(ql_log_info, vha, 0x8015,
7155 "Attempting retry of stop-firmware command.\n");
e315cd28 7156 ret = qla2x00_stop_firmware(vha);
18c6c127 7157 }
ec7193e2 7158
4b60c827 7159 QLA_FW_STOPPED(ha);
ec7193e2 7160 ha->flags.fw_init_done = 0;
18c6c127 7161}
2c3dfe3f
SJ		 7162
7163int
e315cd28 7164qla24xx_configure_vhba(scsi_qla_host_t *vha)
2c3dfe3f
SJ		 7165{
7166 int rval = QLA_SUCCESS;
0b91d116 7167 int rval2;
2c3dfe3f 7168 uint16_t mb[MAILBOX_REGISTER_COUNT];
e315cd28
AC		 7169 struct qla_hw_data *ha = vha->hw;
7170 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
67c2e93a
AC		 7171 struct req_que *req;
7172 struct rsp_que *rsp;
2c3dfe3f 7173
e315cd28 7174 if (!vha->vp_idx)
2c3dfe3f
SJ		 7175 return -EINVAL;
7176
e315cd28 7177 rval = qla2x00_fw_ready(base_vha);
d7459527
MH		 7178 if (vha->qpair)
7179 req = vha->qpair->req;
67c2e93a 7180 else
d7459527 7181 req = ha->req_q_map[0];
67c2e93a
AC		 7182 rsp = req->rsp;
7183
2c3dfe3f 7184 if (rval == QLA_SUCCESS) {
e315cd28 7185 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
73208dfd 7186 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
2c3dfe3f
SJ		 7187 }
7188
e315cd28 7189 vha->flags.management_server_logged_in = 0;
2c3dfe3f
SJ		 7190
7191 /* Login to SNS first */
0b91d116
CD		 7192 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
7193 BIT_1);
7194 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
7195 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
7196 ql_dbg(ql_dbg_init, vha, 0x0120,
7197 "Failed SNS login: loop_id=%x, rval2=%d\n",
7198 NPH_SNS, rval2);
7199 else
7200 ql_dbg(ql_dbg_init, vha, 0x0103,
7201 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
7202 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
7203 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
2c3dfe3f
SJ		 7204 return (QLA_FUNCTION_FAILED);
7205 }
7206
e315cd28
AC		 7207 atomic_set(&vha->loop_down_timer, 0);
7208 atomic_set(&vha->loop_state, LOOP_UP);
7209 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7210 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
7211 rval = qla2x00_loop_resync(base_vha);
2c3dfe3f
SJ		 7212
7213 return rval;
7214}
4d4df193
HK		 7215
7216/* 84XX Support **************************************************************/
7217
7218static LIST_HEAD(qla_cs84xx_list);
7219static DEFINE_MUTEX(qla_cs84xx_mutex);
7220
7221static struct qla_chip_state_84xx *
e315cd28 7222qla84xx_get_chip(struct scsi_qla_host *vha)
4d4df193
HK		 7223{
7224 struct qla_chip_state_84xx *cs84xx;
e315cd28 7225 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7226
7227 mutex_lock(&qla_cs84xx_mutex);
7228
7229 /* Find any shared 84xx chip. */
7230 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
7231 if (cs84xx->bus == ha->pdev->bus) {
7232 kref_get(&cs84xx->kref);
7233 goto done;
7234 }
7235 }
7236
7237 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
7238 if (!cs84xx)
7239 goto done;
7240
7241 kref_init(&cs84xx->kref);
7242 spin_lock_init(&cs84xx->access_lock);
7243 mutex_init(&cs84xx->fw_update_mutex);
7244 cs84xx->bus = ha->pdev->bus;
7245
7246 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
7247done:
7248 mutex_unlock(&qla_cs84xx_mutex);
7249 return cs84xx;
7250}
7251
7252static void
7253__qla84xx_chip_release(struct kref *kref)
7254{
7255 struct qla_chip_state_84xx *cs84xx =
7256 container_of(kref, struct qla_chip_state_84xx, kref);
7257
7258 mutex_lock(&qla_cs84xx_mutex);
7259 list_del(&cs84xx->list);
7260 mutex_unlock(&qla_cs84xx_mutex);
7261 kfree(cs84xx);
7262}
7263
7264void
e315cd28 7265qla84xx_put_chip(struct scsi_qla_host *vha)
4d4df193 7266{
e315cd28 7267 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7268 if (ha->cs84xx)
7269 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
7270}
7271
7272static int
e315cd28 7273qla84xx_init_chip(scsi_qla_host_t *vha)
4d4df193
HK		 7274{
7275 int rval;
7276 uint16_t status[2];
e315cd28 7277 struct qla_hw_data *ha = vha->hw;
4d4df193
HK		 7278
7279 mutex_lock(&ha->cs84xx->fw_update_mutex);
7280
e315cd28 7281 rval = qla84xx_verify_chip(vha, status);
4d4df193
HK		 7282
7283 mutex_unlock(&ha->cs84xx->fw_update_mutex);
7284
7285 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED:
7286 QLA_SUCCESS;
7287}
3a03eb79
AV		 7288
7289/* 81XX Support **************************************************************/
7290
7291int
7292qla81xx_nvram_config(scsi_qla_host_t *vha)
7293{
7294 int rval;
7295 struct init_cb_81xx *icb;
7296 struct nvram_81xx *nv;
7297 uint32_t *dptr;
7298 uint8_t *dptr1, *dptr2;
7299 uint32_t chksum;
7300 uint16_t cnt;
7301 struct qla_hw_data *ha = vha->hw;
7302
7303 rval = QLA_SUCCESS;
7304 icb = (struct init_cb_81xx *)ha->init_cb;
7305 nv = ha->nvram;
7306
7307 /* Determine NVRAM starting address. */
7308 ha->nvram_size = sizeof(struct nvram_81xx);
3a03eb79 7309 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7ec0effd
AD		 7310 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
7311 ha->vpd_size = FA_VPD_SIZE_82XX;
3a03eb79
AV		 7312
7313 /* Get VPD data into cache */
7314 ha->vpd = ha->nvram + VPD_OFFSET;
3d79038f
AV		 7315 ha->isp_ops->read_optrom(vha, ha->vpd, ha->flt_region_vpd << 2,
7316 ha->vpd_size);
3a03eb79
AV		 7317
7318 /* Get NVRAM data into cache and calculate checksum. */
3d79038f 7319 ha->isp_ops->read_optrom(vha, ha->nvram, ha->flt_region_nvram << 2,
3a03eb79 7320 ha->nvram_size);
3d79038f 7321 dptr = (uint32_t *)nv;
da08ef5c
JC		 7322 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7323 chksum += le32_to_cpu(*dptr);
3a03eb79 7324
7c3df132
SK		 7325 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
7326 "Contents of NVRAM:\n");
7327 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
7328 (uint8_t *)nv, ha->nvram_size);
3a03eb79
AV		 7329
7330 /* Bad NVRAM data, set defaults parameters. */
7331 if (chksum || nv->id[0] != 'I' || nv->id[1] != 'S' || nv->id[2] != 'P'
7332 || nv->id[3] != ' ' ||
ad950360 7333 nv->nvram_version < cpu_to_le16(ICB_VERSION)) {
3a03eb79 7334 /* Reset NVRAM data. */
7c3df132 7335 ql_log(ql_log_info, vha, 0x0073,
9e336520 7336 "Inconsistent NVRAM detected: checksum=0x%x id=%c "
7c3df132 7337 "version=0x%x.\n", chksum, nv->id[0],
3a03eb79 7338 le16_to_cpu(nv->nvram_version));
7c3df132
SK		 7339 ql_log(ql_log_info, vha, 0x0074,
7340 "Falling back to functioning (yet invalid -- WWPN) "
7341 "defaults.\n");
3a03eb79
AV		 7342
7343 /*
7344 * Set default initialization control block.
7345 */
7346 memset(nv, 0, ha->nvram_size);
ad950360
BVA		 7347 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7348 nv->version = cpu_to_le16(ICB_VERSION);
98aee70d 7349 nv->frame_payload_size = 2048;
ad950360
BVA		 7350 nv->execution_throttle = cpu_to_le16(0xFFFF);
7351 nv->exchange_count = cpu_to_le16(0);
3a03eb79 7352 nv->port_name[0] = 0x21;
f73cb695 7353 nv->port_name[1] = 0x00 + ha->port_no + 1;
3a03eb79
AV		 7354 nv->port_name[2] = 0x00;
7355 nv->port_name[3] = 0xe0;
7356 nv->port_name[4] = 0x8b;
7357 nv->port_name[5] = 0x1c;
7358 nv->port_name[6] = 0x55;
7359 nv->port_name[7] = 0x86;
7360 nv->node_name[0] = 0x20;
7361 nv->node_name[1] = 0x00;
7362 nv->node_name[2] = 0x00;
7363 nv->node_name[3] = 0xe0;
7364 nv->node_name[4] = 0x8b;
7365 nv->node_name[5] = 0x1c;
7366 nv->node_name[6] = 0x55;
7367 nv->node_name[7] = 0x86;
ad950360
BVA		 7368 nv->login_retry_count = cpu_to_le16(8);
7369 nv->interrupt_delay_timer = cpu_to_le16(0);
7370 nv->login_timeout = cpu_to_le16(0);
3a03eb79 7371 nv->firmware_options_1 =
ad950360
BVA		 7372 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7373 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7374 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7375 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7376 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7377 nv->efi_parameters = cpu_to_le32(0);
3a03eb79 7378 nv->reset_delay = 5;
ad950360
BVA		 7379 nv->max_luns_per_target = cpu_to_le16(128);
7380 nv->port_down_retry_count = cpu_to_le16(30);
7381 nv->link_down_timeout = cpu_to_le16(180);
eeebcc92 7382 nv->enode_mac[0] = 0x00;
6246b8a1
GM		 7383 nv->enode_mac[1] = 0xC0;
7384 nv->enode_mac[2] = 0xDD;
3a03eb79
AV		 7385 nv->enode_mac[3] = 0x04;
7386 nv->enode_mac[4] = 0x05;
f73cb695 7387 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7388
7389 rval = 1;
7390 }
7391
9e522cd8
AE		 7392 if (IS_T10_PI_CAPABLE(ha))
7393 nv->frame_payload_size &= ~7;
7394
aa230bc5
AE		 7395 qlt_81xx_config_nvram_stage1(vha, nv);
7396
3a03eb79 7397 /* Reset Initialization control block */
773120e4 7398 memset(icb, 0, ha->init_cb_size);
3a03eb79
AV		 7399
7400 /* Copy 1st segment. */
7401 dptr1 = (uint8_t *)icb;
7402 dptr2 = (uint8_t *)&nv->version;
7403 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7404 while (cnt--)
7405 *dptr1++ = *dptr2++;
7406
7407 icb->login_retry_count = nv->login_retry_count;
7408
7409 /* Copy 2nd segment. */
7410 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7411 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7412 cnt = (uint8_t *)&icb->reserved_5 -
7413 (uint8_t *)&icb->interrupt_delay_timer;
7414 while (cnt--)
7415 *dptr1++ = *dptr2++;
7416
7417 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
7418 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */
7419 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
69e5f1ea
AV		 7420 icb->enode_mac[0] = 0x00;
7421 icb->enode_mac[1] = 0xC0;
7422 icb->enode_mac[2] = 0xDD;
3a03eb79
AV		 7423 icb->enode_mac[3] = 0x04;
7424 icb->enode_mac[4] = 0x05;
f73cb695 7425 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
3a03eb79
AV		 7426 }
7427
b64b0e8f
AV		 7428 /* Use extended-initialization control block. */
7429 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
7430
3a03eb79
AV		 7431 /*
7432 * Setup driver NVRAM options.
7433 */
7434 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
a9083016 7435 "QLE8XXX");
3a03eb79 7436
aa230bc5
AE		 7437 qlt_81xx_config_nvram_stage2(vha, icb);
7438
3a03eb79 7439 /* Use alternate WWN? */
ad950360 7440 if (nv->host_p & cpu_to_le32(BIT_15)) {
3a03eb79
AV		 7441 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7442 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7443 }
7444
7445 /* Prepare nodename */
ad950360 7446 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
3a03eb79
AV		 7447 /*
7448 * Firmware will apply the following mask if the nodename was
7449 * not provided.
7450 */
7451 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7452 icb->node_name[0] &= 0xF0;
7453 }
7454
7455 /* Set host adapter parameters. */
7456 ha->flags.disable_risc_code_load = 0;
7457 ha->flags.enable_lip_reset = 0;
7458 ha->flags.enable_lip_full_login =
7459 le32_to_cpu(nv->host_p) & BIT_10 ? 1: 0;
7460 ha->flags.enable_target_reset =
7461 le32_to_cpu(nv->host_p) & BIT_11 ? 1: 0;
7462 ha->flags.enable_led_scheme = 0;
7463 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1: 0;
7464
7465 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7466 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7467
7468 /* save HBA serial number */
7469 ha->serial0 = icb->port_name[5];
7470 ha->serial1 = icb->port_name[6];
7471 ha->serial2 = icb->port_name[7];
7472 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7473 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7474
ad950360 7475 icb->execution_throttle = cpu_to_le16(0xFFFF);
3a03eb79
AV		 7476
7477 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7478
7479 /* Set minimum login_timeout to 4 seconds. */
7480 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7481 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7482 if (le16_to_cpu(nv->login_timeout) < 4)
ad950360 7483 nv->login_timeout = cpu_to_le16(4);
3a03eb79 7484 ha->login_timeout = le16_to_cpu(nv->login_timeout);
3a03eb79
AV		 7485
7486 /* Set minimum RATOV to 100 tenths of a second. */
7487 ha->r_a_tov = 100;
7488
7489 ha->loop_reset_delay = nv->reset_delay;
7490
7491 /* Link Down Timeout = 0:
7492 *
7ec0effd 7493 * When Port Down timer expires we will start returning
3a03eb79
AV		 7494 * I/O's to OS with "DID_NO_CONNECT".
7495 *
7496 * Link Down Timeout != 0:
7497 *
7498 * The driver waits for the link to come up after link down
7499 * before returning I/Os to OS with "DID_NO_CONNECT".
7500 */
7501 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7502 ha->loop_down_abort_time =
7503 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7504 } else {
7505 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7506 ha->loop_down_abort_time =
7507 (LOOP_DOWN_TIME - ha->link_down_timeout);
7508 }
7509
7510 /* Need enough time to try and get the port back. */
7511 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7512 if (qlport_down_retry)
7513 ha->port_down_retry_count = qlport_down_retry;
7514
7515 /* Set login_retry_count */
7516 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7517 if (ha->port_down_retry_count ==
7518 le16_to_cpu(nv->port_down_retry_count) &&
7519 ha->port_down_retry_count > 3)
7520 ha->login_retry_count = ha->port_down_retry_count;
7521 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7522 ha->login_retry_count = ha->port_down_retry_count;
7523 if (ql2xloginretrycount)
7524 ha->login_retry_count = ql2xloginretrycount;
7525
6246b8a1 7526 /* if not running MSI-X we need handshaking on interrupts */
f73cb695 7527 if (!vha->hw->flags.msix_enabled && (IS_QLA83XX(ha) || IS_QLA27XX(ha)))
ad950360 7528 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
6246b8a1 7529
3a03eb79
AV		 7530 /* Enable ZIO. */
7531 if (!vha->flags.init_done) {
7532 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7533 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7534 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7535 le16_to_cpu(icb->interrupt_delay_timer): 2;
7536 }
ad950360 7537 icb->firmware_options_2 &= cpu_to_le32(
3a03eb79
AV		 7538 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7539 vha->flags.process_response_queue = 0;
7540 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7541 ha->zio_mode = QLA_ZIO_MODE_6;
7542
7c3df132 7543 ql_log(ql_log_info, vha, 0x0075,
3a03eb79 7544 "ZIO mode %d enabled; timer delay (%d us).\n",
7c3df132
SK		 7545 ha->zio_mode,
7546 ha->zio_timer * 100);
3a03eb79
AV		 7547
7548 icb->firmware_options_2 |= cpu_to_le32(
7549 (uint32_t)ha->zio_mode);
7550 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7551 vha->flags.process_response_queue = 1;
7552 }
7553
41dc529a
QT		 7554 /* enable RIDA Format2 */
7555 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha))
7556 icb->firmware_options_3 |= BIT_0;
7557
3a03eb79 7558 if (rval) {
7c3df132
SK		 7559 ql_log(ql_log_warn, vha, 0x0076,
7560 "NVRAM configuration failed.\n");
3a03eb79
AV		 7561 }
7562 return (rval);
7563}
7564
a9083016
GM		 7565int
7566qla82xx_restart_isp(scsi_qla_host_t *vha)
7567{
7568 int status, rval;
a9083016
GM		 7569 struct qla_hw_data *ha = vha->hw;
7570 struct req_que *req = ha->req_q_map[0];
7571 struct rsp_que *rsp = ha->rsp_q_map[0];
7572 struct scsi_qla_host *vp;
feafb7b1 7573 unsigned long flags;
a9083016
GM		 7574
7575 status = qla2x00_init_rings(vha);
7576 if (!status) {
7577 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7578 ha->flags.chip_reset_done = 1;
7579
7580 status = qla2x00_fw_ready(vha);
7581 if (!status) {
a9083016
GM		 7582 /* Issue a marker after FW becomes ready. */
7583 qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL);
a9083016 7584 vha->flags.online = 1;
7108b76e 7585 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
a9083016
GM		 7586 }
7587
7588 /* if no cable then assume it's good */
7589 if ((vha->device_flags & DFLG_NO_CABLE))
7590 status = 0;
a9083016
GM		 7591 }
7592
7593 if (!status) {
7594 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7595
7596 if (!atomic_read(&vha->loop_down_timer)) {
7597 /*
7598 * Issue marker command only when we are going
7599 * to start the I/O .
7600 */
7601 vha->marker_needed = 1;
7602 }
7603
a9083016
GM		 7604 ha->isp_ops->enable_intrs(ha);
7605
7606 ha->isp_abort_cnt = 0;
7607 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7608
53296788 7609 /* Update the firmware version */
3173167f 7610 status = qla82xx_check_md_needed(vha);
53296788 7611
a9083016
GM		 7612 if (ha->fce) {
7613 ha->flags.fce_enabled = 1;
7614 memset(ha->fce, 0,
7615 fce_calc_size(ha->fce_bufs));
7616 rval = qla2x00_enable_fce_trace(vha,
7617 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7618 &ha->fce_bufs);
7619 if (rval) {
cfb0919c 7620 ql_log(ql_log_warn, vha, 0x8001,
7c3df132
SK		 7621 "Unable to reinitialize FCE (%d).\n",
7622 rval);
a9083016
GM		 7623 ha->flags.fce_enabled = 0;
7624 }
7625 }
7626
7627 if (ha->eft) {
7628 memset(ha->eft, 0, EFT_SIZE);
7629 rval = qla2x00_enable_eft_trace(vha,
7630 ha->eft_dma, EFT_NUM_BUFFERS);
7631 if (rval) {
cfb0919c 7632 ql_log(ql_log_warn, vha, 0x8010,
7c3df132
SK		 7633 "Unable to reinitialize EFT (%d).\n",
7634 rval);
a9083016
GM		 7635 }
7636 }
a9083016
GM		 7637 }
7638
7639 if (!status) {
cfb0919c 7640 ql_dbg(ql_dbg_taskm, vha, 0x8011,
7c3df132 7641 "qla82xx_restart_isp succeeded.\n");
feafb7b1
AE		 7642
7643 spin_lock_irqsave(&ha->vport_slock, flags);
7644 list_for_each_entry(vp, &ha->vp_list, list) {
7645 if (vp->vp_idx) {
7646 atomic_inc(&vp->vref_count);
7647 spin_unlock_irqrestore(&ha->vport_slock, flags);
7648
a9083016 7649 qla2x00_vp_abort_isp(vp);
feafb7b1
AE		 7650
7651 spin_lock_irqsave(&ha->vport_slock, flags);
7652 atomic_dec(&vp->vref_count);
7653 }
a9083016 7654 }
feafb7b1
AE		 7655 spin_unlock_irqrestore(&ha->vport_slock, flags);
7656
a9083016 7657 } else {
cfb0919c 7658 ql_log(ql_log_warn, vha, 0x8016,
7c3df132 7659 "qla82xx_restart_isp **** FAILED ****.\n");
a9083016
GM		 7660 }
7661
7662 return status;
7663}
7664
3a03eb79 7665void
ae97c91e 7666qla81xx_update_fw_options(scsi_qla_host_t *vha)
3a03eb79 7667{
ae97c91e
AV		 7668 struct qla_hw_data *ha = vha->hw;
7669
f198cafa
HM		 7670 /* Hold status IOCBs until ABTS response received. */
7671 if (ql2xfwholdabts)
7672 ha->fw_options[3] |= BIT_12;
7673
088d09d4
GM		 7674 /* Set Retry FLOGI in case of P2P connection */
7675 if (ha->operating_mode == P2P) {
7676 ha->fw_options[2] |= BIT_3;
7677 ql_dbg(ql_dbg_disc, vha, 0x2103,
7678 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
7679 __func__, ha->fw_options[2]);
7680 }
7681
41dc529a
QT		 7682 /* Move PUREX, ABTS RX & RIDA to ATIOQ */
7683 if (ql2xmvasynctoatio) {
7684 if (qla_tgt_mode_enabled(vha) ||
7685 qla_dual_mode_enabled(vha))
7686 ha->fw_options[2] |= BIT_11;
7687 else
7688 ha->fw_options[2] &= ~BIT_11;
7689 }
7690
f7e761f5 7691 if (qla_tgt_mode_enabled(vha) ||
2da52737
QT		 7692 qla_dual_mode_enabled(vha)) {
7693 /* FW auto send SCSI status during */
7694 ha->fw_options[1] |= BIT_8;
7695 ha->fw_options[10] |= (u16)SAM_STAT_BUSY << 8;
7696
7697 /* FW perform Exchange validation */
f7e761f5 7698 ha->fw_options[2] |= BIT_4;
2da52737
QT		 7699 } else {
7700 ha->fw_options[1] &= ~BIT_8;
7701 ha->fw_options[10] &= 0x00ff;
7702
f7e761f5 7703 ha->fw_options[2] &= ~BIT_4;
2da52737 7704 }
f7e761f5 7705
41dc529a
QT		 7706 if (ql2xetsenable) {
7707 /* Enable ETS Burst. */
7708 memset(ha->fw_options, 0, sizeof(ha->fw_options));
7709 ha->fw_options[2] |= BIT_9;
7710 }
7711
83548fe2
QT		 7712 ql_dbg(ql_dbg_init, vha, 0x00e9,
7713 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
7714 __func__, ha->fw_options[1], ha->fw_options[2],
7715 ha->fw_options[3], vha->host->active_mode);
ae97c91e 7716
ae97c91e 7717 qla2x00_set_fw_options(vha, ha->fw_options);
3a03eb79 7718}
09ff701a
SR		 7719
7720/*
7721 * qla24xx_get_fcp_prio
7722 * Gets the fcp cmd priority value for the logged in port.
7723 * Looks for a match of the port descriptors within
7724 * each of the fcp prio config entries. If a match is found,
7725 * the tag (priority) value is returned.
7726 *
7727 * Input:
21090cbe 7728 * vha = scsi host structure pointer.
09ff701a
SR		 7729 * fcport = port structure pointer.
7730 *
7731 * Return:
6c452a45 7732 * non-zero (if found)
f28a0a96 7733 * -1 (if not found)
09ff701a
SR		 7734 *
7735 * Context:
7736 * Kernel context
7737 */
f28a0a96 7738static int
09ff701a
SR		 7739qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
7740{
7741 int i, entries;
7742 uint8_t pid_match, wwn_match;
f28a0a96 7743 int priority;
09ff701a
SR		 7744 uint32_t pid1, pid2;
7745 uint64_t wwn1, wwn2;
7746 struct qla_fcp_prio_entry *pri_entry;
7747 struct qla_hw_data *ha = vha->hw;
7748
7749 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
f28a0a96 7750 return -1;
09ff701a 7751
f28a0a96 7752 priority = -1;
09ff701a
SR		 7753 entries = ha->fcp_prio_cfg->num_entries;
7754 pri_entry = &ha->fcp_prio_cfg->entry[0];
7755
7756 for (i = 0; i < entries; i++) {
7757 pid_match = wwn_match = 0;
7758
7759 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
7760 pri_entry++;
7761 continue;
7762 }
7763
7764 /* check source pid for a match */
7765 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
7766 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
7767 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
7768 if (pid1 == INVALID_PORT_ID)
7769 pid_match++;
7770 else if (pid1 == pid2)
7771 pid_match++;
7772 }
7773
7774 /* check destination pid for a match */
7775 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
7776 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
7777 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
7778 if (pid1 == INVALID_PORT_ID)
7779 pid_match++;
7780 else if (pid1 == pid2)
7781 pid_match++;
7782 }
7783
7784 /* check source WWN for a match */
7785 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
7786 wwn1 = wwn_to_u64(vha->port_name);
7787 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
7788 if (wwn2 == (uint64_t)-1)
7789 wwn_match++;
7790 else if (wwn1 == wwn2)
7791 wwn_match++;
7792 }
7793
7794 /* check destination WWN for a match */
7795 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
7796 wwn1 = wwn_to_u64(fcport->port_name);
7797 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
7798 if (wwn2 == (uint64_t)-1)
7799 wwn_match++;
7800 else if (wwn1 == wwn2)
7801 wwn_match++;
7802 }
7803
7804 if (pid_match == 2 || wwn_match == 2) {
7805 /* Found a matching entry */
7806 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
7807 priority = pri_entry->tag;
7808 break;
7809 }
7810
7811 pri_entry++;
7812 }
7813
7814 return priority;
7815}
7816
7817/*
7818 * qla24xx_update_fcport_fcp_prio
7819 * Activates fcp priority for the logged in fc port
7820 *
7821 * Input:
21090cbe 7822 * vha = scsi host structure pointer.
09ff701a
SR		 7823 * fcp = port structure pointer.
7824 *
7825 * Return:
7826 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7827 *
7828 * Context:
7829 * Kernel context.
7830 */
7831int
21090cbe 7832qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
09ff701a
SR		 7833{
7834 int ret;
f28a0a96 7835 int priority;
09ff701a
SR		 7836 uint16_t mb[5];
7837
21090cbe
MI		 7838 if (fcport->port_type != FCT_TARGET ||
7839 fcport->loop_id == FC_NO_LOOP_ID)
09ff701a
SR		 7840 return QLA_FUNCTION_FAILED;
7841
21090cbe 7842 priority = qla24xx_get_fcp_prio(vha, fcport);
f28a0a96
AV		 7843 if (priority < 0)
7844 return QLA_FUNCTION_FAILED;
7845
7ec0effd 7846 if (IS_P3P_TYPE(vha->hw)) {
a00f6296
SK		 7847 fcport->fcp_prio = priority & 0xf;
7848 return QLA_SUCCESS;
7849 }
7850
21090cbe 7851 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
cfb0919c
CD		 7852 if (ret == QLA_SUCCESS) {
7853 if (fcport->fcp_prio != priority)
7854 ql_dbg(ql_dbg_user, vha, 0x709e,
7855 "Updated FCP_CMND priority - value=%d loop_id=%d "
7856 "port_id=%02x%02x%02x.\n", priority,
7857 fcport->loop_id, fcport->d_id.b.domain,
7858 fcport->d_id.b.area, fcport->d_id.b.al_pa);
a00f6296 7859 fcport->fcp_prio = priority & 0xf;
cfb0919c 7860 } else
7c3df132 7861 ql_dbg(ql_dbg_user, vha, 0x704f,
cfb0919c
CD		 7862 "Unable to update FCP_CMND priority - ret=0x%x for "
7863 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
7864 fcport->d_id.b.domain, fcport->d_id.b.area,
7865 fcport->d_id.b.al_pa);
09ff701a
SR		 7866 return ret;
7867}
7868
7869/*
7870 * qla24xx_update_all_fcp_prio
7871 * Activates fcp priority for all the logged in ports
7872 *
7873 * Input:
7874 * ha = adapter block pointer.
7875 *
7876 * Return:
7877 * QLA_SUCCESS or QLA_FUNCTION_FAILED
7878 *
7879 * Context:
7880 * Kernel context.
7881 */
7882int
7883qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
7884{
7885 int ret;
7886 fc_port_t *fcport;
7887
7888 ret = QLA_FUNCTION_FAILED;
7889 /* We need to set priority for all logged in ports */
7890 list_for_each_entry(fcport, &vha->vp_fcports, list)
7891 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
7892
7893 return ret;
7894}
d7459527 7895
82de802a
QT		 7896struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
7897 int vp_idx, bool startqp)
d7459527
MH		 7898{
7899 int rsp_id = 0;
7900 int req_id = 0;
7901 int i;
7902 struct qla_hw_data *ha = vha->hw;
7903 uint16_t qpair_id = 0;
7904 struct qla_qpair *qpair = NULL;
7905 struct qla_msix_entry *msix;
7906
7907 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
7908 ql_log(ql_log_warn, vha, 0x00181,
7909 "FW/Driver is not multi-queue capable.\n");
7910 return NULL;
7911 }
7912
7913 if (ql2xmqsupport) {
7914 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
7915 if (qpair == NULL) {
7916 ql_log(ql_log_warn, vha, 0x0182,
7917 "Failed to allocate memory for queue pair.\n");
7918 return NULL;
7919 }
7920 memset(qpair, 0, sizeof(struct qla_qpair));
7921
7922 qpair->hw = vha->hw;
25ff6af1 7923 qpair->vha = vha;
82de802a
QT		 7924 qpair->qp_lock_ptr = &qpair->qp_lock;
7925 spin_lock_init(&qpair->qp_lock);
af7bb382 7926 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
d7459527
MH		 7927
7928 /* Assign available que pair id */
7929 mutex_lock(&ha->mq_lock);
7930 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
b95b9452 7931 if (ha->num_qpairs >= ha->max_qpairs) {
d7459527
MH		 7932 mutex_unlock(&ha->mq_lock);
7933 ql_log(ql_log_warn, vha, 0x0183,
7934 "No resources to create additional q pair.\n");
7935 goto fail_qid_map;
7936 }
b95b9452 7937 ha->num_qpairs++;
d7459527
MH		 7938 set_bit(qpair_id, ha->qpair_qid_map);
7939 ha->queue_pair_map[qpair_id] = qpair;
7940 qpair->id = qpair_id;
7941 qpair->vp_idx = vp_idx;
e6373f33 7942 qpair->fw_started = ha->flags.fw_started;
e326d22a 7943 INIT_LIST_HEAD(&qpair->hints_list);
cf19c45d 7944 INIT_LIST_HEAD(&qpair->nvme_done_list);
7c3f8fd1
QT		 7945 qpair->chip_reset = ha->base_qpair->chip_reset;
7946 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
7947 qpair->enable_explicit_conf =
7948 ha->base_qpair->enable_explicit_conf;
d7459527
MH		 7949
7950 for (i = 0; i < ha->msix_count; i++) {
093df737 7951 msix = &ha->msix_entries[i];
d7459527
MH		 7952 if (msix->in_use)
7953 continue;
7954 qpair->msix = msix;
83548fe2 7955 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
d7459527
MH		 7956 "Vector %x selected for qpair\n", msix->vector);
7957 break;
7958 }
7959 if (!qpair->msix) {
7960 ql_log(ql_log_warn, vha, 0x0184,
7961 "Out of MSI-X vectors!.\n");
7962 goto fail_msix;
7963 }
7964
7965 qpair->msix->in_use = 1;
7966 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
8abfa9e2
QT		 7967 qpair->pdev = ha->pdev;
7968 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
7969 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
d7459527
MH		 7970
7971 mutex_unlock(&ha->mq_lock);
7972
7973 /* Create response queue first */
82de802a 7974 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
d7459527
MH		 7975 if (!rsp_id) {
7976 ql_log(ql_log_warn, vha, 0x0185,
7977 "Failed to create response queue.\n");
7978 goto fail_rsp;
7979 }
7980
7981 qpair->rsp = ha->rsp_q_map[rsp_id];
7982
7983 /* Create request queue */
82de802a
QT		 7984 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
7985 startqp);
d7459527
MH		 7986 if (!req_id) {
7987 ql_log(ql_log_warn, vha, 0x0186,
7988 "Failed to create request queue.\n");
7989 goto fail_req;
7990 }
7991
7992 qpair->req = ha->req_q_map[req_id];
7993 qpair->rsp->req = qpair->req;
82de802a 7994 qpair->rsp->qpair = qpair;
e326d22a
QT		 7995 /* init qpair to this cpu. Will adjust at run time. */
7996 qla_cpu_update(qpair, smp_processor_id());
d7459527
MH		 7997
7998 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
7999 if (ha->fw_attributes & BIT_4)
8000 qpair->difdix_supported = 1;
8001 }
8002
8003 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
8004 if (!qpair->srb_mempool) {
83548fe2 8005 ql_log(ql_log_warn, vha, 0xd036,
d7459527
MH		 8006 "Failed to create srb mempool for qpair %d\n",
8007 qpair->id);
8008 goto fail_mempool;
8009 }
8010
8011 /* Mark as online */
8012 qpair->online = 1;
8013
8014 if (!vha->flags.qpairs_available)
8015 vha->flags.qpairs_available = 1;
8016
8017 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
8018 "Request/Response queue pair created, id %d\n",
8019 qpair->id);
8020 ql_dbg(ql_dbg_init, vha, 0x0187,
8021 "Request/Response queue pair created, id %d\n",
8022 qpair->id);
8023 }
8024 return qpair;
8025
8026fail_mempool:
8027fail_req:
8028 qla25xx_delete_rsp_que(vha, qpair->rsp);
8029fail_rsp:
8030 mutex_lock(&ha->mq_lock);
8031 qpair->msix->in_use = 0;
8032 list_del(&qpair->qp_list_elem);
8033 if (list_empty(&vha->qp_list))
8034 vha->flags.qpairs_available = 0;
8035fail_msix:
8036 ha->queue_pair_map[qpair_id] = NULL;
8037 clear_bit(qpair_id, ha->qpair_qid_map);
b95b9452 8038 ha->num_qpairs--;
d7459527
MH		 8039 mutex_unlock(&ha->mq_lock);
8040fail_qid_map:
8041 kfree(qpair);
8042 return NULL;
8043}
8044
8045int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
8046{
d65237c7 8047 int ret = QLA_FUNCTION_FAILED;
d7459527
MH		 8048 struct qla_hw_data *ha = qpair->hw;
8049
d65237c7
SC		 8050 if (!vha->flags.qpairs_req_created && !vha->flags.qpairs_rsp_created)
8051 goto fail;
8052
d7459527
MH		 8053 qpair->delete_in_progress = 1;
8054 while (atomic_read(&qpair->ref_count))
8055 msleep(500);
8056
8057 ret = qla25xx_delete_req_que(vha, qpair->req);
8058 if (ret != QLA_SUCCESS)
8059 goto fail;
8060 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
8061 if (ret != QLA_SUCCESS)
8062 goto fail;
8063
8064 mutex_lock(&ha->mq_lock);
8065 ha->queue_pair_map[qpair->id] = NULL;
8066 clear_bit(qpair->id, ha->qpair_qid_map);
b95b9452 8067 ha->num_qpairs--;
d7459527 8068 list_del(&qpair->qp_list_elem);
d65237c7 8069 if (list_empty(&vha->qp_list)) {
d7459527 8070 vha->flags.qpairs_available = 0;
d65237c7
SC		 8071 vha->flags.qpairs_req_created = 0;
8072 vha->flags.qpairs_rsp_created = 0;
8073 }
d7459527
MH		 8074 mempool_destroy(qpair->srb_mempool);
8075 kfree(qpair);
8076 mutex_unlock(&ha->mq_lock);
8077
8078 return QLA_SUCCESS;
8079fail:
8080 return ret;
8081}
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