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scsi: qla2xxx: Convert timers to use timer_setup()
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
CommitLineData
1da177e4 1/*
fa90c54f 2 * QLogic Fibre Channel HBA Driver
bd21eaf9 3 * Copyright (c) 2003-2014 QLogic Corporation
1da177e4 4 *
fa90c54f 5 * See LICENSE.qla2xxx for copyright and licensing details.
1da177e4
LT		 6 */
7#include "qla_def.h"
8
9#include <linux/moduleparam.h>
10#include <linux/vmalloc.h>
1da177e4 11#include <linux/delay.h>
39a11240 12#include <linux/kthread.h>
e1e82b6f 13#include <linux/mutex.h>
3420d36c 14#include <linux/kobject.h>
5a0e3ad6 15#include <linux/slab.h>
5601236b 16#include <linux/blk-mq-pci.h>
1da177e4
LT		 17#include <scsi/scsi_tcq.h>
18#include <scsi/scsicam.h>
19#include <scsi/scsi_transport.h>
20#include <scsi/scsi_transport_fc.h>
21
2d70c103
NB		 22#include "qla_target.h"
23
1da177e4
LT		 24/*
25 * Driver version
26 */
27char qla2x00_version_str[40];
28
6a03b4cd
HZ		 29static int apidev_major;
30
1da177e4
LT		 31/*
32 * SRB allocation cache
33 */
d7459527 34struct kmem_cache *srb_cachep;
1da177e4 35
a9083016
GM		 36/*
37 * CT6 CTX allocation cache
38 */
39static struct kmem_cache *ctx_cachep;
3ce8866c
SK		 40/*
41 * error level for logging
42 */
43int ql_errlev = ql_log_all;
a9083016 44
fa492630 45static int ql2xenableclass2;
2d70c103
NB		 46module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
47MODULE_PARM_DESC(ql2xenableclass2,
48 "Specify if Class 2 operations are supported from the very "
49 "beginning. Default is 0 - class 2 not supported.");
50
8ae6d9c7 51
1da177e4 52int ql2xlogintimeout = 20;
f2019cb1 53module_param(ql2xlogintimeout, int, S_IRUGO);
1da177e4
LT		 54MODULE_PARM_DESC(ql2xlogintimeout,
55 "Login timeout value in seconds.");
56
a7b61842 57int qlport_down_retry;
f2019cb1 58module_param(qlport_down_retry, int, S_IRUGO);
1da177e4 59MODULE_PARM_DESC(qlport_down_retry,
900d9f98 60 "Maximum number of command retries to a port that returns "
1da177e4
LT		 61 "a PORT-DOWN status.");
62
1da177e4
LT		 63int ql2xplogiabsentdevice;
64module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
65MODULE_PARM_DESC(ql2xplogiabsentdevice,
66 "Option to enable PLOGI to devices that are not present after "
900d9f98 67 "a Fabric scan. This is needed for several broken switches. "
1da177e4
LT		 68 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
69
1da177e4 70int ql2xloginretrycount = 0;
f2019cb1 71module_param(ql2xloginretrycount, int, S_IRUGO);
1da177e4
LT		 72MODULE_PARM_DESC(ql2xloginretrycount,
73 "Specify an alternate value for the NVRAM login retry count.");
74
a7a167bf 75int ql2xallocfwdump = 1;
f2019cb1 76module_param(ql2xallocfwdump, int, S_IRUGO);
a7a167bf
AV		 77MODULE_PARM_DESC(ql2xallocfwdump,
78 "Option to enable allocation of memory for a firmware dump "
79 "during HBA initialization. Memory allocation requirements "
80 "vary by ISP type. Default is 1 - allocate memory.");
81
11010fec 82int ql2xextended_error_logging;
27d94035 83module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
a2b3e01d 84module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
11010fec 85MODULE_PARM_DESC(ql2xextended_error_logging,
3ce8866c
SK		 86 "Option to enable extended error logging,\n"
87 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
88 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
89 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
90 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
91 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
92 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
93 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
94 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
29f9f90c
CD		 95 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
96 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
3ce8866c 97 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
cfb0919c
CD		 98 "\t\t0x1e400000 - Preferred value for capturing essential "
99 "debug information (equivalent to old "
100 "ql2xextended_error_logging=1).\n"
3ce8866c 101 "\t\tDo LOGICAL OR of the value to enable more than one level");
0181944f 102
a9083016 103int ql2xshiftctondsd = 6;
f2019cb1 104module_param(ql2xshiftctondsd, int, S_IRUGO);
a9083016
GM		 105MODULE_PARM_DESC(ql2xshiftctondsd,
106 "Set to control shifting of command type processing "
107 "based on total number of SG elements.");
108
7e47e5ca 109int ql2xfdmienable=1;
de187df8 110module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
a2b3e01d 111module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
cca5335c 112MODULE_PARM_DESC(ql2xfdmienable,
7794a5af
FW		 113 "Enables FDMI registrations. "
114 "0 - no FDMI. Default is 1 - perform FDMI.");
cca5335c 115
d213a4b7 116#define MAX_Q_DEPTH 64
50280c01 117static int ql2xmaxqdepth = MAX_Q_DEPTH;
df7baa50
AV		 118module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
119MODULE_PARM_DESC(ql2xmaxqdepth,
e92e4a8f 120 "Maximum queue depth to set for each LUN. "
d213a4b7 121 "Default is 64.");
df7baa50 122
e84067d7
DG		 123#if (IS_ENABLED(CONFIG_NVME_FC))
124int ql2xenabledif;
125#else
9e522cd8 126int ql2xenabledif = 2;
e84067d7 127#endif
9e522cd8 128module_param(ql2xenabledif, int, S_IRUGO);
bad75002 129MODULE_PARM_DESC(ql2xenabledif,
b97f5d0b
SM		 130 " Enable T10-CRC-DIF:\n"
131 " Default is 2.\n"
132 " 0 -- No DIF Support\n"
133 " 1 -- Enable DIF for all types\n"
134 " 2 -- Enable DIF for all types, except Type 0.\n");
bad75002 135
e84067d7
DG		 136#if (IS_ENABLED(CONFIG_NVME_FC))
137int ql2xnvmeenable = 1;
138#else
139int ql2xnvmeenable;
140#endif
141module_param(ql2xnvmeenable, int, 0644);
142MODULE_PARM_DESC(ql2xnvmeenable,
143 "Enables NVME support. "
144 "0 - no NVMe. Default is Y");
145
8cb2049c 146int ql2xenablehba_err_chk = 2;
bad75002
AE		 147module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
148MODULE_PARM_DESC(ql2xenablehba_err_chk,
8cb2049c 149 " Enable T10-CRC-DIF Error isolation by HBA:\n"
b97f5d0b 150 " Default is 2.\n"
8cb2049c
AE		 151 " 0 -- Error isolation disabled\n"
152 " 1 -- Error isolation enabled only for DIX Type 0\n"
153 " 2 -- Error isolation enabled for all Types\n");
bad75002 154
e5896bd5 155int ql2xiidmaenable=1;
f2019cb1 156module_param(ql2xiidmaenable, int, S_IRUGO);
e5896bd5
AV		 157MODULE_PARM_DESC(ql2xiidmaenable,
158 "Enables iIDMA settings "
159 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
160
d7459527
MH		 161int ql2xmqsupport = 1;
162module_param(ql2xmqsupport, int, S_IRUGO);
163MODULE_PARM_DESC(ql2xmqsupport,
164 "Enable on demand multiple queue pairs support "
165 "Default is 1 for supported. "
166 "Set it to 0 to turn off mq qpair support.");
e337d907
AV		 167
168int ql2xfwloadbin;
86e45bf6 169module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
a2b3e01d 170module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
e337d907 171MODULE_PARM_DESC(ql2xfwloadbin,
7c3df132
SK		 172 "Option to specify location from which to load ISP firmware:.\n"
173 " 2 -- load firmware via the request_firmware() (hotplug).\n"
e337d907
AV		 174 " interface.\n"
175 " 1 -- load firmware from flash.\n"
176 " 0 -- use default semantics.\n");
177
ae97c91e 178int ql2xetsenable;
f2019cb1 179module_param(ql2xetsenable, int, S_IRUGO);
ae97c91e
AV		 180MODULE_PARM_DESC(ql2xetsenable,
181 "Enables firmware ETS burst."
182 "Default is 0 - skip ETS enablement.");
183
6907869d 184int ql2xdbwr = 1;
86e45bf6 185module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
a9083016 186MODULE_PARM_DESC(ql2xdbwr,
08de2844
GM		 187 "Option to specify scheme for request queue posting.\n"
188 " 0 -- Regular doorbell.\n"
189 " 1 -- CAMRAM doorbell (faster).\n");
a9083016 190
f4c496c1 191int ql2xtargetreset = 1;
f2019cb1 192module_param(ql2xtargetreset, int, S_IRUGO);
f4c496c1
GM		 193MODULE_PARM_DESC(ql2xtargetreset,
194 "Enable target reset."
195 "Default is 1 - use hw defaults.");
196
4da26e16 197int ql2xgffidenable;
f2019cb1 198module_param(ql2xgffidenable, int, S_IRUGO);
4da26e16
CD		 199MODULE_PARM_DESC(ql2xgffidenable,
200 "Enables GFF_ID checks of port type. "
201 "Default is 0 - Do not use GFF_ID information.");
a9083016 202
043dc1d7 203int ql2xasynctmfenable = 1;
f2019cb1 204module_param(ql2xasynctmfenable, int, S_IRUGO);
3822263e
MI		 205MODULE_PARM_DESC(ql2xasynctmfenable,
206 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
207 "Default is 0 - Issue TM IOCBs via mailbox mechanism.");
ed0de87c
GM		 208
209int ql2xdontresethba;
86e45bf6 210module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
ed0de87c 211MODULE_PARM_DESC(ql2xdontresethba,
08de2844
GM		 212 "Option to specify reset behaviour.\n"
213 " 0 (Default) -- Reset on failure.\n"
214 " 1 -- Do not reset on failure.\n");
ed0de87c 215
1abf635d
HR		 216uint64_t ql2xmaxlun = MAX_LUNS;
217module_param(ql2xmaxlun, ullong, S_IRUGO);
82515920
AV		 218MODULE_PARM_DESC(ql2xmaxlun,
219 "Defines the maximum LU number to register with the SCSI "
220 "midlayer. Default is 65535.");
221
08de2844
GM		 222int ql2xmdcapmask = 0x1F;
223module_param(ql2xmdcapmask, int, S_IRUGO);
224MODULE_PARM_DESC(ql2xmdcapmask,
225 "Set the Minidump driver capture mask level. "
6e96fa7b 226 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
08de2844 227
3aadff35 228int ql2xmdenable = 1;
08de2844
GM		 229module_param(ql2xmdenable, int, S_IRUGO);
230MODULE_PARM_DESC(ql2xmdenable,
231 "Enable/disable MiniDump. "
3aadff35
GM		 232 "0 - MiniDump disabled. "
233 "1 (Default) - MiniDump enabled.");
08de2844 234
b0d6cabd
HM		 235int ql2xexlogins = 0;
236module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
237MODULE_PARM_DESC(ql2xexlogins,
238 "Number of extended Logins. "
239 "0 (Default)- Disabled.");
240
99e1b683
QT		 241int ql2xexchoffld = 1024;
242module_param(ql2xexchoffld, uint, 0644);
2f56a7f1 243MODULE_PARM_DESC(ql2xexchoffld,
99e1b683
QT		 244 "Number of target exchanges.");
245
246int ql2xiniexchg = 1024;
247module_param(ql2xiniexchg, uint, 0644);
248MODULE_PARM_DESC(ql2xiniexchg,
249 "Number of initiator exchanges.");
2f56a7f1 250
f198cafa
HM		 251int ql2xfwholdabts = 0;
252module_param(ql2xfwholdabts, int, S_IRUGO);
253MODULE_PARM_DESC(ql2xfwholdabts,
254 "Allow FW to hold status IOCB until ABTS rsp received. "
255 "0 (Default) Do not set fw option. "
256 "1 - Set fw option to hold ABTS.");
257
41dc529a
QT		 258int ql2xmvasynctoatio = 1;
259module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
260MODULE_PARM_DESC(ql2xmvasynctoatio,
261 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
262 "0 (Default). Do not move IOCBs"
263 "1 - Move IOCBs.");
264
e4e3a2ce
QT		 265int ql2xautodetectsfp = 1;
266module_param(ql2xautodetectsfp, int, 0444);
267MODULE_PARM_DESC(ql2xautodetectsfp,
268 "Detect SFP range and set appropriate distance.\n"
269 "1 (Default): Enable\n");
270
1da177e4 271/*
fa2a1ce5 272 * SCSI host template entry points
1da177e4
LT		 273 */
274static int qla2xxx_slave_configure(struct scsi_device * device);
f4f051eb 275static int qla2xxx_slave_alloc(struct scsi_device *);
1e99e33a
AV		 276static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
277static void qla2xxx_scan_start(struct Scsi_Host *);
f4f051eb 278static void qla2xxx_slave_destroy(struct scsi_device *);
f281233d 279static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1da177e4
LT		 280static int qla2xxx_eh_abort(struct scsi_cmnd *);
281static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
523ec773 282static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
1da177e4
LT		 283static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
284static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
1da177e4 285
1a2fbf18 286static void qla2x00_clear_drv_active(struct qla_hw_data *);
3491255e 287static void qla2x00_free_device(scsi_qla_host_t *);
2d5a4c34 288static void qla83xx_disable_laser(scsi_qla_host_t *vha);
5601236b 289static int qla2xxx_map_queues(struct Scsi_Host *shost);
e84067d7 290static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
ce7e4af7 291
a5326f86 292struct scsi_host_template qla2xxx_driver_template = {
1da177e4 293 .module = THIS_MODULE,
cb63067a 294 .name = QLA2XXX_DRIVER_NAME,
a5326f86 295 .queuecommand = qla2xxx_queuecommand,
fca29703 296
b6a05c82 297 .eh_timed_out = fc_eh_timed_out,
fca29703
AV		 298 .eh_abort_handler = qla2xxx_eh_abort,
299 .eh_device_reset_handler = qla2xxx_eh_device_reset,
523ec773 300 .eh_target_reset_handler = qla2xxx_eh_target_reset,
fca29703
AV		 301 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
302 .eh_host_reset_handler = qla2xxx_eh_host_reset,
303
304 .slave_configure = qla2xxx_slave_configure,
305
306 .slave_alloc = qla2xxx_slave_alloc,
307 .slave_destroy = qla2xxx_slave_destroy,
ed677086
AV		 308 .scan_finished = qla2xxx_scan_finished,
309 .scan_start = qla2xxx_scan_start,
db5ed4df 310 .change_queue_depth = scsi_change_queue_depth,
5601236b 311 .map_queues = qla2xxx_map_queues,
fca29703
AV		 312 .this_id = -1,
313 .cmd_per_lun = 3,
314 .use_clustering = ENABLE_CLUSTERING,
315 .sg_tablesize = SG_ALL,
316
317 .max_sectors = 0xFFFF,
afb046e2 318 .shost_attrs = qla2x00_host_attrs,
2d70c103
NB		 319
320 .supported_mode = MODE_INITIATOR,
c40ecc12 321 .track_queue_depth = 1,
fca29703
AV		 322};
323
1da177e4 324static struct scsi_transport_template *qla2xxx_transport_template = NULL;
2c3dfe3f 325struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
1da177e4 326
1da177e4
LT		 327/* TODO Convert to inlines
328 *
329 * Timer routines
330 */
1da177e4 331
2c3dfe3f 332__inline__ void
8e5f4ba0 333qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 334{
8e5f4ba0 335 timer_setup(&vha->timer, qla2x00_timer, 0);
e315cd28 336 vha->timer.expires = jiffies + interval * HZ;
e315cd28
AC		 337 add_timer(&vha->timer);
338 vha->timer_active = 1;
1da177e4
LT		 339}
340
341static inline void
e315cd28 342qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
1da177e4 343{
a9083016 344 /* Currently used for 82XX only. */
7c3df132
SK		 345 if (vha->device_flags & DFLG_DEV_FAILED) {
346 ql_dbg(ql_dbg_timer, vha, 0x600d,
347 "Device in a failed state, returning.\n");
a9083016 348 return;
7c3df132 349 }
a9083016 350
e315cd28 351 mod_timer(&vha->timer, jiffies + interval * HZ);
1da177e4
LT		 352}
353
a824ebb3 354static __inline__ void
e315cd28 355qla2x00_stop_timer(scsi_qla_host_t *vha)
1da177e4 356{
e315cd28
AC		 357 del_timer_sync(&vha->timer);
358 vha->timer_active = 0;
1da177e4
LT		 359}
360
1da177e4
LT		 361static int qla2x00_do_dpc(void *data);
362
363static void qla2x00_rst_aen(scsi_qla_host_t *);
364
73208dfd
AC		 365static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
366 struct req_que **, struct rsp_que **);
e30d1756 367static void qla2x00_free_fw_dump(struct qla_hw_data *);
e315cd28 368static void qla2x00_mem_free(struct qla_hw_data *);
d7459527
MH		 369int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
370 struct qla_qpair *qpair);
1da177e4 371
1da177e4 372/* -------------------------------------------------------------------------- */
8abfa9e2
QT		 373static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
374 struct rsp_que *rsp)
375{
376 struct qla_hw_data *ha = vha->hw;
377 rsp->qpair = ha->base_qpair;
378 rsp->req = req;
379 ha->base_qpair->req = req;
380 ha->base_qpair->rsp = rsp;
381 ha->base_qpair->vha = vha;
382 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
383 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
384 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
385 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
cf19c45d 386 INIT_LIST_HEAD(&ha->base_qpair->nvme_done_list);
8abfa9e2
QT		 387 ha->base_qpair->enable_class_2 = ql2xenableclass2;
388 /* init qpair to this cpu. Will adjust at run time. */
389 qla_cpu_update(rsp->qpair, smp_processor_id());
390 ha->base_qpair->pdev = ha->pdev;
391
392 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
393 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
394}
395
9a347ff4
CD		 396static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
397 struct rsp_que *rsp)
73208dfd 398{
7c3df132 399 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2afa19a9 400 ha->req_q_map = kzalloc(sizeof(struct req_que *) * ha->max_req_queues,
73208dfd
AC		 401 GFP_KERNEL);
402 if (!ha->req_q_map) {
7c3df132
SK		 403 ql_log(ql_log_fatal, vha, 0x003b,
404 "Unable to allocate memory for request queue ptrs.\n");
73208dfd
AC		 405 goto fail_req_map;
406 }
407
2afa19a9 408 ha->rsp_q_map = kzalloc(sizeof(struct rsp_que *) * ha->max_rsp_queues,
73208dfd
AC		 409 GFP_KERNEL);
410 if (!ha->rsp_q_map) {
7c3df132
SK		 411 ql_log(ql_log_fatal, vha, 0x003c,
412 "Unable to allocate memory for response queue ptrs.\n");
73208dfd
AC		 413 goto fail_rsp_map;
414 }
d7459527 415
e326d22a
QT		 416 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
417 if (ha->base_qpair == NULL) {
418 ql_log(ql_log_warn, vha, 0x00e0,
419 "Failed to allocate base queue pair memory.\n");
420 goto fail_base_qpair;
421 }
422
8abfa9e2 423 qla_init_base_qpair(vha, req, rsp);
e326d22a 424
d7459527
MH		 425 if (ql2xmqsupport && ha->max_qpairs) {
426 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
427 GFP_KERNEL);
428 if (!ha->queue_pair_map) {
429 ql_log(ql_log_fatal, vha, 0x0180,
430 "Unable to allocate memory for queue pair ptrs.\n");
431 goto fail_qpair_map;
432 }
d7459527
MH		 433 }
434
9a347ff4
CD		 435 /*
436 * Make sure we record at least the request and response queue zero in
437 * case we need to free them if part of the probe fails.
438 */
439 ha->rsp_q_map[0] = rsp;
440 ha->req_q_map[0] = req;
73208dfd
AC		 441 set_bit(0, ha->rsp_qid_map);
442 set_bit(0, ha->req_qid_map);
443 return 1;
444
d7459527 445fail_qpair_map:
82de802a
QT		 446 kfree(ha->base_qpair);
447 ha->base_qpair = NULL;
448fail_base_qpair:
d7459527
MH		 449 kfree(ha->rsp_q_map);
450 ha->rsp_q_map = NULL;
73208dfd
AC		 451fail_rsp_map:
452 kfree(ha->req_q_map);
453 ha->req_q_map = NULL;
454fail_req_map:
455 return -ENOMEM;
456}
457
2afa19a9 458static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
73208dfd 459{
8ae6d9c7
GM		 460 if (IS_QLAFX00(ha)) {
461 if (req && req->ring_fx00)
462 dma_free_coherent(&ha->pdev->dev,
463 (req->length_fx00 + 1) * sizeof(request_t),
464 req->ring_fx00, req->dma_fx00);
465 } else if (req && req->ring)
73208dfd
AC		 466 dma_free_coherent(&ha->pdev->dev,
467 (req->length + 1) * sizeof(request_t),
468 req->ring, req->dma);
469
8d93f550
CD		 470 if (req)
471 kfree(req->outstanding_cmds);
472
73208dfd 473 kfree(req);
73208dfd
AC		 474}
475
2afa19a9
AC		 476static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
477{
8ae6d9c7
GM		 478 if (IS_QLAFX00(ha)) {
479 if (rsp && rsp->ring)
480 dma_free_coherent(&ha->pdev->dev,
481 (rsp->length_fx00 + 1) * sizeof(request_t),
482 rsp->ring_fx00, rsp->dma_fx00);
483 } else if (rsp && rsp->ring) {
2afa19a9
AC		 484 dma_free_coherent(&ha->pdev->dev,
485 (rsp->length + 1) * sizeof(response_t),
486 rsp->ring, rsp->dma);
8ae6d9c7 487 }
2afa19a9 488 kfree(rsp);
2afa19a9
AC		 489}
490
73208dfd
AC		 491static void qla2x00_free_queues(struct qla_hw_data *ha)
492{
493 struct req_que *req;
494 struct rsp_que *rsp;
495 int cnt;
093df737 496 unsigned long flags;
73208dfd 497
82de802a
QT		 498 if (ha->queue_pair_map) {
499 kfree(ha->queue_pair_map);
500 ha->queue_pair_map = NULL;
501 }
502 if (ha->base_qpair) {
503 kfree(ha->base_qpair);
504 ha->base_qpair = NULL;
505 }
506
093df737 507 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 508 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
cb43285f
QT		 509 if (!test_bit(cnt, ha->req_qid_map))
510 continue;
511
73208dfd 512 req = ha->req_q_map[cnt];
093df737
QT		 513 clear_bit(cnt, ha->req_qid_map);
514 ha->req_q_map[cnt] = NULL;
515
516 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 517 qla2x00_free_req_que(ha, req);
093df737 518 spin_lock_irqsave(&ha->hardware_lock, flags);
73208dfd 519 }
093df737
QT		 520 spin_unlock_irqrestore(&ha->hardware_lock, flags);
521
73208dfd
AC		 522 kfree(ha->req_q_map);
523 ha->req_q_map = NULL;
2afa19a9 524
093df737
QT		 525
526 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 527 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
cb43285f
QT		 528 if (!test_bit(cnt, ha->rsp_qid_map))
529 continue;
530
2afa19a9 531 rsp = ha->rsp_q_map[cnt];
c3c42394 532 clear_bit(cnt, ha->rsp_qid_map);
093df737
QT		 533 ha->rsp_q_map[cnt] = NULL;
534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2afa19a9 535 qla2x00_free_rsp_que(ha, rsp);
093df737 536 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 537 }
093df737
QT		 538 spin_unlock_irqrestore(&ha->hardware_lock, flags);
539
2afa19a9
AC		 540 kfree(ha->rsp_q_map);
541 ha->rsp_q_map = NULL;
73208dfd
AC		 542}
543
1da177e4 544static char *
e315cd28 545qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
1da177e4 546{
e315cd28 547 struct qla_hw_data *ha = vha->hw;
1da177e4
LT		 548 static char *pci_bus_modes[] = {
549 "33", "66", "100", "133",
550 };
551 uint16_t pci_bus;
552
553 strcpy(str, "PCI");
554 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
555 if (pci_bus) {
556 strcat(str, "-X (");
557 strcat(str, pci_bus_modes[pci_bus]);
558 } else {
559 pci_bus = (ha->pci_attr & BIT_8) >> 8;
560 strcat(str, " (");
561 strcat(str, pci_bus_modes[pci_bus]);
562 }
563 strcat(str, " MHz)");
564
565 return (str);
566}
567
fca29703 568static char *
e315cd28 569qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
fca29703
AV		 570{
571 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
e315cd28 572 struct qla_hw_data *ha = vha->hw;
fca29703 573 uint32_t pci_bus;
fca29703 574
62a276f8 575 if (pci_is_pcie(ha->pdev)) {
fca29703 576 char lwstr[6];
62a276f8 577 uint32_t lstat, lspeed, lwidth;
fca29703 578
62a276f8
BH		 579 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
580 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
581 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
fca29703
AV		 582
583 strcpy(str, "PCIe (");
49300af7
SK		 584 switch (lspeed) {
585 case 1:
c87a0d8c 586 strcat(str, "2.5GT/s ");
49300af7
SK		 587 break;
588 case 2:
c87a0d8c 589 strcat(str, "5.0GT/s ");
49300af7
SK		 590 break;
591 case 3:
592 strcat(str, "8.0GT/s ");
593 break;
594 default:
fca29703 595 strcat(str, "<unknown> ");
49300af7
SK		 596 break;
597 }
fca29703
AV		 598 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
599 strcat(str, lwstr);
600
601 return str;
602 }
603
604 strcpy(str, "PCI");
605 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
606 if (pci_bus == 0 || pci_bus == 8) {
607 strcat(str, " (");
608 strcat(str, pci_bus_modes[pci_bus >> 3]);
609 } else {
610 strcat(str, "-X ");
611 if (pci_bus & BIT_2)
612 strcat(str, "Mode 2");
613 else
614 strcat(str, "Mode 1");
615 strcat(str, " (");
616 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
617 }
618 strcat(str, " MHz)");
619
620 return str;
621}
622
e5f82ab8 623static char *
df57caba 624qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
1da177e4
LT		 625{
626 char un_str[10];
e315cd28 627 struct qla_hw_data *ha = vha->hw;
fa2a1ce5 628
df57caba
HM		 629 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
630 ha->fw_minor_version, ha->fw_subminor_version);
1da177e4
LT		 631
632 if (ha->fw_attributes & BIT_9) {
633 strcat(str, "FLX");
634 return (str);
635 }
636
637 switch (ha->fw_attributes & 0xFF) {
638 case 0x7:
639 strcat(str, "EF");
640 break;
641 case 0x17:
642 strcat(str, "TP");
643 break;
644 case 0x37:
645 strcat(str, "IP");
646 break;
647 case 0x77:
648 strcat(str, "VI");
649 break;
650 default:
651 sprintf(un_str, "(%x)", ha->fw_attributes);
652 strcat(str, un_str);
653 break;
654 }
655 if (ha->fw_attributes & 0x100)
656 strcat(str, "X");
657
658 return (str);
659}
660
e5f82ab8 661static char *
df57caba 662qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
fca29703 663{
e315cd28 664 struct qla_hw_data *ha = vha->hw;
f0883ac6 665
df57caba 666 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
3a03eb79 667 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
fca29703 668 return str;
fca29703
AV		 669}
670
9ba56b95 671void
25ff6af1 672qla2x00_sp_free_dma(void *ptr)
fca29703 673{
25ff6af1
JC		 674 srb_t *sp = ptr;
675 struct qla_hw_data *ha = sp->vha->hw;
9ba56b95 676 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
9ba56b95 677 void *ctx = GET_CMD_CTX_SP(sp);
fca29703 678
9ba56b95
GM		 679 if (sp->flags & SRB_DMA_VALID) {
680 scsi_dma_unmap(cmd);
681 sp->flags &= ~SRB_DMA_VALID;
7c3df132 682 }
fca29703 683
9ba56b95
GM		 684 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
685 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
686 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
687 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
688 }
689
d5ff0eed
JC		 690 if (!ctx)
691 goto end;
692
9ba56b95
GM		 693 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
694 /* List assured to be having elements */
d5ff0eed 695 qla2x00_clean_dsd_pool(ha, ctx);
9ba56b95
GM		 696 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
697 }
698
699 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 700 struct crc_context *ctx0 = ctx;
701
702 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
9ba56b95
GM		 703 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
704 }
705
706 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 707 struct ct6_dsd *ctx1 = ctx;
fca29703 708
9ba56b95 709 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
d5ff0eed 710 ctx1->fcp_cmnd_dma);
9ba56b95
GM		 711 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
712 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
713 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
714 mempool_free(ctx1, ha->ctx_mempool);
9ba56b95
GM		 715 }
716
d5ff0eed 717end:
6fcd98fd 718 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
7401bc18
DG		 719 CMD_SP(cmd) = NULL;
720 qla2x00_rel_sp(sp);
721 }
9ba56b95
GM		 722}
723
d7459527 724void
25ff6af1 725qla2x00_sp_compl(void *ptr, int res)
9ba56b95 726{
25ff6af1 727 srb_t *sp = ptr;
9ba56b95
GM		 728 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
729
730 cmd->result = res;
731
732 if (atomic_read(&sp->ref_count) == 0) {
25ff6af1 733 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
9ba56b95
GM		 734 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
735 sp, GET_CMD_SP(sp));
736 if (ql2xextended_error_logging & ql_dbg_io)
8fbdac8c 737 WARN_ON(atomic_read(&sp->ref_count) == 0);
9ba56b95
GM		 738 return;
739 }
740 if (!atomic_dec_and_test(&sp->ref_count))
741 return;
742
f3caa990 743 sp->free(sp);
9ba56b95 744 cmd->scsi_done(cmd);
fca29703
AV		 745}
746
d7459527 747void
25ff6af1 748qla2xxx_qpair_sp_free_dma(void *ptr)
d7459527
MH		 749{
750 srb_t *sp = (srb_t *)ptr;
751 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
752 struct qla_hw_data *ha = sp->fcport->vha->hw;
753 void *ctx = GET_CMD_CTX_SP(sp);
754
755 if (sp->flags & SRB_DMA_VALID) {
756 scsi_dma_unmap(cmd);
757 sp->flags &= ~SRB_DMA_VALID;
758 }
759
760 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
761 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
762 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
763 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
764 }
765
d5ff0eed
JC		 766 if (!ctx)
767 goto end;
768
d7459527
MH		 769 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
770 /* List assured to be having elements */
d5ff0eed 771 qla2x00_clean_dsd_pool(ha, ctx);
d7459527
MH		 772 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
773 }
774
775 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
d5ff0eed
JC		 776 struct crc_context *ctx0 = ctx;
777
778 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
d7459527
MH		 779 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
780 }
781
782 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
d5ff0eed 783 struct ct6_dsd *ctx1 = ctx;
d7459527
MH		 784 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
785 ctx1->fcp_cmnd_dma);
786 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
787 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
788 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
789 mempool_free(ctx1, ha->ctx_mempool);
790 }
d5ff0eed 791end:
d7459527
MH		 792 CMD_SP(cmd) = NULL;
793 qla2xxx_rel_qpair_sp(sp->qpair, sp);
794}
795
796void
25ff6af1 797qla2xxx_qpair_sp_compl(void *ptr, int res)
d7459527 798{
25ff6af1 799 srb_t *sp = ptr;
d7459527
MH		 800 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
801
802 cmd->result = res;
803
804 if (atomic_read(&sp->ref_count) == 0) {
805 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
806 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
807 sp, GET_CMD_SP(sp));
808 if (ql2xextended_error_logging & ql_dbg_io)
809 WARN_ON(atomic_read(&sp->ref_count) == 0);
810 return;
811 }
812 if (!atomic_dec_and_test(&sp->ref_count))
813 return;
814
f3caa990 815 sp->free(sp);
d7459527
MH		 816 cmd->scsi_done(cmd);
817}
818
8ae6d9c7
GM		 819/* If we are SP1 here, we need to still take and release the host_lock as SP1
820 * does not have the changes necessary to avoid taking host->host_lock.
821 */
1da177e4 822static int
f5e3e40b 823qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
fca29703 824{
134ae078 825 scsi_qla_host_t *vha = shost_priv(host);
fca29703 826 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
19a7b4ae 827 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
e315cd28
AC		 828 struct qla_hw_data *ha = vha->hw;
829 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
fca29703
AV		 830 srb_t *sp;
831 int rval;
5601236b
MH		 832 struct qla_qpair *qpair = NULL;
833 uint32_t tag;
834 uint16_t hwq;
fca29703 835
04dfaa53
MFO		 836 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
837 cmd->result = DID_NO_CONNECT << 16;
838 goto qc24_fail_command;
839 }
840
5601236b
MH		 841 if (ha->mqenable) {
842 if (shost_use_blk_mq(vha->host)) {
843 tag = blk_mq_unique_tag(cmd->request);
844 hwq = blk_mq_unique_tag_to_hwq(tag);
845 qpair = ha->queue_pair_map[hwq];
846 } else if (vha->vp_idx && vha->qpair) {
847 qpair = vha->qpair;
848 }
849
850 if (qpair)
851 return qla2xxx_mqueuecommand(host, cmd, qpair);
d7459527
MH		 852 }
853
85880801 854 if (ha->flags.eeh_busy) {
7c3df132 855 if (ha->flags.pci_channel_io_perm_failure) {
5f28d2d7 856 ql_dbg(ql_dbg_aer, vha, 0x9010,
7c3df132
SK		 857 "PCI Channel IO permanent failure, exiting "
858 "cmd=%p.\n", cmd);
b9b12f73 859 cmd->result = DID_NO_CONNECT << 16;
7c3df132 860 } else {
5f28d2d7 861 ql_dbg(ql_dbg_aer, vha, 0x9011,
7c3df132 862 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
85880801 863 cmd->result = DID_REQUEUE << 16;
7c3df132 864 }
14e660e6
SJ		 865 goto qc24_fail_command;
866 }
867
19a7b4ae
JSEC		 868 rval = fc_remote_port_chkready(rport);
869 if (rval) {
870 cmd->result = rval;
5f28d2d7 871 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
7c3df132
SK		 872 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
873 cmd, rval);
fca29703
AV		 874 goto qc24_fail_command;
875 }
876
bad75002
AE		 877 if (!vha->flags.difdix_supported &&
878 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
7c3df132
SK		 879 ql_dbg(ql_dbg_io, vha, 0x3004,
880 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
881 cmd);
bad75002
AE		 882 cmd->result = DID_NO_CONNECT << 16;
883 goto qc24_fail_command;
884 }
aa651be8
CD		 885
886 if (!fcport) {
887 cmd->result = DID_NO_CONNECT << 16;
888 goto qc24_fail_command;
889 }
890
fca29703
AV		 891 if (atomic_read(&fcport->state) != FCS_ONLINE) {
892 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
38170fa8 893 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
7c3df132
SK		 894 ql_dbg(ql_dbg_io, vha, 0x3005,
895 "Returning DNC, fcport_state=%d loop_state=%d.\n",
896 atomic_read(&fcport->state),
897 atomic_read(&base_vha->loop_state));
fca29703
AV		 898 cmd->result = DID_NO_CONNECT << 16;
899 goto qc24_fail_command;
900 }
7b594131 901 goto qc24_target_busy;
fca29703
AV		 902 }
903
e05fe292
CD		 904 /*
905 * Return target busy if we've received a non-zero retry_delay_timer
906 * in a FCP_RSP.
907 */
975f7d46
BP		 908 if (fcport->retry_delay_timestamp == 0) {
909 /* retry delay not set */
910 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
e05fe292
CD		 911 fcport->retry_delay_timestamp = 0;
912 else
913 goto qc24_target_busy;
914
b00ee7d7 915 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
50280c01 916 if (!sp)
f5e3e40b 917 goto qc24_host_busy;
fca29703 918
9ba56b95
GM		 919 sp->u.scmd.cmd = cmd;
920 sp->type = SRB_SCSI_CMD;
921 atomic_set(&sp->ref_count, 1);
922 CMD_SP(cmd) = (void *)sp;
923 sp->free = qla2x00_sp_free_dma;
924 sp->done = qla2x00_sp_compl;
925
e315cd28 926 rval = ha->isp_ops->start_scsi(sp);
7c3df132 927 if (rval != QLA_SUCCESS) {
53016ed3 928 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
7c3df132 929 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
fca29703 930 goto qc24_host_busy_free_sp;
7c3df132 931 }
fca29703 932
fca29703
AV		 933 return 0;
934
935qc24_host_busy_free_sp:
f3caa990 936 sp->free(sp);
fca29703 937
f5e3e40b 938qc24_host_busy:
fca29703
AV		 939 return SCSI_MLQUEUE_HOST_BUSY;
940
7b594131
MC		 941qc24_target_busy:
942 return SCSI_MLQUEUE_TARGET_BUSY;
943
fca29703 944qc24_fail_command:
f5e3e40b 945 cmd->scsi_done(cmd);
fca29703
AV		 946
947 return 0;
948}
949
d7459527
MH		 950/* For MQ supported I/O */
951int
952qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
953 struct qla_qpair *qpair)
954{
955 scsi_qla_host_t *vha = shost_priv(host);
956 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
957 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
958 struct qla_hw_data *ha = vha->hw;
959 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
960 srb_t *sp;
961 int rval;
962
963 rval = fc_remote_port_chkready(rport);
964 if (rval) {
965 cmd->result = rval;
966 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
967 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
968 cmd, rval);
969 goto qc24_fail_command;
970 }
971
972 if (!fcport) {
973 cmd->result = DID_NO_CONNECT << 16;
974 goto qc24_fail_command;
975 }
976
977 if (atomic_read(&fcport->state) != FCS_ONLINE) {
978 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
979 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
980 ql_dbg(ql_dbg_io, vha, 0x3077,
981 "Returning DNC, fcport_state=%d loop_state=%d.\n",
982 atomic_read(&fcport->state),
983 atomic_read(&base_vha->loop_state));
984 cmd->result = DID_NO_CONNECT << 16;
985 goto qc24_fail_command;
986 }
987 goto qc24_target_busy;
988 }
989
990 /*
991 * Return target busy if we've received a non-zero retry_delay_timer
992 * in a FCP_RSP.
993 */
994 if (fcport->retry_delay_timestamp == 0) {
995 /* retry delay not set */
996 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
997 fcport->retry_delay_timestamp = 0;
998 else
999 goto qc24_target_busy;
1000
1001 sp = qla2xxx_get_qpair_sp(qpair, fcport, GFP_ATOMIC);
1002 if (!sp)
1003 goto qc24_host_busy;
1004
1005 sp->u.scmd.cmd = cmd;
1006 sp->type = SRB_SCSI_CMD;
1007 atomic_set(&sp->ref_count, 1);
1008 CMD_SP(cmd) = (void *)sp;
1009 sp->free = qla2xxx_qpair_sp_free_dma;
1010 sp->done = qla2xxx_qpair_sp_compl;
1011 sp->qpair = qpair;
1012
1013 rval = ha->isp_ops->start_scsi_mq(sp);
1014 if (rval != QLA_SUCCESS) {
1015 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1016 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1017 if (rval == QLA_INTERFACE_ERROR)
1018 goto qc24_fail_command;
1019 goto qc24_host_busy_free_sp;
1020 }
1021
1022 return 0;
1023
1024qc24_host_busy_free_sp:
f3caa990 1025 sp->free(sp);
d7459527
MH		 1026
1027qc24_host_busy:
1028 return SCSI_MLQUEUE_HOST_BUSY;
1029
1030qc24_target_busy:
1031 return SCSI_MLQUEUE_TARGET_BUSY;
1032
1033qc24_fail_command:
1034 cmd->scsi_done(cmd);
1035
1036 return 0;
1037}
1038
1da177e4
LT		 1039/*
1040 * qla2x00_eh_wait_on_command
1041 * Waits for the command to be returned by the Firmware for some
1042 * max time.
1043 *
1044 * Input:
1da177e4 1045 * cmd = Scsi Command to wait on.
1da177e4
LT		 1046 *
1047 * Return:
1048 * Not Found : 0
1049 * Found : 1
1050 */
1051static int
e315cd28 1052qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1da177e4 1053{
fe74c71f 1054#define ABORT_POLLING_PERIOD 1000
478c3b03 1055#define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
f4f051eb 1056 unsigned long wait_iter = ABORT_WAIT_ITER;
85880801
AV		 1057 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1058 struct qla_hw_data *ha = vha->hw;
f4f051eb 1059 int ret = QLA_SUCCESS;
1da177e4 1060
85880801 1061 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
7c3df132
SK		 1062 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1063 "Return:eh_wait.\n");
85880801
AV		 1064 return ret;
1065 }
1066
d970432c 1067 while (CMD_SP(cmd) && wait_iter--) {
fe74c71f 1068 msleep(ABORT_POLLING_PERIOD);
f4f051eb
AV		 1069 }
1070 if (CMD_SP(cmd))
1071 ret = QLA_FUNCTION_FAILED;
1da177e4 1072
f4f051eb 1073 return ret;
1da177e4
LT		 1074}
1075
1076/*
1077 * qla2x00_wait_for_hba_online
fa2a1ce5 1078 * Wait till the HBA is online after going through
1da177e4
LT		 1079 * <= MAX_RETRIES_OF_ISP_ABORT or
1080 * finally HBA is disabled ie marked offline
1081 *
1082 * Input:
1083 * ha - pointer to host adapter structure
fa2a1ce5
AV		 1084 *
1085 * Note:
1da177e4
LT		 1086 * Does context switching-Release SPIN_LOCK
1087 * (if any) before calling this routine.
1088 *
1089 * Return:
1090 * Success (Adapter is online) : 0
1091 * Failed (Adapter is offline/disabled) : 1
1092 */
854165f4 1093int
e315cd28 1094qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1da177e4 1095{
fca29703
AV		 1096 int return_status;
1097 unsigned long wait_online;
e315cd28
AC		 1098 struct qla_hw_data *ha = vha->hw;
1099 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1100
fa2a1ce5 1101 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
e315cd28
AC		 1102 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1103 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1104 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1105 ha->dpc_active) && time_before(jiffies, wait_online)) {
1da177e4
LT		 1106
1107 msleep(1000);
1108 }
e315cd28 1109 if (base_vha->flags.online)
fa2a1ce5 1110 return_status = QLA_SUCCESS;
1da177e4
LT		 1111 else
1112 return_status = QLA_FUNCTION_FAILED;
1113
1da177e4
LT		 1114 return (return_status);
1115}
1116
726b8548
QT		 1117static inline int test_fcport_count(scsi_qla_host_t *vha)
1118{
1119 struct qla_hw_data *ha = vha->hw;
1120 unsigned long flags;
1121 int res;
1122
1123 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
83548fe2
QT		 1124 ql_dbg(ql_dbg_init, vha, 0x00ec,
1125 "tgt %p, fcport_count=%d\n",
1126 vha, vha->fcport_count);
726b8548
QT		 1127 res = (vha->fcport_count == 0);
1128 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1129
1130 return res;
1131}
1132
1133/*
1134 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1135 * it has dependency on UNLOADING flag to stop device discovery
1136 */
1137static void
1138qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1139{
1140 qla2x00_mark_all_devices_lost(vha, 0);
1141
b85e0957 1142 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
726b8548
QT		 1143}
1144
86fbee86 1145/*
638a1a01
SC		 1146 * qla2x00_wait_for_hba_ready
1147 * Wait till the HBA is ready before doing driver unload
86fbee86
LC		 1148 *
1149 * Input:
1150 * ha - pointer to host adapter structure
1151 *
1152 * Note:
1153 * Does context switching-Release SPIN_LOCK
1154 * (if any) before calling this routine.
1155 *
86fbee86 1156 */
638a1a01
SC		 1157static void
1158qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
86fbee86 1159{
86fbee86 1160 struct qla_hw_data *ha = vha->hw;
783e0dc4 1161 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
86fbee86 1162
1d483901
DC		 1163 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1164 ha->flags.mbox_busy) ||
1165 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1166 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1167 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1168 break;
86fbee86 1169 msleep(1000);
783e0dc4 1170 }
86fbee86
LC		 1171}
1172
2533cf67
LC		 1173int
1174qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1175{
1176 int return_status;
1177 unsigned long wait_reset;
1178 struct qla_hw_data *ha = vha->hw;
1179 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1180
1181 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1182 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1183 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1184 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1185 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1186
1187 msleep(1000);
1188
1189 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1190 ha->flags.chip_reset_done)
1191 break;
1192 }
1193 if (ha->flags.chip_reset_done)
1194 return_status = QLA_SUCCESS;
1195 else
1196 return_status = QLA_FUNCTION_FAILED;
1197
1198 return return_status;
1199}
1200
083a469d
GM		 1201static void
1202sp_get(struct srb *sp)
1203{
1204 atomic_inc(&sp->ref_count);
1205}
1206
a465537a
SC		 1207#define ISP_REG_DISCONNECT 0xffffffffU
1208/**************************************************************************
1209* qla2x00_isp_reg_stat
1210*
1211* Description:
1212* Read the host status register of ISP before aborting the command.
1213*
1214* Input:
1215* ha = pointer to host adapter structure.
1216*
1217*
1218* Returns:
1219* Either true or false.
1220*
1221* Note: Return true if there is register disconnect.
1222**************************************************************************/
1223static inline
1224uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1225{
1226 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
bf6061b1 1227 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
a465537a 1228
bf6061b1
SC		 1229 if (IS_P3P_TYPE(ha))
1230 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1231 else
1232 return ((RD_REG_DWORD(&reg->host_status)) ==
1233 ISP_REG_DISCONNECT);
a465537a
SC		 1234}
1235
1da177e4
LT		 1236/**************************************************************************
1237* qla2xxx_eh_abort
1238*
1239* Description:
1240* The abort function will abort the specified command.
1241*
1242* Input:
1243* cmd = Linux SCSI command packet to be aborted.
1244*
1245* Returns:
1246* Either SUCCESS or FAILED.
1247*
1248* Note:
2ea00202 1249* Only return FAILED if command not returned by firmware.
1da177e4 1250**************************************************************************/
e5f82ab8 1251static int
1da177e4
LT		 1252qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1253{
e315cd28 1254 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
f4f051eb 1255 srb_t *sp;
4e98d3b8 1256 int ret;
9cb78c16
HR		 1257 unsigned int id;
1258 uint64_t lun;
18e144d3 1259 unsigned long flags;
f934c9d0 1260 int rval, wait = 0;
e315cd28 1261 struct qla_hw_data *ha = vha->hw;
1da177e4 1262
a465537a
SC		 1263 if (qla2x00_isp_reg_stat(ha)) {
1264 ql_log(ql_log_info, vha, 0x8042,
1265 "PCI/Register disconnect, exiting.\n");
1266 return FAILED;
1267 }
f4f051eb 1268 if (!CMD_SP(cmd))
2ea00202 1269 return SUCCESS;
1da177e4 1270
4e98d3b8
AV		 1271 ret = fc_block_scsi_eh(cmd);
1272 if (ret != 0)
1273 return ret;
1274 ret = SUCCESS;
1275
f4f051eb
AV		 1276 id = cmd->device->id;
1277 lun = cmd->device->lun;
1da177e4 1278
e315cd28 1279 spin_lock_irqsave(&ha->hardware_lock, flags);
170babc3
MC		 1280 sp = (srb_t *) CMD_SP(cmd);
1281 if (!sp) {
1282 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1283 return SUCCESS;
1284 }
1da177e4 1285
7c3df132 1286 ql_dbg(ql_dbg_taskm, vha, 0x8002,
c7bc4cae
CD		 1287 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1288 vha->host_no, id, lun, sp, cmd, sp->handle);
17d98630 1289
170babc3
MC		 1290 /* Get a reference to the sp and drop the lock.*/
1291 sp_get(sp);
083a469d 1292
e315cd28 1293 spin_unlock_irqrestore(&ha->hardware_lock, flags);
f934c9d0
CD		 1294 rval = ha->isp_ops->abort_command(sp);
1295 if (rval) {
96219424 1296 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
f934c9d0 1297 ret = SUCCESS;
96219424 1298 else
f934c9d0
CD		 1299 ret = FAILED;
1300
7c3df132 1301 ql_dbg(ql_dbg_taskm, vha, 0x8003,
f934c9d0 1302 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
170babc3 1303 } else {
7c3df132 1304 ql_dbg(ql_dbg_taskm, vha, 0x8004,
cfb0919c 1305 "Abort command mbx success cmd=%p.\n", cmd);
170babc3
MC		 1306 wait = 1;
1307 }
75942064
SK		 1308
1309 spin_lock_irqsave(&ha->hardware_lock, flags);
25ff6af1 1310 sp->done(sp, 0);
75942064 1311 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1da177e4 1312
bc91ade9
CD		 1313 /* Did the command return during mailbox execution? */
1314 if (ret == FAILED && !CMD_SP(cmd))
1315 ret = SUCCESS;
1316
f4f051eb 1317 /* Wait for the command to be returned. */
2ea00202 1318 if (wait) {
e315cd28 1319 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
7c3df132 1320 ql_log(ql_log_warn, vha, 0x8006,
cfb0919c 1321 "Abort handler timed out cmd=%p.\n", cmd);
2ea00202 1322 ret = FAILED;
f4f051eb 1323 }
1da177e4 1324 }
1da177e4 1325
7c3df132 1326 ql_log(ql_log_info, vha, 0x801c,
9cb78c16 1327 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
cfb0919c 1328 vha->host_no, id, lun, wait, ret);
1da177e4 1329
f4f051eb
AV		 1330 return ret;
1331}
1da177e4 1332
4d78c973 1333int
e315cd28 1334qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
9cb78c16 1335 uint64_t l, enum nexus_wait_type type)
f4f051eb 1336{
17d98630 1337 int cnt, match, status;
18e144d3 1338 unsigned long flags;
e315cd28 1339 struct qla_hw_data *ha = vha->hw;
73208dfd 1340 struct req_que *req;
4d78c973 1341 srb_t *sp;
9ba56b95 1342 struct scsi_cmnd *cmd;
1da177e4 1343
523ec773 1344 status = QLA_SUCCESS;
17d98630 1345
e315cd28 1346 spin_lock_irqsave(&ha->hardware_lock, flags);
67c2e93a 1347 req = vha->req;
17d98630 1348 for (cnt = 1; status == QLA_SUCCESS &&
8d93f550 1349 cnt < req->num_outstanding_cmds; cnt++) {
17d98630
AC		 1350 sp = req->outstanding_cmds[cnt];
1351 if (!sp)
523ec773 1352 continue;
9ba56b95 1353 if (sp->type != SRB_SCSI_CMD)
cf53b069 1354 continue;
25ff6af1 1355 if (vha->vp_idx != sp->vha->vp_idx)
17d98630
AC		 1356 continue;
1357 match = 0;
9ba56b95 1358 cmd = GET_CMD_SP(sp);
17d98630
AC		 1359 switch (type) {
1360 case WAIT_HOST:
1361 match = 1;
1362 break;
1363 case WAIT_TARGET:
9ba56b95 1364 match = cmd->device->id == t;
17d98630
AC		 1365 break;
1366 case WAIT_LUN:
9ba56b95
GM		 1367 match = (cmd->device->id == t &&
1368 cmd->device->lun == l);
17d98630 1369 break;
73208dfd 1370 }
17d98630
AC		 1371 if (!match)
1372 continue;
1373
1374 spin_unlock_irqrestore(&ha->hardware_lock, flags);
9ba56b95 1375 status = qla2x00_eh_wait_on_command(cmd);
17d98630 1376 spin_lock_irqsave(&ha->hardware_lock, flags);
1da177e4 1377 }
e315cd28 1378 spin_unlock_irqrestore(&ha->hardware_lock, flags);
523ec773
AV		 1379
1380 return status;
1da177e4
LT		 1381}
1382
523ec773
AV		 1383static char *reset_errors[] = {
1384 "HBA not online",
1385 "HBA not ready",
1386 "Task management failed",
1387 "Waiting for command completions",
1388};
1da177e4 1389
e5f82ab8 1390static int
523ec773 1391__qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
9cb78c16 1392 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1da177e4 1393{
e315cd28 1394 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1395 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
523ec773 1396 int err;
1da177e4 1397
7c3df132 1398 if (!fcport) {
523ec773 1399 return FAILED;
7c3df132 1400 }
1da177e4 1401
4e98d3b8
AV		 1402 err = fc_block_scsi_eh(cmd);
1403 if (err != 0)
1404 return err;
1405
7c3df132 1406 ql_log(ql_log_info, vha, 0x8009,
9cb78c16 1407 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
7c3df132 1408 cmd->device->id, cmd->device->lun, cmd);
1da177e4 1409
523ec773 1410 err = 0;
7c3df132
SK		 1411 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1412 ql_log(ql_log_warn, vha, 0x800a,
1413 "Wait for hba online failed for cmd=%p.\n", cmd);
523ec773 1414 goto eh_reset_failed;
7c3df132 1415 }
523ec773 1416 err = 2;
2afa19a9 1417 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
7c3df132
SK		 1418 != QLA_SUCCESS) {
1419 ql_log(ql_log_warn, vha, 0x800c,
1420 "do_reset failed for cmd=%p.\n", cmd);
523ec773 1421 goto eh_reset_failed;
7c3df132 1422 }
523ec773 1423 err = 3;
e315cd28 1424 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
7c3df132
SK		 1425 cmd->device->lun, type) != QLA_SUCCESS) {
1426 ql_log(ql_log_warn, vha, 0x800d,
d6a03581 1427 "wait for pending cmds failed for cmd=%p.\n", cmd);
523ec773 1428 goto eh_reset_failed;
7c3df132 1429 }
523ec773 1430
7c3df132 1431 ql_log(ql_log_info, vha, 0x800e,
9cb78c16 1432 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
cfb0919c 1433 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
523ec773
AV		 1434
1435 return SUCCESS;
1436
4d78c973 1437eh_reset_failed:
7c3df132 1438 ql_log(ql_log_info, vha, 0x800f,
9cb78c16 1439 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
cfb0919c
CD		 1440 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1441 cmd);
523ec773
AV		 1442 return FAILED;
1443}
1da177e4 1444
523ec773
AV		 1445static int
1446qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1447{
e315cd28
AC		 1448 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1449 struct qla_hw_data *ha = vha->hw;
1da177e4 1450
a465537a
SC		 1451 if (qla2x00_isp_reg_stat(ha)) {
1452 ql_log(ql_log_info, vha, 0x803e,
1453 "PCI/Register disconnect, exiting.\n");
1454 return FAILED;
1455 }
1456
523ec773
AV		 1457 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1458 ha->isp_ops->lun_reset);
1da177e4
LT		 1459}
1460
1da177e4 1461static int
523ec773 1462qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1da177e4 1463{
e315cd28
AC		 1464 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1465 struct qla_hw_data *ha = vha->hw;
1da177e4 1466
a465537a
SC		 1467 if (qla2x00_isp_reg_stat(ha)) {
1468 ql_log(ql_log_info, vha, 0x803f,
1469 "PCI/Register disconnect, exiting.\n");
1470 return FAILED;
1471 }
1472
523ec773
AV		 1473 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1474 ha->isp_ops->target_reset);
1da177e4
LT		 1475}
1476
1da177e4
LT		 1477/**************************************************************************
1478* qla2xxx_eh_bus_reset
1479*
1480* Description:
1481* The bus reset function will reset the bus and abort any executing
1482* commands.
1483*
1484* Input:
1485* cmd = Linux SCSI command packet of the command that cause the
1486* bus reset.
1487*
1488* Returns:
1489* SUCCESS/FAILURE (defined as macro in scsi.h).
1490*
1491**************************************************************************/
e5f82ab8 1492static int
1da177e4
LT		 1493qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1494{
e315cd28 1495 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
bdf79621 1496 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
2c3dfe3f 1497 int ret = FAILED;
9cb78c16
HR		 1498 unsigned int id;
1499 uint64_t lun;
a465537a
SC		 1500 struct qla_hw_data *ha = vha->hw;
1501
1502 if (qla2x00_isp_reg_stat(ha)) {
1503 ql_log(ql_log_info, vha, 0x8040,
1504 "PCI/Register disconnect, exiting.\n");
1505 return FAILED;
1506 }
f4f051eb 1507
f4f051eb
AV		 1508 id = cmd->device->id;
1509 lun = cmd->device->lun;
1da177e4 1510
7c3df132 1511 if (!fcport) {
f4f051eb 1512 return ret;
7c3df132 1513 }
1da177e4 1514
4e98d3b8
AV		 1515 ret = fc_block_scsi_eh(cmd);
1516 if (ret != 0)
1517 return ret;
1518 ret = FAILED;
1519
7c3df132 1520 ql_log(ql_log_info, vha, 0x8012,
9cb78c16 1521 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1522
e315cd28 1523 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
7c3df132
SK		 1524 ql_log(ql_log_fatal, vha, 0x8013,
1525 "Wait for hba online failed board disabled.\n");
f4f051eb 1526 goto eh_bus_reset_done;
1da177e4
LT		 1527 }
1528
ad537689
SK		 1529 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1530 ret = SUCCESS;
1531
f4f051eb
AV		 1532 if (ret == FAILED)
1533 goto eh_bus_reset_done;
1da177e4 1534
9a41a62b 1535 /* Flush outstanding commands. */
4d78c973 1536 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
7c3df132
SK		 1537 QLA_SUCCESS) {
1538 ql_log(ql_log_warn, vha, 0x8014,
1539 "Wait for pending commands failed.\n");
9a41a62b 1540 ret = FAILED;
7c3df132 1541 }
1da177e4 1542
f4f051eb 1543eh_bus_reset_done:
7c3df132 1544 ql_log(ql_log_warn, vha, 0x802b,
9cb78c16 1545 "BUS RESET %s nexus=%ld:%d:%llu.\n",
d6a03581 1546 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1547
f4f051eb 1548 return ret;
1da177e4
LT		 1549}
1550
1551/**************************************************************************
1552* qla2xxx_eh_host_reset
1553*
1554* Description:
1555* The reset function will reset the Adapter.
1556*
1557* Input:
1558* cmd = Linux SCSI command packet of the command that cause the
1559* adapter reset.
1560*
1561* Returns:
1562* Either SUCCESS or FAILED.
1563*
1564* Note:
1565**************************************************************************/
e5f82ab8 1566static int
1da177e4
LT		 1567qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1568{
e315cd28 1569 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
e315cd28 1570 struct qla_hw_data *ha = vha->hw;
2c3dfe3f 1571 int ret = FAILED;
9cb78c16
HR		 1572 unsigned int id;
1573 uint64_t lun;
e315cd28 1574 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1da177e4 1575
a465537a
SC		 1576 if (qla2x00_isp_reg_stat(ha)) {
1577 ql_log(ql_log_info, vha, 0x8041,
1578 "PCI/Register disconnect, exiting.\n");
1579 schedule_work(&ha->board_disable);
1580 return SUCCESS;
1581 }
1582
f4f051eb
AV		 1583 id = cmd->device->id;
1584 lun = cmd->device->lun;
f4f051eb 1585
7c3df132 1586 ql_log(ql_log_info, vha, 0x8018,
9cb78c16 1587 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1da177e4 1588
63ee7072
CD		 1589 /*
1590 * No point in issuing another reset if one is active. Also do not
1591 * attempt a reset if we are updating flash.
1592 */
1593 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
f4f051eb 1594 goto eh_host_reset_lock;
1da177e4 1595
e315cd28
AC		 1596 if (vha != base_vha) {
1597 if (qla2x00_vp_abort_isp(vha))
f4f051eb 1598 goto eh_host_reset_lock;
e315cd28 1599 } else {
7ec0effd 1600 if (IS_P3P_TYPE(vha->hw)) {
a9083016
GM		 1601 if (!qla82xx_fcoe_ctx_reset(vha)) {
1602 /* Ctx reset success */
1603 ret = SUCCESS;
1604 goto eh_host_reset_lock;
1605 }
1606 /* fall thru if ctx reset failed */
1607 }
68ca949c
AC		 1608 if (ha->wq)
1609 flush_workqueue(ha->wq);
1610
e315cd28 1611 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 1612 if (ha->isp_ops->abort_isp(base_vha)) {
e315cd28
AC		 1613 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1614 /* failed. schedule dpc to try */
1615 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1616
7c3df132
SK		 1617 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1618 ql_log(ql_log_warn, vha, 0x802a,
1619 "wait for hba online failed.\n");
e315cd28 1620 goto eh_host_reset_lock;
7c3df132 1621 }
e315cd28
AC		 1622 }
1623 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
fa2a1ce5 1624 }
1da177e4 1625
e315cd28 1626 /* Waiting for command to be returned to OS.*/
4d78c973 1627 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
e315cd28 1628 QLA_SUCCESS)
f4f051eb 1629 ret = SUCCESS;
1da177e4 1630
f4f051eb 1631eh_host_reset_lock:
cfb0919c 1632 ql_log(ql_log_info, vha, 0x8017,
9cb78c16 1633 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
cfb0919c 1634 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1da177e4 1635
f4f051eb
AV		 1636 return ret;
1637}
1da177e4
LT		 1638
1639/*
1640* qla2x00_loop_reset
1641* Issue loop reset.
1642*
1643* Input:
1644* ha = adapter block pointer.
1645*
1646* Returns:
1647* 0 = success
1648*/
a4722cf2 1649int
e315cd28 1650qla2x00_loop_reset(scsi_qla_host_t *vha)
1da177e4 1651{
0c8c39af 1652 int ret;
bdf79621 1653 struct fc_port *fcport;
e315cd28 1654 struct qla_hw_data *ha = vha->hw;
1da177e4 1655
5854771e
AB		 1656 if (IS_QLAFX00(ha)) {
1657 return qlafx00_loop_reset(vha);
1658 }
1659
f4c496c1 1660 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
55e5ed27
AV		 1661 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1662 if (fcport->port_type != FCT_TARGET)
1663 continue;
1664
1665 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1666 if (ret != QLA_SUCCESS) {
7c3df132 1667 ql_dbg(ql_dbg_taskm, vha, 0x802c,
5854771e 1668 "Bus Reset failed: Reset=%d "
7c3df132 1669 "d_id=%x.\n", ret, fcport->d_id.b24);
55e5ed27
AV		 1670 }
1671 }
1672 }
1673
8ae6d9c7 1674
6246b8a1 1675 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
0b7e7c53
AV		 1676 atomic_set(&vha->loop_state, LOOP_DOWN);
1677 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1678 qla2x00_mark_all_devices_lost(vha, 0);
e315cd28 1679 ret = qla2x00_full_login_lip(vha);
0c8c39af 1680 if (ret != QLA_SUCCESS) {
7c3df132
SK		 1681 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1682 "full_login_lip=%d.\n", ret);
749af3d5 1683 }
0c8c39af
AV		 1684 }
1685
0d6e61bc 1686 if (ha->flags.enable_lip_reset) {
e315cd28 1687 ret = qla2x00_lip_reset(vha);
ad537689 1688 if (ret != QLA_SUCCESS)
7c3df132
SK		 1689 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1690 "lip_reset failed (%d).\n", ret);
1da177e4
LT		 1691 }
1692
1da177e4 1693 /* Issue marker command only when we are going to start the I/O */
e315cd28 1694 vha->marker_needed = 1;
1da177e4 1695
0c8c39af 1696 return QLA_SUCCESS;
1da177e4
LT		 1697}
1698
df4bf0bb 1699void
e315cd28 1700qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
df4bf0bb 1701{
4cd3b6eb 1702 int que, cnt, status;
df4bf0bb
AV		 1703 unsigned long flags;
1704 srb_t *sp;
e315cd28 1705 struct qla_hw_data *ha = vha->hw;
73208dfd 1706 struct req_que *req;
c5419e26
QT		 1707 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1708 struct qla_tgt_cmd *cmd;
1709 uint8_t trace = 0;
c0cb4496 1710
df4bf0bb 1711 spin_lock_irqsave(&ha->hardware_lock, flags);
2afa19a9 1712 for (que = 0; que < ha->max_req_queues; que++) {
29bdccbe 1713 req = ha->req_q_map[que];
73208dfd
AC		 1714 if (!req)
1715 continue;
8d93f550
CD		 1716 if (!req->outstanding_cmds)
1717 continue;
1718 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
73208dfd 1719 sp = req->outstanding_cmds[cnt];
e612d465 1720 if (sp) {
c5419e26
QT		 1721 req->outstanding_cmds[cnt] = NULL;
1722 if (sp->cmd_type == TYPE_SRB) {
6fcd98fd 1723 if (sp->type == SRB_NVME_CMD ||
1724 sp->type == SRB_NVME_LS) {
e84067d7
DG		 1725 sp_get(sp);
1726 spin_unlock_irqrestore(
1727 &ha->hardware_lock, flags);
1728 qla_nvme_abort(ha, sp);
1729 spin_lock_irqsave(
1730 &ha->hardware_lock, flags);
1731 } else if (GET_CMD_SP(sp) &&
c5419e26 1732 !ha->flags.eeh_busy &&
d61cca60
SC		 1733 (!test_bit(ABORT_ISP_ACTIVE,
1734 &vha->dpc_flags)) &&
c5419e26
QT		 1735 (sp->type == SRB_SCSI_CMD)) {
1736 /*
e84067d7
DG		 1737 * Don't abort commands in
1738 * adapter during EEH
1739 * recovery as it's not
1740 * accessible/responding.
1741 *
c5419e26
QT		 1742 * Get a reference to the sp
1743 * and drop the lock. The
1744 * reference ensures this
1745 * sp->done() call and not the
1746 * call in qla2xxx_eh_abort()
1747 * ends the SCSI command (with
1748 * result 'res').
1749 */
1750 sp_get(sp);
1751 spin_unlock_irqrestore(
1752 &ha->hardware_lock, flags);
1753 status = qla2xxx_eh_abort(
1754 GET_CMD_SP(sp));
1755 spin_lock_irqsave(
1756 &ha->hardware_lock, flags);
1757 /*
1758 * Get rid of extra reference
1759 * if immediate exit from
1760 * ql2xxx_eh_abort
1761 */
1762 if (status == FAILED &&
1763 (qla2x00_isp_reg_stat(ha)))
1764 atomic_dec(
1765 &sp->ref_count);
1766 }
1767 sp->done(sp, res);
1768 } else {
1769 if (!vha->hw->tgt.tgt_ops || !tgt ||
1770 qla_ini_mode_enabled(vha)) {
1771 if (!trace)
1772 ql_dbg(ql_dbg_tgt_mgt,
1773 vha, 0xf003,
1774 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1775 vha->dpc_flags);
1776 continue;
1777 }
1778 cmd = (struct qla_tgt_cmd *)sp;
1779 qlt_abort_cmd_on_host_reset(cmd->vha,
1780 cmd);
c733ab35 1781 }
73208dfd 1782 }
df4bf0bb
AV		 1783 }
1784 }
1785 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1786}
1787
f4f051eb
AV		 1788static int
1789qla2xxx_slave_alloc(struct scsi_device *sdev)
1da177e4 1790{
bdf79621 1791 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1da177e4 1792
19a7b4ae 1793 if (!rport || fc_remote_port_chkready(rport))
f4f051eb 1794 return -ENXIO;
bdf79621 1795
19a7b4ae 1796 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1da177e4 1797
f4f051eb
AV		 1798 return 0;
1799}
1da177e4 1800
f4f051eb
AV		 1801static int
1802qla2xxx_slave_configure(struct scsi_device *sdev)
1803{
e315cd28 1804 scsi_qla_host_t *vha = shost_priv(sdev->host);
2afa19a9 1805 struct req_que *req = vha->req;
8482e118 1806
9e522cd8
AE		 1807 if (IS_T10_PI_CAPABLE(vha->hw))
1808 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1809
db5ed4df 1810 scsi_change_queue_depth(sdev, req->max_q_depth);
f4f051eb
AV		 1811 return 0;
1812}
1da177e4 1813
f4f051eb
AV		 1814static void
1815qla2xxx_slave_destroy(struct scsi_device *sdev)
1816{
1817 sdev->hostdata = NULL;
1da177e4
LT		 1818}
1819
1820/**
1821 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1822 * @ha: HA context
1823 *
1824 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1825 * supported addressing method.
1826 */
1827static void
53303c42 1828qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1da177e4 1829{
7524f9b9 1830 /* Assume a 32bit DMA mask. */
1da177e4 1831 ha->flags.enable_64bit_addressing = 0;
1da177e4 1832
6a35528a 1833 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
7524f9b9
AV		 1834 /* Any upper-dword bits set? */
1835 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
6a35528a 1836 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
7524f9b9 1837 /* Ok, a 64bit DMA mask is applicable. */
1da177e4 1838 ha->flags.enable_64bit_addressing = 1;
fd34f556
AV		 1839 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1840 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
7524f9b9 1841 return;
1da177e4 1842 }
1da177e4 1843 }
7524f9b9 1844
284901a9
YH		 1845 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1846 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1da177e4
LT		 1847}
1848
fd34f556 1849static void
e315cd28 1850qla2x00_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1851{
1852 unsigned long flags = 0;
1853 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1854
1855 spin_lock_irqsave(&ha->hardware_lock, flags);
1856 ha->interrupts_on = 1;
1857 /* enable risc and host interrupts */
1858 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1859 RD_REG_WORD(&reg->ictrl);
1860 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1861
1862}
1863
1864static void
e315cd28 1865qla2x00_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1866{
1867 unsigned long flags = 0;
1868 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1869
1870 spin_lock_irqsave(&ha->hardware_lock, flags);
1871 ha->interrupts_on = 0;
1872 /* disable risc and host interrupts */
1873 WRT_REG_WORD(&reg->ictrl, 0);
1874 RD_REG_WORD(&reg->ictrl);
1875 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1876}
1877
1878static void
e315cd28 1879qla24xx_enable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1880{
1881 unsigned long flags = 0;
1882 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1883
1884 spin_lock_irqsave(&ha->hardware_lock, flags);
1885 ha->interrupts_on = 1;
1886 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1887 RD_REG_DWORD(&reg->ictrl);
1888 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1889}
1890
1891static void
e315cd28 1892qla24xx_disable_intrs(struct qla_hw_data *ha)
fd34f556
AV		 1893{
1894 unsigned long flags = 0;
1895 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1896
124f85e6
AV		 1897 if (IS_NOPOLLING_TYPE(ha))
1898 return;
fd34f556
AV		 1899 spin_lock_irqsave(&ha->hardware_lock, flags);
1900 ha->interrupts_on = 0;
1901 WRT_REG_DWORD(&reg->ictrl, 0);
1902 RD_REG_DWORD(&reg->ictrl);
1903 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1904}
1905
706f457d
GM		 1906static int
1907qla2x00_iospace_config(struct qla_hw_data *ha)
1908{
1909 resource_size_t pio;
1910 uint16_t msix;
706f457d 1911
706f457d
GM		 1912 if (pci_request_selected_regions(ha->pdev, ha->bars,
1913 QLA2XXX_DRIVER_NAME)) {
1914 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1915 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1916 pci_name(ha->pdev));
1917 goto iospace_error_exit;
1918 }
1919 if (!(ha->bars & 1))
1920 goto skip_pio;
1921
1922 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1923 pio = pci_resource_start(ha->pdev, 0);
1924 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1925 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1926 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1927 "Invalid pci I/O region size (%s).\n",
1928 pci_name(ha->pdev));
1929 pio = 0;
1930 }
1931 } else {
1932 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1933 "Region #0 no a PIO resource (%s).\n",
1934 pci_name(ha->pdev));
1935 pio = 0;
1936 }
1937 ha->pio_address = pio;
1938 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
1939 "PIO address=%llu.\n",
1940 (unsigned long long)ha->pio_address);
1941
1942skip_pio:
1943 /* Use MMIO operations for all accesses. */
1944 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
1945 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
1946 "Region #1 not an MMIO resource (%s), aborting.\n",
1947 pci_name(ha->pdev));
1948 goto iospace_error_exit;
1949 }
1950 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
1951 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
1952 "Invalid PCI mem region size (%s), aborting.\n",
1953 pci_name(ha->pdev));
1954 goto iospace_error_exit;
1955 }
1956
1957 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
1958 if (!ha->iobase) {
1959 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
1960 "Cannot remap MMIO (%s), aborting.\n",
1961 pci_name(ha->pdev));
1962 goto iospace_error_exit;
1963 }
1964
1965 /* Determine queue resources */
1966 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 1967 ha->msix_count = QLA_BASE_VECTORS;
d7459527 1968 if (!ql2xmqsupport || (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
706f457d
GM		 1969 goto mqiobase_exit;
1970
1971 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
1972 pci_resource_len(ha->pdev, 3));
1973 if (ha->mqiobase) {
1974 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
1975 "MQIO Base=%p.\n", ha->mqiobase);
1976 /* Read MSIX vector size of the board */
1977 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
d7459527 1978 ha->msix_count = msix + 1;
706f457d 1979 /* Max queues are bounded by available msix vectors */
d7459527
MH		 1980 /* MB interrupt uses 1 vector */
1981 ha->max_req_queues = ha->msix_count - 1;
1982 ha->max_rsp_queues = ha->max_req_queues;
1983 /* Queue pairs is the max value minus the base queue pair */
1984 ha->max_qpairs = ha->max_rsp_queues - 1;
1985 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
1986 "Max no of queues pairs: %d.\n", ha->max_qpairs);
1987
706f457d 1988 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
d7459527 1989 "MSI-X vector count: %d.\n", ha->msix_count);
706f457d
GM		 1990 } else
1991 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
1992 "BAR 3 not enabled.\n");
1993
1994mqiobase_exit:
706f457d 1995 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
f54f2cb5 1996 "MSIX Count: %d.\n", ha->msix_count);
706f457d
GM		 1997 return (0);
1998
1999iospace_error_exit:
2000 return (-ENOMEM);
2001}
2002
2003
6246b8a1
GM		 2004static int
2005qla83xx_iospace_config(struct qla_hw_data *ha)
2006{
2007 uint16_t msix;
6246b8a1
GM		 2008
2009 if (pci_request_selected_regions(ha->pdev, ha->bars,
2010 QLA2XXX_DRIVER_NAME)) {
2011 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2012 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2013 pci_name(ha->pdev));
2014
2015 goto iospace_error_exit;
2016 }
2017
2018 /* Use MMIO operations for all accesses. */
2019 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2020 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2021 "Invalid pci I/O region size (%s).\n",
2022 pci_name(ha->pdev));
2023 goto iospace_error_exit;
2024 }
2025 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2026 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2027 "Invalid PCI mem region size (%s), aborting\n",
2028 pci_name(ha->pdev));
2029 goto iospace_error_exit;
2030 }
2031
2032 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2033 if (!ha->iobase) {
2034 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2035 "Cannot remap MMIO (%s), aborting.\n",
2036 pci_name(ha->pdev));
2037 goto iospace_error_exit;
2038 }
2039
2040 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2041 /* 83XX 26XX always use MQ type access for queues
2042 * - mbar 2, a.k.a region 4 */
2043 ha->max_req_queues = ha->max_rsp_queues = 1;
f54f2cb5 2044 ha->msix_count = QLA_BASE_VECTORS;
6246b8a1
GM		 2045 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2046 pci_resource_len(ha->pdev, 4));
2047
2048 if (!ha->mqiobase) {
2049 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2050 "BAR2/region4 not enabled\n");
2051 goto mqiobase_exit;
2052 }
2053
2054 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2055 pci_resource_len(ha->pdev, 2));
2056 if (ha->msixbase) {
2057 /* Read MSIX vector size of the board */
2058 pci_read_config_word(ha->pdev,
2059 QLA_83XX_PCI_MSIX_CONTROL, &msix);
e326d22a 2060 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
093df737
QT		 2061 /*
2062 * By default, driver uses at least two msix vectors
2063 * (default & rspq)
2064 */
d7459527
MH		 2065 if (ql2xmqsupport) {
2066 /* MB interrupt uses 1 vector */
2067 ha->max_req_queues = ha->msix_count - 1;
093df737
QT		 2068
2069 /* ATIOQ needs 1 vector. That's 1 less QPair */
2070 if (QLA_TGT_MODE_ENABLED())
2071 ha->max_req_queues--;
2072
d0d2c68b
MH		 2073 ha->max_rsp_queues = ha->max_req_queues;
2074
d7459527
MH		 2075 /* Queue pairs is the max value minus
2076 * the base queue pair */
2077 ha->max_qpairs = ha->max_req_queues - 1;
83548fe2 2078 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
d7459527 2079 "Max no of queues pairs: %d.\n", ha->max_qpairs);
6246b8a1
GM		 2080 }
2081 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
d7459527 2082 "MSI-X vector count: %d.\n", ha->msix_count);
6246b8a1
GM		 2083 } else
2084 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2085 "BAR 1 not enabled.\n");
2086
2087mqiobase_exit:
6246b8a1 2088 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
f54f2cb5 2089 "MSIX Count: %d.\n", ha->msix_count);
6246b8a1
GM		 2090 return 0;
2091
2092iospace_error_exit:
2093 return -ENOMEM;
2094}
2095
fd34f556
AV		 2096static struct isp_operations qla2100_isp_ops = {
2097 .pci_config = qla2100_pci_config,
2098 .reset_chip = qla2x00_reset_chip,
2099 .chip_diag = qla2x00_chip_diag,
2100 .config_rings = qla2x00_config_rings,
2101 .reset_adapter = qla2x00_reset_adapter,
2102 .nvram_config = qla2x00_nvram_config,
2103 .update_fw_options = qla2x00_update_fw_options,
2104 .load_risc = qla2x00_load_risc,
2105 .pci_info_str = qla2x00_pci_info_str,
2106 .fw_version_str = qla2x00_fw_version_str,
2107 .intr_handler = qla2100_intr_handler,
2108 .enable_intrs = qla2x00_enable_intrs,
2109 .disable_intrs = qla2x00_disable_intrs,
2110 .abort_command = qla2x00_abort_command,
523ec773
AV		 2111 .target_reset = qla2x00_abort_target,
2112 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2113 .fabric_login = qla2x00_login_fabric,
2114 .fabric_logout = qla2x00_fabric_logout,
2115 .calc_req_entries = qla2x00_calc_iocbs_32,
2116 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2117 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2118 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2119 .read_nvram = qla2x00_read_nvram_data,
2120 .write_nvram = qla2x00_write_nvram_data,
2121 .fw_dump = qla2100_fw_dump,
2122 .beacon_on = NULL,
2123 .beacon_off = NULL,
2124 .beacon_blink = NULL,
2125 .read_optrom = qla2x00_read_optrom_data,
2126 .write_optrom = qla2x00_write_optrom_data,
2127 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2128 .start_scsi = qla2x00_start_scsi,
d7459527 2129 .start_scsi_mq = NULL,
a9083016 2130 .abort_isp = qla2x00_abort_isp,
706f457d 2131 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2132 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2133};
2134
2135static struct isp_operations qla2300_isp_ops = {
2136 .pci_config = qla2300_pci_config,
2137 .reset_chip = qla2x00_reset_chip,
2138 .chip_diag = qla2x00_chip_diag,
2139 .config_rings = qla2x00_config_rings,
2140 .reset_adapter = qla2x00_reset_adapter,
2141 .nvram_config = qla2x00_nvram_config,
2142 .update_fw_options = qla2x00_update_fw_options,
2143 .load_risc = qla2x00_load_risc,
2144 .pci_info_str = qla2x00_pci_info_str,
2145 .fw_version_str = qla2x00_fw_version_str,
2146 .intr_handler = qla2300_intr_handler,
2147 .enable_intrs = qla2x00_enable_intrs,
2148 .disable_intrs = qla2x00_disable_intrs,
2149 .abort_command = qla2x00_abort_command,
523ec773
AV		 2150 .target_reset = qla2x00_abort_target,
2151 .lun_reset = qla2x00_lun_reset,
fd34f556
AV		 2152 .fabric_login = qla2x00_login_fabric,
2153 .fabric_logout = qla2x00_fabric_logout,
2154 .calc_req_entries = qla2x00_calc_iocbs_32,
2155 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2156 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2157 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2158 .read_nvram = qla2x00_read_nvram_data,
2159 .write_nvram = qla2x00_write_nvram_data,
2160 .fw_dump = qla2300_fw_dump,
2161 .beacon_on = qla2x00_beacon_on,
2162 .beacon_off = qla2x00_beacon_off,
2163 .beacon_blink = qla2x00_beacon_blink,
2164 .read_optrom = qla2x00_read_optrom_data,
2165 .write_optrom = qla2x00_write_optrom_data,
2166 .get_flash_version = qla2x00_get_flash_version,
e315cd28 2167 .start_scsi = qla2x00_start_scsi,
d7459527 2168 .start_scsi_mq = NULL,
a9083016 2169 .abort_isp = qla2x00_abort_isp,
7ec0effd 2170 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2171 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2172};
2173
2174static struct isp_operations qla24xx_isp_ops = {
2175 .pci_config = qla24xx_pci_config,
2176 .reset_chip = qla24xx_reset_chip,
2177 .chip_diag = qla24xx_chip_diag,
2178 .config_rings = qla24xx_config_rings,
2179 .reset_adapter = qla24xx_reset_adapter,
2180 .nvram_config = qla24xx_nvram_config,
2181 .update_fw_options = qla24xx_update_fw_options,
2182 .load_risc = qla24xx_load_risc,
2183 .pci_info_str = qla24xx_pci_info_str,
2184 .fw_version_str = qla24xx_fw_version_str,
2185 .intr_handler = qla24xx_intr_handler,
2186 .enable_intrs = qla24xx_enable_intrs,
2187 .disable_intrs = qla24xx_disable_intrs,
2188 .abort_command = qla24xx_abort_command,
523ec773
AV		 2189 .target_reset = qla24xx_abort_target,
2190 .lun_reset = qla24xx_lun_reset,
fd34f556
AV		 2191 .fabric_login = qla24xx_login_fabric,
2192 .fabric_logout = qla24xx_fabric_logout,
2193 .calc_req_entries = NULL,
2194 .build_iocbs = NULL,
2195 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2196 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2197 .read_nvram = qla24xx_read_nvram_data,
2198 .write_nvram = qla24xx_write_nvram_data,
2199 .fw_dump = qla24xx_fw_dump,
2200 .beacon_on = qla24xx_beacon_on,
2201 .beacon_off = qla24xx_beacon_off,
2202 .beacon_blink = qla24xx_beacon_blink,
2203 .read_optrom = qla24xx_read_optrom_data,
2204 .write_optrom = qla24xx_write_optrom_data,
2205 .get_flash_version = qla24xx_get_flash_version,
e315cd28 2206 .start_scsi = qla24xx_start_scsi,
d7459527 2207 .start_scsi_mq = NULL,
a9083016 2208 .abort_isp = qla2x00_abort_isp,
7ec0effd 2209 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2210 .initialize_adapter = qla2x00_initialize_adapter,
fd34f556
AV		 2211};
2212
c3a2f0df
AV		 2213static struct isp_operations qla25xx_isp_ops = {
2214 .pci_config = qla25xx_pci_config,
2215 .reset_chip = qla24xx_reset_chip,
2216 .chip_diag = qla24xx_chip_diag,
2217 .config_rings = qla24xx_config_rings,
2218 .reset_adapter = qla24xx_reset_adapter,
2219 .nvram_config = qla24xx_nvram_config,
2220 .update_fw_options = qla24xx_update_fw_options,
2221 .load_risc = qla24xx_load_risc,
2222 .pci_info_str = qla24xx_pci_info_str,
2223 .fw_version_str = qla24xx_fw_version_str,
2224 .intr_handler = qla24xx_intr_handler,
2225 .enable_intrs = qla24xx_enable_intrs,
2226 .disable_intrs = qla24xx_disable_intrs,
2227 .abort_command = qla24xx_abort_command,
523ec773
AV		 2228 .target_reset = qla24xx_abort_target,
2229 .lun_reset = qla24xx_lun_reset,
c3a2f0df
AV		 2230 .fabric_login = qla24xx_login_fabric,
2231 .fabric_logout = qla24xx_fabric_logout,
2232 .calc_req_entries = NULL,
2233 .build_iocbs = NULL,
2234 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2235 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2236 .read_nvram = qla25xx_read_nvram_data,
2237 .write_nvram = qla25xx_write_nvram_data,
2238 .fw_dump = qla25xx_fw_dump,
2239 .beacon_on = qla24xx_beacon_on,
2240 .beacon_off = qla24xx_beacon_off,
2241 .beacon_blink = qla24xx_beacon_blink,
338c9161 2242 .read_optrom = qla25xx_read_optrom_data,
c3a2f0df
AV		 2243 .write_optrom = qla24xx_write_optrom_data,
2244 .get_flash_version = qla24xx_get_flash_version,
bad75002 2245 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2246 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2247 .abort_isp = qla2x00_abort_isp,
7ec0effd 2248 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2249 .initialize_adapter = qla2x00_initialize_adapter,
c3a2f0df
AV		 2250};
2251
3a03eb79
AV		 2252static struct isp_operations qla81xx_isp_ops = {
2253 .pci_config = qla25xx_pci_config,
2254 .reset_chip = qla24xx_reset_chip,
2255 .chip_diag = qla24xx_chip_diag,
2256 .config_rings = qla24xx_config_rings,
2257 .reset_adapter = qla24xx_reset_adapter,
2258 .nvram_config = qla81xx_nvram_config,
2259 .update_fw_options = qla81xx_update_fw_options,
eaac30be 2260 .load_risc = qla81xx_load_risc,
3a03eb79
AV		 2261 .pci_info_str = qla24xx_pci_info_str,
2262 .fw_version_str = qla24xx_fw_version_str,
2263 .intr_handler = qla24xx_intr_handler,
2264 .enable_intrs = qla24xx_enable_intrs,
2265 .disable_intrs = qla24xx_disable_intrs,
2266 .abort_command = qla24xx_abort_command,
2267 .target_reset = qla24xx_abort_target,
2268 .lun_reset = qla24xx_lun_reset,
2269 .fabric_login = qla24xx_login_fabric,
2270 .fabric_logout = qla24xx_fabric_logout,
2271 .calc_req_entries = NULL,
2272 .build_iocbs = NULL,
2273 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2274 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
3d79038f
AV		 2275 .read_nvram = NULL,
2276 .write_nvram = NULL,
3a03eb79
AV		 2277 .fw_dump = qla81xx_fw_dump,
2278 .beacon_on = qla24xx_beacon_on,
2279 .beacon_off = qla24xx_beacon_off,
6246b8a1 2280 .beacon_blink = qla83xx_beacon_blink,
3a03eb79
AV		 2281 .read_optrom = qla25xx_read_optrom_data,
2282 .write_optrom = qla24xx_write_optrom_data,
2283 .get_flash_version = qla24xx_get_flash_version,
ba77ef53 2284 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2285 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
a9083016 2286 .abort_isp = qla2x00_abort_isp,
7ec0effd 2287 .iospace_config = qla2x00_iospace_config,
8ae6d9c7 2288 .initialize_adapter = qla2x00_initialize_adapter,
a9083016
GM		 2289};
2290
2291static struct isp_operations qla82xx_isp_ops = {
2292 .pci_config = qla82xx_pci_config,
2293 .reset_chip = qla82xx_reset_chip,
2294 .chip_diag = qla24xx_chip_diag,
2295 .config_rings = qla82xx_config_rings,
2296 .reset_adapter = qla24xx_reset_adapter,
2297 .nvram_config = qla81xx_nvram_config,
2298 .update_fw_options = qla24xx_update_fw_options,
2299 .load_risc = qla82xx_load_risc,
9d55ca66 2300 .pci_info_str = qla24xx_pci_info_str,
a9083016
GM		 2301 .fw_version_str = qla24xx_fw_version_str,
2302 .intr_handler = qla82xx_intr_handler,
2303 .enable_intrs = qla82xx_enable_intrs,
2304 .disable_intrs = qla82xx_disable_intrs,
2305 .abort_command = qla24xx_abort_command,
2306 .target_reset = qla24xx_abort_target,
2307 .lun_reset = qla24xx_lun_reset,
2308 .fabric_login = qla24xx_login_fabric,
2309 .fabric_logout = qla24xx_fabric_logout,
2310 .calc_req_entries = NULL,
2311 .build_iocbs = NULL,
2312 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2313 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2314 .read_nvram = qla24xx_read_nvram_data,
2315 .write_nvram = qla24xx_write_nvram_data,
a1b23c5a 2316 .fw_dump = qla82xx_fw_dump,
999916dc
SK		 2317 .beacon_on = qla82xx_beacon_on,
2318 .beacon_off = qla82xx_beacon_off,
2319 .beacon_blink = NULL,
a9083016
GM		 2320 .read_optrom = qla82xx_read_optrom_data,
2321 .write_optrom = qla82xx_write_optrom_data,
7ec0effd 2322 .get_flash_version = qla82xx_get_flash_version,
a9083016 2323 .start_scsi = qla82xx_start_scsi,
d7459527 2324 .start_scsi_mq = NULL,
a9083016 2325 .abort_isp = qla82xx_abort_isp,
706f457d 2326 .iospace_config = qla82xx_iospace_config,
8ae6d9c7 2327 .initialize_adapter = qla2x00_initialize_adapter,
3a03eb79
AV		 2328};
2329
7ec0effd
AD		 2330static struct isp_operations qla8044_isp_ops = {
2331 .pci_config = qla82xx_pci_config,
2332 .reset_chip = qla82xx_reset_chip,
2333 .chip_diag = qla24xx_chip_diag,
2334 .config_rings = qla82xx_config_rings,
2335 .reset_adapter = qla24xx_reset_adapter,
2336 .nvram_config = qla81xx_nvram_config,
2337 .update_fw_options = qla24xx_update_fw_options,
2338 .load_risc = qla82xx_load_risc,
2339 .pci_info_str = qla24xx_pci_info_str,
2340 .fw_version_str = qla24xx_fw_version_str,
2341 .intr_handler = qla8044_intr_handler,
2342 .enable_intrs = qla82xx_enable_intrs,
2343 .disable_intrs = qla82xx_disable_intrs,
2344 .abort_command = qla24xx_abort_command,
2345 .target_reset = qla24xx_abort_target,
2346 .lun_reset = qla24xx_lun_reset,
2347 .fabric_login = qla24xx_login_fabric,
2348 .fabric_logout = qla24xx_fabric_logout,
2349 .calc_req_entries = NULL,
2350 .build_iocbs = NULL,
2351 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2352 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2353 .read_nvram = NULL,
2354 .write_nvram = NULL,
a1b23c5a 2355 .fw_dump = qla8044_fw_dump,
7ec0effd
AD		 2356 .beacon_on = qla82xx_beacon_on,
2357 .beacon_off = qla82xx_beacon_off,
2358 .beacon_blink = NULL,
888e639d 2359 .read_optrom = qla8044_read_optrom_data,
7ec0effd
AD		 2360 .write_optrom = qla8044_write_optrom_data,
2361 .get_flash_version = qla82xx_get_flash_version,
2362 .start_scsi = qla82xx_start_scsi,
d7459527 2363 .start_scsi_mq = NULL,
7ec0effd
AD		 2364 .abort_isp = qla8044_abort_isp,
2365 .iospace_config = qla82xx_iospace_config,
2366 .initialize_adapter = qla2x00_initialize_adapter,
2367};
2368
6246b8a1
GM		 2369static struct isp_operations qla83xx_isp_ops = {
2370 .pci_config = qla25xx_pci_config,
2371 .reset_chip = qla24xx_reset_chip,
2372 .chip_diag = qla24xx_chip_diag,
2373 .config_rings = qla24xx_config_rings,
2374 .reset_adapter = qla24xx_reset_adapter,
2375 .nvram_config = qla81xx_nvram_config,
2376 .update_fw_options = qla81xx_update_fw_options,
2377 .load_risc = qla81xx_load_risc,
2378 .pci_info_str = qla24xx_pci_info_str,
2379 .fw_version_str = qla24xx_fw_version_str,
2380 .intr_handler = qla24xx_intr_handler,
2381 .enable_intrs = qla24xx_enable_intrs,
2382 .disable_intrs = qla24xx_disable_intrs,
2383 .abort_command = qla24xx_abort_command,
2384 .target_reset = qla24xx_abort_target,
2385 .lun_reset = qla24xx_lun_reset,
2386 .fabric_login = qla24xx_login_fabric,
2387 .fabric_logout = qla24xx_fabric_logout,
2388 .calc_req_entries = NULL,
2389 .build_iocbs = NULL,
2390 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2391 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2392 .read_nvram = NULL,
2393 .write_nvram = NULL,
2394 .fw_dump = qla83xx_fw_dump,
2395 .beacon_on = qla24xx_beacon_on,
2396 .beacon_off = qla24xx_beacon_off,
2397 .beacon_blink = qla83xx_beacon_blink,
2398 .read_optrom = qla25xx_read_optrom_data,
2399 .write_optrom = qla24xx_write_optrom_data,
2400 .get_flash_version = qla24xx_get_flash_version,
2401 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2402 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
6246b8a1
GM		 2403 .abort_isp = qla2x00_abort_isp,
2404 .iospace_config = qla83xx_iospace_config,
8ae6d9c7
GM		 2405 .initialize_adapter = qla2x00_initialize_adapter,
2406};
2407
2408static struct isp_operations qlafx00_isp_ops = {
2409 .pci_config = qlafx00_pci_config,
2410 .reset_chip = qlafx00_soft_reset,
2411 .chip_diag = qlafx00_chip_diag,
2412 .config_rings = qlafx00_config_rings,
2413 .reset_adapter = qlafx00_soft_reset,
2414 .nvram_config = NULL,
2415 .update_fw_options = NULL,
2416 .load_risc = NULL,
2417 .pci_info_str = qlafx00_pci_info_str,
2418 .fw_version_str = qlafx00_fw_version_str,
2419 .intr_handler = qlafx00_intr_handler,
2420 .enable_intrs = qlafx00_enable_intrs,
2421 .disable_intrs = qlafx00_disable_intrs,
4440e46d 2422 .abort_command = qla24xx_async_abort_command,
8ae6d9c7
GM		 2423 .target_reset = qlafx00_abort_target,
2424 .lun_reset = qlafx00_lun_reset,
2425 .fabric_login = NULL,
2426 .fabric_logout = NULL,
2427 .calc_req_entries = NULL,
2428 .build_iocbs = NULL,
2429 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2430 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2431 .read_nvram = qla24xx_read_nvram_data,
2432 .write_nvram = qla24xx_write_nvram_data,
2433 .fw_dump = NULL,
2434 .beacon_on = qla24xx_beacon_on,
2435 .beacon_off = qla24xx_beacon_off,
2436 .beacon_blink = NULL,
2437 .read_optrom = qla24xx_read_optrom_data,
2438 .write_optrom = qla24xx_write_optrom_data,
2439 .get_flash_version = qla24xx_get_flash_version,
2440 .start_scsi = qlafx00_start_scsi,
d7459527 2441 .start_scsi_mq = NULL,
8ae6d9c7
GM		 2442 .abort_isp = qlafx00_abort_isp,
2443 .iospace_config = qlafx00_iospace_config,
2444 .initialize_adapter = qlafx00_initialize_adapter,
6246b8a1
GM		 2445};
2446
f73cb695
CD		 2447static struct isp_operations qla27xx_isp_ops = {
2448 .pci_config = qla25xx_pci_config,
2449 .reset_chip = qla24xx_reset_chip,
2450 .chip_diag = qla24xx_chip_diag,
2451 .config_rings = qla24xx_config_rings,
2452 .reset_adapter = qla24xx_reset_adapter,
2453 .nvram_config = qla81xx_nvram_config,
2454 .update_fw_options = qla81xx_update_fw_options,
2455 .load_risc = qla81xx_load_risc,
2456 .pci_info_str = qla24xx_pci_info_str,
2457 .fw_version_str = qla24xx_fw_version_str,
2458 .intr_handler = qla24xx_intr_handler,
2459 .enable_intrs = qla24xx_enable_intrs,
2460 .disable_intrs = qla24xx_disable_intrs,
2461 .abort_command = qla24xx_abort_command,
2462 .target_reset = qla24xx_abort_target,
2463 .lun_reset = qla24xx_lun_reset,
2464 .fabric_login = qla24xx_login_fabric,
2465 .fabric_logout = qla24xx_fabric_logout,
2466 .calc_req_entries = NULL,
2467 .build_iocbs = NULL,
2468 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2469 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2470 .read_nvram = NULL,
2471 .write_nvram = NULL,
2472 .fw_dump = qla27xx_fwdump,
2473 .beacon_on = qla24xx_beacon_on,
2474 .beacon_off = qla24xx_beacon_off,
2475 .beacon_blink = qla83xx_beacon_blink,
2476 .read_optrom = qla25xx_read_optrom_data,
2477 .write_optrom = qla24xx_write_optrom_data,
2478 .get_flash_version = qla24xx_get_flash_version,
2479 .start_scsi = qla24xx_dif_start_scsi,
d7459527 2480 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
f73cb695
CD		 2481 .abort_isp = qla2x00_abort_isp,
2482 .iospace_config = qla83xx_iospace_config,
2483 .initialize_adapter = qla2x00_initialize_adapter,
2484};
2485
ea5b6382 2486static inline void
e315cd28 2487qla2x00_set_isp_flags(struct qla_hw_data *ha)
ea5b6382
AV		 2488{
2489 ha->device_type = DT_EXTENDED_IDS;
2490 switch (ha->pdev->device) {
2491 case PCI_DEVICE_ID_QLOGIC_ISP2100:
9e052e2d 2492 ha->isp_type |= DT_ISP2100;
ea5b6382 2493 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2494 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2495 break;
2496 case PCI_DEVICE_ID_QLOGIC_ISP2200:
9e052e2d 2497 ha->isp_type |= DT_ISP2200;
ea5b6382 2498 ha->device_type &= ~DT_EXTENDED_IDS;
441d1072 2499 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
ea5b6382
AV		 2500 break;
2501 case PCI_DEVICE_ID_QLOGIC_ISP2300:
9e052e2d 2502 ha->isp_type |= DT_ISP2300;
4a59f71d 2503 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2504 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2505 break;
2506 case PCI_DEVICE_ID_QLOGIC_ISP2312:
9e052e2d 2507 ha->isp_type |= DT_ISP2312;
4a59f71d 2508 ha->device_type |= DT_ZIO_SUPPORTED;
441d1072 2509 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2510 break;
2511 case PCI_DEVICE_ID_QLOGIC_ISP2322:
9e052e2d 2512 ha->isp_type |= DT_ISP2322;
4a59f71d 2513 ha->device_type |= DT_ZIO_SUPPORTED;
ea5b6382
AV		 2514 if (ha->pdev->subsystem_vendor == 0x1028 &&
2515 ha->pdev->subsystem_device == 0x0170)
2516 ha->device_type |= DT_OEM_001;
441d1072 2517 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2518 break;
2519 case PCI_DEVICE_ID_QLOGIC_ISP6312:
9e052e2d 2520 ha->isp_type |= DT_ISP6312;
441d1072 2521 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2522 break;
2523 case PCI_DEVICE_ID_QLOGIC_ISP6322:
9e052e2d 2524 ha->isp_type |= DT_ISP6322;
441d1072 2525 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
ea5b6382
AV		 2526 break;
2527 case PCI_DEVICE_ID_QLOGIC_ISP2422:
9e052e2d 2528 ha->isp_type |= DT_ISP2422;
4a59f71d 2529 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2530 ha->device_type |= DT_FWI2;
c76f2c01 2531 ha->device_type |= DT_IIDMA;
441d1072 2532 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382
AV		 2533 break;
2534 case PCI_DEVICE_ID_QLOGIC_ISP2432:
9e052e2d 2535 ha->isp_type |= DT_ISP2432;
4a59f71d 2536 ha->device_type |= DT_ZIO_SUPPORTED;
e428924c 2537 ha->device_type |= DT_FWI2;
c76f2c01 2538 ha->device_type |= DT_IIDMA;
441d1072 2539 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2540 break;
4d4df193 2541 case PCI_DEVICE_ID_QLOGIC_ISP8432:
9e052e2d 2542 ha->isp_type |= DT_ISP8432;
4d4df193
HK		 2543 ha->device_type |= DT_ZIO_SUPPORTED;
2544 ha->device_type |= DT_FWI2;
2545 ha->device_type |= DT_IIDMA;
2546 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2547 break;
044cc6c8 2548 case PCI_DEVICE_ID_QLOGIC_ISP5422:
9e052e2d 2549 ha->isp_type |= DT_ISP5422;
e428924c 2550 ha->device_type |= DT_FWI2;
441d1072 2551 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2552 break;
044cc6c8 2553 case PCI_DEVICE_ID_QLOGIC_ISP5432:
9e052e2d 2554 ha->isp_type |= DT_ISP5432;
e428924c 2555 ha->device_type |= DT_FWI2;
441d1072 2556 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2557 break;
c3a2f0df 2558 case PCI_DEVICE_ID_QLOGIC_ISP2532:
9e052e2d 2559 ha->isp_type |= DT_ISP2532;
c3a2f0df
AV		 2560 ha->device_type |= DT_ZIO_SUPPORTED;
2561 ha->device_type |= DT_FWI2;
2562 ha->device_type |= DT_IIDMA;
441d1072 2563 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
ea5b6382 2564 break;
3a03eb79 2565 case PCI_DEVICE_ID_QLOGIC_ISP8001:
9e052e2d 2566 ha->isp_type |= DT_ISP8001;
3a03eb79
AV		 2567 ha->device_type |= DT_ZIO_SUPPORTED;
2568 ha->device_type |= DT_FWI2;
2569 ha->device_type |= DT_IIDMA;
2570 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2571 break;
a9083016 2572 case PCI_DEVICE_ID_QLOGIC_ISP8021:
9e052e2d 2573 ha->isp_type |= DT_ISP8021;
a9083016
GM		 2574 ha->device_type |= DT_ZIO_SUPPORTED;
2575 ha->device_type |= DT_FWI2;
2576 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2577 /* Initialize 82XX ISP flags */
2578 qla82xx_init_flags(ha);
2579 break;
7ec0effd 2580 case PCI_DEVICE_ID_QLOGIC_ISP8044:
9e052e2d 2581 ha->isp_type |= DT_ISP8044;
7ec0effd
AD		 2582 ha->device_type |= DT_ZIO_SUPPORTED;
2583 ha->device_type |= DT_FWI2;
2584 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2585 /* Initialize 82XX ISP flags */
2586 qla82xx_init_flags(ha);
2587 break;
6246b8a1 2588 case PCI_DEVICE_ID_QLOGIC_ISP2031:
9e052e2d 2589 ha->isp_type |= DT_ISP2031;
6246b8a1
GM		 2590 ha->device_type |= DT_ZIO_SUPPORTED;
2591 ha->device_type |= DT_FWI2;
2592 ha->device_type |= DT_IIDMA;
2593 ha->device_type |= DT_T10_PI;
2594 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2595 break;
2596 case PCI_DEVICE_ID_QLOGIC_ISP8031:
9e052e2d 2597 ha->isp_type |= DT_ISP8031;
6246b8a1
GM		 2598 ha->device_type |= DT_ZIO_SUPPORTED;
2599 ha->device_type |= DT_FWI2;
2600 ha->device_type |= DT_IIDMA;
2601 ha->device_type |= DT_T10_PI;
2602 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2603 break;
8ae6d9c7 2604 case PCI_DEVICE_ID_QLOGIC_ISPF001:
9e052e2d 2605 ha->isp_type |= DT_ISPFX00;
8ae6d9c7 2606 break;
f73cb695 2607 case PCI_DEVICE_ID_QLOGIC_ISP2071:
9e052e2d 2608 ha->isp_type |= DT_ISP2071;
f73cb695
CD		 2609 ha->device_type |= DT_ZIO_SUPPORTED;
2610 ha->device_type |= DT_FWI2;
2611 ha->device_type |= DT_IIDMA;
8ce3f570 2612 ha->device_type |= DT_T10_PI;
f73cb695
CD		 2613 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2614 break;
2c5bbbb2 2615 case PCI_DEVICE_ID_QLOGIC_ISP2271:
9e052e2d 2616 ha->isp_type |= DT_ISP2271;
2c5bbbb2
JC		 2617 ha->device_type |= DT_ZIO_SUPPORTED;
2618 ha->device_type |= DT_FWI2;
2619 ha->device_type |= DT_IIDMA;
8ce3f570 2620 ha->device_type |= DT_T10_PI;
2c5bbbb2
JC		 2621 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2622 break;
2b48992f 2623 case PCI_DEVICE_ID_QLOGIC_ISP2261:
9e052e2d 2624 ha->isp_type |= DT_ISP2261;
2b48992f
SC		 2625 ha->device_type |= DT_ZIO_SUPPORTED;
2626 ha->device_type |= DT_FWI2;
2627 ha->device_type |= DT_IIDMA;
8ce3f570 2628 ha->device_type |= DT_T10_PI;
2b48992f
SC		 2629 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2630 break;
ea5b6382 2631 }
e5b68a61 2632
a9083016 2633 if (IS_QLA82XX(ha))
43a9c38b 2634 ha->port_no = ha->portnum & 1;
f73cb695 2635 else {
a9083016
GM		 2636 /* Get adapter physical port no from interrupt pin register. */
2637 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
f73cb695
CD		 2638 if (IS_QLA27XX(ha))
2639 ha->port_no--;
2640 else
2641 ha->port_no = !(ha->port_no & 1);
2642 }
a9083016 2643
7c3df132 2644 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
d8424f68 2645 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
f73cb695 2646 ha->device_type, ha->port_no, ha->fw_srisc_address);
ea5b6382
AV		 2647}
2648
1e99e33a
AV		 2649static void
2650qla2xxx_scan_start(struct Scsi_Host *shost)
2651{
e315cd28 2652 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2653
cbc8eb67
AV		 2654 if (vha->hw->flags.running_gold_fw)
2655 return;
2656
e315cd28
AC		 2657 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2658 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2659 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2660 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
1e99e33a
AV		 2661}
2662
2663static int
2664qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2665{
e315cd28 2666 scsi_qla_host_t *vha = shost_priv(shost);
1e99e33a 2667
a5dd506e
BK		 2668 if (test_bit(UNLOADING, &vha->dpc_flags))
2669 return 1;
e315cd28 2670 if (!vha->host)
1e99e33a 2671 return 1;
e315cd28 2672 if (time > vha->hw->loop_reset_delay * HZ)
1e99e33a
AV		 2673 return 1;
2674
e315cd28 2675 return atomic_read(&vha->loop_state) == LOOP_READY;
1e99e33a
AV		 2676}
2677
ec7193e2
QT		 2678static void qla2x00_iocb_work_fn(struct work_struct *work)
2679{
2680 struct scsi_qla_host *vha = container_of(work,
2681 struct scsi_qla_host, iocb_work);
2682 int cnt = 0;
2683
2684 while (!list_empty(&vha->work_list)) {
2685 qla2x00_do_work(vha);
2686 cnt++;
2687 if (cnt > 10)
2688 break;
2689 }
2690}
2691
1da177e4
LT		 2692/*
2693 * PCI driver interface
2694 */
6f039790 2695static int
7ee61397 2696qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
1da177e4 2697{
a1541d5a 2698 int ret = -ENODEV;
1da177e4 2699 struct Scsi_Host *host;
e315cd28
AC		 2700 scsi_qla_host_t *base_vha = NULL;
2701 struct qla_hw_data *ha;
29856e28 2702 char pci_info[30];
7d613ac6 2703 char fw_str[30], wq_name[30];
5433383e 2704 struct scsi_host_template *sht;
642ef983 2705 int bars, mem_only = 0;
e315cd28 2706 uint16_t req_length = 0, rsp_length = 0;
73208dfd
AC		 2707 struct req_que *req = NULL;
2708 struct rsp_que *rsp = NULL;
5601236b 2709 int i;
d7459527 2710
285d0321 2711 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
a5326f86 2712 sht = &qla2xxx_driver_template;
5433383e 2713 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
8bc69e7d 2714 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
4d4df193 2715 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
8bc69e7d 2716 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
c3a2f0df 2717 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
3a03eb79 2718 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
a9083016 2719 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
6246b8a1
GM		 2720 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2721 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
8ae6d9c7 2722 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
7ec0effd 2723 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
f73cb695 2724 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2c5bbbb2 2725 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2b48992f
SC		 2726 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2727 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
285d0321 2728 bars = pci_select_bars(pdev, IORESOURCE_MEM);
09483916 2729 mem_only = 1;
7c3df132
SK		 2730 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2731 "Mem only adapter.\n");
285d0321 2732 }
7c3df132
SK		 2733 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2734 "Bars=%d.\n", bars);
285d0321 2735
09483916
BH		 2736 if (mem_only) {
2737 if (pci_enable_device_mem(pdev))
ddff7ed4 2738 return ret;
09483916
BH		 2739 } else {
2740 if (pci_enable_device(pdev))
ddff7ed4 2741 return ret;
09483916 2742 }
285d0321 2743
0927678f
JB		 2744 /* This may fail but that's ok */
2745 pci_enable_pcie_error_reporting(pdev);
285d0321 2746
e315cd28
AC		 2747 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2748 if (!ha) {
7c3df132
SK		 2749 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2750 "Unable to allocate memory for ha.\n");
ddff7ed4 2751 goto disable_device;
1da177e4 2752 }
7c3df132
SK		 2753 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2754 "Memory allocated for ha=%p.\n", ha);
e315cd28 2755 ha->pdev = pdev;
33e79977
QT		 2756 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2757 spin_lock_init(&ha->tgt.q_full_lock);
7560151b 2758 spin_lock_init(&ha->tgt.sess_lock);
2f424b9b
QT		 2759 spin_lock_init(&ha->tgt.atio_lock);
2760
deeae7a6 2761 atomic_set(&ha->nvme_active_aen_cnt, 0);
1da177e4
LT		 2762
2763 /* Clear our data area */
285d0321 2764 ha->bars = bars;
09483916 2765 ha->mem_only = mem_only;
df4bf0bb 2766 spin_lock_init(&ha->hardware_lock);
339aa70e 2767 spin_lock_init(&ha->vport_slock);
a9b6f722 2768 mutex_init(&ha->selflogin_lock);
7a8ab9c8 2769 mutex_init(&ha->optrom_mutex);
1da177e4 2770
ea5b6382
AV		 2771 /* Set ISP-type information. */
2772 qla2x00_set_isp_flags(ha);
ca79cf66
DG		 2773
2774 /* Set EEH reset type to fundamental if required by hba */
95676112 2775 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
f73cb695 2776 IS_QLA83XX(ha) || IS_QLA27XX(ha))
ca79cf66 2777 pdev->needs_freset = 1;
ca79cf66 2778
cba1e47f
CD		 2779 ha->prev_topology = 0;
2780 ha->init_cb_size = sizeof(init_cb_t);
2781 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2782 ha->optrom_size = OPTROM_SIZE_2300;
2783
abbd8870 2784 /* Assign ISP specific operations. */
1da177e4 2785 if (IS_QLA2100(ha)) {
642ef983 2786 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2787 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
e315cd28
AC		 2788 req_length = REQUEST_ENTRY_CNT_2100;
2789 rsp_length = RESPONSE_ENTRY_CNT_2100;
2790 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2791 ha->gid_list_info_size = 4;
3a03eb79
AV		 2792 ha->flash_conf_off = ~0;
2793 ha->flash_data_off = ~0;
2794 ha->nvram_conf_off = ~0;
2795 ha->nvram_data_off = ~0;
fd34f556 2796 ha->isp_ops = &qla2100_isp_ops;
1da177e4 2797 } else if (IS_QLA2200(ha)) {
642ef983 2798 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
67ddda35 2799 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
e315cd28
AC		 2800 req_length = REQUEST_ENTRY_CNT_2200;
2801 rsp_length = RESPONSE_ENTRY_CNT_2100;
2802 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
abbd8870 2803 ha->gid_list_info_size = 4;
3a03eb79
AV		 2804 ha->flash_conf_off = ~0;
2805 ha->flash_data_off = ~0;
2806 ha->nvram_conf_off = ~0;
2807 ha->nvram_data_off = ~0;
fd34f556 2808 ha->isp_ops = &qla2100_isp_ops;
fca29703 2809 } else if (IS_QLA23XX(ha)) {
642ef983 2810 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
1da177e4 2811 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2812 req_length = REQUEST_ENTRY_CNT_2200;
2813 rsp_length = RESPONSE_ENTRY_CNT_2300;
2814 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
abbd8870 2815 ha->gid_list_info_size = 6;
854165f4
AV		 2816 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2817 ha->optrom_size = OPTROM_SIZE_2322;
3a03eb79
AV		 2818 ha->flash_conf_off = ~0;
2819 ha->flash_data_off = ~0;
2820 ha->nvram_conf_off = ~0;
2821 ha->nvram_data_off = ~0;
fd34f556 2822 ha->isp_ops = &qla2300_isp_ops;
4d4df193 2823 } else if (IS_QLA24XX_TYPE(ha)) {
642ef983 2824 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
fca29703 2825 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2826 req_length = REQUEST_ENTRY_CNT_24XX;
2827 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2828 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2829 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2c3dfe3f 2830 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
fca29703 2831 ha->gid_list_info_size = 8;
854165f4 2832 ha->optrom_size = OPTROM_SIZE_24XX;
73208dfd 2833 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
fd34f556 2834 ha->isp_ops = &qla24xx_isp_ops;
3a03eb79
AV		 2835 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2836 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2837 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2838 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
c3a2f0df 2839 } else if (IS_QLA25XX(ha)) {
642ef983 2840 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
c3a2f0df 2841 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e315cd28
AC		 2842 req_length = REQUEST_ENTRY_CNT_24XX;
2843 rsp_length = RESPONSE_ENTRY_CNT_2300;
2d70c103 2844 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
e315cd28 2845 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
c3a2f0df 2846 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
c3a2f0df
AV		 2847 ha->gid_list_info_size = 8;
2848 ha->optrom_size = OPTROM_SIZE_25XX;
73208dfd 2849 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
c3a2f0df 2850 ha->isp_ops = &qla25xx_isp_ops;
3a03eb79
AV		 2851 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2852 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2853 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2854 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2855 } else if (IS_QLA81XX(ha)) {
642ef983 2856 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3a03eb79
AV		 2857 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2858 req_length = REQUEST_ENTRY_CNT_24XX;
2859 rsp_length = RESPONSE_ENTRY_CNT_2300;
aa230bc5 2860 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3a03eb79
AV		 2861 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2862 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2863 ha->gid_list_info_size = 8;
2864 ha->optrom_size = OPTROM_SIZE_81XX;
40859ae5 2865 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3a03eb79
AV		 2866 ha->isp_ops = &qla81xx_isp_ops;
2867 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2868 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2869 ha->nvram_conf_off = ~0;
2870 ha->nvram_data_off = ~0;
a9083016 2871 } else if (IS_QLA82XX(ha)) {
642ef983 2872 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
a9083016
GM		 2873 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2874 req_length = REQUEST_ENTRY_CNT_82XX;
2875 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2876 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2877 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2878 ha->gid_list_info_size = 8;
2879 ha->optrom_size = OPTROM_SIZE_82XX;
087c621e 2880 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
a9083016
GM		 2881 ha->isp_ops = &qla82xx_isp_ops;
2882 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2883 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2884 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2885 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
7ec0effd
AD		 2886 } else if (IS_QLA8044(ha)) {
2887 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2888 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2889 req_length = REQUEST_ENTRY_CNT_82XX;
2890 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2891 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2892 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2893 ha->gid_list_info_size = 8;
2894 ha->optrom_size = OPTROM_SIZE_83XX;
2895 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2896 ha->isp_ops = &qla8044_isp_ops;
2897 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2898 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2899 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2900 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
6246b8a1 2901 } else if (IS_QLA83XX(ha)) {
7d613ac6 2902 ha->portnum = PCI_FUNC(ha->pdev->devfn);
642ef983 2903 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
6246b8a1 2904 ha->mbx_count = MAILBOX_REGISTER_COUNT;
f2ea653f 2905 req_length = REQUEST_ENTRY_CNT_83XX;
e7b42e33 2906 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b8aa4bdf 2907 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
6246b8a1
GM		 2908 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2909 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2910 ha->gid_list_info_size = 8;
2911 ha->optrom_size = OPTROM_SIZE_83XX;
2912 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2913 ha->isp_ops = &qla83xx_isp_ops;
2914 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2915 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2916 ha->nvram_conf_off = ~0;
2917 ha->nvram_data_off = ~0;
8ae6d9c7
GM		 2918 } else if (IS_QLAFX00(ha)) {
2919 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2920 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2921 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
2922 req_length = REQUEST_ENTRY_CNT_FX00;
2923 rsp_length = RESPONSE_ENTRY_CNT_FX00;
8ae6d9c7
GM		 2924 ha->isp_ops = &qlafx00_isp_ops;
2925 ha->port_down_retry_count = 30; /* default value */
2926 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
2927 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
71e56003 2928 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
8ae6d9c7 2929 ha->mr.fw_hbt_en = 1;
e8f5e95d
AB		 2930 ha->mr.host_info_resend = false;
2931 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
f73cb695
CD		 2932 } else if (IS_QLA27XX(ha)) {
2933 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2934 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2935 ha->mbx_count = MAILBOX_REGISTER_COUNT;
e7b42e33
QT		 2936 req_length = REQUEST_ENTRY_CNT_83XX;
2937 rsp_length = RESPONSE_ENTRY_CNT_83XX;
b20f02e1 2938 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
f73cb695
CD		 2939 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2940 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2941 ha->gid_list_info_size = 8;
2942 ha->optrom_size = OPTROM_SIZE_83XX;
2943 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2944 ha->isp_ops = &qla27xx_isp_ops;
2945 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2946 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2947 ha->nvram_conf_off = ~0;
2948 ha->nvram_data_off = ~0;
1da177e4 2949 }
6246b8a1 2950
7c3df132
SK		 2951 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
2952 "mbx_count=%d, req_length=%d, "
2953 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
642ef983
CD		 2954 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
2955 "max_fibre_devices=%d.\n",
7c3df132
SK		 2956 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
2957 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
642ef983 2958 ha->nvram_npiv_size, ha->max_fibre_devices);
7c3df132
SK		 2959 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
2960 "isp_ops=%p, flash_conf_off=%d, "
2961 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
2962 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
2963 ha->nvram_conf_off, ha->nvram_data_off);
706f457d
GM		 2964
2965 /* Configure PCI I/O space */
2966 ret = ha->isp_ops->iospace_config(ha);
2967 if (ret)
0a63ad12 2968 goto iospace_config_failed;
706f457d
GM		 2969
2970 ql_log_pci(ql_log_info, pdev, 0x001d,
2971 "Found an ISP%04X irq %d iobase 0x%p.\n",
2972 pdev->device, pdev->irq, ha->iobase);
6c2f527c 2973 mutex_init(&ha->vport_lock);
d7459527 2974 mutex_init(&ha->mq_lock);
0b05a1f0
MB		 2975 init_completion(&ha->mbx_cmd_comp);
2976 complete(&ha->mbx_cmd_comp);
2977 init_completion(&ha->mbx_intr_comp);
23f2ebd1 2978 init_completion(&ha->dcbx_comp);
f356bef1 2979 init_completion(&ha->lb_portup_comp);
1da177e4 2980
2c3dfe3f 2981 set_bit(0, (unsigned long *) ha->vp_idx_map);
1da177e4 2982
53303c42 2983 qla2x00_config_dma_addressing(ha);
7c3df132
SK		 2984 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
2985 "64 Bit addressing is %s.\n",
2986 ha->flags.enable_64bit_addressing ? "enable" :
2987 "disable");
73208dfd 2988 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
b2a72ec3 2989 if (ret) {
7c3df132
SK		 2990 ql_log_pci(ql_log_fatal, pdev, 0x0031,
2991 "Failed to allocate memory for adapter, aborting.\n");
1da177e4 2992
e315cd28
AC		 2993 goto probe_hw_failed;
2994 }
2995
73208dfd 2996 req->max_q_depth = MAX_Q_DEPTH;
e315cd28 2997 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
73208dfd
AC		 2998 req->max_q_depth = ql2xmaxqdepth;
2999
e315cd28
AC		 3000
3001 base_vha = qla2x00_create_host(sht, ha);
3002 if (!base_vha) {
a1541d5a 3003 ret = -ENOMEM;
6e9f21f3 3004 qla2x00_mem_free(ha);
2afa19a9
AC		 3005 qla2x00_free_req_que(ha, req);
3006 qla2x00_free_rsp_que(ha, rsp);
e315cd28 3007 goto probe_hw_failed;
1da177e4
LT		 3008 }
3009
e315cd28 3010 pci_set_drvdata(pdev, base_vha);
6b383979 3011 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
e315cd28 3012
e315cd28 3013 host = base_vha->host;
2afa19a9 3014 base_vha->req = req;
73208dfd 3015 if (IS_QLA2XXX_MIDTYPE(ha))
e315cd28 3016 base_vha->mgmt_svr_loop_id = 10 + base_vha->vp_idx;
73208dfd 3017 else
e315cd28
AC		 3018 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3019 base_vha->vp_idx;
58548cb5 3020
8ae6d9c7
GM		 3021 /* Setup fcport template structure. */
3022 ha->mr.fcport.vha = base_vha;
3023 ha->mr.fcport.port_type = FCT_UNKNOWN;
3024 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3025 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3026 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3027 ha->mr.fcport.scan_state = 1;
3028
58548cb5
GM		 3029 /* Set the SG table size based on ISP type */
3030 if (!IS_FWI2_CAPABLE(ha)) {
3031 if (IS_QLA2100(ha))
3032 host->sg_tablesize = 32;
3033 } else {
3034 if (!IS_QLA82XX(ha))
3035 host->sg_tablesize = QLA_SG_ALL;
3036 }
642ef983 3037 host->max_id = ha->max_fibre_devices;
e315cd28
AC		 3038 host->cmd_per_lun = 3;
3039 host->unique_id = host->host_no;
e02587d7 3040 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
0c470874
AE		 3041 host->max_cmd_len = 32;
3042 else
3043 host->max_cmd_len = MAX_CMDSZ;
e315cd28 3044 host->max_channel = MAX_BUSES - 1;
755f516b
HR		 3045 /* Older HBAs support only 16-bit LUNs */
3046 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3047 ql2xmaxlun > 0xffff)
3048 host->max_lun = 0xffff;
3049 else
3050 host->max_lun = ql2xmaxlun;
e315cd28 3051 host->transportt = qla2xxx_transport_template;
9a069e19 3052 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
e315cd28 3053
7c3df132
SK		 3054 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3055 "max_id=%d this_id=%d "
3056 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
1abf635d 3057 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
7c3df132
SK		 3058 host->this_id, host->cmd_per_lun, host->unique_id,
3059 host->max_cmd_len, host->max_channel, host->max_lun,
3060 host->transportt, sht->vendor_id);
3061
d7459527
MH		 3062 /* Set up the irqs */
3063 ret = qla2x00_request_irqs(ha, rsp);
3064 if (ret)
3065 goto probe_init_failed;
3066
9a347ff4
CD		 3067 /* Alloc arrays of request and response ring ptrs */
3068 if (!qla2x00_alloc_queues(ha, req, rsp)) {
3069 ql_log(ql_log_fatal, base_vha, 0x003d,
3070 "Failed to allocate memory for queue pointers..."
3071 "aborting.\n");
3072 goto probe_init_failed;
3073 }
3074
5601236b
MH		 3075 if (ha->mqenable && shost_use_blk_mq(host)) {
3076 /* number of hardware queues supported by blk/scsi-mq*/
3077 host->nr_hw_queues = ha->max_qpairs;
3078
3079 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3080 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3081 } else
3082 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3083 "blk/scsi-mq disabled.\n");
3084
2d70c103 3085 qlt_probe_one_stage1(base_vha, ha);
9a347ff4 3086
90a86fc0
JC		 3087 pci_save_state(pdev);
3088
9a347ff4 3089 /* Assign back pointers */
2afa19a9
AC		 3090 rsp->req = req;
3091 req->rsp = rsp;
9a347ff4 3092
8ae6d9c7
GM		 3093 if (IS_QLAFX00(ha)) {
3094 ha->rsp_q_map[0] = rsp;
3095 ha->req_q_map[0] = req;
3096 set_bit(0, ha->req_qid_map);
3097 set_bit(0, ha->rsp_qid_map);
3098 }
3099
08029990
AV		 3100 /* FWI2-capable only. */
3101 req->req_q_in = &ha->iobase->isp24.req_q_in;
3102 req->req_q_out = &ha->iobase->isp24.req_q_out;
3103 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3104 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
f73cb695 3105 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
08029990
AV		 3106 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3107 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3108 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3109 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
17d98630
AC		 3110 }
3111
8ae6d9c7
GM		 3112 if (IS_QLAFX00(ha)) {
3113 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3114 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3115 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3116 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3117 }
3118
7ec0effd 3119 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3120 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3121 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3122 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3123 }
3124
7c3df132
SK		 3125 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3126 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3127 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3128 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3129 "req->req_q_in=%p req->req_q_out=%p "
3130 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3131 req->req_q_in, req->req_q_out,
3132 rsp->rsp_q_in, rsp->rsp_q_out);
3133 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3134 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3135 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3136 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3137 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3138 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
1da177e4 3139
8ae6d9c7 3140 if (ha->isp_ops->initialize_adapter(base_vha)) {
7c3df132
SK		 3141 ql_log(ql_log_fatal, base_vha, 0x00d6,
3142 "Failed to initialize adapter - Adapter flags %x.\n",
3143 base_vha->device_flags);
1da177e4 3144
a9083016
GM		 3145 if (IS_QLA82XX(ha)) {
3146 qla82xx_idc_lock(ha);
3147 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 3148 QLA8XXX_DEV_FAILED);
a9083016 3149 qla82xx_idc_unlock(ha);
7c3df132
SK		 3150 ql_log(ql_log_fatal, base_vha, 0x00d7,
3151 "HW State: FAILED.\n");
7ec0effd
AD		 3152 } else if (IS_QLA8044(ha)) {
3153 qla8044_idc_lock(ha);
3154 qla8044_wr_direct(base_vha,
3155 QLA8044_CRB_DEV_STATE_INDEX,
3156 QLA8XXX_DEV_FAILED);
3157 qla8044_idc_unlock(ha);
3158 ql_log(ql_log_fatal, base_vha, 0x0150,
3159 "HW State: FAILED.\n");
a9083016
GM		 3160 }
3161
a1541d5a 3162 ret = -ENODEV;
1da177e4
LT		 3163 goto probe_failed;
3164 }
3165
3b1bef64
CD		 3166 if (IS_QLAFX00(ha))
3167 host->can_queue = QLAFX00_MAX_CANQUEUE;
3168 else
3169 host->can_queue = req->num_outstanding_cmds - 10;
3170
3171 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3172 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3173 host->can_queue, base_vha->req,
3174 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3175
e326d22a
QT		 3176 if (ha->mqenable) {
3177 bool mq = false;
3178 bool startit = false;
18ada18e 3179 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM, 0);
e326d22a
QT		 3180
3181 if (QLA_TGT_MODE_ENABLED()) {
3182 mq = true;
3183 startit = false;
3184 }
3185
3186 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3187 shost_use_blk_mq(host)) {
3188 mq = true;
3189 startit = true;
3190 }
3191
3192 if (mq) {
3193 /* Create start of day qpairs for Block MQ */
5601236b 3194 for (i = 0; i < ha->max_qpairs; i++)
e326d22a 3195 qla2xxx_create_qpair(base_vha, 5, 0, startit);
5601236b
MH		 3196 }
3197 }
68ca949c 3198
cbc8eb67
AV		 3199 if (ha->flags.running_gold_fw)
3200 goto skip_dpc;
3201
1da177e4
LT		 3202 /*
3203 * Startup the kernel thread for this host adapter
3204 */
39a11240 3205 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
7c3df132 3206 "%s_dpc", base_vha->host_str);
39a11240 3207 if (IS_ERR(ha->dpc_thread)) {
7c3df132
SK		 3208 ql_log(ql_log_fatal, base_vha, 0x00ed,
3209 "Failed to start DPC thread.\n");
39a11240 3210 ret = PTR_ERR(ha->dpc_thread);
1da177e4
LT		 3211 goto probe_failed;
3212 }
7c3df132
SK		 3213 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3214 "DPC thread started successfully.\n");
1da177e4 3215
2d70c103
NB		 3216 /*
3217 * If we're not coming up in initiator mode, we might sit for
3218 * a while without waking up the dpc thread, which leads to a
3219 * stuck process warning. So just kick the dpc once here and
3220 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3221 */
3222 qla2xxx_wake_dpc(base_vha);
3223
ec7193e2 3224 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
f3ddac19
CD		 3225 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3226
81178772
SK		 3227 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3228 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3229 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3230 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3231
3232 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3233 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3234 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3235 INIT_WORK(&ha->idc_state_handler,
3236 qla83xx_idc_state_handler_work);
3237 INIT_WORK(&ha->nic_core_unrecoverable,
3238 qla83xx_nic_core_unrecoverable_work);
3239 }
3240
cbc8eb67 3241skip_dpc:
e315cd28
AC		 3242 list_add_tail(&base_vha->list, &ha->vp_list);
3243 base_vha->host->irq = ha->pdev->irq;
1da177e4
LT		 3244
3245 /* Initialized the timer */
8e5f4ba0 3246 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
7c3df132
SK		 3247 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3248 "Started qla2x00_timer with "
3249 "interval=%d.\n", WATCH_INTERVAL);
3250 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3251 "Detected hba at address=%p.\n",
3252 ha);
d19044c3 3253
e02587d7 3254 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
bad75002 3255 if (ha->fw_attributes & BIT_4) {
9e522cd8 3256 int prot = 0, guard;
bad75002 3257 base_vha->flags.difdix_supported = 1;
7c3df132
SK		 3258 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3259 "Registering for DIF/DIX type 1 and 3 protection.\n");
8cb2049c
AE		 3260 if (ql2xenabledif == 1)
3261 prot = SHOST_DIX_TYPE0_PROTECTION;
bad75002 3262 scsi_host_set_prot(host,
8cb2049c 3263 prot | SHOST_DIF_TYPE1_PROTECTION
0c470874 3264 | SHOST_DIF_TYPE2_PROTECTION
bad75002
AE		 3265 | SHOST_DIF_TYPE3_PROTECTION
3266 | SHOST_DIX_TYPE1_PROTECTION
0c470874 3267 | SHOST_DIX_TYPE2_PROTECTION
bad75002 3268 | SHOST_DIX_TYPE3_PROTECTION);
9e522cd8
AE		 3269
3270 guard = SHOST_DIX_GUARD_CRC;
3271
3272 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3273 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3274 guard |= SHOST_DIX_GUARD_IP;
3275
3276 scsi_host_set_guard(host, guard);
bad75002
AE		 3277 } else
3278 base_vha->flags.difdix_supported = 0;
3279 }
3280
a9083016
GM		 3281 ha->isp_ops->enable_intrs(ha);
3282
1fe19ee4
AB		 3283 if (IS_QLAFX00(ha)) {
3284 ret = qlafx00_fx_disc(base_vha,
3285 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3286 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3287 QLA_SG_ALL : 128;
3288 }
3289
a1541d5a
AV		 3290 ret = scsi_add_host(host, &pdev->dev);
3291 if (ret)
3292 goto probe_failed;
3293
1486400f
MR		 3294 base_vha->flags.init_done = 1;
3295 base_vha->flags.online = 1;
edaa5c74 3296 ha->prev_minidump_failed = 0;
1486400f 3297
7c3df132
SK		 3298 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3299 "Init done and hba is online.\n");
3300
726b8548
QT		 3301 if (qla_ini_mode_enabled(base_vha) ||
3302 qla_dual_mode_enabled(base_vha))
2d70c103
NB		 3303 scsi_scan_host(host);
3304 else
3305 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3306 "skipping scsi_scan_host() for non-initiator port\n");
1e99e33a 3307
e315cd28 3308 qla2x00_alloc_sysfs_attr(base_vha);
a1541d5a 3309
8ae6d9c7 3310 if (IS_QLAFX00(ha)) {
8ae6d9c7
GM		 3311 ret = qlafx00_fx_disc(base_vha,
3312 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3313
3314 /* Register system information */
3315 ret = qlafx00_fx_disc(base_vha,
3316 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3317 }
3318
e315cd28 3319 qla2x00_init_host_attr(base_vha);
a1541d5a 3320
e315cd28 3321 qla2x00_dfs_setup(base_vha);
df613b96 3322
03eb912a
AB		 3323 ql_log(ql_log_info, base_vha, 0x00fb,
3324 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
7c3df132
SK		 3325 ql_log(ql_log_info, base_vha, 0x00fc,
3326 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3327 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3328 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3329 base_vha->host_no,
df57caba 3330 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
1da177e4 3331
2d70c103
NB		 3332 qlt_add_target(ha, base_vha);
3333
6b383979 3334 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
a29b3dd7
JC		 3335
3336 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3337 return -ENODEV;
3338
e4e3a2ce
QT		 3339 if (ha->flags.detected_lr_sfp) {
3340 ql_log(ql_log_info, base_vha, 0xffff,
3341 "Reset chip to pick up LR SFP setting\n");
3342 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3343 qla2xxx_wake_dpc(base_vha);
3344 }
3345
1da177e4
LT		 3346 return 0;
3347
6e9f21f3 3348probe_init_failed:
2afa19a9 3349 qla2x00_free_req_que(ha, req);
9a347ff4
CD		 3350 ha->req_q_map[0] = NULL;
3351 clear_bit(0, ha->req_qid_map);
2afa19a9 3352 qla2x00_free_rsp_que(ha, rsp);
9a347ff4
CD		 3353 ha->rsp_q_map[0] = NULL;
3354 clear_bit(0, ha->rsp_qid_map);
2afa19a9 3355 ha->max_req_queues = ha->max_rsp_queues = 0;
6e9f21f3 3356
1da177e4 3357probe_failed:
b9978769
AV		 3358 if (base_vha->timer_active)
3359 qla2x00_stop_timer(base_vha);
3360 base_vha->flags.online = 0;
3361 if (ha->dpc_thread) {
3362 struct task_struct *t = ha->dpc_thread;
3363
3364 ha->dpc_thread = NULL;
3365 kthread_stop(t);
3366 }
3367
e315cd28 3368 qla2x00_free_device(base_vha);
1da177e4 3369
e315cd28 3370 scsi_host_put(base_vha->host);
1da177e4 3371
e315cd28 3372probe_hw_failed:
1a2fbf18
JL		 3373 qla2x00_clear_drv_active(ha);
3374
0a63ad12 3375iospace_config_failed:
7ec0effd 3376 if (IS_P3P_TYPE(ha)) {
0a63ad12 3377 if (!ha->nx_pcibase)
f73cb695 3378 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3379 if (!ql2xdbwr)
f73cb695 3380 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3381 } else {
3382 if (ha->iobase)
3383 iounmap(ha->iobase);
8ae6d9c7
GM		 3384 if (ha->cregbase)
3385 iounmap(ha->cregbase);
a9083016 3386 }
e315cd28
AC		 3387 pci_release_selected_regions(ha->pdev, ha->bars);
3388 kfree(ha);
1da177e4 3389
ddff7ed4 3390disable_device:
e315cd28 3391 pci_disable_device(pdev);
a1541d5a 3392 return ret;
1da177e4 3393}
1da177e4 3394
e30d1756
MI		 3395static void
3396qla2x00_shutdown(struct pci_dev *pdev)
3397{
3398 scsi_qla_host_t *vha;
3399 struct qla_hw_data *ha;
3400
3401 vha = pci_get_drvdata(pdev);
3402 ha = vha->hw;
3403
efdb5760
SC		 3404 ql_log(ql_log_info, vha, 0xfffa,
3405 "Adapter shutdown\n");
3406
3407 /*
3408 * Prevent future board_disable and wait
3409 * until any pending board_disable has completed.
3410 */
3411 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3412 cancel_work_sync(&ha->board_disable);
3413
3414 if (!atomic_read(&pdev->enable_cnt))
3415 return;
3416
42479343
AB		 3417 /* Notify ISPFX00 firmware */
3418 if (IS_QLAFX00(ha))
3419 qlafx00_driver_shutdown(vha, 20);
3420
e30d1756
MI		 3421 /* Turn-off FCE trace */
3422 if (ha->flags.fce_enabled) {
3423 qla2x00_disable_fce_trace(vha, NULL, NULL);
3424 ha->flags.fce_enabled = 0;
3425 }
3426
3427 /* Turn-off EFT trace */
3428 if (ha->eft)
3429 qla2x00_disable_eft_trace(vha);
3430
3431 /* Stop currently executing firmware. */
3432 qla2x00_try_to_stop_firmware(vha);
3433
3434 /* Turn adapter off line */
3435 vha->flags.online = 0;
3436
3437 /* turn-off interrupts on the card */
3438 if (ha->interrupts_on) {
3439 vha->flags.init_done = 0;
3440 ha->isp_ops->disable_intrs(ha);
3441 }
3442
3443 qla2x00_free_irqs(vha);
3444
3445 qla2x00_free_fw_dump(ha);
61d41f61 3446
61d41f61 3447 pci_disable_device(pdev);
efdb5760
SC		 3448 ql_log(ql_log_info, vha, 0xfffe,
3449 "Adapter shutdown successfully.\n");
e30d1756
MI		 3450}
3451
fe1b806f 3452/* Deletes all the virtual ports for a given ha */
4c993f76 3453static void
fe1b806f 3454qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
1da177e4 3455{
fe1b806f 3456 scsi_qla_host_t *vha;
feafb7b1 3457 unsigned long flags;
e315cd28 3458
43ebf16d
AE		 3459 mutex_lock(&ha->vport_lock);
3460 while (ha->cur_vport_count) {
43ebf16d 3461 spin_lock_irqsave(&ha->vport_slock, flags);
feafb7b1 3462
43ebf16d
AE		 3463 BUG_ON(base_vha->list.next == &ha->vp_list);
3464 /* This assumes first entry in ha->vp_list is always base vha */
3465 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
52c82823 3466 scsi_host_get(vha->host);
feafb7b1 3467
43ebf16d
AE		 3468 spin_unlock_irqrestore(&ha->vport_slock, flags);
3469 mutex_unlock(&ha->vport_lock);
3470
3471 fc_vport_terminate(vha->fc_vport);
3472 scsi_host_put(vha->host);
feafb7b1 3473
43ebf16d 3474 mutex_lock(&ha->vport_lock);
e315cd28 3475 }
43ebf16d 3476 mutex_unlock(&ha->vport_lock);
fe1b806f 3477}
1da177e4 3478
fe1b806f
CD		 3479/* Stops all deferred work threads */
3480static void
3481qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3482{
7d613ac6
SV		 3483 /* Cancel all work and destroy DPC workqueues */
3484 if (ha->dpc_lp_wq) {
3485 cancel_work_sync(&ha->idc_aen);
3486 destroy_workqueue(ha->dpc_lp_wq);
3487 ha->dpc_lp_wq = NULL;
3488 }
3489
3490 if (ha->dpc_hp_wq) {
3491 cancel_work_sync(&ha->nic_core_reset);
3492 cancel_work_sync(&ha->idc_state_handler);
3493 cancel_work_sync(&ha->nic_core_unrecoverable);
3494 destroy_workqueue(ha->dpc_hp_wq);
3495 ha->dpc_hp_wq = NULL;
3496 }
3497
b9978769
AV		 3498 /* Kill the kernel thread for this host */
3499 if (ha->dpc_thread) {
3500 struct task_struct *t = ha->dpc_thread;
3501
3502 /*
3503 * qla2xxx_wake_dpc checks for ->dpc_thread
3504 * so we need to zero it out.
3505 */
3506 ha->dpc_thread = NULL;
3507 kthread_stop(t);
3508 }
fe1b806f 3509}
1da177e4 3510
fe1b806f
CD		 3511static void
3512qla2x00_unmap_iobases(struct qla_hw_data *ha)
3513{
a9083016 3514 if (IS_QLA82XX(ha)) {
b963752f 3515
f73cb695 3516 iounmap((device_reg_t *)ha->nx_pcibase);
a9083016 3517 if (!ql2xdbwr)
f73cb695 3518 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
a9083016
GM		 3519 } else {
3520 if (ha->iobase)
3521 iounmap(ha->iobase);
1da177e4 3522
8ae6d9c7
GM		 3523 if (ha->cregbase)
3524 iounmap(ha->cregbase);
3525
a9083016
GM		 3526 if (ha->mqiobase)
3527 iounmap(ha->mqiobase);
6246b8a1 3528
f73cb695 3529 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
6246b8a1 3530 iounmap(ha->msixbase);
a9083016 3531 }
fe1b806f
CD		 3532}
3533
3534static void
db7157d4 3535qla2x00_clear_drv_active(struct qla_hw_data *ha)
fe1b806f 3536{
fe1b806f
CD		 3537 if (IS_QLA8044(ha)) {
3538 qla8044_idc_lock(ha);
c41afc9a 3539 qla8044_clear_drv_active(ha);
fe1b806f
CD		 3540 qla8044_idc_unlock(ha);
3541 } else if (IS_QLA82XX(ha)) {
3542 qla82xx_idc_lock(ha);
3543 qla82xx_clear_drv_active(ha);
3544 qla82xx_idc_unlock(ha);
3545 }
3546}
3547
3548static void
3549qla2x00_remove_one(struct pci_dev *pdev)
3550{
3551 scsi_qla_host_t *base_vha;
3552 struct qla_hw_data *ha;
3553
beb9e315
JL		 3554 base_vha = pci_get_drvdata(pdev);
3555 ha = base_vha->hw;
3556
3557 /* Indicate device removal to prevent future board_disable and wait
3558 * until any pending board_disable has completed. */
3559 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3560 cancel_work_sync(&ha->board_disable);
3561
fe1b806f 3562 /*
beb9e315
JL		 3563 * If the PCI device is disabled then there was a PCI-disconnect and
3564 * qla2x00_disable_board_on_pci_error has taken care of most of the
3565 * resources.
fe1b806f 3566 */
beb9e315 3567 if (!atomic_read(&pdev->enable_cnt)) {
726b8548
QT		 3568 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3569 base_vha->gnl.l, base_vha->gnl.ldma);
3570
beb9e315
JL		 3571 scsi_host_put(base_vha->host);
3572 kfree(ha);
3573 pci_set_drvdata(pdev, NULL);
fe1b806f 3574 return;
beb9e315 3575 }
638a1a01
SC		 3576 qla2x00_wait_for_hba_ready(base_vha);
3577
726b8548
QT		 3578 /*
3579 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 3580 * where it was set first.
3581 */
3582 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3583 return;
3584
fe1b806f 3585 set_bit(UNLOADING, &base_vha->dpc_flags);
e84067d7
DG		 3586
3587 qla_nvme_delete(base_vha);
3588
726b8548
QT		 3589 dma_free_coherent(&ha->pdev->dev,
3590 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
fe1b806f
CD		 3591
3592 if (IS_QLAFX00(ha))
3593 qlafx00_driver_shutdown(base_vha, 20);
3594
3595 qla2x00_delete_all_vps(ha, base_vha);
3596
3597 if (IS_QLA8031(ha)) {
3598 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3599 "Clearing fcoe driver presence.\n");
3600 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3601 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3602 "Error while clearing DRV-Presence.\n");
3603 }
3604
3605 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3606
3607 qla2x00_dfs_remove(base_vha);
3608
3609 qla84xx_put_chip(base_vha);
3610
2d5a4c34
HM		 3611 /* Laser should be disabled only for ISP2031 */
3612 if (IS_QLA2031(ha))
3613 qla83xx_disable_laser(base_vha);
3614
fe1b806f
CD		 3615 /* Disable timer */
3616 if (base_vha->timer_active)
3617 qla2x00_stop_timer(base_vha);
3618
3619 base_vha->flags.online = 0;
3620
b0d6cabd
HM		 3621 /* free DMA memory */
3622 if (ha->exlogin_buf)
3623 qla2x00_free_exlogin_buffer(ha);
3624
2f56a7f1
HM		 3625 /* free DMA memory */
3626 if (ha->exchoffld_buf)
3627 qla2x00_free_exchoffld_buffer(ha);
3628
fe1b806f
CD		 3629 qla2x00_destroy_deferred_work(ha);
3630
3631 qlt_remove_target(ha, base_vha);
3632
3633 qla2x00_free_sysfs_attr(base_vha, true);
3634
3635 fc_remove_host(base_vha->host);
482c9dc7 3636 qlt_remove_target_resources(ha);
fe1b806f
CD		 3637
3638 scsi_remove_host(base_vha->host);
3639
3640 qla2x00_free_device(base_vha);
3641
db7157d4 3642 qla2x00_clear_drv_active(ha);
fe1b806f 3643
d2749ffa
AE		 3644 scsi_host_put(base_vha->host);
3645
fe1b806f 3646 qla2x00_unmap_iobases(ha);
73208dfd 3647
e315cd28
AC		 3648 pci_release_selected_regions(ha->pdev, ha->bars);
3649 kfree(ha);
1da177e4 3650
90a86fc0
JC		 3651 pci_disable_pcie_error_reporting(pdev);
3652
665db93b 3653 pci_disable_device(pdev);
1da177e4 3654}
1da177e4
LT		 3655
3656static void
e315cd28 3657qla2x00_free_device(scsi_qla_host_t *vha)
1da177e4 3658{
e315cd28 3659 struct qla_hw_data *ha = vha->hw;
1da177e4 3660
85880801
AV		 3661 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3662
3663 /* Disable timer */
3664 if (vha->timer_active)
3665 qla2x00_stop_timer(vha);
3666
2afa19a9 3667 qla25xx_delete_queues(vha);
fe1b806f 3668
df613b96 3669 if (ha->flags.fce_enabled)
e315cd28 3670 qla2x00_disable_fce_trace(vha, NULL, NULL);
df613b96 3671
a7a167bf 3672 if (ha->eft)
e315cd28 3673 qla2x00_disable_eft_trace(vha);
a7a167bf 3674
f6ef3b18 3675 /* Stop currently executing firmware. */
e315cd28 3676 qla2x00_try_to_stop_firmware(vha);
1da177e4 3677
85880801
AV		 3678 vha->flags.online = 0;
3679
f6ef3b18 3680 /* turn-off interrupts on the card */
a9083016
GM		 3681 if (ha->interrupts_on) {
3682 vha->flags.init_done = 0;
fd34f556 3683 ha->isp_ops->disable_intrs(ha);
a9083016 3684 }
f6ef3b18 3685
093df737
QT		 3686 qla2x00_free_fcports(vha);
3687
e315cd28 3688 qla2x00_free_irqs(vha);
1da177e4 3689
093df737
QT		 3690 /* Flush the work queue and remove it */
3691 if (ha->wq) {
3692 flush_workqueue(ha->wq);
3693 destroy_workqueue(ha->wq);
3694 ha->wq = NULL;
3695 }
3696
8867048b 3697
e315cd28 3698 qla2x00_mem_free(ha);
73208dfd 3699
08de2844
GM		 3700 qla82xx_md_free(vha);
3701
73208dfd 3702 qla2x00_free_queues(ha);
1da177e4
LT		 3703}
3704
8867048b
CD		 3705void qla2x00_free_fcports(struct scsi_qla_host *vha)
3706{
3707 fc_port_t *fcport, *tfcport;
3708
3709 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3710 list_del(&fcport->list);
5f16b331 3711 qla2x00_clear_loop_id(fcport);
8867048b 3712 kfree(fcport);
8867048b
CD		 3713 }
3714}
3715
d97994dc 3716static inline void
e315cd28 3717qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
d97994dc
AV		 3718 int defer)
3719{
d97994dc 3720 struct fc_rport *rport;
67becc00 3721 scsi_qla_host_t *base_vha;
044d78e1 3722 unsigned long flags;
d97994dc
AV		 3723
3724 if (!fcport->rport)
3725 return;
3726
3727 rport = fcport->rport;
3728 if (defer) {
67becc00 3729 base_vha = pci_get_drvdata(vha->hw->pdev);
044d78e1 3730 spin_lock_irqsave(vha->host->host_lock, flags);
d97994dc 3731 fcport->drport = rport;
044d78e1 3732 spin_unlock_irqrestore(vha->host->host_lock, flags);
df673274 3733 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
67becc00
AV		 3734 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3735 qla2xxx_wake_dpc(base_vha);
2d70c103 3736 } else {
df673274 3737 int now;
726b8548 3738 if (rport) {
83548fe2
QT		 3739 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3740 "%s %8phN. rport %p roles %x\n",
3741 __func__, fcport->port_name, rport,
3742 rport->roles);
d20ed91b 3743 fc_remote_port_delete(rport);
726b8548 3744 }
df673274 3745 qlt_do_generation_tick(vha, &now);
2d70c103 3746 }
d97994dc
AV		 3747}
3748
1da177e4
LT		 3749/*
3750 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3751 *
3752 * Input: ha = adapter block pointer. fcport = port structure pointer.
3753 *
3754 * Return: None.
3755 *
3756 * Context:
3757 */
e315cd28 3758void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
d97994dc 3759 int do_login, int defer)
1da177e4 3760{
8ae6d9c7
GM		 3761 if (IS_QLAFX00(vha->hw)) {
3762 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3763 qla2x00_schedule_rport_del(vha, fcport, defer);
3764 return;
3765 }
3766
2c3dfe3f 3767 if (atomic_read(&fcport->state) == FCS_ONLINE &&
c6d39e23 3768 vha->vp_idx == fcport->vha->vp_idx) {
ec426e10 3769 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
e315cd28
AC		 3770 qla2x00_schedule_rport_del(vha, fcport, defer);
3771 }
fa2a1ce5 3772 /*
1da177e4
LT		 3773 * We may need to retry the login, so don't change the state of the
3774 * port but do the retries.
3775 */
3776 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
ec426e10 3777 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
1da177e4
LT		 3778
3779 if (!do_login)
3780 return;
3781
a1d0285e
AE		 3782 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3783
1da177e4 3784 if (fcport->login_retry == 0) {
e315cd28 3785 fcport->login_retry = vha->hw->login_retry_count;
1da177e4 3786
83548fe2 3787 ql_dbg(ql_dbg_disc, vha, 0x20a3,
726b8548 3788 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n",
7b833558 3789 fcport->port_name, fcport->loop_id, fcport->login_retry);
1da177e4
LT		 3790 }
3791}
3792
3793/*
3794 * qla2x00_mark_all_devices_lost
3795 * Updates fcport state when device goes offline.
3796 *
3797 * Input:
3798 * ha = adapter block pointer.
3799 * fcport = port structure pointer.
3800 *
3801 * Return:
3802 * None.
3803 *
3804 * Context:
3805 */
3806void
e315cd28 3807qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
1da177e4
LT		 3808{
3809 fc_port_t *fcport;
3810
83548fe2
QT		 3811 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3812 "Mark all dev lost\n");
726b8548 3813
e315cd28 3814 list_for_each_entry(fcport, &vha->vp_fcports, list) {
726b8548
QT		 3815 fcport->scan_state = 0;
3816 qlt_schedule_sess_for_deletion_lock(fcport);
3817
c6d39e23 3818 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
1da177e4 3819 continue;
0d6e61bc 3820
1da177e4
LT		 3821 /*
3822 * No point in marking the device as lost, if the device is
3823 * already DEAD.
3824 */
3825 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3826 continue;
e315cd28 3827 if (atomic_read(&fcport->state) == FCS_ONLINE) {
ec426e10 3828 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
0d6e61bc
AV		 3829 if (defer)
3830 qla2x00_schedule_rport_del(vha, fcport, defer);
c6d39e23 3831 else if (vha->vp_idx == fcport->vha->vp_idx)
0d6e61bc
AV		 3832 qla2x00_schedule_rport_del(vha, fcport, defer);
3833 }
1da177e4
LT		 3834 }
3835}
3836
3837/*
3838* qla2x00_mem_alloc
3839* Allocates adapter memory.
3840*
3841* Returns:
3842* 0 = success.
e8711085 3843* !0 = failure.
1da177e4 3844*/
e8711085 3845static int
73208dfd
AC		 3846qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3847 struct req_que **req, struct rsp_que **rsp)
1da177e4
LT		 3848{
3849 char name[16];
1da177e4 3850
e8711085 3851 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
e315cd28 3852 &ha->init_cb_dma, GFP_KERNEL);
e8711085 3853 if (!ha->init_cb)
e315cd28 3854 goto fail;
e8711085 3855
2d70c103
NB		 3856 if (qlt_mem_alloc(ha) < 0)
3857 goto fail_free_init_cb;
3858
642ef983
CD		 3859 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3860 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
e315cd28 3861 if (!ha->gid_list)
2d70c103 3862 goto fail_free_tgt_mem;
1da177e4 3863
e8711085
AV		 3864 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3865 if (!ha->srb_mempool)
e315cd28 3866 goto fail_free_gid_list;
e8711085 3867
7ec0effd 3868 if (IS_P3P_TYPE(ha)) {
a9083016
GM		 3869 /* Allocate cache for CT6 Ctx. */
3870 if (!ctx_cachep) {
3871 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3872 sizeof(struct ct6_dsd), 0,
3873 SLAB_HWCACHE_ALIGN, NULL);
3874 if (!ctx_cachep)
fc1ffd6c 3875 goto fail_free_srb_mempool;
a9083016
GM		 3876 }
3877 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3878 ctx_cachep);
3879 if (!ha->ctx_mempool)
3880 goto fail_free_srb_mempool;
7c3df132
SK		 3881 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3882 "ctx_cachep=%p ctx_mempool=%p.\n",
3883 ctx_cachep, ha->ctx_mempool);
a9083016
GM		 3884 }
3885
e8711085
AV		 3886 /* Get memory for cached NVRAM */
3887 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3888 if (!ha->nvram)
a9083016 3889 goto fail_free_ctx_mempool;
e8711085 3890
e315cd28
AC		 3891 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3892 ha->pdev->device);
3893 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3894 DMA_POOL_SIZE, 8, 0);
3895 if (!ha->s_dma_pool)
3896 goto fail_free_nvram;
3897
7c3df132
SK		 3898 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3899 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3900 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3901
7ec0effd 3902 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
a9083016
GM		 3903 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3904 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3905 if (!ha->dl_dma_pool) {
7c3df132
SK		 3906 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3907 "Failed to allocate memory for dl_dma_pool.\n");
a9083016
GM		 3908 goto fail_s_dma_pool;
3909 }
3910
3911 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3912 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3913 if (!ha->fcp_cmnd_dma_pool) {
7c3df132
SK		 3914 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
3915 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
a9083016
GM		 3916 goto fail_dl_dma_pool;
3917 }
7c3df132
SK		 3918 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
3919 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
3920 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
a9083016
GM		 3921 }
3922
e8711085
AV		 3923 /* Allocate memory for SNS commands */
3924 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
e315cd28 3925 /* Get consistent memory allocated for SNS commands */
e8711085 3926 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3927 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
e8711085 3928 if (!ha->sns_cmd)
e315cd28 3929 goto fail_dma_pool;
7c3df132 3930 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
d8424f68 3931 "sns_cmd: %p.\n", ha->sns_cmd);
e8711085 3932 } else {
e315cd28 3933 /* Get consistent memory allocated for MS IOCB */
e8711085 3934 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
e315cd28 3935 &ha->ms_iocb_dma);
e8711085 3936 if (!ha->ms_iocb)
e315cd28
AC		 3937 goto fail_dma_pool;
3938 /* Get consistent memory allocated for CT SNS commands */
e8711085 3939 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
e315cd28 3940 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
e8711085
AV		 3941 if (!ha->ct_sns)
3942 goto fail_free_ms_iocb;
7c3df132
SK		 3943 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
3944 "ms_iocb=%p ct_sns=%p.\n",
3945 ha->ms_iocb, ha->ct_sns);
1da177e4
LT		 3946 }
3947
e315cd28 3948 /* Allocate memory for request ring */
73208dfd
AC		 3949 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
3950 if (!*req) {
7c3df132
SK		 3951 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
3952 "Failed to allocate memory for req.\n");
e315cd28
AC		 3953 goto fail_req;
3954 }
73208dfd
AC		 3955 (*req)->length = req_len;
3956 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
3957 ((*req)->length + 1) * sizeof(request_t),
3958 &(*req)->dma, GFP_KERNEL);
3959 if (!(*req)->ring) {
7c3df132
SK		 3960 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
3961 "Failed to allocate memory for req_ring.\n");
e315cd28
AC		 3962 goto fail_req_ring;
3963 }
3964 /* Allocate memory for response ring */
73208dfd
AC		 3965 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
3966 if (!*rsp) {
7c3df132
SK		 3967 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
3968 "Failed to allocate memory for rsp.\n");
e315cd28
AC		 3969 goto fail_rsp;
3970 }
73208dfd
AC		 3971 (*rsp)->hw = ha;
3972 (*rsp)->length = rsp_len;
3973 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
3974 ((*rsp)->length + 1) * sizeof(response_t),
3975 &(*rsp)->dma, GFP_KERNEL);
3976 if (!(*rsp)->ring) {
7c3df132
SK		 3977 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
3978 "Failed to allocate memory for rsp_ring.\n");
e315cd28
AC		 3979 goto fail_rsp_ring;
3980 }
73208dfd
AC		 3981 (*req)->rsp = *rsp;
3982 (*rsp)->req = *req;
7c3df132
SK		 3983 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
3984 "req=%p req->length=%d req->ring=%p rsp=%p "
3985 "rsp->length=%d rsp->ring=%p.\n",
3986 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
3987 (*rsp)->ring);
73208dfd
AC		 3988 /* Allocate memory for NVRAM data for vports */
3989 if (ha->nvram_npiv_size) {
3990 ha->npiv_info = kzalloc(sizeof(struct qla_npiv_entry) *
7c3df132 3991 ha->nvram_npiv_size, GFP_KERNEL);
73208dfd 3992 if (!ha->npiv_info) {
7c3df132
SK		 3993 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
3994 "Failed to allocate memory for npiv_info.\n");
73208dfd
AC		 3995 goto fail_npiv_info;
3996 }
3997 } else
3998 ha->npiv_info = NULL;
e8711085 3999
b64b0e8f 4000 /* Get consistent memory allocated for EX-INIT-CB. */
f73cb695 4001 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
b64b0e8f
AV		 4002 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4003 &ha->ex_init_cb_dma);
4004 if (!ha->ex_init_cb)
4005 goto fail_ex_init_cb;
7c3df132
SK		 4006 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4007 "ex_init_cb=%p.\n", ha->ex_init_cb);
b64b0e8f
AV		 4008 }
4009
a9083016
GM		 4010 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4011
5ff1d584
AV		 4012 /* Get consistent memory allocated for Async Port-Database. */
4013 if (!IS_FWI2_CAPABLE(ha)) {
4014 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4015 &ha->async_pd_dma);
4016 if (!ha->async_pd)
4017 goto fail_async_pd;
7c3df132
SK		 4018 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4019 "async_pd=%p.\n", ha->async_pd);
5ff1d584
AV		 4020 }
4021
e315cd28 4022 INIT_LIST_HEAD(&ha->vp_list);
5f16b331
CD		 4023
4024 /* Allocate memory for our loop_id bitmap */
4025 ha->loop_id_map = kzalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE) * sizeof(long),
4026 GFP_KERNEL);
4027 if (!ha->loop_id_map)
fc1ffd6c 4028 goto fail_loop_id_map;
5f16b331
CD		 4029 else {
4030 qla2x00_set_reserved_loop_ids(ha);
4031 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
b2a72ec3 4032 "loop_id_map=%p.\n", ha->loop_id_map);
5f16b331
CD		 4033 }
4034
e4e3a2ce
QT		 4035 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4036 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4037 if (!ha->sfp_data) {
4038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4039 "Unable to allocate memory for SFP read-data.\n");
4040 goto fail_sfp_data;
4041 }
4042
b2a72ec3 4043 return 0;
e315cd28 4044
e4e3a2ce
QT		 4045fail_sfp_data:
4046 kfree(ha->loop_id_map);
fc1ffd6c
QT		 4047fail_loop_id_map:
4048 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
5ff1d584
AV		 4049fail_async_pd:
4050 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f
AV		 4051fail_ex_init_cb:
4052 kfree(ha->npiv_info);
73208dfd
AC		 4053fail_npiv_info:
4054 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4055 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4056 (*rsp)->ring = NULL;
4057 (*rsp)->dma = 0;
e315cd28 4058fail_rsp_ring:
73208dfd 4059 kfree(*rsp);
e315cd28 4060fail_rsp:
73208dfd
AC		 4061 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4062 sizeof(request_t), (*req)->ring, (*req)->dma);
4063 (*req)->ring = NULL;
4064 (*req)->dma = 0;
e315cd28 4065fail_req_ring:
73208dfd 4066 kfree(*req);
e315cd28
AC		 4067fail_req:
4068 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4069 ha->ct_sns, ha->ct_sns_dma);
4070 ha->ct_sns = NULL;
4071 ha->ct_sns_dma = 0;
e8711085
AV		 4072fail_free_ms_iocb:
4073 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4074 ha->ms_iocb = NULL;
4075 ha->ms_iocb_dma = 0;
fc1ffd6c
QT		 4076
4077 if (ha->sns_cmd)
4078 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4079 ha->sns_cmd, ha->sns_cmd_dma);
e315cd28 4080fail_dma_pool:
bad75002 4081 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4082 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4083 ha->fcp_cmnd_dma_pool = NULL;
4084 }
4085fail_dl_dma_pool:
bad75002 4086 if (IS_QLA82XX(ha) || ql2xenabledif) {
a9083016
GM		 4087 dma_pool_destroy(ha->dl_dma_pool);
4088 ha->dl_dma_pool = NULL;
4089 }
4090fail_s_dma_pool:
e315cd28
AC		 4091 dma_pool_destroy(ha->s_dma_pool);
4092 ha->s_dma_pool = NULL;
e8711085
AV		 4093fail_free_nvram:
4094 kfree(ha->nvram);
4095 ha->nvram = NULL;
a9083016 4096fail_free_ctx_mempool:
fc1ffd6c
QT		 4097 if (ha->ctx_mempool)
4098 mempool_destroy(ha->ctx_mempool);
a9083016 4099 ha->ctx_mempool = NULL;
e8711085 4100fail_free_srb_mempool:
fc1ffd6c
QT		 4101 if (ha->srb_mempool)
4102 mempool_destroy(ha->srb_mempool);
e8711085 4103 ha->srb_mempool = NULL;
e8711085 4104fail_free_gid_list:
642ef983
CD		 4105 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4106 ha->gid_list,
e315cd28 4107 ha->gid_list_dma);
e8711085
AV		 4108 ha->gid_list = NULL;
4109 ha->gid_list_dma = 0;
2d70c103
NB		 4110fail_free_tgt_mem:
4111 qlt_mem_free(ha);
e315cd28
AC		 4112fail_free_init_cb:
4113 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4114 ha->init_cb_dma);
4115 ha->init_cb = NULL;
4116 ha->init_cb_dma = 0;
e8711085 4117fail:
7c3df132
SK		 4118 ql_log(ql_log_fatal, NULL, 0x0030,
4119 "Memory allocation failure.\n");
e8711085 4120 return -ENOMEM;
1da177e4
LT		 4121}
4122
b0d6cabd
HM		 4123int
4124qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4125{
4126 int rval;
4127 uint16_t size, max_cnt, temp;
4128 struct qla_hw_data *ha = vha->hw;
4129
4130 /* Return if we don't need to alloacate any extended logins */
4131 if (!ql2xexlogins)
4132 return QLA_SUCCESS;
4133
99e1b683
QT		 4134 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4135 return QLA_SUCCESS;
4136
b0d6cabd
HM		 4137 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4138 max_cnt = 0;
4139 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4140 if (rval != QLA_SUCCESS) {
4141 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4142 "Failed to get exlogin status.\n");
4143 return rval;
4144 }
4145
4146 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
99e1b683
QT		 4147 temp *= size;
4148
4149 if (temp != ha->exlogin_size) {
4150 qla2x00_free_exlogin_buffer(ha);
4151 ha->exlogin_size = temp;
4152
4153 ql_log(ql_log_info, vha, 0xd024,
4154 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4155 max_cnt, size, temp);
4156
4157 ql_log(ql_log_info, vha, 0xd025,
4158 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4159
4160 /* Get consistent memory for extended logins */
4161 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4162 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4163 if (!ha->exlogin_buf) {
4164 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
b0d6cabd 4165 "Failed to allocate memory for exlogin_buf_dma.\n");
99e1b683
QT		 4166 return -ENOMEM;
4167 }
b0d6cabd
HM		 4168 }
4169
4170 /* Now configure the dma buffer */
4171 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4172 if (rval) {
83548fe2 4173 ql_log(ql_log_fatal, vha, 0xd033,
b0d6cabd
HM		 4174 "Setup extended login buffer ****FAILED****.\n");
4175 qla2x00_free_exlogin_buffer(ha);
4176 }
4177
4178 return rval;
4179}
4180
4181/*
4182* qla2x00_free_exlogin_buffer
4183*
4184* Input:
4185* ha = adapter block pointer
4186*/
4187void
4188qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4189{
4190 if (ha->exlogin_buf) {
4191 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4192 ha->exlogin_buf, ha->exlogin_buf_dma);
4193 ha->exlogin_buf = NULL;
4194 ha->exlogin_size = 0;
4195 }
4196}
4197
99e1b683
QT		 4198static void
4199qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4200{
4201 u32 temp;
4202 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4203
4204 if (qla_ini_mode_enabled(vha)) {
4205 if (ql2xiniexchg > max_cnt)
4206 ql2xiniexchg = max_cnt;
4207
4208 if (ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4209 *ret_cnt = ql2xiniexchg;
4210 } else if (qla_tgt_mode_enabled(vha)) {
4211 if (ql2xexchoffld > max_cnt)
4212 ql2xexchoffld = max_cnt;
4213
4214 if (ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4215 *ret_cnt = ql2xexchoffld;
4216 } else if (qla_dual_mode_enabled(vha)) {
4217 temp = ql2xiniexchg + ql2xexchoffld;
4218 if (temp > max_cnt) {
4219 ql2xiniexchg -= (temp - max_cnt)/2;
4220 ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4221 temp = max_cnt;
4222 }
4223
4224 if (temp > FW_DEF_EXCHANGES_CNT)
4225 *ret_cnt = temp;
4226 }
4227}
4228
2f56a7f1
HM		 4229int
4230qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4231{
4232 int rval;
99e1b683
QT		 4233 u16 size, max_cnt;
4234 u32 temp;
2f56a7f1
HM		 4235 struct qla_hw_data *ha = vha->hw;
4236
99e1b683
QT		 4237 if (!ha->flags.exchoffld_enabled)
4238 return QLA_SUCCESS;
4239
4240 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
2f56a7f1
HM		 4241 return QLA_SUCCESS;
4242
2f56a7f1
HM		 4243 max_cnt = 0;
4244 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4245 if (rval != QLA_SUCCESS) {
4246 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4247 "Failed to get exlogin status.\n");
4248 return rval;
4249 }
4250
99e1b683
QT		 4251 qla2x00_number_of_exch(vha, &temp, max_cnt);
4252 temp *= size;
2f56a7f1 4253
99e1b683
QT		 4254 if (temp != ha->exchoffld_size) {
4255 qla2x00_free_exchoffld_buffer(ha);
4256 ha->exchoffld_size = temp;
4257
4258 ql_log(ql_log_info, vha, 0xd016,
4259 "Exchange offload: max_count=%d, buffers=0x%x, total=%d.\n",
4260 max_cnt, size, temp);
4261
4262 ql_log(ql_log_info, vha, 0xd017,
4263 "Exchange Buffers requested size = 0x%x\n",
4264 ha->exchoffld_size);
4265
4266 /* Get consistent memory for extended logins */
4267 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4268 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4269 if (!ha->exchoffld_buf) {
4270 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4271 "Failed to allocate memory for exchoffld_buf_dma.\n");
4272 return -ENOMEM;
4273 }
2f56a7f1
HM		 4274 }
4275
4276 /* Now configure the dma buffer */
99e1b683 4277 rval = qla_set_exchoffld_mem_cfg(vha);
2f56a7f1
HM		 4278 if (rval) {
4279 ql_log(ql_log_fatal, vha, 0xd02e,
4280 "Setup exchange offload buffer ****FAILED****.\n");
4281 qla2x00_free_exchoffld_buffer(ha);
99e1b683
QT		 4282 } else {
4283 /* re-adjust number of target exchange */
4284 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4285
4286 if (qla_ini_mode_enabled(vha))
4287 icb->exchange_count = 0;
4288 else
4289 icb->exchange_count = cpu_to_le16(ql2xexchoffld);
2f56a7f1
HM		 4290 }
4291
4292 return rval;
4293}
4294
4295/*
4296* qla2x00_free_exchoffld_buffer
4297*
4298* Input:
4299* ha = adapter block pointer
4300*/
4301void
4302qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4303{
4304 if (ha->exchoffld_buf) {
4305 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4306 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4307 ha->exchoffld_buf = NULL;
4308 ha->exchoffld_size = 0;
4309 }
4310}
4311
1da177e4 4312/*
e30d1756
MI		 4313* qla2x00_free_fw_dump
4314* Frees fw dump stuff.
1da177e4
LT		 4315*
4316* Input:
7ec0effd 4317* ha = adapter block pointer
1da177e4 4318*/
a824ebb3 4319static void
e30d1756 4320qla2x00_free_fw_dump(struct qla_hw_data *ha)
1da177e4 4321{
df613b96 4322 if (ha->fce)
f73cb695
CD		 4323 dma_free_coherent(&ha->pdev->dev,
4324 FCE_SIZE, ha->fce, ha->fce_dma);
df613b96 4325
f73cb695
CD		 4326 if (ha->eft)
4327 dma_free_coherent(&ha->pdev->dev,
4328 EFT_SIZE, ha->eft, ha->eft_dma);
4329
4330 if (ha->fw_dump)
a7a167bf 4331 vfree(ha->fw_dump);
f73cb695
CD		 4332 if (ha->fw_dump_template)
4333 vfree(ha->fw_dump_template);
4334
e30d1756
MI		 4335 ha->fce = NULL;
4336 ha->fce_dma = 0;
4337 ha->eft = NULL;
4338 ha->eft_dma = 0;
e30d1756 4339 ha->fw_dumped = 0;
61f098dd 4340 ha->fw_dump_cap_flags = 0;
e30d1756 4341 ha->fw_dump_reading = 0;
f73cb695
CD		 4342 ha->fw_dump = NULL;
4343 ha->fw_dump_len = 0;
4344 ha->fw_dump_template = NULL;
4345 ha->fw_dump_template_len = 0;
e30d1756
MI		 4346}
4347
4348/*
4349* qla2x00_mem_free
4350* Frees all adapter allocated memory.
4351*
4352* Input:
4353* ha = adapter block pointer.
4354*/
4355static void
4356qla2x00_mem_free(struct qla_hw_data *ha)
4357{
4358 qla2x00_free_fw_dump(ha);
4359
81178772
SK		 4360 if (ha->mctp_dump)
4361 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4362 ha->mctp_dump_dma);
4363
e30d1756
MI		 4364 if (ha->srb_mempool)
4365 mempool_destroy(ha->srb_mempool);
a7a167bf 4366
11bbc1d8
AV		 4367 if (ha->dcbx_tlv)
4368 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4369 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4370
ce0423f4
AV		 4371 if (ha->xgmac_data)
4372 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4373 ha->xgmac_data, ha->xgmac_data_dma);
4374
1da177e4
LT		 4375 if (ha->sns_cmd)
4376 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
e315cd28 4377 ha->sns_cmd, ha->sns_cmd_dma);
1da177e4
LT		 4378
4379 if (ha->ct_sns)
4380 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
e315cd28 4381 ha->ct_sns, ha->ct_sns_dma);
1da177e4 4382
88729e53 4383 if (ha->sfp_data)
e4e3a2ce
QT		 4384 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4385 ha->sfp_data_dma);
88729e53 4386
1da177e4
LT		 4387 if (ha->ms_iocb)
4388 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4389
b64b0e8f 4390 if (ha->ex_init_cb)
a9083016
GM		 4391 dma_pool_free(ha->s_dma_pool,
4392 ha->ex_init_cb, ha->ex_init_cb_dma);
b64b0e8f 4393
5ff1d584
AV		 4394 if (ha->async_pd)
4395 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4396
1da177e4
LT		 4397 if (ha->s_dma_pool)
4398 dma_pool_destroy(ha->s_dma_pool);
4399
1da177e4 4400 if (ha->gid_list)
642ef983
CD		 4401 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4402 ha->gid_list, ha->gid_list_dma);
1da177e4 4403
a9083016
GM		 4404 if (IS_QLA82XX(ha)) {
4405 if (!list_empty(&ha->gbl_dsd_list)) {
4406 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4407
4408 /* clean up allocated prev pool */
4409 list_for_each_entry_safe(dsd_ptr,
4410 tdsd_ptr, &ha->gbl_dsd_list, list) {
4411 dma_pool_free(ha->dl_dma_pool,
4412 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4413 list_del(&dsd_ptr->list);
4414 kfree(dsd_ptr);
4415 }
4416 }
4417 }
4418
4419 if (ha->dl_dma_pool)
4420 dma_pool_destroy(ha->dl_dma_pool);
4421
4422 if (ha->fcp_cmnd_dma_pool)
4423 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4424
4425 if (ha->ctx_mempool)
4426 mempool_destroy(ha->ctx_mempool);
4427
2d70c103
NB		 4428 qlt_mem_free(ha);
4429
e315cd28
AC		 4430 if (ha->init_cb)
4431 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
a9083016 4432 ha->init_cb, ha->init_cb_dma);
e315cd28
AC		 4433 vfree(ha->optrom_buffer);
4434 kfree(ha->nvram);
73208dfd 4435 kfree(ha->npiv_info);
7a67735b 4436 kfree(ha->swl);
5f16b331 4437 kfree(ha->loop_id_map);
1da177e4 4438
e8711085 4439 ha->srb_mempool = NULL;
a9083016 4440 ha->ctx_mempool = NULL;
1da177e4
LT		 4441 ha->sns_cmd = NULL;
4442 ha->sns_cmd_dma = 0;
4443 ha->ct_sns = NULL;
4444 ha->ct_sns_dma = 0;
4445 ha->ms_iocb = NULL;
4446 ha->ms_iocb_dma = 0;
1da177e4
LT		 4447 ha->init_cb = NULL;
4448 ha->init_cb_dma = 0;
b64b0e8f
AV		 4449 ha->ex_init_cb = NULL;
4450 ha->ex_init_cb_dma = 0;
5ff1d584
AV		 4451 ha->async_pd = NULL;
4452 ha->async_pd_dma = 0;
1da177e4
LT		 4453
4454 ha->s_dma_pool = NULL;
a9083016
GM		 4455 ha->dl_dma_pool = NULL;
4456 ha->fcp_cmnd_dma_pool = NULL;
1da177e4 4457
1da177e4
LT		 4458 ha->gid_list = NULL;
4459 ha->gid_list_dma = 0;
2d70c103
NB		 4460
4461 ha->tgt.atio_ring = NULL;
4462 ha->tgt.atio_dma = 0;
4463 ha->tgt.tgt_vp_map = NULL;
e315cd28 4464}
1da177e4 4465
e315cd28
AC		 4466struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4467 struct qla_hw_data *ha)
4468{
4469 struct Scsi_Host *host;
4470 struct scsi_qla_host *vha = NULL;
854165f4 4471
e315cd28 4472 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
41dc529a 4473 if (!host) {
7c3df132
SK		 4474 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4475 "Failed to allocate host from the scsi layer, aborting.\n");
41dc529a 4476 return NULL;
e315cd28
AC		 4477 }
4478
4479 /* Clear our data area */
4480 vha = shost_priv(host);
4481 memset(vha, 0, sizeof(scsi_qla_host_t));
4482
4483 vha->host = host;
4484 vha->host_no = host->host_no;
4485 vha->hw = ha;
4486
4487 INIT_LIST_HEAD(&vha->vp_fcports);
4488 INIT_LIST_HEAD(&vha->work_list);
4489 INIT_LIST_HEAD(&vha->list);
8b2f5ff3
SN		 4490 INIT_LIST_HEAD(&vha->qla_cmd_list);
4491 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
71cdc079 4492 INIT_LIST_HEAD(&vha->logo_list);
b7bd104e 4493 INIT_LIST_HEAD(&vha->plogi_ack_list);
d7459527 4494 INIT_LIST_HEAD(&vha->qp_list);
41dc529a 4495 INIT_LIST_HEAD(&vha->gnl.fcports);
a5d42f4c 4496 INIT_LIST_HEAD(&vha->nvme_rport_list);
e315cd28 4497
f999f4c1 4498 spin_lock_init(&vha->work_lock);
8b2f5ff3 4499 spin_lock_init(&vha->cmd_list_lock);
726b8548 4500 init_waitqueue_head(&vha->fcport_waitQ);
c4a9b538 4501 init_waitqueue_head(&vha->vref_waitq);
f999f4c1 4502
2fdbc65e
BVA		 4503 vha->gnl.size = sizeof(struct get_name_list_extended) *
4504 (ha->max_loop_id + 1);
41dc529a
QT		 4505 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4506 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4507 if (!vha->gnl.l) {
83548fe2 4508 ql_log(ql_log_fatal, vha, 0xd04a,
41dc529a
QT		 4509 "Alloc failed for name list.\n");
4510 scsi_remove_host(vha->host);
4511 return NULL;
4512 }
f999f4c1 4513
e315cd28 4514 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
7c3df132
SK		 4515 ql_dbg(ql_dbg_init, vha, 0x0041,
4516 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4517 vha->host, vha->hw, vha,
4518 dev_name(&(ha->pdev->dev)));
4519
e315cd28 4520 return vha;
1da177e4
LT		 4521}
4522
726b8548 4523struct qla_work_evt *
f999f4c1 4524qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
0971de7f
AV		 4525{
4526 struct qla_work_evt *e;
feafb7b1
AE		 4527 uint8_t bail;
4528
4529 QLA_VHA_MARK_BUSY(vha, bail);
4530 if (bail)
4531 return NULL;
0971de7f 4532
f999f4c1 4533 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
feafb7b1
AE		 4534 if (!e) {
4535 QLA_VHA_MARK_NOT_BUSY(vha);
0971de7f 4536 return NULL;
feafb7b1 4537 }
0971de7f
AV		 4538
4539 INIT_LIST_HEAD(&e->list);
4540 e->type = type;
4541 e->flags = QLA_EVT_FLAG_FREE;
4542 return e;
4543}
4544
726b8548 4545int
f999f4c1 4546qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
0971de7f 4547{
f999f4c1 4548 unsigned long flags;
0971de7f 4549
f999f4c1 4550 spin_lock_irqsave(&vha->work_lock, flags);
e315cd28 4551 list_add_tail(&e->list, &vha->work_list);
f999f4c1 4552 spin_unlock_irqrestore(&vha->work_lock, flags);
ec7193e2
QT		 4553
4554 if (QLA_EARLY_LINKUP(vha->hw))
4555 schedule_work(&vha->iocb_work);
4556 else
4557 qla2xxx_wake_dpc(vha);
f999f4c1 4558
0971de7f
AV		 4559 return QLA_SUCCESS;
4560}
4561
4562int
e315cd28 4563qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
0971de7f
AV		 4564 u32 data)
4565{
4566 struct qla_work_evt *e;
4567
f999f4c1 4568 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
0971de7f
AV		 4569 if (!e)
4570 return QLA_FUNCTION_FAILED;
4571
4572 e->u.aen.code = code;
4573 e->u.aen.data = data;
f999f4c1 4574 return qla2x00_post_work(vha, e);
0971de7f
AV		 4575}
4576
8a659571
AV		 4577int
4578qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4579{
4580 struct qla_work_evt *e;
4581
f999f4c1 4582 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
8a659571
AV		 4583 if (!e)
4584 return QLA_FUNCTION_FAILED;
4585
4586 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
f999f4c1 4587 return qla2x00_post_work(vha, e);
8a659571
AV		 4588}
4589
ac280b67
AV		 4590#define qla2x00_post_async_work(name, type) \
4591int qla2x00_post_async_##name##_work( \
4592 struct scsi_qla_host *vha, \
4593 fc_port_t *fcport, uint16_t *data) \
4594{ \
4595 struct qla_work_evt *e; \
4596 \
4597 e = qla2x00_alloc_work(vha, type); \
4598 if (!e) \
4599 return QLA_FUNCTION_FAILED; \
4600 \
4601 e->u.logio.fcport = fcport; \
4602 if (data) { \
4603 e->u.logio.data[0] = data[0]; \
4604 e->u.logio.data[1] = data[1]; \
4605 } \
4606 return qla2x00_post_work(vha, e); \
4607}
4608
4609qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
ac280b67
AV		 4610qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4611qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
5ff1d584
AV		 4612qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4613qla2x00_post_async_work(adisc_done, QLA_EVT_ASYNC_ADISC_DONE);
ac280b67 4614
3420d36c
AV		 4615int
4616qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4617{
4618 struct qla_work_evt *e;
4619
4620 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4621 if (!e)
4622 return QLA_FUNCTION_FAILED;
4623
4624 e->u.uevent.code = code;
4625 return qla2x00_post_work(vha, e);
4626}
4627
4628static void
4629qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4630{
4631 char event_string[40];
4632 char *envp[] = { event_string, NULL };
4633
4634 switch (code) {
4635 case QLA_UEVENT_CODE_FW_DUMP:
4636 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4637 vha->host_no);
4638 break;
4639 default:
4640 /* do nothing */
4641 break;
4642 }
4643 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4644}
4645
8ae6d9c7
GM		 4646int
4647qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4648 uint32_t *data, int cnt)
4649{
4650 struct qla_work_evt *e;
4651
4652 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4653 if (!e)
4654 return QLA_FUNCTION_FAILED;
4655
4656 e->u.aenfx.evtcode = evtcode;
4657 e->u.aenfx.count = cnt;
4658 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4659 return qla2x00_post_work(vha, e);
4660}
4661
726b8548
QT		 4662int qla24xx_post_upd_fcport_work(struct scsi_qla_host *vha, fc_port_t *fcport)
4663{
4664 struct qla_work_evt *e;
4665
4666 e = qla2x00_alloc_work(vha, QLA_EVT_UPD_FCPORT);
4667 if (!e)
4668 return QLA_FUNCTION_FAILED;
4669
4670 e->u.fcport.fcport = fcport;
4671 return qla2x00_post_work(vha, e);
4672}
4673
4674static
4675void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4676{
4677 unsigned long flags;
b5d15312 4678 fc_port_t *fcport = NULL, *tfcp;
726b8548
QT		 4679 struct qlt_plogi_ack_t *pla =
4680 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
b5d15312 4681 uint8_t free_fcport = 0;
726b8548
QT		 4682
4683 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4684 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4685 if (fcport) {
4686 fcport->d_id = e->u.new_sess.id;
4687 if (pla) {
4688 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4689 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4690 /* we took an extra ref_count to prevent PLOGI ACK when
4691 * fcport/sess has not been created.
4692 */
4693 pla->ref_count--;
4694 }
4695 } else {
b5d15312 4696 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
726b8548
QT		 4697 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4698 if (fcport) {
4699 fcport->d_id = e->u.new_sess.id;
4700 fcport->scan_state = QLA_FCPORT_FOUND;
4701 fcport->flags |= FCF_FABRIC_DEVICE;
4702 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4703
4704 memcpy(fcport->port_name, e->u.new_sess.port_name,
4705 WWN_SIZE);
b5d15312
QT		 4706 } else {
4707 ql_dbg(ql_dbg_disc, vha, 0xffff,
4708 "%s %8phC mem alloc fail.\n",
4709 __func__, e->u.new_sess.port_name);
4710
4711 if (pla)
4712 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4713 return;
4714 }
4715
4716 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4717 /* search again to make sure one else got ahead */
4718 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4719 e->u.new_sess.port_name, 1);
4720 if (tfcp) {
4721 /* should rarily happen */
4722 ql_dbg(ql_dbg_disc, vha, 0xffff,
4723 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4724 __func__, tfcp->port_name, tfcp->disc_state,
4725 tfcp->fw_login_state);
4726
4727 free_fcport = 1;
4728 } else {
726b8548
QT		 4729 list_add_tail(&fcport->list, &vha->vp_fcports);
4730
4731 if (pla) {
4732 qlt_plogi_ack_link(vha, pla, fcport,
4733 QLT_PLOGI_LINK_SAME_WWN);
4734 pla->ref_count--;
4735 }
4736 }
4737 }
4738 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4739
4740 if (fcport) {
4741 if (pla)
4742 qlt_plogi_ack_unref(vha, pla);
4743 else
4744 qla24xx_async_gnl(vha, fcport);
4745 }
b5d15312
QT		 4746
4747 if (free_fcport) {
4748 qla2x00_free_fcport(fcport);
4749 if (pla)
4750 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4751 }
726b8548
QT		 4752}
4753
ac280b67 4754void
e315cd28 4755qla2x00_do_work(struct scsi_qla_host *vha)
0971de7f 4756{
f999f4c1
AV		 4757 struct qla_work_evt *e, *tmp;
4758 unsigned long flags;
4759 LIST_HEAD(work);
0971de7f 4760
f999f4c1
AV		 4761 spin_lock_irqsave(&vha->work_lock, flags);
4762 list_splice_init(&vha->work_list, &work);
4763 spin_unlock_irqrestore(&vha->work_lock, flags);
4764
4765 list_for_each_entry_safe(e, tmp, &work, list) {
0971de7f 4766 list_del_init(&e->list);
0971de7f
AV		 4767
4768 switch (e->type) {
4769 case QLA_EVT_AEN:
e315cd28 4770 fc_host_post_event(vha->host, fc_get_event_number(),
0971de7f
AV		 4771 e->u.aen.code, e->u.aen.data);
4772 break;
8a659571
AV		 4773 case QLA_EVT_IDC_ACK:
4774 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
4775 break;
ac280b67
AV		 4776 case QLA_EVT_ASYNC_LOGIN:
4777 qla2x00_async_login(vha, e->u.logio.fcport,
4778 e->u.logio.data);
4779 break;
ac280b67
AV		 4780 case QLA_EVT_ASYNC_LOGOUT:
4781 qla2x00_async_logout(vha, e->u.logio.fcport);
4782 break;
4783 case QLA_EVT_ASYNC_LOGOUT_DONE:
4784 qla2x00_async_logout_done(vha, e->u.logio.fcport,
4785 e->u.logio.data);
4786 break;
5ff1d584
AV		 4787 case QLA_EVT_ASYNC_ADISC:
4788 qla2x00_async_adisc(vha, e->u.logio.fcport,
4789 e->u.logio.data);
4790 break;
4791 case QLA_EVT_ASYNC_ADISC_DONE:
4792 qla2x00_async_adisc_done(vha, e->u.logio.fcport,
4793 e->u.logio.data);
4794 break;
3420d36c
AV		 4795 case QLA_EVT_UEVENT:
4796 qla2x00_uevent_emit(vha, e->u.uevent.code);
4797 break;
8ae6d9c7
GM		 4798 case QLA_EVT_AENFX:
4799 qlafx00_process_aen(vha, e);
4800 break;
726b8548
QT		 4801 case QLA_EVT_GIDPN:
4802 qla24xx_async_gidpn(vha, e->u.fcport.fcport);
4803 break;
4804 case QLA_EVT_GPNID:
4805 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
4806 break;
4807 case QLA_EVT_GPNID_DONE:
4808 qla24xx_async_gpnid_done(vha, e->u.iosb.sp);
4809 break;
4810 case QLA_EVT_NEW_SESS:
4811 qla24xx_create_new_sess(vha, e);
4812 break;
4813 case QLA_EVT_GPDB:
4814 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
4815 e->u.fcport.opt);
4816 break;
a5d42f4c
DG		 4817 case QLA_EVT_PRLI:
4818 qla24xx_async_prli(vha, e->u.fcport.fcport);
4819 break;
726b8548
QT		 4820 case QLA_EVT_GPSC:
4821 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
4822 break;
4823 case QLA_EVT_UPD_FCPORT:
4824 qla2x00_update_fcport(vha, e->u.fcport.fcport);
4825 break;
4826 case QLA_EVT_GNL:
4827 qla24xx_async_gnl(vha, e->u.fcport.fcport);
4828 break;
4829 case QLA_EVT_NACK:
4830 qla24xx_do_nack_work(vha, e);
4831 break;
0971de7f
AV		 4832 }
4833 if (e->flags & QLA_EVT_FLAG_FREE)
4834 kfree(e);
feafb7b1
AE		 4835
4836 /* For each work completed decrement vha ref count */
4837 QLA_VHA_MARK_NOT_BUSY(vha);
e315cd28 4838 }
e315cd28 4839}
f999f4c1 4840
e315cd28
AC		 4841/* Relogins all the fcports of a vport
4842 * Context: dpc thread
4843 */
4844void qla2x00_relogin(struct scsi_qla_host *vha)
4845{
4846 fc_port_t *fcport;
c6b2fca8 4847 int status;
726b8548 4848 struct event_arg ea;
e315cd28
AC		 4849
4850 list_for_each_entry(fcport, &vha->vp_fcports, list) {
4851 /*
4852 * If the port is not ONLINE then try to login
4853 * to it if we haven't run out of retries.
4854 */
5ff1d584
AV		 4855 if (atomic_read(&fcport->state) != FCS_ONLINE &&
4856 fcport->login_retry && !(fcport->flags & FCF_ASYNC_SENT)) {
ac280b67 4857 fcport->login_retry--;
e315cd28 4858 if (fcport->flags & FCF_FABRIC_DEVICE) {
83548fe2 4859 ql_dbg(ql_dbg_disc, fcport->vha, 0x2108,
726b8548
QT		 4860 "%s %8phC DS %d LS %d\n", __func__,
4861 fcport->port_name, fcport->disc_state,
4862 fcport->fw_login_state);
4863 memset(&ea, 0, sizeof(ea));
4864 ea.event = FCME_RELOGIN;
4865 ea.fcport = fcport;
4866 qla2x00_fcport_event_handler(vha, &ea);
4867 } else {
e315cd28
AC		 4868 status = qla2x00_local_device_login(vha,
4869 fcport);
726b8548
QT		 4870 if (status == QLA_SUCCESS) {
4871 fcport->old_loop_id = fcport->loop_id;
4872 ql_dbg(ql_dbg_disc, vha, 0x2003,
4873 "Port login OK: logged in ID 0x%x.\n",
4874 fcport->loop_id);
4875 qla2x00_update_fcport(vha, fcport);
4876 } else if (status == 1) {
4877 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
4878 /* retry the login again */
4879 ql_dbg(ql_dbg_disc, vha, 0x2007,
4880 "Retrying %d login again loop_id 0x%x.\n",
4881 fcport->login_retry,
4882 fcport->loop_id);
4883 } else {
4884 fcport->login_retry = 0;
4885 }
e315cd28 4886
726b8548
QT		 4887 if (fcport->login_retry == 0 &&
4888 status != QLA_SUCCESS)
4889 qla2x00_clear_loop_id(fcport);
e315cd28 4890 }
e315cd28
AC		 4891 }
4892 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
4893 break;
0971de7f 4894 }
0971de7f
AV		 4895}
4896
7d613ac6
SV		 4897/* Schedule work on any of the dpc-workqueues */
4898void
4899qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
4900{
4901 struct qla_hw_data *ha = base_vha->hw;
4902
4903 switch (work_code) {
4904 case MBA_IDC_AEN: /* 0x8200 */
4905 if (ha->dpc_lp_wq)
4906 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
4907 break;
4908
4909 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
4910 if (!ha->flags.nic_core_reset_hdlr_active) {
4911 if (ha->dpc_hp_wq)
4912 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
4913 } else
4914 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
4915 "NIC Core reset is already active. Skip "
4916 "scheduling it again.\n");
4917 break;
4918 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
4919 if (ha->dpc_hp_wq)
4920 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
4921 break;
4922 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
4923 if (ha->dpc_hp_wq)
4924 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
4925 break;
4926 default:
4927 ql_log(ql_log_warn, base_vha, 0xb05f,
d939be3a 4928 "Unknown work-code=0x%x.\n", work_code);
7d613ac6
SV		 4929 }
4930
4931 return;
4932}
4933
4934/* Work: Perform NIC Core Unrecoverable state handling */
4935void
4936qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
4937{
4938 struct qla_hw_data *ha =
2ad1b67c 4939 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
7d613ac6
SV		 4940 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4941 uint32_t dev_state = 0;
4942
4943 qla83xx_idc_lock(base_vha, 0);
4944 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4945 qla83xx_reset_ownership(base_vha);
4946 if (ha->flags.nic_core_reset_owner) {
4947 ha->flags.nic_core_reset_owner = 0;
4948 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
4949 QLA8XXX_DEV_FAILED);
4950 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
4951 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
4952 }
4953 qla83xx_idc_unlock(base_vha, 0);
4954}
4955
4956/* Work: Execute IDC state handler */
4957void
4958qla83xx_idc_state_handler_work(struct work_struct *work)
4959{
4960 struct qla_hw_data *ha =
2ad1b67c 4961 container_of(work, struct qla_hw_data, idc_state_handler);
7d613ac6
SV		 4962 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4963 uint32_t dev_state = 0;
4964
4965 qla83xx_idc_lock(base_vha, 0);
4966 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
4967 if (dev_state == QLA8XXX_DEV_FAILED ||
4968 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
4969 qla83xx_idc_state_handler(base_vha);
4970 qla83xx_idc_unlock(base_vha, 0);
4971}
4972
fa492630 4973static int
7d613ac6
SV		 4974qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
4975{
4976 int rval = QLA_SUCCESS;
4977 unsigned long heart_beat_wait = jiffies + (1 * HZ);
4978 uint32_t heart_beat_counter1, heart_beat_counter2;
4979
4980 do {
4981 if (time_after(jiffies, heart_beat_wait)) {
4982 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
4983 "Nic Core f/w is not alive.\n");
4984 rval = QLA_FUNCTION_FAILED;
4985 break;
4986 }
4987
4988 qla83xx_idc_lock(base_vha, 0);
4989 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4990 &heart_beat_counter1);
4991 qla83xx_idc_unlock(base_vha, 0);
4992 msleep(100);
4993 qla83xx_idc_lock(base_vha, 0);
4994 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
4995 &heart_beat_counter2);
4996 qla83xx_idc_unlock(base_vha, 0);
4997 } while (heart_beat_counter1 == heart_beat_counter2);
4998
4999 return rval;
5000}
5001
5002/* Work: Perform NIC Core Reset handling */
5003void
5004qla83xx_nic_core_reset_work(struct work_struct *work)
5005{
5006 struct qla_hw_data *ha =
5007 container_of(work, struct qla_hw_data, nic_core_reset);
5008 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5009 uint32_t dev_state = 0;
5010
81178772
SK		 5011 if (IS_QLA2031(ha)) {
5012 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5013 ql_log(ql_log_warn, base_vha, 0xb081,
5014 "Failed to dump mctp\n");
5015 return;
5016 }
5017
7d613ac6
SV		 5018 if (!ha->flags.nic_core_reset_hdlr_active) {
5019 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5020 qla83xx_idc_lock(base_vha, 0);
5021 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5022 &dev_state);
5023 qla83xx_idc_unlock(base_vha, 0);
5024 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5025 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5026 "Nic Core f/w is alive.\n");
5027 return;
5028 }
5029 }
5030
5031 ha->flags.nic_core_reset_hdlr_active = 1;
5032 if (qla83xx_nic_core_reset(base_vha)) {
5033 /* NIC Core reset failed. */
5034 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5035 "NIC Core reset failed.\n");
5036 }
5037 ha->flags.nic_core_reset_hdlr_active = 0;
5038 }
5039}
5040
5041/* Work: Handle 8200 IDC aens */
5042void
5043qla83xx_service_idc_aen(struct work_struct *work)
5044{
5045 struct qla_hw_data *ha =
5046 container_of(work, struct qla_hw_data, idc_aen);
5047 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5048 uint32_t dev_state, idc_control;
5049
5050 qla83xx_idc_lock(base_vha, 0);
5051 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5052 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5053 qla83xx_idc_unlock(base_vha, 0);
5054 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5055 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5056 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5057 "Application requested NIC Core Reset.\n");
5058 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5059 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5060 QLA_SUCCESS) {
5061 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5062 "Other protocol driver requested NIC Core Reset.\n");
5063 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5064 }
5065 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5066 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5067 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5068 }
5069}
5070
5071static void
5072qla83xx_wait_logic(void)
5073{
5074 int i;
5075
5076 /* Yield CPU */
5077 if (!in_interrupt()) {
5078 /*
5079 * Wait about 200ms before retrying again.
5080 * This controls the number of retries for single
5081 * lock operation.
5082 */
5083 msleep(100);
5084 schedule();
5085 } else {
5086 for (i = 0; i < 20; i++)
5087 cpu_relax(); /* This a nop instr on i386 */
5088 }
5089}
5090
fa492630 5091static int
7d613ac6
SV		 5092qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5093{
5094 int rval;
5095 uint32_t data;
5096 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5097 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5098 struct qla_hw_data *ha = base_vha->hw;
6c315553
SK		 5099 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5100 "Trying force recovery of the IDC lock.\n");
7d613ac6
SV		 5101
5102 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5103 if (rval)
5104 return rval;
5105
5106 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5107 return QLA_SUCCESS;
5108 } else {
5109 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5110 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5111 data);
5112 if (rval)
5113 return rval;
5114
5115 msleep(200);
5116
5117 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5118 &data);
5119 if (rval)
5120 return rval;
5121
5122 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5123 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5124 ~(idc_lck_rcvry_stage_mask));
5125 rval = qla83xx_wr_reg(base_vha,
5126 QLA83XX_IDC_LOCK_RECOVERY, data);
5127 if (rval)
5128 return rval;
5129
5130 /* Forcefully perform IDC UnLock */
5131 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5132 &data);
5133 if (rval)
5134 return rval;
5135 /* Clear lock-id by setting 0xff */
5136 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5137 0xff);
5138 if (rval)
5139 return rval;
5140 /* Clear lock-recovery by setting 0x0 */
5141 rval = qla83xx_wr_reg(base_vha,
5142 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5143 if (rval)
5144 return rval;
5145 } else
5146 return QLA_SUCCESS;
5147 }
5148
5149 return rval;
5150}
5151
fa492630 5152static int
7d613ac6
SV		 5153qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5154{
5155 int rval = QLA_SUCCESS;
5156 uint32_t o_drv_lockid, n_drv_lockid;
5157 unsigned long lock_recovery_timeout;
5158
5159 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5160retry_lockid:
5161 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5162 if (rval)
5163 goto exit;
5164
5165 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5166 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5167 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5168 return QLA_SUCCESS;
5169 else
5170 return QLA_FUNCTION_FAILED;
5171 }
5172
5173 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5174 if (rval)
5175 goto exit;
5176
5177 if (o_drv_lockid == n_drv_lockid) {
5178 qla83xx_wait_logic();
5179 goto retry_lockid;
5180 } else
5181 return QLA_SUCCESS;
5182
5183exit:
5184 return rval;
5185}
5186
5187void
5188qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5189{
5190 uint16_t options = (requester_id << 15) | BIT_6;
5191 uint32_t data;
6c315553 5192 uint32_t lock_owner;
7d613ac6
SV		 5193 struct qla_hw_data *ha = base_vha->hw;
5194
5195 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5196retry_lock:
5197 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5198 == QLA_SUCCESS) {
5199 if (data) {
5200 /* Setting lock-id to our function-number */
5201 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5202 ha->portnum);
5203 } else {
6c315553
SK		 5204 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5205 &lock_owner);
7d613ac6 5206 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
6c315553
SK		 5207 "Failed to acquire IDC lock, acquired by %d, "
5208 "retrying...\n", lock_owner);
7d613ac6
SV		 5209
5210 /* Retry/Perform IDC-Lock recovery */
5211 if (qla83xx_idc_lock_recovery(base_vha)
5212 == QLA_SUCCESS) {
5213 qla83xx_wait_logic();
5214 goto retry_lock;
5215 } else
5216 ql_log(ql_log_warn, base_vha, 0xb075,
5217 "IDC Lock recovery FAILED.\n");
5218 }
5219
5220 }
5221
5222 return;
5223
5224 /* XXX: IDC-lock implementation using access-control mbx */
5225retry_lock2:
5226 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5227 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5228 "Failed to acquire IDC lock. retrying...\n");
5229 /* Retry/Perform IDC-Lock recovery */
5230 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5231 qla83xx_wait_logic();
5232 goto retry_lock2;
5233 } else
5234 ql_log(ql_log_warn, base_vha, 0xb076,
5235 "IDC Lock recovery FAILED.\n");
5236 }
5237
5238 return;
5239}
5240
5241void
5242qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5243{
5897cb2f
BVA		 5244#if 0
5245 uint16_t options = (requester_id << 15) | BIT_7;
5246#endif
5247 uint16_t retry;
7d613ac6
SV		 5248 uint32_t data;
5249 struct qla_hw_data *ha = base_vha->hw;
5250
5251 /* IDC-unlock implementation using driver-unlock/lock-id
5252 * remote registers
5253 */
5254 retry = 0;
5255retry_unlock:
5256 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5257 == QLA_SUCCESS) {
5258 if (data == ha->portnum) {
5259 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5260 /* Clearing lock-id by setting 0xff */
5261 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5262 } else if (retry < 10) {
5263 /* SV: XXX: IDC unlock retrying needed here? */
5264
5265 /* Retry for IDC-unlock */
5266 qla83xx_wait_logic();
5267 retry++;
5268 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
ee6a8773 5269 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5270 goto retry_unlock;
5271 }
5272 } else if (retry < 10) {
5273 /* Retry for IDC-unlock */
5274 qla83xx_wait_logic();
5275 retry++;
5276 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
ee6a8773 5277 "Failed to read drv-lockid, retrying=%d\n", retry);
7d613ac6
SV		 5278 goto retry_unlock;
5279 }
5280
5281 return;
5282
5897cb2f 5283#if 0
7d613ac6
SV		 5284 /* XXX: IDC-unlock implementation using access-control mbx */
5285 retry = 0;
5286retry_unlock2:
5287 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5288 if (retry < 10) {
5289 /* Retry for IDC-unlock */
5290 qla83xx_wait_logic();
5291 retry++;
5292 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
ee6a8773 5293 "Failed to release IDC lock, retrying=%d\n", retry);
7d613ac6
SV		 5294 goto retry_unlock2;
5295 }
5296 }
5297
5298 return;
5897cb2f 5299#endif
7d613ac6
SV		 5300}
5301
5302int
5303__qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5304{
5305 int rval = QLA_SUCCESS;
5306 struct qla_hw_data *ha = vha->hw;
5307 uint32_t drv_presence;
5308
5309 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5310 if (rval == QLA_SUCCESS) {
5311 drv_presence |= (1 << ha->portnum);
5312 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5313 drv_presence);
5314 }
5315
5316 return rval;
5317}
5318
5319int
5320qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5321{
5322 int rval = QLA_SUCCESS;
5323
5324 qla83xx_idc_lock(vha, 0);
5325 rval = __qla83xx_set_drv_presence(vha);
5326 qla83xx_idc_unlock(vha, 0);
5327
5328 return rval;
5329}
5330
5331int
5332__qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5333{
5334 int rval = QLA_SUCCESS;
5335 struct qla_hw_data *ha = vha->hw;
5336 uint32_t drv_presence;
5337
5338 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5339 if (rval == QLA_SUCCESS) {
5340 drv_presence &= ~(1 << ha->portnum);
5341 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5342 drv_presence);
5343 }
5344
5345 return rval;
5346}
5347
5348int
5349qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5350{
5351 int rval = QLA_SUCCESS;
5352
5353 qla83xx_idc_lock(vha, 0);
5354 rval = __qla83xx_clear_drv_presence(vha);
5355 qla83xx_idc_unlock(vha, 0);
5356
5357 return rval;
5358}
5359
fa492630 5360static void
7d613ac6
SV		 5361qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5362{
5363 struct qla_hw_data *ha = vha->hw;
5364 uint32_t drv_ack, drv_presence;
5365 unsigned long ack_timeout;
5366
5367 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5368 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5369 while (1) {
5370 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5371 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
807fb6d8 5372 if ((drv_ack & drv_presence) == drv_presence)
7d613ac6
SV		 5373 break;
5374
5375 if (time_after_eq(jiffies, ack_timeout)) {
5376 ql_log(ql_log_warn, vha, 0xb067,
5377 "RESET ACK TIMEOUT! drv_presence=0x%x "
5378 "drv_ack=0x%x\n", drv_presence, drv_ack);
5379 /*
5380 * The function(s) which did not ack in time are forced
5381 * to withdraw any further participation in the IDC
5382 * reset.
5383 */
5384 if (drv_ack != drv_presence)
5385 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5386 drv_ack);
5387 break;
5388 }
5389
5390 qla83xx_idc_unlock(vha, 0);
5391 msleep(1000);
5392 qla83xx_idc_lock(vha, 0);
5393 }
5394
5395 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5396 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5397}
5398
fa492630 5399static int
7d613ac6
SV		 5400qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5401{
5402 int rval = QLA_SUCCESS;
5403 uint32_t idc_control;
5404
5405 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5406 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5407
5408 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5409 __qla83xx_get_idc_control(vha, &idc_control);
5410 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5411 __qla83xx_set_idc_control(vha, 0);
5412
5413 qla83xx_idc_unlock(vha, 0);
5414 rval = qla83xx_restart_nic_firmware(vha);
5415 qla83xx_idc_lock(vha, 0);
5416
5417 if (rval != QLA_SUCCESS) {
5418 ql_log(ql_log_fatal, vha, 0xb06a,
5419 "Failed to restart NIC f/w.\n");
5420 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5421 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5422 } else {
5423 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5424 "Success in restarting nic f/w.\n");
5425 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5426 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5427 }
5428
5429 return rval;
5430}
5431
5432/* Assumes idc_lock always held on entry */
5433int
5434qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5435{
5436 struct qla_hw_data *ha = base_vha->hw;
5437 int rval = QLA_SUCCESS;
5438 unsigned long dev_init_timeout;
5439 uint32_t dev_state;
5440
5441 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5442 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5443
5444 while (1) {
5445
5446 if (time_after_eq(jiffies, dev_init_timeout)) {
5447 ql_log(ql_log_warn, base_vha, 0xb06e,
5448 "Initialization TIMEOUT!\n");
5449 /* Init timeout. Disable further NIC Core
5450 * communication.
5451 */
5452 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5453 QLA8XXX_DEV_FAILED);
5454 ql_log(ql_log_info, base_vha, 0xb06f,
5455 "HW State: FAILED.\n");
5456 }
5457
5458 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5459 switch (dev_state) {
5460 case QLA8XXX_DEV_READY:
5461 if (ha->flags.nic_core_reset_owner)
5462 qla83xx_idc_audit(base_vha,
5463 IDC_AUDIT_COMPLETION);
5464 ha->flags.nic_core_reset_owner = 0;
5465 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5466 "Reset_owner reset by 0x%x.\n",
5467 ha->portnum);
5468 goto exit;
5469 case QLA8XXX_DEV_COLD:
5470 if (ha->flags.nic_core_reset_owner)
5471 rval = qla83xx_device_bootstrap(base_vha);
5472 else {
5473 /* Wait for AEN to change device-state */
5474 qla83xx_idc_unlock(base_vha, 0);
5475 msleep(1000);
5476 qla83xx_idc_lock(base_vha, 0);
5477 }
5478 break;
5479 case QLA8XXX_DEV_INITIALIZING:
5480 /* Wait for AEN to change device-state */
5481 qla83xx_idc_unlock(base_vha, 0);
5482 msleep(1000);
5483 qla83xx_idc_lock(base_vha, 0);
5484 break;
5485 case QLA8XXX_DEV_NEED_RESET:
5486 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5487 qla83xx_need_reset_handler(base_vha);
5488 else {
5489 /* Wait for AEN to change device-state */
5490 qla83xx_idc_unlock(base_vha, 0);
5491 msleep(1000);
5492 qla83xx_idc_lock(base_vha, 0);
5493 }
5494 /* reset timeout value after need reset handler */
5495 dev_init_timeout = jiffies +
5496 (ha->fcoe_dev_init_timeout * HZ);
5497 break;
5498 case QLA8XXX_DEV_NEED_QUIESCENT:
5499 /* XXX: DEBUG for now */
5500 qla83xx_idc_unlock(base_vha, 0);
5501 msleep(1000);
5502 qla83xx_idc_lock(base_vha, 0);
5503 break;
5504 case QLA8XXX_DEV_QUIESCENT:
5505 /* XXX: DEBUG for now */
5506 if (ha->flags.quiesce_owner)
5507 goto exit;
5508
5509 qla83xx_idc_unlock(base_vha, 0);
5510 msleep(1000);
5511 qla83xx_idc_lock(base_vha, 0);
5512 dev_init_timeout = jiffies +
5513 (ha->fcoe_dev_init_timeout * HZ);
5514 break;
5515 case QLA8XXX_DEV_FAILED:
5516 if (ha->flags.nic_core_reset_owner)
5517 qla83xx_idc_audit(base_vha,
5518 IDC_AUDIT_COMPLETION);
5519 ha->flags.nic_core_reset_owner = 0;
5520 __qla83xx_clear_drv_presence(base_vha);
5521 qla83xx_idc_unlock(base_vha, 0);
5522 qla8xxx_dev_failed_handler(base_vha);
5523 rval = QLA_FUNCTION_FAILED;
5524 qla83xx_idc_lock(base_vha, 0);
5525 goto exit;
5526 case QLA8XXX_BAD_VALUE:
5527 qla83xx_idc_unlock(base_vha, 0);
5528 msleep(1000);
5529 qla83xx_idc_lock(base_vha, 0);
5530 break;
5531 default:
5532 ql_log(ql_log_warn, base_vha, 0xb071,
d939be3a 5533 "Unknown Device State: %x.\n", dev_state);
7d613ac6
SV		 5534 qla83xx_idc_unlock(base_vha, 0);
5535 qla8xxx_dev_failed_handler(base_vha);
5536 rval = QLA_FUNCTION_FAILED;
5537 qla83xx_idc_lock(base_vha, 0);
5538 goto exit;
5539 }
5540 }
5541
5542exit:
5543 return rval;
5544}
5545
f3ddac19
CD		 5546void
5547qla2x00_disable_board_on_pci_error(struct work_struct *work)
5548{
5549 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5550 board_disable);
5551 struct pci_dev *pdev = ha->pdev;
5552 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5553
726b8548
QT		 5554 /*
5555 * if UNLOAD flag is already set, then continue unload,
783e0dc4
SC		 5556 * where it was set first.
5557 */
5558 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5559 return;
5560
f3ddac19
CD		 5561 ql_log(ql_log_warn, base_vha, 0x015b,
5562 "Disabling adapter.\n");
5563
efdb5760
SC		 5564 if (!atomic_read(&pdev->enable_cnt)) {
5565 ql_log(ql_log_info, base_vha, 0xfffc,
5566 "PCI device disabled, no action req for PCI error=%lx\n",
5567 base_vha->pci_flags);
5568 return;
5569 }
5570
726b8548
QT		 5571 qla2x00_wait_for_sess_deletion(base_vha);
5572
f3ddac19
CD		 5573 set_bit(UNLOADING, &base_vha->dpc_flags);
5574
5575 qla2x00_delete_all_vps(ha, base_vha);
5576
5577 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5578
5579 qla2x00_dfs_remove(base_vha);
5580
5581 qla84xx_put_chip(base_vha);
5582
5583 if (base_vha->timer_active)
5584 qla2x00_stop_timer(base_vha);
5585
5586 base_vha->flags.online = 0;
5587
5588 qla2x00_destroy_deferred_work(ha);
5589
5590 /*
5591 * Do not try to stop beacon blink as it will issue a mailbox
5592 * command.
5593 */
5594 qla2x00_free_sysfs_attr(base_vha, false);
5595
5596 fc_remove_host(base_vha->host);
5597
5598 scsi_remove_host(base_vha->host);
5599
5600 base_vha->flags.init_done = 0;
5601 qla25xx_delete_queues(base_vha);
f3ddac19 5602 qla2x00_free_fcports(base_vha);
093df737 5603 qla2x00_free_irqs(base_vha);
f3ddac19
CD		 5604 qla2x00_mem_free(ha);
5605 qla82xx_md_free(base_vha);
5606 qla2x00_free_queues(ha);
5607
f3ddac19
CD		 5608 qla2x00_unmap_iobases(ha);
5609
5610 pci_release_selected_regions(ha->pdev, ha->bars);
f3ddac19
CD		 5611 pci_disable_pcie_error_reporting(pdev);
5612 pci_disable_device(pdev);
f3ddac19 5613
beb9e315
JL		 5614 /*
5615 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5616 */
f3ddac19
CD		 5617}
5618
1da177e4
LT		 5619/**************************************************************************
5620* qla2x00_do_dpc
5621* This kernel thread is a task that is schedule by the interrupt handler
5622* to perform the background processing for interrupts.
5623*
5624* Notes:
5625* This task always run in the context of a kernel thread. It
5626* is kick-off by the driver's detect code and starts up
5627* up one per adapter. It immediately goes to sleep and waits for
5628* some fibre event. When either the interrupt handler or
5629* the timer routine detects a event it will one of the task
5630* bits then wake us up.
5631**************************************************************************/
5632static int
5633qla2x00_do_dpc(void *data)
5634{
e315cd28
AC		 5635 scsi_qla_host_t *base_vha;
5636 struct qla_hw_data *ha;
d7459527
MH		 5637 uint32_t online;
5638 struct qla_qpair *qpair;
1da177e4 5639
e315cd28
AC		 5640 ha = (struct qla_hw_data *)data;
5641 base_vha = pci_get_drvdata(ha->pdev);
1da177e4 5642
8698a745 5643 set_user_nice(current, MIN_NICE);
1da177e4 5644
563585ec 5645 set_current_state(TASK_INTERRUPTIBLE);
39a11240 5646 while (!kthread_should_stop()) {
7c3df132
SK		 5647 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5648 "DPC handler sleeping.\n");
1da177e4 5649
39a11240 5650 schedule();
1da177e4 5651
c142caf0
AV		 5652 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5653 goto end_loop;
1da177e4 5654
85880801 5655 if (ha->flags.eeh_busy) {
7c3df132
SK		 5656 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5657 "eeh_busy=%d.\n", ha->flags.eeh_busy);
c142caf0 5658 goto end_loop;
85880801
AV		 5659 }
5660
1da177e4
LT		 5661 ha->dpc_active = 1;
5662
5f28d2d7
SK		 5663 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5664 "DPC handler waking up, dpc_flags=0x%lx.\n",
5665 base_vha->dpc_flags);
1da177e4 5666
a29b3dd7
JC		 5667 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5668 break;
5669
e315cd28 5670 qla2x00_do_work(base_vha);
0971de7f 5671
7ec0effd
AD		 5672 if (IS_P3P_TYPE(ha)) {
5673 if (IS_QLA8044(ha)) {
5674 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5675 &base_vha->dpc_flags)) {
5676 qla8044_idc_lock(ha);
5677 qla8044_wr_direct(base_vha,
5678 QLA8044_CRB_DEV_STATE_INDEX,
5679 QLA8XXX_DEV_FAILED);
5680 qla8044_idc_unlock(ha);
5681 ql_log(ql_log_info, base_vha, 0x4004,
5682 "HW State: FAILED.\n");
5683 qla8044_device_state_handler(base_vha);
5684 continue;
5685 }
5686
5687 } else {
5688 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5689 &base_vha->dpc_flags)) {
5690 qla82xx_idc_lock(ha);
5691 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
5692 QLA8XXX_DEV_FAILED);
5693 qla82xx_idc_unlock(ha);
5694 ql_log(ql_log_info, base_vha, 0x0151,
5695 "HW State: FAILED.\n");
5696 qla82xx_device_state_handler(base_vha);
5697 continue;
5698 }
a9083016
GM		 5699 }
5700
5701 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
5702 &base_vha->dpc_flags)) {
5703
7c3df132
SK		 5704 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
5705 "FCoE context reset scheduled.\n");
a9083016
GM		 5706 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
5707 &base_vha->dpc_flags))) {
5708 if (qla82xx_fcoe_ctx_reset(base_vha)) {
5709 /* FCoE-ctx reset failed.
5710 * Escalate to chip-reset
5711 */
5712 set_bit(ISP_ABORT_NEEDED,
5713 &base_vha->dpc_flags);
5714 }
5715 clear_bit(ABORT_ISP_ACTIVE,
5716 &base_vha->dpc_flags);
5717 }
5718
7c3df132
SK		 5719 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
5720 "FCoE context reset end.\n");
a9083016 5721 }
8ae6d9c7
GM		 5722 } else if (IS_QLAFX00(ha)) {
5723 if (test_and_clear_bit(ISP_UNRECOVERABLE,
5724 &base_vha->dpc_flags)) {
5725 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
5726 "Firmware Reset Recovery\n");
5727 if (qlafx00_reset_initialize(base_vha)) {
5728 /* Failed. Abort isp later. */
5729 if (!test_bit(UNLOADING,
f92f82d6 5730 &base_vha->dpc_flags)) {
8ae6d9c7
GM		 5731 set_bit(ISP_UNRECOVERABLE,
5732 &base_vha->dpc_flags);
5733 ql_dbg(ql_dbg_dpc, base_vha,
5734 0x4021,
5735 "Reset Recovery Failed\n");
f92f82d6 5736 }
8ae6d9c7
GM		 5737 }
5738 }
5739
5740 if (test_and_clear_bit(FX00_TARGET_SCAN,
5741 &base_vha->dpc_flags)) {
5742 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
5743 "ISPFx00 Target Scan scheduled\n");
5744 if (qlafx00_rescan_isp(base_vha)) {
5745 if (!test_bit(UNLOADING,
5746 &base_vha->dpc_flags))
5747 set_bit(ISP_UNRECOVERABLE,
5748 &base_vha->dpc_flags);
5749 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
5750 "ISPFx00 Target Scan Failed\n");
5751 }
5752 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
5753 "ISPFx00 Target Scan End\n");
5754 }
e8f5e95d
AB		 5755 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
5756 &base_vha->dpc_flags)) {
5757 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
5758 "ISPFx00 Host Info resend scheduled\n");
5759 qlafx00_fx_disc(base_vha,
5760 &base_vha->hw->mr.fcport,
5761 FXDISC_REG_HOST_INFO);
5762 }
a9083016
GM		 5763 }
5764
e4e3a2ce
QT		 5765 if (test_and_clear_bit(DETECT_SFP_CHANGE,
5766 &base_vha->dpc_flags) &&
5767 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
5768 qla24xx_detect_sfp(base_vha);
5769
5770 if (ha->flags.detected_lr_sfp !=
5771 ha->flags.using_lr_setting)
5772 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
5773 }
5774
e315cd28
AC		 5775 if (test_and_clear_bit(ISP_ABORT_NEEDED,
5776 &base_vha->dpc_flags)) {
1da177e4 5777
7c3df132
SK		 5778 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
5779 "ISP abort scheduled.\n");
1da177e4 5780 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
e315cd28 5781 &base_vha->dpc_flags))) {
1da177e4 5782
a9083016 5783 if (ha->isp_ops->abort_isp(base_vha)) {
1da177e4
LT		 5784 /* failed. retry later */
5785 set_bit(ISP_ABORT_NEEDED,
e315cd28 5786 &base_vha->dpc_flags);
99363ef8 5787 }
e315cd28
AC		 5788 clear_bit(ABORT_ISP_ACTIVE,
5789 &base_vha->dpc_flags);
99363ef8
SJ		 5790 }
5791
7c3df132
SK		 5792 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
5793 "ISP abort end.\n");
1da177e4
LT		 5794 }
5795
a394aac8
DJ		 5796 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
5797 &base_vha->dpc_flags)) {
e315cd28 5798 qla2x00_update_fcports(base_vha);
c9c5ced9 5799 }
d97994dc 5800
8ae6d9c7
GM		 5801 if (IS_QLAFX00(ha))
5802 goto loop_resync_check;
5803
579d12b5 5804 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
7c3df132
SK		 5805 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
5806 "Quiescence mode scheduled.\n");
7ec0effd
AD		 5807 if (IS_P3P_TYPE(ha)) {
5808 if (IS_QLA82XX(ha))
5809 qla82xx_device_state_handler(base_vha);
5810 if (IS_QLA8044(ha))
5811 qla8044_device_state_handler(base_vha);
8fcd6b8b
CD		 5812 clear_bit(ISP_QUIESCE_NEEDED,
5813 &base_vha->dpc_flags);
5814 if (!ha->flags.quiesce_owner) {
5815 qla2x00_perform_loop_resync(base_vha);
7ec0effd
AD		 5816 if (IS_QLA82XX(ha)) {
5817 qla82xx_idc_lock(ha);
5818 qla82xx_clear_qsnt_ready(
5819 base_vha);
5820 qla82xx_idc_unlock(ha);
5821 } else if (IS_QLA8044(ha)) {
5822 qla8044_idc_lock(ha);
5823 qla8044_clear_qsnt_ready(
5824 base_vha);
5825 qla8044_idc_unlock(ha);
5826 }
8fcd6b8b
CD		 5827 }
5828 } else {
5829 clear_bit(ISP_QUIESCE_NEEDED,
5830 &base_vha->dpc_flags);
5831 qla2x00_quiesce_io(base_vha);
579d12b5 5832 }
7c3df132
SK		 5833 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
5834 "Quiescence mode end.\n");
579d12b5
SK		 5835 }
5836
e315cd28 5837 if (test_and_clear_bit(RESET_MARKER_NEEDED,
8ae6d9c7 5838 &base_vha->dpc_flags) &&
e315cd28 5839 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
1da177e4 5840
7c3df132
SK		 5841 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
5842 "Reset marker scheduled.\n");
e315cd28
AC		 5843 qla2x00_rst_aen(base_vha);
5844 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
7c3df132
SK		 5845 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
5846 "Reset marker end.\n");
1da177e4
LT		 5847 }
5848
5849 /* Retry each device up to login retry count */
e315cd28
AC		 5850 if ((test_and_clear_bit(RELOGIN_NEEDED,
5851 &base_vha->dpc_flags)) &&
5852 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
5853 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
1da177e4 5854
7c3df132
SK		 5855 ql_dbg(ql_dbg_dpc, base_vha, 0x400d,
5856 "Relogin scheduled.\n");
e315cd28 5857 qla2x00_relogin(base_vha);
7c3df132
SK		 5858 ql_dbg(ql_dbg_dpc, base_vha, 0x400e,
5859 "Relogin end.\n");
1da177e4 5860 }
8ae6d9c7 5861loop_resync_check:
e315cd28 5862 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
8ae6d9c7 5863 &base_vha->dpc_flags)) {
1da177e4 5864
7c3df132
SK		 5865 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
5866 "Loop resync scheduled.\n");
1da177e4
LT		 5867
5868 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
e315cd28 5869 &base_vha->dpc_flags))) {
1da177e4 5870
52c82823 5871 qla2x00_loop_resync(base_vha);
1da177e4 5872
e315cd28
AC		 5873 clear_bit(LOOP_RESYNC_ACTIVE,
5874 &base_vha->dpc_flags);
1da177e4
LT		 5875 }
5876
7c3df132
SK		 5877 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
5878 "Loop resync end.\n");
1da177e4
LT		 5879 }
5880
8ae6d9c7
GM		 5881 if (IS_QLAFX00(ha))
5882 goto intr_on_check;
5883
e315cd28
AC		 5884 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
5885 atomic_read(&base_vha->loop_state) == LOOP_READY) {
5886 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
5887 qla2xxx_flash_npiv_conf(base_vha);
272976ca
AV		 5888 }
5889
8ae6d9c7 5890intr_on_check:
1da177e4 5891 if (!ha->interrupts_on)
fd34f556 5892 ha->isp_ops->enable_intrs(ha);
1da177e4 5893
e315cd28 5894 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
90b604f2
HM		 5895 &base_vha->dpc_flags)) {
5896 if (ha->beacon_blink_led == 1)
5897 ha->isp_ops->beacon_blink(base_vha);
5898 }
f6df144c 5899
d7459527
MH		 5900 /* qpair online check */
5901 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
5902 &base_vha->dpc_flags)) {
5903 if (ha->flags.eeh_busy ||
5904 ha->flags.pci_channel_io_perm_failure)
5905 online = 0;
5906 else
5907 online = 1;
5908
5909 mutex_lock(&ha->mq_lock);
5910 list_for_each_entry(qpair, &base_vha->qp_list,
5911 qp_list_elem)
5912 qpair->online = online;
5913 mutex_unlock(&ha->mq_lock);
5914 }
5915
deeae7a6
DG		 5916 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, &base_vha->dpc_flags)) {
5917 ql_log(ql_log_info, base_vha, 0xffffff,
5918 "nvme: SET ZIO Activity exchange threshold to %d.\n",
5919 ha->nvme_last_rptd_aen);
5920 if (qla27xx_set_zio_threshold(base_vha, ha->nvme_last_rptd_aen)) {
5921 ql_log(ql_log_info, base_vha, 0xffffff,
5922 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
5923 ha->nvme_last_rptd_aen);
5924 }
5925 }
5926
8ae6d9c7
GM		 5927 if (!IS_QLAFX00(ha))
5928 qla2x00_do_dpc_all_vps(base_vha);
2c3dfe3f 5929
1da177e4 5930 ha->dpc_active = 0;
c142caf0 5931end_loop:
563585ec 5932 set_current_state(TASK_INTERRUPTIBLE);
1da177e4 5933 } /* End of while(1) */
563585ec 5934 __set_current_state(TASK_RUNNING);
1da177e4 5935
7c3df132
SK		 5936 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
5937 "DPC handler exiting.\n");
1da177e4
LT		 5938
5939 /*
5940 * Make sure that nobody tries to wake us up again.
5941 */
1da177e4
LT		 5942 ha->dpc_active = 0;
5943
ac280b67
AV		 5944 /* Cleanup any residual CTX SRBs. */
5945 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5946
39a11240
CH		 5947 return 0;
5948}
5949
5950void
e315cd28 5951qla2xxx_wake_dpc(struct scsi_qla_host *vha)
39a11240 5952{
e315cd28 5953 struct qla_hw_data *ha = vha->hw;
c795c1e4
AV		 5954 struct task_struct *t = ha->dpc_thread;
5955
e315cd28 5956 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
c795c1e4 5957 wake_up_process(t);
1da177e4
LT		 5958}
5959
1da177e4
LT		 5960/*
5961* qla2x00_rst_aen
5962* Processes asynchronous reset.
5963*
5964* Input:
5965* ha = adapter block pointer.
5966*/
5967static void
e315cd28 5968qla2x00_rst_aen(scsi_qla_host_t *vha)
1da177e4 5969{
e315cd28
AC		 5970 if (vha->flags.online && !vha->flags.reset_active &&
5971 !atomic_read(&vha->loop_down_timer) &&
5972 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
1da177e4 5973 do {
e315cd28 5974 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
1da177e4
LT		 5975
5976 /*
5977 * Issue marker command only when we are going to start
5978 * the I/O.
5979 */
e315cd28
AC		 5980 vha->marker_needed = 1;
5981 } while (!atomic_read(&vha->loop_down_timer) &&
5982 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
1da177e4
LT		 5983 }
5984}
5985
1da177e4
LT		 5986/**************************************************************************
5987* qla2x00_timer
5988*
5989* Description:
5990* One second timer
5991*
5992* Context: Interrupt
5993***************************************************************************/
2c3dfe3f 5994void
8e5f4ba0 5995qla2x00_timer(struct timer_list *t)
1da177e4 5996{
8e5f4ba0 5997 scsi_qla_host_t *vha = from_timer(vha, t, timer);
1da177e4 5998 unsigned long cpu_flags = 0;
1da177e4
LT		 5999 int start_dpc = 0;
6000 int index;
6001 srb_t *sp;
85880801 6002 uint16_t w;
e315cd28 6003 struct qla_hw_data *ha = vha->hw;
73208dfd 6004 struct req_que *req;
85880801 6005
a5b36321 6006 if (ha->flags.eeh_busy) {
7c3df132
SK		 6007 ql_dbg(ql_dbg_timer, vha, 0x6000,
6008 "EEH = %d, restarting timer.\n",
6009 ha->flags.eeh_busy);
a5b36321
LC		 6010 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6011 return;
6012 }
6013
f3ddac19
CD		 6014 /*
6015 * Hardware read to raise pending EEH errors during mailbox waits. If
6016 * the read returns -1 then disable the board.
6017 */
6018 if (!pci_channel_offline(ha->pdev)) {
85880801 6019 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
c821e0d5 6020 qla2x00_check_reg16_for_disconnect(vha, w);
f3ddac19 6021 }
1da177e4 6022
cefcaba6 6023 /* Make sure qla82xx_watchdog is run only for physical port */
7ec0effd 6024 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
579d12b5
SK		 6025 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6026 start_dpc++;
7ec0effd
AD		 6027 if (IS_QLA82XX(ha))
6028 qla82xx_watchdog(vha);
6029 else if (IS_QLA8044(ha))
6030 qla8044_watchdog(vha);
579d12b5
SK		 6031 }
6032
8ae6d9c7
GM		 6033 if (!vha->vp_idx && IS_QLAFX00(ha))
6034 qlafx00_timer_routine(vha);
6035
1da177e4 6036 /* Loop down handler. */
e315cd28 6037 if (atomic_read(&vha->loop_down_timer) > 0 &&
8f7daead
GM		 6038 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6039 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
e315cd28 6040 && vha->flags.online) {
1da177e4 6041
e315cd28
AC		 6042 if (atomic_read(&vha->loop_down_timer) ==
6043 vha->loop_down_abort_time) {
1da177e4 6044
7c3df132
SK		 6045 ql_log(ql_log_info, vha, 0x6008,
6046 "Loop down - aborting the queues before time expires.\n");
1da177e4 6047
e315cd28
AC		 6048 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6049 atomic_set(&vha->loop_state, LOOP_DEAD);
1da177e4 6050
f08b7251
AV		 6051 /*
6052 * Schedule an ISP abort to return any FCP2-device
6053 * commands.
6054 */
2c3dfe3f 6055 /* NPIV - scan physical port only */
e315cd28 6056 if (!vha->vp_idx) {
2c3dfe3f
SJ		 6057 spin_lock_irqsave(&ha->hardware_lock,
6058 cpu_flags);
73208dfd 6059 req = ha->req_q_map[0];
2c3dfe3f 6060 for (index = 1;
8d93f550 6061 index < req->num_outstanding_cmds;
2c3dfe3f
SJ		 6062 index++) {
6063 fc_port_t *sfcp;
6064
e315cd28 6065 sp = req->outstanding_cmds[index];
2c3dfe3f
SJ		 6066 if (!sp)
6067 continue;
c5419e26
QT		 6068 if (sp->cmd_type != TYPE_SRB)
6069 continue;
9ba56b95 6070 if (sp->type != SRB_SCSI_CMD)
cf53b069 6071 continue;
2c3dfe3f 6072 sfcp = sp->fcport;
f08b7251 6073 if (!(sfcp->flags & FCF_FCP2_DEVICE))
2c3dfe3f 6074 continue;
bdf79621 6075
8f7daead
GM		 6076 if (IS_QLA82XX(ha))
6077 set_bit(FCOE_CTX_RESET_NEEDED,
6078 &vha->dpc_flags);
6079 else
6080 set_bit(ISP_ABORT_NEEDED,
e315cd28 6081 &vha->dpc_flags);
2c3dfe3f
SJ		 6082 break;
6083 }
6084 spin_unlock_irqrestore(&ha->hardware_lock,
e315cd28 6085 cpu_flags);
1da177e4 6086 }
1da177e4
LT		 6087 start_dpc++;
6088 }
6089
6090 /* if the loop has been down for 4 minutes, reinit adapter */
e315cd28 6091 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
0d6e61bc 6092 if (!(vha->device_flags & DFLG_NO_CABLE)) {
7c3df132 6093 ql_log(ql_log_warn, vha, 0x6009,
1da177e4
LT		 6094 "Loop down - aborting ISP.\n");
6095
8f7daead
GM		 6096 if (IS_QLA82XX(ha))
6097 set_bit(FCOE_CTX_RESET_NEEDED,
6098 &vha->dpc_flags);
6099 else
6100 set_bit(ISP_ABORT_NEEDED,
6101 &vha->dpc_flags);
1da177e4
LT		 6102 }
6103 }
7c3df132
SK		 6104 ql_dbg(ql_dbg_timer, vha, 0x600a,
6105 "Loop down - seconds remaining %d.\n",
6106 atomic_read(&vha->loop_down_timer));
1da177e4 6107 }
cefcaba6
SK		 6108 /* Check if beacon LED needs to be blinked for physical host only */
6109 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
999916dc 6110 /* There is no beacon_blink function for ISP82xx */
7ec0effd 6111 if (!IS_P3P_TYPE(ha)) {
999916dc
SK		 6112 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6113 start_dpc++;
6114 }
f6df144c
AV		 6115 }
6116
550bf57d 6117 /* Process any deferred work. */
e315cd28 6118 if (!list_empty(&vha->work_list))
550bf57d
AV		 6119 start_dpc++;
6120
7401bc18
DG		 6121 /*
6122 * FC-NVME
6123 * see if the active AEN count has changed from what was last reported.
6124 */
deeae7a6
DG		 6125 if (!vha->vp_idx &&
6126 atomic_read(&ha->nvme_active_aen_cnt) != ha->nvme_last_rptd_aen &&
6127 ha->zio_mode == QLA_ZIO_MODE_6) {
7401bc18 6128 ql_log(ql_log_info, vha, 0x3002,
deeae7a6
DG		 6129 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6130 ha->nvme_last_rptd_aen);
6131 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6132 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6133 start_dpc++;
7401bc18
DG		 6134 }
6135
1da177e4 6136 /* Schedule the DPC routine if needed */
e315cd28
AC		 6137 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6138 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6139 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
1da177e4 6140 start_dpc ||
e315cd28
AC		 6141 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6142 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
a9083016
GM		 6143 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6144 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
e315cd28 6145 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
50280c01 6146 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
7c3df132
SK		 6147 ql_dbg(ql_dbg_timer, vha, 0x600b,
6148 "isp_abort_needed=%d loop_resync_needed=%d "
6149 "fcport_update_needed=%d start_dpc=%d "
6150 "reset_marker_needed=%d",
6151 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6152 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6153 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6154 start_dpc,
6155 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6156 ql_dbg(ql_dbg_timer, vha, 0x600c,
6157 "beacon_blink_needed=%d isp_unrecoverable=%d "
6158 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
50280c01 6159 "relogin_needed=%d.\n",
7c3df132
SK		 6160 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6161 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6162 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6163 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
50280c01 6164 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
e315cd28 6165 qla2xxx_wake_dpc(vha);
7c3df132 6166 }
1da177e4 6167
e315cd28 6168 qla2x00_restart_timer(vha, WATCH_INTERVAL);
1da177e4
LT		 6169}
6170
5433383e
AV		 6171/* Firmware interface routines. */
6172
f73cb695 6173#define FW_BLOBS 11
5433383e
AV		 6174#define FW_ISP21XX 0
6175#define FW_ISP22XX 1
6176#define FW_ISP2300 2
6177#define FW_ISP2322 3
48c02fde 6178#define FW_ISP24XX 4
c3a2f0df 6179#define FW_ISP25XX 5
3a03eb79 6180#define FW_ISP81XX 6
a9083016 6181#define FW_ISP82XX 7
6246b8a1
GM		 6182#define FW_ISP2031 8
6183#define FW_ISP8031 9
2c5bbbb2 6184#define FW_ISP27XX 10
5433383e 6185
bb8ee499
AV		 6186#define FW_FILE_ISP21XX "ql2100_fw.bin"
6187#define FW_FILE_ISP22XX "ql2200_fw.bin"
6188#define FW_FILE_ISP2300 "ql2300_fw.bin"
6189#define FW_FILE_ISP2322 "ql2322_fw.bin"
6190#define FW_FILE_ISP24XX "ql2400_fw.bin"
c3a2f0df 6191#define FW_FILE_ISP25XX "ql2500_fw.bin"
3a03eb79 6192#define FW_FILE_ISP81XX "ql8100_fw.bin"
a9083016 6193#define FW_FILE_ISP82XX "ql8200_fw.bin"
6246b8a1
GM		 6194#define FW_FILE_ISP2031 "ql2600_fw.bin"
6195#define FW_FILE_ISP8031 "ql8300_fw.bin"
2c5bbbb2 6196#define FW_FILE_ISP27XX "ql2700_fw.bin"
f73cb695 6197
bb8ee499 6198
e1e82b6f 6199static DEFINE_MUTEX(qla_fw_lock);
5433383e
AV		 6200
6201static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
bb8ee499
AV		 6202 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6203 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6204 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6205 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6206 { .name = FW_FILE_ISP24XX, },
c3a2f0df 6207 { .name = FW_FILE_ISP25XX, },
3a03eb79 6208 { .name = FW_FILE_ISP81XX, },
a9083016 6209 { .name = FW_FILE_ISP82XX, },
6246b8a1
GM		 6210 { .name = FW_FILE_ISP2031, },
6211 { .name = FW_FILE_ISP8031, },
2c5bbbb2 6212 { .name = FW_FILE_ISP27XX, },
5433383e
AV		 6213};
6214
6215struct fw_blob *
e315cd28 6216qla2x00_request_firmware(scsi_qla_host_t *vha)
5433383e 6217{
e315cd28 6218 struct qla_hw_data *ha = vha->hw;
5433383e
AV		 6219 struct fw_blob *blob;
6220
5433383e
AV		 6221 if (IS_QLA2100(ha)) {
6222 blob = &qla_fw_blobs[FW_ISP21XX];
6223 } else if (IS_QLA2200(ha)) {
6224 blob = &qla_fw_blobs[FW_ISP22XX];
48c02fde 6225 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
5433383e 6226 blob = &qla_fw_blobs[FW_ISP2300];
48c02fde 6227 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
5433383e 6228 blob = &qla_fw_blobs[FW_ISP2322];
4d4df193 6229 } else if (IS_QLA24XX_TYPE(ha)) {
5433383e 6230 blob = &qla_fw_blobs[FW_ISP24XX];
c3a2f0df
AV		 6231 } else if (IS_QLA25XX(ha)) {
6232 blob = &qla_fw_blobs[FW_ISP25XX];
3a03eb79
AV		 6233 } else if (IS_QLA81XX(ha)) {
6234 blob = &qla_fw_blobs[FW_ISP81XX];
a9083016
GM		 6235 } else if (IS_QLA82XX(ha)) {
6236 blob = &qla_fw_blobs[FW_ISP82XX];
6246b8a1
GM		 6237 } else if (IS_QLA2031(ha)) {
6238 blob = &qla_fw_blobs[FW_ISP2031];
6239 } else if (IS_QLA8031(ha)) {
6240 blob = &qla_fw_blobs[FW_ISP8031];
2c5bbbb2
JC		 6241 } else if (IS_QLA27XX(ha)) {
6242 blob = &qla_fw_blobs[FW_ISP27XX];
8a655229
DC		 6243 } else {
6244 return NULL;
5433383e
AV		 6245 }
6246
e1e82b6f 6247 mutex_lock(&qla_fw_lock);
5433383e
AV		 6248 if (blob->fw)
6249 goto out;
6250
6251 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
7c3df132
SK		 6252 ql_log(ql_log_warn, vha, 0x0063,
6253 "Failed to load firmware image (%s).\n", blob->name);
5433383e
AV		 6254 blob->fw = NULL;
6255 blob = NULL;
6256 goto out;
6257 }
6258
6259out:
e1e82b6f 6260 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6261 return blob;
6262}
6263
6264static void
6265qla2x00_release_firmware(void)
6266{
6267 int idx;
6268
e1e82b6f 6269 mutex_lock(&qla_fw_lock);
5433383e 6270 for (idx = 0; idx < FW_BLOBS; idx++)
cf92549f 6271 release_firmware(qla_fw_blobs[idx].fw);
e1e82b6f 6272 mutex_unlock(&qla_fw_lock);
5433383e
AV		 6273}
6274
14e660e6
SJ		 6275static pci_ers_result_t
6276qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6277{
85880801
AV		 6278 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6279 struct qla_hw_data *ha = vha->hw;
6280
7c3df132
SK		 6281 ql_dbg(ql_dbg_aer, vha, 0x9000,
6282 "PCI error detected, state %x.\n", state);
b9b12f73 6283
efdb5760
SC		 6284 if (!atomic_read(&pdev->enable_cnt)) {
6285 ql_log(ql_log_info, vha, 0xffff,
6286 "PCI device is disabled,state %x\n", state);
6287 return PCI_ERS_RESULT_NEED_RESET;
6288 }
6289
14e660e6
SJ		 6290 switch (state) {
6291 case pci_channel_io_normal:
85880801 6292 ha->flags.eeh_busy = 0;
d7459527
MH		 6293 if (ql2xmqsupport) {
6294 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6295 qla2xxx_wake_dpc(vha);
6296 }
14e660e6
SJ		 6297 return PCI_ERS_RESULT_CAN_RECOVER;
6298 case pci_channel_io_frozen:
85880801 6299 ha->flags.eeh_busy = 1;
a5b36321
LC		 6300 /* For ISP82XX complete any pending mailbox cmd */
6301 if (IS_QLA82XX(ha)) {
7190575f 6302 ha->flags.isp82xx_fw_hung = 1;
c8f6544e
CD		 6303 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6304 qla82xx_clear_pending_mbx(vha);
a5b36321 6305 }
90a86fc0 6306 qla2x00_free_irqs(vha);
14e660e6 6307 pci_disable_device(pdev);
bddd2d65
LC		 6308 /* Return back all IOs */
6309 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
d7459527
MH		 6310 if (ql2xmqsupport) {
6311 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6312 qla2xxx_wake_dpc(vha);
6313 }
14e660e6
SJ		 6314 return PCI_ERS_RESULT_NEED_RESET;
6315 case pci_channel_io_perm_failure:
85880801
AV		 6316 ha->flags.pci_channel_io_perm_failure = 1;
6317 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
d7459527
MH		 6318 if (ql2xmqsupport) {
6319 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6320 qla2xxx_wake_dpc(vha);
6321 }
14e660e6
SJ		 6322 return PCI_ERS_RESULT_DISCONNECT;
6323 }
6324 return PCI_ERS_RESULT_NEED_RESET;
6325}
6326
6327static pci_ers_result_t
6328qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6329{
6330 int risc_paused = 0;
6331 uint32_t stat;
6332 unsigned long flags;
e315cd28
AC		 6333 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6334 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6335 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6336 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6337
bcc5b6d3
SK		 6338 if (IS_QLA82XX(ha))
6339 return PCI_ERS_RESULT_RECOVERED;
6340
14e660e6
SJ		 6341 spin_lock_irqsave(&ha->hardware_lock, flags);
6342 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6343 stat = RD_REG_DWORD(&reg->hccr);
6344 if (stat & HCCR_RISC_PAUSE)
6345 risc_paused = 1;
6346 } else if (IS_QLA23XX(ha)) {
6347 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6348 if (stat & HSR_RISC_PAUSED)
6349 risc_paused = 1;
6350 } else if (IS_FWI2_CAPABLE(ha)) {
6351 stat = RD_REG_DWORD(&reg24->host_status);
6352 if (stat & HSRX_RISC_PAUSED)
6353 risc_paused = 1;
6354 }
6355 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6356
6357 if (risc_paused) {
7c3df132
SK		 6358 ql_log(ql_log_info, base_vha, 0x9003,
6359 "RISC paused -- mmio_enabled, Dumping firmware.\n");
e315cd28 6360 ha->isp_ops->fw_dump(base_vha, 0);
14e660e6
SJ		 6361
6362 return PCI_ERS_RESULT_NEED_RESET;
6363 } else
6364 return PCI_ERS_RESULT_RECOVERED;
6365}
6366
fa492630
SK		 6367static uint32_t
6368qla82xx_error_recovery(scsi_qla_host_t *base_vha)
a5b36321
LC		 6369{
6370 uint32_t rval = QLA_FUNCTION_FAILED;
6371 uint32_t drv_active = 0;
6372 struct qla_hw_data *ha = base_vha->hw;
6373 int fn;
6374 struct pci_dev *other_pdev = NULL;
6375
7c3df132
SK		 6376 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6377 "Entered %s.\n", __func__);
a5b36321
LC		 6378
6379 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6380
6381 if (base_vha->flags.online) {
6382 /* Abort all outstanding commands,
6383 * so as to be requeued later */
6384 qla2x00_abort_isp_cleanup(base_vha);
6385 }
6386
6387
6388 fn = PCI_FUNC(ha->pdev->devfn);
6389 while (fn > 0) {
6390 fn--;
7c3df132
SK		 6391 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6392 "Finding pci device at function = 0x%x.\n", fn);
a5b36321
LC		 6393 other_pdev =
6394 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6395 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6396 fn));
6397
6398 if (!other_pdev)
6399 continue;
6400 if (atomic_read(&other_pdev->enable_cnt)) {
7c3df132
SK		 6401 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6402 "Found PCI func available and enable at 0x%x.\n",
6403 fn);
a5b36321
LC		 6404 pci_dev_put(other_pdev);
6405 break;
6406 }
6407 pci_dev_put(other_pdev);
6408 }
6409
6410 if (!fn) {
6411 /* Reset owner */
7c3df132
SK		 6412 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6413 "This devfn is reset owner = 0x%x.\n",
6414 ha->pdev->devfn);
a5b36321
LC		 6415 qla82xx_idc_lock(ha);
6416
6417 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6418 QLA8XXX_DEV_INITIALIZING);
a5b36321
LC		 6419
6420 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6421 QLA82XX_IDC_VERSION);
6422
6423 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
7c3df132
SK		 6424 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6425 "drv_active = 0x%x.\n", drv_active);
a5b36321
LC		 6426
6427 qla82xx_idc_unlock(ha);
6428 /* Reset if device is not already reset
6429 * drv_active would be 0 if a reset has already been done
6430 */
6431 if (drv_active)
6432 rval = qla82xx_start_firmware(base_vha);
6433 else
6434 rval = QLA_SUCCESS;
6435 qla82xx_idc_lock(ha);
6436
6437 if (rval != QLA_SUCCESS) {
7c3df132
SK		 6438 ql_log(ql_log_info, base_vha, 0x900b,
6439 "HW State: FAILED.\n");
a5b36321
LC		 6440 qla82xx_clear_drv_active(ha);
6441 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6442 QLA8XXX_DEV_FAILED);
a5b36321 6443 } else {
7c3df132
SK		 6444 ql_log(ql_log_info, base_vha, 0x900c,
6445 "HW State: READY.\n");
a5b36321 6446 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
7d613ac6 6447 QLA8XXX_DEV_READY);
a5b36321 6448 qla82xx_idc_unlock(ha);
7190575f 6449 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6450 rval = qla82xx_restart_isp(base_vha);
6451 qla82xx_idc_lock(ha);
6452 /* Clear driver state register */
6453 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6454 qla82xx_set_drv_active(base_vha);
6455 }
6456 qla82xx_idc_unlock(ha);
6457 } else {
7c3df132
SK		 6458 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6459 "This devfn is not reset owner = 0x%x.\n",
6460 ha->pdev->devfn);
a5b36321 6461 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
7d613ac6 6462 QLA8XXX_DEV_READY)) {
7190575f 6463 ha->flags.isp82xx_fw_hung = 0;
a5b36321
LC		 6464 rval = qla82xx_restart_isp(base_vha);
6465 qla82xx_idc_lock(ha);
6466 qla82xx_set_drv_active(base_vha);
6467 qla82xx_idc_unlock(ha);
6468 }
6469 }
6470 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6471
6472 return rval;
6473}
6474
14e660e6
SJ		 6475static pci_ers_result_t
6476qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6477{
6478 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
e315cd28
AC		 6479 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6480 struct qla_hw_data *ha = base_vha->hw;
90a86fc0
JC		 6481 struct rsp_que *rsp;
6482 int rc, retries = 10;
09483916 6483
7c3df132
SK		 6484 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6485 "Slot Reset.\n");
85880801 6486
90a86fc0
JC		 6487 /* Workaround: qla2xxx driver which access hardware earlier
6488 * needs error state to be pci_channel_io_online.
6489 * Otherwise mailbox command timesout.
6490 */
6491 pdev->error_state = pci_channel_io_normal;
6492
6493 pci_restore_state(pdev);
6494
8c1496bd
RL		 6495 /* pci_restore_state() clears the saved_state flag of the device
6496 * save restored state which resets saved_state flag
6497 */
6498 pci_save_state(pdev);
6499
09483916
BH		 6500 if (ha->mem_only)
6501 rc = pci_enable_device_mem(pdev);
6502 else
6503 rc = pci_enable_device(pdev);
14e660e6 6504
09483916 6505 if (rc) {
7c3df132 6506 ql_log(ql_log_warn, base_vha, 0x9005,
14e660e6 6507 "Can't re-enable PCI device after reset.\n");
a5b36321 6508 goto exit_slot_reset;
14e660e6 6509 }
14e660e6 6510
90a86fc0
JC		 6511 rsp = ha->rsp_q_map[0];
6512 if (qla2x00_request_irqs(ha, rsp))
a5b36321 6513 goto exit_slot_reset;
90a86fc0 6514
e315cd28 6515 if (ha->isp_ops->pci_config(base_vha))
a5b36321
LC		 6516 goto exit_slot_reset;
6517
6518 if (IS_QLA82XX(ha)) {
6519 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6520 ret = PCI_ERS_RESULT_RECOVERED;
6521 goto exit_slot_reset;
6522 } else
6523 goto exit_slot_reset;
6524 }
14e660e6 6525
90a86fc0
JC		 6526 while (ha->flags.mbox_busy && retries--)
6527 msleep(1000);
85880801 6528
e315cd28 6529 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
a9083016 6530 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
14e660e6 6531 ret = PCI_ERS_RESULT_RECOVERED;
e315cd28 6532 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
14e660e6 6533
90a86fc0 6534
a5b36321 6535exit_slot_reset:
7c3df132
SK		 6536 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6537 "slot_reset return %x.\n", ret);
85880801 6538
14e660e6
SJ		 6539 return ret;
6540}
6541
6542static void
6543qla2xxx_pci_resume(struct pci_dev *pdev)
6544{
e315cd28
AC		 6545 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6546 struct qla_hw_data *ha = base_vha->hw;
14e660e6
SJ		 6547 int ret;
6548
7c3df132
SK		 6549 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6550 "pci_resume.\n");
85880801 6551
e315cd28 6552 ret = qla2x00_wait_for_hba_online(base_vha);
14e660e6 6553 if (ret != QLA_SUCCESS) {
7c3df132
SK		 6554 ql_log(ql_log_fatal, base_vha, 0x9002,
6555 "The device failed to resume I/O from slot/link_reset.\n");
14e660e6 6556 }
85880801 6557
3e46f031
LC		 6558 pci_cleanup_aer_uncorrect_error_status(pdev);
6559
85880801 6560 ha->flags.eeh_busy = 0;
14e660e6
SJ		 6561}
6562
2d5a4c34
HM		 6563static void
6564qla83xx_disable_laser(scsi_qla_host_t *vha)
6565{
6566 uint32_t reg, data, fn;
6567 struct qla_hw_data *ha = vha->hw;
6568 struct device_reg_24xx __iomem *isp_reg = &ha->iobase->isp24;
6569
6570 /* pci func #/port # */
6571 ql_dbg(ql_dbg_init, vha, 0x004b,
6572 "Disabling Laser for hba: %p\n", vha);
6573
6574 fn = (RD_REG_DWORD(&isp_reg->ctrl_status) &
6575 (BIT_15|BIT_14|BIT_13|BIT_12));
6576
6577 fn = (fn >> 12);
6578
6579 if (fn & 1)
6580 reg = PORT_1_2031;
6581 else
6582 reg = PORT_0_2031;
6583
6584 data = LASER_OFF_2031;
6585
6586 qla83xx_wr_reg(vha, reg, data);
6587}
6588
5601236b
MH		 6589static int qla2xxx_map_queues(struct Scsi_Host *shost)
6590{
6591 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6592
6593 return blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev);
6594}
6595
a55b2d21 6596static const struct pci_error_handlers qla2xxx_err_handler = {
14e660e6
SJ		 6597 .error_detected = qla2xxx_pci_error_detected,
6598 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6599 .slot_reset = qla2xxx_pci_slot_reset,
6600 .resume = qla2xxx_pci_resume,
6601};
6602
5433383e 6603static struct pci_device_id qla2xxx_pci_tbl[] = {
47f5e069
AV		 6604 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6605 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6606 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6607 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6608 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6609 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6610 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6611 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6612 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
4d4df193 6613 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
47f5e069
AV		 6614 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6615 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
c3a2f0df 6616 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6246b8a1 6617 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
3a03eb79 6618 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
a9083016 6619 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
650f528f 6620 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
8ae6d9c7 6621 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
7ec0effd 6622 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
f73cb695 6623 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
2c5bbbb2 6624 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
2b48992f 6625 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
5433383e
AV		 6626 { 0 },
6627};
6628MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6629
fca29703 6630static struct pci_driver qla2xxx_pci_driver = {
cb63067a 6631 .name = QLA2XXX_DRIVER_NAME,
0a21ef1e
JB		 6632 .driver = {
6633 .owner = THIS_MODULE,
6634 },
fca29703 6635 .id_table = qla2xxx_pci_tbl,
7ee61397 6636 .probe = qla2x00_probe_one,
4c993f76 6637 .remove = qla2x00_remove_one,
e30d1756 6638 .shutdown = qla2x00_shutdown,
14e660e6 6639 .err_handler = &qla2xxx_err_handler,
fca29703
AV		 6640};
6641
75ef9de1 6642static const struct file_operations apidev_fops = {
6a03b4cd 6643 .owner = THIS_MODULE,
6038f373 6644 .llseek = noop_llseek,
6a03b4cd
HZ		 6645};
6646
1da177e4
LT		 6647/**
6648 * qla2x00_module_init - Module initialization.
6649 **/
6650static int __init
6651qla2x00_module_init(void)
6652{
fca29703
AV		 6653 int ret = 0;
6654
1da177e4 6655 /* Allocate cache for SRBs. */
354d6b21 6656 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
20c2df83 6657 SLAB_HWCACHE_ALIGN, NULL);
1da177e4 6658 if (srb_cachep == NULL) {
7c3df132
SK		 6659 ql_log(ql_log_fatal, NULL, 0x0001,
6660 "Unable to allocate SRB cache...Failing load!.\n");
1da177e4
LT		 6661 return -ENOMEM;
6662 }
6663
2d70c103
NB		 6664 /* Initialize target kmem_cache and mem_pools */
6665 ret = qlt_init();
6666 if (ret < 0) {
6667 kmem_cache_destroy(srb_cachep);
6668 return ret;
6669 } else if (ret > 0) {
6670 /*
6671 * If initiator mode is explictly disabled by qlt_init(),
6672 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
6673 * performing scsi_scan_target() during LOOP UP event.
6674 */
6675 qla2xxx_transport_functions.disable_target_scan = 1;
6676 qla2xxx_transport_vport_functions.disable_target_scan = 1;
6677 }
6678
1da177e4
LT		 6679 /* Derive version string. */
6680 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
11010fec 6681 if (ql2xextended_error_logging)
0181944f 6682 strcat(qla2x00_version_str, "-debug");
fed0f68a
JC		 6683 if (ql2xextended_error_logging == 1)
6684 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
0181944f 6685
1c97a12a
AV		 6686 qla2xxx_transport_template =
6687 fc_attach_transport(&qla2xxx_transport_functions);
2c3dfe3f
SJ		 6688 if (!qla2xxx_transport_template) {
6689 kmem_cache_destroy(srb_cachep);
7c3df132
SK		 6690 ql_log(ql_log_fatal, NULL, 0x0002,
6691 "fc_attach_transport failed...Failing load!.\n");
2d70c103 6692 qlt_exit();
1da177e4 6693 return -ENODEV;
2c3dfe3f 6694 }
6a03b4cd
HZ		 6695
6696 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
6697 if (apidev_major < 0) {
7c3df132
SK		 6698 ql_log(ql_log_fatal, NULL, 0x0003,
6699 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
6a03b4cd
HZ		 6700 }
6701
2c3dfe3f
SJ		 6702 qla2xxx_transport_vport_template =
6703 fc_attach_transport(&qla2xxx_transport_vport_functions);
6704 if (!qla2xxx_transport_vport_template) {
6705 kmem_cache_destroy(srb_cachep);
2d70c103 6706 qlt_exit();
2c3dfe3f 6707 fc_release_transport(qla2xxx_transport_template);
7c3df132
SK		 6708 ql_log(ql_log_fatal, NULL, 0x0004,
6709 "fc_attach_transport vport failed...Failing load!.\n");
1da177e4 6710 return -ENODEV;
2c3dfe3f 6711 }
7c3df132
SK		 6712 ql_log(ql_log_info, NULL, 0x0005,
6713 "QLogic Fibre Channel HBA Driver: %s.\n",
fd9a29f0 6714 qla2x00_version_str);
7ee61397 6715 ret = pci_register_driver(&qla2xxx_pci_driver);
fca29703
AV		 6716 if (ret) {
6717 kmem_cache_destroy(srb_cachep);
2d70c103 6718 qlt_exit();
fca29703 6719 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6720 fc_release_transport(qla2xxx_transport_vport_template);
7c3df132
SK		 6721 ql_log(ql_log_fatal, NULL, 0x0006,
6722 "pci_register_driver failed...ret=%d Failing load!.\n",
6723 ret);
fca29703
AV		 6724 }
6725 return ret;
1da177e4
LT		 6726}
6727
6728/**
6729 * qla2x00_module_exit - Module cleanup.
6730 **/
6731static void __exit
6732qla2x00_module_exit(void)
6733{
6a03b4cd 6734 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7ee61397 6735 pci_unregister_driver(&qla2xxx_pci_driver);
5433383e 6736 qla2x00_release_firmware();
354d6b21 6737 kmem_cache_destroy(srb_cachep);
2d70c103 6738 qlt_exit();
a9083016
GM		 6739 if (ctx_cachep)
6740 kmem_cache_destroy(ctx_cachep);
1da177e4 6741 fc_release_transport(qla2xxx_transport_template);
2c3dfe3f 6742 fc_release_transport(qla2xxx_transport_vport_template);
1da177e4
LT		 6743}
6744
6745module_init(qla2x00_module_init);
6746module_exit(qla2x00_module_exit);
6747
6748MODULE_AUTHOR("QLogic Corporation");
6749MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
6750MODULE_LICENSE("GPL");
6751MODULE_VERSION(QLA2XXX_VERSION);
bb8ee499
AV		 6752MODULE_FIRMWARE(FW_FILE_ISP21XX);
6753MODULE_FIRMWARE(FW_FILE_ISP22XX);
6754MODULE_FIRMWARE(FW_FILE_ISP2300);
6755MODULE_FIRMWARE(FW_FILE_ISP2322);
6756MODULE_FIRMWARE(FW_FILE_ISP24XX);
61623fc3 6757MODULE_FIRMWARE(FW_FILE_ISP25XX);
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