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Commit | Line | Data |
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e3b3d0f5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
c9e2e946 JL |
2 | /* |
3 | * Freescale lpuart serial port driver | |
4 | * | |
380c966c | 5 | * Copyright 2012-2014 Freescale Semiconductor, Inc. |
c9e2e946 JL |
6 | */ |
7 | ||
8 | #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
9 | #define SUPPORT_SYSRQ | |
10 | #endif | |
11 | ||
f1cd8c87 YY |
12 | #include <linux/clk.h> |
13 | #include <linux/console.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/dmaengine.h> | |
16 | #include <linux/dmapool.h> | |
c9e2e946 JL |
17 | #include <linux/io.h> |
18 | #include <linux/irq.h> | |
f1cd8c87 | 19 | #include <linux/module.h> |
c9e2e946 JL |
20 | #include <linux/of.h> |
21 | #include <linux/of_device.h> | |
f1cd8c87 | 22 | #include <linux/of_dma.h> |
c9e2e946 | 23 | #include <linux/serial_core.h> |
f1cd8c87 | 24 | #include <linux/slab.h> |
c9e2e946 JL |
25 | #include <linux/tty_flip.h> |
26 | ||
27 | /* All registers are 8-bit width */ | |
28 | #define UARTBDH 0x00 | |
29 | #define UARTBDL 0x01 | |
30 | #define UARTCR1 0x02 | |
31 | #define UARTCR2 0x03 | |
32 | #define UARTSR1 0x04 | |
33 | #define UARTCR3 0x06 | |
34 | #define UARTDR 0x07 | |
35 | #define UARTCR4 0x0a | |
36 | #define UARTCR5 0x0b | |
37 | #define UARTMODEM 0x0d | |
38 | #define UARTPFIFO 0x10 | |
39 | #define UARTCFIFO 0x11 | |
40 | #define UARTSFIFO 0x12 | |
41 | #define UARTTWFIFO 0x13 | |
42 | #define UARTTCFIFO 0x14 | |
43 | #define UARTRWFIFO 0x15 | |
44 | ||
45 | #define UARTBDH_LBKDIE 0x80 | |
46 | #define UARTBDH_RXEDGIE 0x40 | |
47 | #define UARTBDH_SBR_MASK 0x1f | |
48 | ||
49 | #define UARTCR1_LOOPS 0x80 | |
50 | #define UARTCR1_RSRC 0x20 | |
51 | #define UARTCR1_M 0x10 | |
52 | #define UARTCR1_WAKE 0x08 | |
53 | #define UARTCR1_ILT 0x04 | |
54 | #define UARTCR1_PE 0x02 | |
55 | #define UARTCR1_PT 0x01 | |
56 | ||
57 | #define UARTCR2_TIE 0x80 | |
58 | #define UARTCR2_TCIE 0x40 | |
59 | #define UARTCR2_RIE 0x20 | |
60 | #define UARTCR2_ILIE 0x10 | |
61 | #define UARTCR2_TE 0x08 | |
62 | #define UARTCR2_RE 0x04 | |
63 | #define UARTCR2_RWU 0x02 | |
64 | #define UARTCR2_SBK 0x01 | |
65 | ||
66 | #define UARTSR1_TDRE 0x80 | |
67 | #define UARTSR1_TC 0x40 | |
68 | #define UARTSR1_RDRF 0x20 | |
69 | #define UARTSR1_IDLE 0x10 | |
70 | #define UARTSR1_OR 0x08 | |
71 | #define UARTSR1_NF 0x04 | |
72 | #define UARTSR1_FE 0x02 | |
73 | #define UARTSR1_PE 0x01 | |
74 | ||
75 | #define UARTCR3_R8 0x80 | |
76 | #define UARTCR3_T8 0x40 | |
77 | #define UARTCR3_TXDIR 0x20 | |
78 | #define UARTCR3_TXINV 0x10 | |
79 | #define UARTCR3_ORIE 0x08 | |
80 | #define UARTCR3_NEIE 0x04 | |
81 | #define UARTCR3_FEIE 0x02 | |
82 | #define UARTCR3_PEIE 0x01 | |
83 | ||
84 | #define UARTCR4_MAEN1 0x80 | |
85 | #define UARTCR4_MAEN2 0x40 | |
86 | #define UARTCR4_M10 0x20 | |
87 | #define UARTCR4_BRFA_MASK 0x1f | |
88 | #define UARTCR4_BRFA_OFF 0 | |
89 | ||
90 | #define UARTCR5_TDMAS 0x80 | |
91 | #define UARTCR5_RDMAS 0x20 | |
92 | ||
93 | #define UARTMODEM_RXRTSE 0x08 | |
94 | #define UARTMODEM_TXRTSPOL 0x04 | |
95 | #define UARTMODEM_TXRTSE 0x02 | |
96 | #define UARTMODEM_TXCTSE 0x01 | |
97 | ||
98 | #define UARTPFIFO_TXFE 0x80 | |
99 | #define UARTPFIFO_FIFOSIZE_MASK 0x7 | |
100 | #define UARTPFIFO_TXSIZE_OFF 4 | |
101 | #define UARTPFIFO_RXFE 0x08 | |
102 | #define UARTPFIFO_RXSIZE_OFF 0 | |
103 | ||
104 | #define UARTCFIFO_TXFLUSH 0x80 | |
105 | #define UARTCFIFO_RXFLUSH 0x40 | |
106 | #define UARTCFIFO_RXOFE 0x04 | |
107 | #define UARTCFIFO_TXOFE 0x02 | |
108 | #define UARTCFIFO_RXUFE 0x01 | |
109 | ||
110 | #define UARTSFIFO_TXEMPT 0x80 | |
111 | #define UARTSFIFO_RXEMPT 0x40 | |
112 | #define UARTSFIFO_RXOF 0x04 | |
113 | #define UARTSFIFO_TXOF 0x02 | |
114 | #define UARTSFIFO_RXUF 0x01 | |
115 | ||
a5fa2660 | 116 | /* 32-bit register definition */ |
380c966c JL |
117 | #define UARTBAUD 0x00 |
118 | #define UARTSTAT 0x04 | |
119 | #define UARTCTRL 0x08 | |
120 | #define UARTDATA 0x0C | |
121 | #define UARTMATCH 0x10 | |
122 | #define UARTMODIR 0x14 | |
123 | #define UARTFIFO 0x18 | |
124 | #define UARTWATER 0x1c | |
125 | ||
126 | #define UARTBAUD_MAEN1 0x80000000 | |
127 | #define UARTBAUD_MAEN2 0x40000000 | |
128 | #define UARTBAUD_M10 0x20000000 | |
129 | #define UARTBAUD_TDMAE 0x00800000 | |
130 | #define UARTBAUD_RDMAE 0x00200000 | |
131 | #define UARTBAUD_MATCFG 0x00400000 | |
132 | #define UARTBAUD_BOTHEDGE 0x00020000 | |
133 | #define UARTBAUD_RESYNCDIS 0x00010000 | |
134 | #define UARTBAUD_LBKDIE 0x00008000 | |
135 | #define UARTBAUD_RXEDGIE 0x00004000 | |
136 | #define UARTBAUD_SBNS 0x00002000 | |
137 | #define UARTBAUD_SBR 0x00000000 | |
138 | #define UARTBAUD_SBR_MASK 0x1fff | |
a6d7514b DA |
139 | #define UARTBAUD_OSR_MASK 0x1f |
140 | #define UARTBAUD_OSR_SHIFT 24 | |
380c966c JL |
141 | |
142 | #define UARTSTAT_LBKDIF 0x80000000 | |
143 | #define UARTSTAT_RXEDGIF 0x40000000 | |
144 | #define UARTSTAT_MSBF 0x20000000 | |
145 | #define UARTSTAT_RXINV 0x10000000 | |
146 | #define UARTSTAT_RWUID 0x08000000 | |
147 | #define UARTSTAT_BRK13 0x04000000 | |
148 | #define UARTSTAT_LBKDE 0x02000000 | |
149 | #define UARTSTAT_RAF 0x01000000 | |
150 | #define UARTSTAT_TDRE 0x00800000 | |
151 | #define UARTSTAT_TC 0x00400000 | |
152 | #define UARTSTAT_RDRF 0x00200000 | |
153 | #define UARTSTAT_IDLE 0x00100000 | |
154 | #define UARTSTAT_OR 0x00080000 | |
155 | #define UARTSTAT_NF 0x00040000 | |
156 | #define UARTSTAT_FE 0x00020000 | |
157 | #define UARTSTAT_PE 0x00010000 | |
158 | #define UARTSTAT_MA1F 0x00008000 | |
159 | #define UARTSTAT_M21F 0x00004000 | |
160 | ||
161 | #define UARTCTRL_R8T9 0x80000000 | |
162 | #define UARTCTRL_R9T8 0x40000000 | |
163 | #define UARTCTRL_TXDIR 0x20000000 | |
164 | #define UARTCTRL_TXINV 0x10000000 | |
165 | #define UARTCTRL_ORIE 0x08000000 | |
166 | #define UARTCTRL_NEIE 0x04000000 | |
167 | #define UARTCTRL_FEIE 0x02000000 | |
168 | #define UARTCTRL_PEIE 0x01000000 | |
169 | #define UARTCTRL_TIE 0x00800000 | |
170 | #define UARTCTRL_TCIE 0x00400000 | |
171 | #define UARTCTRL_RIE 0x00200000 | |
172 | #define UARTCTRL_ILIE 0x00100000 | |
173 | #define UARTCTRL_TE 0x00080000 | |
174 | #define UARTCTRL_RE 0x00040000 | |
175 | #define UARTCTRL_RWU 0x00020000 | |
176 | #define UARTCTRL_SBK 0x00010000 | |
177 | #define UARTCTRL_MA1IE 0x00008000 | |
178 | #define UARTCTRL_MA2IE 0x00004000 | |
179 | #define UARTCTRL_IDLECFG 0x00000100 | |
180 | #define UARTCTRL_LOOPS 0x00000080 | |
181 | #define UARTCTRL_DOZEEN 0x00000040 | |
182 | #define UARTCTRL_RSRC 0x00000020 | |
183 | #define UARTCTRL_M 0x00000010 | |
184 | #define UARTCTRL_WAKE 0x00000008 | |
185 | #define UARTCTRL_ILT 0x00000004 | |
186 | #define UARTCTRL_PE 0x00000002 | |
187 | #define UARTCTRL_PT 0x00000001 | |
188 | ||
189 | #define UARTDATA_NOISY 0x00008000 | |
190 | #define UARTDATA_PARITYE 0x00004000 | |
191 | #define UARTDATA_FRETSC 0x00002000 | |
192 | #define UARTDATA_RXEMPT 0x00001000 | |
193 | #define UARTDATA_IDLINE 0x00000800 | |
194 | #define UARTDATA_MASK 0x3ff | |
195 | ||
196 | #define UARTMODIR_IREN 0x00020000 | |
197 | #define UARTMODIR_TXCTSSRC 0x00000020 | |
198 | #define UARTMODIR_TXCTSC 0x00000010 | |
199 | #define UARTMODIR_RXRTSE 0x00000008 | |
200 | #define UARTMODIR_TXRTSPOL 0x00000004 | |
201 | #define UARTMODIR_TXRTSE 0x00000002 | |
202 | #define UARTMODIR_TXCTSE 0x00000001 | |
203 | ||
204 | #define UARTFIFO_TXEMPT 0x00800000 | |
205 | #define UARTFIFO_RXEMPT 0x00400000 | |
206 | #define UARTFIFO_TXOF 0x00020000 | |
207 | #define UARTFIFO_RXUF 0x00010000 | |
208 | #define UARTFIFO_TXFLUSH 0x00008000 | |
209 | #define UARTFIFO_RXFLUSH 0x00004000 | |
210 | #define UARTFIFO_TXOFE 0x00000200 | |
211 | #define UARTFIFO_RXUFE 0x00000100 | |
212 | #define UARTFIFO_TXFE 0x00000080 | |
213 | #define UARTFIFO_FIFOSIZE_MASK 0x7 | |
214 | #define UARTFIFO_TXSIZE_OFF 4 | |
215 | #define UARTFIFO_RXFE 0x00000008 | |
216 | #define UARTFIFO_RXSIZE_OFF 0 | |
217 | ||
218 | #define UARTWATER_COUNT_MASK 0xff | |
219 | #define UARTWATER_TXCNT_OFF 8 | |
220 | #define UARTWATER_RXCNT_OFF 24 | |
221 | #define UARTWATER_WATER_MASK 0xff | |
222 | #define UARTWATER_TXWATER_OFF 0 | |
223 | #define UARTWATER_RXWATER_OFF 16 | |
224 | ||
5887ad43 BD |
225 | /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ |
226 | #define DMA_RX_TIMEOUT (10) | |
f1cd8c87 | 227 | |
c9e2e946 JL |
228 | #define DRIVER_NAME "fsl-lpuart" |
229 | #define DEV_NAME "ttyLP" | |
230 | #define UART_NR 6 | |
231 | ||
24b1e5f0 DA |
232 | /* IMX lpuart has four extra unused regs located at the beginning */ |
233 | #define IMX_REG_OFF 0x10 | |
234 | ||
c9e2e946 JL |
235 | struct lpuart_port { |
236 | struct uart_port port; | |
237 | struct clk *clk; | |
238 | unsigned int txfifo_size; | |
239 | unsigned int rxfifo_size; | |
f1cd8c87 | 240 | |
4a818c43 SA |
241 | bool lpuart_dma_tx_use; |
242 | bool lpuart_dma_rx_use; | |
f1cd8c87 YY |
243 | struct dma_chan *dma_tx_chan; |
244 | struct dma_chan *dma_rx_chan; | |
245 | struct dma_async_tx_descriptor *dma_tx_desc; | |
246 | struct dma_async_tx_descriptor *dma_rx_desc; | |
f1cd8c87 YY |
247 | dma_cookie_t dma_tx_cookie; |
248 | dma_cookie_t dma_rx_cookie; | |
f1cd8c87 YY |
249 | unsigned int dma_tx_bytes; |
250 | unsigned int dma_rx_bytes; | |
6250cc30 | 251 | bool dma_tx_in_progress; |
f1cd8c87 YY |
252 | unsigned int dma_rx_timeout; |
253 | struct timer_list lpuart_timer; | |
6250cc30 | 254 | struct scatterlist rx_sgl, tx_sgl[2]; |
5887ad43 BD |
255 | struct circ_buf rx_ring; |
256 | int rx_dma_rng_buf_len; | |
6250cc30 BD |
257 | unsigned int dma_tx_nents; |
258 | wait_queue_head_t dma_wait; | |
c9e2e946 JL |
259 | }; |
260 | ||
0d6fce90 DA |
261 | struct lpuart_soc_data { |
262 | char iotype; | |
24b1e5f0 | 263 | u8 reg_off; |
0d6fce90 DA |
264 | }; |
265 | ||
266 | static const struct lpuart_soc_data vf_data = { | |
267 | .iotype = UPIO_MEM, | |
268 | }; | |
269 | ||
270 | static const struct lpuart_soc_data ls_data = { | |
271 | .iotype = UPIO_MEM32BE, | |
272 | }; | |
273 | ||
24b1e5f0 DA |
274 | static struct lpuart_soc_data imx_data = { |
275 | .iotype = UPIO_MEM32, | |
276 | .reg_off = IMX_REG_OFF, | |
277 | }; | |
278 | ||
ed0bb232 | 279 | static const struct of_device_id lpuart_dt_ids[] = { |
0d6fce90 DA |
280 | { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, |
281 | { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, }, | |
24b1e5f0 | 282 | { .compatible = "fsl,imx7ulp-lpuart", .data = &imx_data, }, |
c9e2e946 JL |
283 | { /* sentinel */ } |
284 | }; | |
285 | MODULE_DEVICE_TABLE(of, lpuart_dt_ids); | |
286 | ||
f1cd8c87 YY |
287 | /* Forward declare this for the dma callbacks*/ |
288 | static void lpuart_dma_tx_complete(void *arg); | |
f1cd8c87 | 289 | |
f98e1fcd DA |
290 | static inline u32 lpuart32_read(struct uart_port *port, u32 off) |
291 | { | |
292 | switch (port->iotype) { | |
293 | case UPIO_MEM32: | |
294 | return readl(port->membase + off); | |
295 | case UPIO_MEM32BE: | |
296 | return ioread32be(port->membase + off); | |
297 | default: | |
298 | return 0; | |
299 | } | |
380c966c JL |
300 | } |
301 | ||
a0204f25 | 302 | static inline void lpuart32_write(struct uart_port *port, u32 val, |
f98e1fcd DA |
303 | u32 off) |
304 | { | |
305 | switch (port->iotype) { | |
306 | case UPIO_MEM32: | |
307 | writel(val, port->membase + off); | |
308 | break; | |
309 | case UPIO_MEM32BE: | |
310 | iowrite32be(val, port->membase + off); | |
311 | break; | |
312 | } | |
380c966c JL |
313 | } |
314 | ||
c9e2e946 JL |
315 | static void lpuart_stop_tx(struct uart_port *port) |
316 | { | |
317 | unsigned char temp; | |
318 | ||
319 | temp = readb(port->membase + UARTCR2); | |
320 | temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); | |
321 | writeb(temp, port->membase + UARTCR2); | |
322 | } | |
323 | ||
380c966c JL |
324 | static void lpuart32_stop_tx(struct uart_port *port) |
325 | { | |
326 | unsigned long temp; | |
327 | ||
a0204f25 | 328 | temp = lpuart32_read(port, UARTCTRL); |
380c966c | 329 | temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); |
a0204f25 | 330 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
331 | } |
332 | ||
c9e2e946 JL |
333 | static void lpuart_stop_rx(struct uart_port *port) |
334 | { | |
335 | unsigned char temp; | |
336 | ||
337 | temp = readb(port->membase + UARTCR2); | |
338 | writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); | |
339 | } | |
340 | ||
380c966c JL |
341 | static void lpuart32_stop_rx(struct uart_port *port) |
342 | { | |
343 | unsigned long temp; | |
344 | ||
a0204f25 DA |
345 | temp = lpuart32_read(port, UARTCTRL); |
346 | lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); | |
380c966c JL |
347 | } |
348 | ||
6250cc30 | 349 | static void lpuart_dma_tx(struct lpuart_port *sport) |
f1cd8c87 YY |
350 | { |
351 | struct circ_buf *xmit = &sport->port.state->xmit; | |
6250cc30 BD |
352 | struct scatterlist *sgl = sport->tx_sgl; |
353 | struct device *dev = sport->port.dev; | |
354 | int ret; | |
f1cd8c87 | 355 | |
6250cc30 BD |
356 | if (sport->dma_tx_in_progress) |
357 | return; | |
f1cd8c87 | 358 | |
6250cc30 | 359 | sport->dma_tx_bytes = uart_circ_chars_pending(xmit); |
f1cd8c87 | 360 | |
d704b2d3 | 361 | if (xmit->tail < xmit->head || xmit->head == 0) { |
6250cc30 BD |
362 | sport->dma_tx_nents = 1; |
363 | sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); | |
364 | } else { | |
365 | sport->dma_tx_nents = 2; | |
366 | sg_init_table(sgl, 2); | |
367 | sg_set_buf(sgl, xmit->buf + xmit->tail, | |
368 | UART_XMIT_SIZE - xmit->tail); | |
369 | sg_set_buf(sgl + 1, xmit->buf, xmit->head); | |
370 | } | |
f1cd8c87 | 371 | |
6250cc30 BD |
372 | ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
373 | if (!ret) { | |
374 | dev_err(dev, "DMA mapping error for TX.\n"); | |
375 | return; | |
376 | } | |
f1cd8c87 | 377 | |
6250cc30 BD |
378 | sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl, |
379 | sport->dma_tx_nents, | |
f1cd8c87 | 380 | DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); |
f1cd8c87 | 381 | if (!sport->dma_tx_desc) { |
6250cc30 BD |
382 | dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
383 | dev_err(dev, "Cannot prepare TX slave DMA!\n"); | |
384 | return; | |
f1cd8c87 YY |
385 | } |
386 | ||
387 | sport->dma_tx_desc->callback = lpuart_dma_tx_complete; | |
388 | sport->dma_tx_desc->callback_param = sport; | |
6250cc30 | 389 | sport->dma_tx_in_progress = true; |
f1cd8c87 YY |
390 | sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); |
391 | dma_async_issue_pending(sport->dma_tx_chan); | |
f1cd8c87 YY |
392 | } |
393 | ||
394 | static void lpuart_dma_tx_complete(void *arg) | |
395 | { | |
396 | struct lpuart_port *sport = arg; | |
6250cc30 | 397 | struct scatterlist *sgl = &sport->tx_sgl[0]; |
f1cd8c87 YY |
398 | struct circ_buf *xmit = &sport->port.state->xmit; |
399 | unsigned long flags; | |
400 | ||
f1cd8c87 YY |
401 | spin_lock_irqsave(&sport->port.lock, flags); |
402 | ||
6250cc30 BD |
403 | dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); |
404 | ||
f1cd8c87 | 405 | xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); |
6250cc30 BD |
406 | |
407 | sport->port.icount.tx += sport->dma_tx_bytes; | |
408 | sport->dma_tx_in_progress = false; | |
409 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
f1cd8c87 YY |
410 | |
411 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
412 | uart_write_wakeup(&sport->port); | |
413 | ||
6250cc30 BD |
414 | if (waitqueue_active(&sport->dma_wait)) { |
415 | wake_up(&sport->dma_wait); | |
416 | return; | |
417 | } | |
418 | ||
419 | spin_lock_irqsave(&sport->port.lock, flags); | |
420 | ||
421 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port)) | |
422 | lpuart_dma_tx(sport); | |
f1cd8c87 YY |
423 | |
424 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
425 | } | |
426 | ||
6250cc30 BD |
427 | static int lpuart_dma_tx_request(struct uart_port *port) |
428 | { | |
429 | struct lpuart_port *sport = container_of(port, | |
430 | struct lpuart_port, port); | |
431 | struct dma_slave_config dma_tx_sconfig = {}; | |
432 | int ret; | |
433 | ||
434 | dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR; | |
435 | dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
436 | dma_tx_sconfig.dst_maxburst = 1; | |
437 | dma_tx_sconfig.direction = DMA_MEM_TO_DEV; | |
438 | ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); | |
439 | ||
440 | if (ret) { | |
441 | dev_err(sport->port.dev, | |
442 | "DMA slave config failed, err = %d\n", ret); | |
443 | return ret; | |
444 | } | |
445 | ||
446 | return 0; | |
447 | } | |
448 | ||
bfc2e07f SA |
449 | static void lpuart_flush_buffer(struct uart_port *port) |
450 | { | |
451 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
6250cc30 | 452 | |
bfc2e07f | 453 | if (sport->lpuart_dma_tx_use) { |
6250cc30 BD |
454 | if (sport->dma_tx_in_progress) { |
455 | dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0], | |
456 | sport->dma_tx_nents, DMA_TO_DEVICE); | |
457 | sport->dma_tx_in_progress = false; | |
458 | } | |
bfc2e07f | 459 | dmaengine_terminate_all(sport->dma_tx_chan); |
bfc2e07f SA |
460 | } |
461 | } | |
462 | ||
2a41bc2a NR |
463 | #if defined(CONFIG_CONSOLE_POLL) |
464 | ||
465 | static int lpuart_poll_init(struct uart_port *port) | |
466 | { | |
467 | struct lpuart_port *sport = container_of(port, | |
468 | struct lpuart_port, port); | |
469 | unsigned long flags; | |
470 | unsigned char temp; | |
471 | ||
472 | sport->port.fifosize = 0; | |
473 | ||
474 | spin_lock_irqsave(&sport->port.lock, flags); | |
475 | /* Disable Rx & Tx */ | |
476 | writeb(0, sport->port.membase + UARTCR2); | |
477 | ||
478 | temp = readb(sport->port.membase + UARTPFIFO); | |
479 | /* Enable Rx and Tx FIFO */ | |
480 | writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, | |
481 | sport->port.membase + UARTPFIFO); | |
482 | ||
483 | /* flush Tx and Rx FIFO */ | |
484 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
485 | sport->port.membase + UARTCFIFO); | |
486 | ||
487 | /* explicitly clear RDRF */ | |
488 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
489 | readb(sport->port.membase + UARTDR); | |
490 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
491 | } | |
492 | ||
493 | writeb(0, sport->port.membase + UARTTWFIFO); | |
494 | writeb(1, sport->port.membase + UARTRWFIFO); | |
495 | ||
496 | /* Enable Rx and Tx */ | |
497 | writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); | |
498 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
499 | ||
500 | return 0; | |
501 | } | |
502 | ||
503 | static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) | |
504 | { | |
2a41bc2a NR |
505 | /* drain */ |
506 | while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) | |
507 | barrier(); | |
508 | ||
509 | writeb(c, port->membase + UARTDR); | |
510 | } | |
511 | ||
512 | static int lpuart_poll_get_char(struct uart_port *port) | |
513 | { | |
514 | if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) | |
515 | return NO_POLL_CHAR; | |
516 | ||
517 | return readb(port->membase + UARTDR); | |
518 | } | |
519 | ||
a5fa2660 MV |
520 | static int lpuart32_poll_init(struct uart_port *port) |
521 | { | |
522 | unsigned long flags; | |
523 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
524 | u32 temp; | |
525 | ||
526 | sport->port.fifosize = 0; | |
527 | ||
528 | spin_lock_irqsave(&sport->port.lock, flags); | |
529 | ||
530 | /* Disable Rx & Tx */ | |
531 | writel(0, sport->port.membase + UARTCTRL); | |
532 | ||
533 | temp = readl(sport->port.membase + UARTFIFO); | |
534 | ||
535 | /* Enable Rx and Tx FIFO */ | |
536 | writel(temp | UARTFIFO_RXFE | UARTFIFO_TXFE, | |
537 | sport->port.membase + UARTFIFO); | |
538 | ||
539 | /* flush Tx and Rx FIFO */ | |
540 | writel(UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, | |
541 | sport->port.membase + UARTFIFO); | |
542 | ||
543 | /* explicitly clear RDRF */ | |
544 | if (readl(sport->port.membase + UARTSTAT) & UARTSTAT_RDRF) { | |
545 | readl(sport->port.membase + UARTDATA); | |
546 | writel(UARTFIFO_RXUF, sport->port.membase + UARTFIFO); | |
547 | } | |
548 | ||
549 | /* Enable Rx and Tx */ | |
550 | writel(UARTCTRL_RE | UARTCTRL_TE, sport->port.membase + UARTCTRL); | |
551 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
552 | ||
553 | return 0; | |
554 | } | |
555 | ||
556 | static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) | |
557 | { | |
558 | while (!(readl(port->membase + UARTSTAT) & UARTSTAT_TDRE)) | |
559 | barrier(); | |
560 | ||
561 | writel(c, port->membase + UARTDATA); | |
562 | } | |
563 | ||
564 | static int lpuart32_poll_get_char(struct uart_port *port) | |
565 | { | |
566 | if (!(readl(port->membase + UARTSTAT) & UARTSTAT_RDRF)) | |
567 | return NO_POLL_CHAR; | |
568 | ||
569 | return readl(port->membase + UARTDATA); | |
570 | } | |
2a41bc2a NR |
571 | #endif |
572 | ||
c9e2e946 JL |
573 | static inline void lpuart_transmit_buffer(struct lpuart_port *sport) |
574 | { | |
575 | struct circ_buf *xmit = &sport->port.state->xmit; | |
576 | ||
577 | while (!uart_circ_empty(xmit) && | |
578 | (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { | |
579 | writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); | |
580 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
581 | sport->port.icount.tx++; | |
582 | } | |
583 | ||
584 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
585 | uart_write_wakeup(&sport->port); | |
586 | ||
587 | if (uart_circ_empty(xmit)) | |
588 | lpuart_stop_tx(&sport->port); | |
589 | } | |
590 | ||
380c966c JL |
591 | static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) |
592 | { | |
593 | struct circ_buf *xmit = &sport->port.state->xmit; | |
594 | unsigned long txcnt; | |
595 | ||
a0204f25 | 596 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
597 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
598 | txcnt &= UARTWATER_COUNT_MASK; | |
599 | while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { | |
a0204f25 | 600 | lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); |
380c966c JL |
601 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
602 | sport->port.icount.tx++; | |
a0204f25 | 603 | txcnt = lpuart32_read(&sport->port, UARTWATER); |
380c966c JL |
604 | txcnt = txcnt >> UARTWATER_TXCNT_OFF; |
605 | txcnt &= UARTWATER_COUNT_MASK; | |
606 | } | |
607 | ||
608 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
609 | uart_write_wakeup(&sport->port); | |
610 | ||
611 | if (uart_circ_empty(xmit)) | |
612 | lpuart32_stop_tx(&sport->port); | |
613 | } | |
614 | ||
c9e2e946 JL |
615 | static void lpuart_start_tx(struct uart_port *port) |
616 | { | |
f1cd8c87 YY |
617 | struct lpuart_port *sport = container_of(port, |
618 | struct lpuart_port, port); | |
619 | struct circ_buf *xmit = &sport->port.state->xmit; | |
c9e2e946 JL |
620 | unsigned char temp; |
621 | ||
622 | temp = readb(port->membase + UARTCR2); | |
623 | writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); | |
624 | ||
4a818c43 | 625 | if (sport->lpuart_dma_tx_use) { |
6250cc30 BD |
626 | if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) |
627 | lpuart_dma_tx(sport); | |
f1cd8c87 YY |
628 | } else { |
629 | if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) | |
630 | lpuart_transmit_buffer(sport); | |
631 | } | |
c9e2e946 JL |
632 | } |
633 | ||
380c966c JL |
634 | static void lpuart32_start_tx(struct uart_port *port) |
635 | { | |
636 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
637 | unsigned long temp; | |
638 | ||
a0204f25 DA |
639 | temp = lpuart32_read(port, UARTCTRL); |
640 | lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); | |
380c966c | 641 | |
a0204f25 | 642 | if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) |
380c966c JL |
643 | lpuart32_transmit_buffer(sport); |
644 | } | |
645 | ||
6250cc30 BD |
646 | /* return TIOCSER_TEMT when transmitter is not busy */ |
647 | static unsigned int lpuart_tx_empty(struct uart_port *port) | |
648 | { | |
649 | struct lpuart_port *sport = container_of(port, | |
650 | struct lpuart_port, port); | |
651 | unsigned char sr1 = readb(port->membase + UARTSR1); | |
652 | unsigned char sfifo = readb(port->membase + UARTSFIFO); | |
653 | ||
654 | if (sport->dma_tx_in_progress) | |
655 | return 0; | |
656 | ||
657 | if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) | |
658 | return TIOCSER_TEMT; | |
659 | ||
660 | return 0; | |
661 | } | |
662 | ||
663 | static unsigned int lpuart32_tx_empty(struct uart_port *port) | |
664 | { | |
a0204f25 | 665 | return (lpuart32_read(port, UARTSTAT) & UARTSTAT_TC) ? |
6250cc30 BD |
666 | TIOCSER_TEMT : 0; |
667 | } | |
668 | ||
3ee5447e FE |
669 | static bool lpuart_is_32(struct lpuart_port *sport) |
670 | { | |
671 | return sport->port.iotype == UPIO_MEM32 || | |
672 | sport->port.iotype == UPIO_MEM32BE; | |
673 | } | |
674 | ||
c9e2e946 JL |
675 | static irqreturn_t lpuart_txint(int irq, void *dev_id) |
676 | { | |
677 | struct lpuart_port *sport = dev_id; | |
678 | struct circ_buf *xmit = &sport->port.state->xmit; | |
679 | unsigned long flags; | |
680 | ||
681 | spin_lock_irqsave(&sport->port.lock, flags); | |
682 | if (sport->port.x_char) { | |
3ee5447e | 683 | if (lpuart_is_32(sport)) |
a0204f25 | 684 | lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); |
380c966c JL |
685 | else |
686 | writeb(sport->port.x_char, sport->port.membase + UARTDR); | |
c9e2e946 JL |
687 | goto out; |
688 | } | |
689 | ||
690 | if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) { | |
3ee5447e | 691 | if (lpuart_is_32(sport)) |
380c966c JL |
692 | lpuart32_stop_tx(&sport->port); |
693 | else | |
694 | lpuart_stop_tx(&sport->port); | |
c9e2e946 JL |
695 | goto out; |
696 | } | |
697 | ||
3ee5447e | 698 | if (lpuart_is_32(sport)) |
380c966c JL |
699 | lpuart32_transmit_buffer(sport); |
700 | else | |
701 | lpuart_transmit_buffer(sport); | |
c9e2e946 JL |
702 | |
703 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
704 | uart_write_wakeup(&sport->port); | |
705 | ||
706 | out: | |
707 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
708 | return IRQ_HANDLED; | |
709 | } | |
710 | ||
711 | static irqreturn_t lpuart_rxint(int irq, void *dev_id) | |
712 | { | |
713 | struct lpuart_port *sport = dev_id; | |
714 | unsigned int flg, ignored = 0; | |
715 | struct tty_port *port = &sport->port.state->port; | |
716 | unsigned long flags; | |
717 | unsigned char rx, sr; | |
718 | ||
719 | spin_lock_irqsave(&sport->port.lock, flags); | |
720 | ||
721 | while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { | |
722 | flg = TTY_NORMAL; | |
723 | sport->port.icount.rx++; | |
724 | /* | |
725 | * to clear the FE, OR, NF, FE, PE flags, | |
726 | * read SR1 then read DR | |
727 | */ | |
728 | sr = readb(sport->port.membase + UARTSR1); | |
729 | rx = readb(sport->port.membase + UARTDR); | |
730 | ||
731 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) | |
732 | continue; | |
733 | ||
734 | if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { | |
735 | if (sr & UARTSR1_PE) | |
736 | sport->port.icount.parity++; | |
737 | else if (sr & UARTSR1_FE) | |
738 | sport->port.icount.frame++; | |
739 | ||
740 | if (sr & UARTSR1_OR) | |
741 | sport->port.icount.overrun++; | |
742 | ||
743 | if (sr & sport->port.ignore_status_mask) { | |
744 | if (++ignored > 100) | |
745 | goto out; | |
746 | continue; | |
747 | } | |
748 | ||
749 | sr &= sport->port.read_status_mask; | |
750 | ||
751 | if (sr & UARTSR1_PE) | |
752 | flg = TTY_PARITY; | |
753 | else if (sr & UARTSR1_FE) | |
754 | flg = TTY_FRAME; | |
755 | ||
756 | if (sr & UARTSR1_OR) | |
757 | flg = TTY_OVERRUN; | |
758 | ||
759 | #ifdef SUPPORT_SYSRQ | |
760 | sport->port.sysrq = 0; | |
761 | #endif | |
762 | } | |
763 | ||
764 | tty_insert_flip_char(port, rx, flg); | |
765 | } | |
766 | ||
767 | out: | |
768 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
769 | ||
770 | tty_flip_buffer_push(port); | |
771 | return IRQ_HANDLED; | |
772 | } | |
773 | ||
380c966c JL |
774 | static irqreturn_t lpuart32_rxint(int irq, void *dev_id) |
775 | { | |
776 | struct lpuart_port *sport = dev_id; | |
777 | unsigned int flg, ignored = 0; | |
778 | struct tty_port *port = &sport->port.state->port; | |
779 | unsigned long flags; | |
780 | unsigned long rx, sr; | |
781 | ||
782 | spin_lock_irqsave(&sport->port.lock, flags); | |
783 | ||
a0204f25 | 784 | while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { |
380c966c JL |
785 | flg = TTY_NORMAL; |
786 | sport->port.icount.rx++; | |
787 | /* | |
788 | * to clear the FE, OR, NF, FE, PE flags, | |
789 | * read STAT then read DATA reg | |
790 | */ | |
a0204f25 DA |
791 | sr = lpuart32_read(&sport->port, UARTSTAT); |
792 | rx = lpuart32_read(&sport->port, UARTDATA); | |
380c966c JL |
793 | rx &= 0x3ff; |
794 | ||
795 | if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) | |
796 | continue; | |
797 | ||
798 | if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { | |
799 | if (sr & UARTSTAT_PE) | |
800 | sport->port.icount.parity++; | |
801 | else if (sr & UARTSTAT_FE) | |
802 | sport->port.icount.frame++; | |
803 | ||
804 | if (sr & UARTSTAT_OR) | |
805 | sport->port.icount.overrun++; | |
806 | ||
807 | if (sr & sport->port.ignore_status_mask) { | |
808 | if (++ignored > 100) | |
809 | goto out; | |
810 | continue; | |
811 | } | |
812 | ||
813 | sr &= sport->port.read_status_mask; | |
814 | ||
815 | if (sr & UARTSTAT_PE) | |
816 | flg = TTY_PARITY; | |
817 | else if (sr & UARTSTAT_FE) | |
818 | flg = TTY_FRAME; | |
819 | ||
820 | if (sr & UARTSTAT_OR) | |
821 | flg = TTY_OVERRUN; | |
822 | ||
823 | #ifdef SUPPORT_SYSRQ | |
824 | sport->port.sysrq = 0; | |
825 | #endif | |
826 | } | |
827 | ||
828 | tty_insert_flip_char(port, rx, flg); | |
829 | } | |
830 | ||
831 | out: | |
832 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
833 | ||
834 | tty_flip_buffer_push(port); | |
835 | return IRQ_HANDLED; | |
836 | } | |
837 | ||
c9e2e946 JL |
838 | static irqreturn_t lpuart_int(int irq, void *dev_id) |
839 | { | |
840 | struct lpuart_port *sport = dev_id; | |
5887ad43 | 841 | unsigned char sts; |
c9e2e946 JL |
842 | |
843 | sts = readb(sport->port.membase + UARTSR1); | |
844 | ||
5887ad43 BD |
845 | if (sts & UARTSR1_RDRF) |
846 | lpuart_rxint(irq, dev_id); | |
847 | ||
6250cc30 BD |
848 | if (sts & UARTSR1_TDRE) |
849 | lpuart_txint(irq, dev_id); | |
c9e2e946 JL |
850 | |
851 | return IRQ_HANDLED; | |
852 | } | |
853 | ||
380c966c JL |
854 | static irqreturn_t lpuart32_int(int irq, void *dev_id) |
855 | { | |
856 | struct lpuart_port *sport = dev_id; | |
857 | unsigned long sts, rxcount; | |
858 | ||
a0204f25 DA |
859 | sts = lpuart32_read(&sport->port, UARTSTAT); |
860 | rxcount = lpuart32_read(&sport->port, UARTWATER); | |
380c966c JL |
861 | rxcount = rxcount >> UARTWATER_RXCNT_OFF; |
862 | ||
863 | if (sts & UARTSTAT_RDRF || rxcount > 0) | |
864 | lpuart32_rxint(irq, dev_id); | |
865 | ||
866 | if ((sts & UARTSTAT_TDRE) && | |
a0204f25 | 867 | !(lpuart32_read(&sport->port, UARTBAUD) & UARTBAUD_TDMAE)) |
380c966c JL |
868 | lpuart_txint(irq, dev_id); |
869 | ||
a0204f25 | 870 | lpuart32_write(&sport->port, sts, UARTSTAT); |
380c966c JL |
871 | return IRQ_HANDLED; |
872 | } | |
873 | ||
5887ad43 BD |
874 | static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) |
875 | { | |
876 | struct tty_port *port = &sport->port.state->port; | |
877 | struct dma_tx_state state; | |
878 | enum dma_status dmastat; | |
879 | struct circ_buf *ring = &sport->rx_ring; | |
880 | unsigned long flags; | |
881 | int count = 0; | |
882 | unsigned char sr; | |
883 | ||
884 | sr = readb(sport->port.membase + UARTSR1); | |
885 | ||
886 | if (sr & (UARTSR1_PE | UARTSR1_FE)) { | |
887 | /* Read DR to clear the error flags */ | |
888 | readb(sport->port.membase + UARTDR); | |
889 | ||
890 | if (sr & UARTSR1_PE) | |
891 | sport->port.icount.parity++; | |
892 | else if (sr & UARTSR1_FE) | |
893 | sport->port.icount.frame++; | |
894 | } | |
895 | ||
896 | async_tx_ack(sport->dma_rx_desc); | |
897 | ||
898 | spin_lock_irqsave(&sport->port.lock, flags); | |
899 | ||
900 | dmastat = dmaengine_tx_status(sport->dma_rx_chan, | |
901 | sport->dma_rx_cookie, | |
902 | &state); | |
903 | ||
904 | if (dmastat == DMA_ERROR) { | |
905 | dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); | |
906 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
907 | return; | |
908 | } | |
909 | ||
910 | /* CPU claims ownership of RX DMA buffer */ | |
911 | dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); | |
912 | ||
913 | /* | |
914 | * ring->head points to the end of data already written by the DMA. | |
915 | * ring->tail points to the beginning of data to be read by the | |
916 | * framework. | |
917 | * The current transfer size should not be larger than the dma buffer | |
918 | * length. | |
919 | */ | |
920 | ring->head = sport->rx_sgl.length - state.residue; | |
921 | BUG_ON(ring->head > sport->rx_sgl.length); | |
922 | /* | |
923 | * At this point ring->head may point to the first byte right after the | |
924 | * last byte of the dma buffer: | |
925 | * 0 <= ring->head <= sport->rx_sgl.length | |
926 | * | |
927 | * However ring->tail must always points inside the dma buffer: | |
928 | * 0 <= ring->tail <= sport->rx_sgl.length - 1 | |
929 | * | |
930 | * Since we use a ring buffer, we have to handle the case | |
931 | * where head is lower than tail. In such a case, we first read from | |
932 | * tail to the end of the buffer then reset tail. | |
933 | */ | |
934 | if (ring->head < ring->tail) { | |
935 | count = sport->rx_sgl.length - ring->tail; | |
936 | ||
937 | tty_insert_flip_string(port, ring->buf + ring->tail, count); | |
938 | ring->tail = 0; | |
939 | sport->port.icount.rx += count; | |
940 | } | |
941 | ||
942 | /* Finally we read data from tail to head */ | |
943 | if (ring->tail < ring->head) { | |
944 | count = ring->head - ring->tail; | |
945 | tty_insert_flip_string(port, ring->buf + ring->tail, count); | |
946 | /* Wrap ring->head if needed */ | |
947 | if (ring->head >= sport->rx_sgl.length) | |
948 | ring->head = 0; | |
949 | ring->tail = ring->head; | |
950 | sport->port.icount.rx += count; | |
951 | } | |
952 | ||
953 | dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1, | |
954 | DMA_FROM_DEVICE); | |
955 | ||
956 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
957 | ||
958 | tty_flip_buffer_push(port); | |
959 | mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); | |
960 | } | |
961 | ||
962 | static void lpuart_dma_rx_complete(void *arg) | |
963 | { | |
964 | struct lpuart_port *sport = arg; | |
965 | ||
966 | lpuart_copy_rx_to_tty(sport); | |
967 | } | |
968 | ||
e99e88a9 | 969 | static void lpuart_timer_func(struct timer_list *t) |
5887ad43 | 970 | { |
e99e88a9 | 971 | struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); |
5887ad43 BD |
972 | |
973 | lpuart_copy_rx_to_tty(sport); | |
974 | } | |
975 | ||
976 | static inline int lpuart_start_rx_dma(struct lpuart_port *sport) | |
977 | { | |
978 | struct dma_slave_config dma_rx_sconfig = {}; | |
979 | struct circ_buf *ring = &sport->rx_ring; | |
980 | int ret, nent; | |
981 | int bits, baud; | |
982 | struct tty_struct *tty = tty_port_tty_get(&sport->port.state->port); | |
983 | struct ktermios *termios = &tty->termios; | |
984 | ||
985 | baud = tty_get_baud_rate(tty); | |
986 | ||
987 | bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; | |
988 | if (termios->c_cflag & PARENB) | |
989 | bits++; | |
990 | ||
991 | /* | |
992 | * Calculate length of one DMA buffer size to keep latency below | |
993 | * 10ms at any baud rate. | |
994 | */ | |
995 | sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; | |
996 | sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); | |
997 | if (sport->rx_dma_rng_buf_len < 16) | |
998 | sport->rx_dma_rng_buf_len = 16; | |
999 | ||
33ddca08 | 1000 | ring->buf = kmalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); |
5887ad43 BD |
1001 | if (!ring->buf) { |
1002 | dev_err(sport->port.dev, "Ring buf alloc failed\n"); | |
1003 | return -ENOMEM; | |
1004 | } | |
1005 | ||
1006 | sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); | |
1007 | sg_set_buf(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); | |
1008 | nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); | |
1009 | ||
1010 | if (!nent) { | |
1011 | dev_err(sport->port.dev, "DMA Rx mapping error\n"); | |
1012 | return -EINVAL; | |
1013 | } | |
1014 | ||
1015 | dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR; | |
1016 | dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
1017 | dma_rx_sconfig.src_maxburst = 1; | |
1018 | dma_rx_sconfig.direction = DMA_DEV_TO_MEM; | |
1019 | ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig); | |
1020 | ||
1021 | if (ret < 0) { | |
1022 | dev_err(sport->port.dev, | |
1023 | "DMA Rx slave config failed, err = %d\n", ret); | |
1024 | return ret; | |
1025 | } | |
1026 | ||
1027 | sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan, | |
1028 | sg_dma_address(&sport->rx_sgl), | |
1029 | sport->rx_sgl.length, | |
1030 | sport->rx_sgl.length / 2, | |
1031 | DMA_DEV_TO_MEM, | |
1032 | DMA_PREP_INTERRUPT); | |
1033 | if (!sport->dma_rx_desc) { | |
1034 | dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); | |
1035 | return -EFAULT; | |
1036 | } | |
1037 | ||
1038 | sport->dma_rx_desc->callback = lpuart_dma_rx_complete; | |
1039 | sport->dma_rx_desc->callback_param = sport; | |
1040 | sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); | |
1041 | dma_async_issue_pending(sport->dma_rx_chan); | |
1042 | ||
1043 | writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, | |
1044 | sport->port.membase + UARTCR5); | |
1045 | ||
1046 | return 0; | |
1047 | } | |
1048 | ||
5887ad43 BD |
1049 | static void lpuart_dma_rx_free(struct uart_port *port) |
1050 | { | |
1051 | struct lpuart_port *sport = container_of(port, | |
1052 | struct lpuart_port, port); | |
1053 | ||
1054 | if (sport->dma_rx_chan) | |
1055 | dmaengine_terminate_all(sport->dma_rx_chan); | |
1056 | ||
1057 | dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); | |
1058 | kfree(sport->rx_ring.buf); | |
1059 | sport->rx_ring.tail = 0; | |
1060 | sport->rx_ring.head = 0; | |
1061 | sport->dma_rx_desc = NULL; | |
1062 | sport->dma_rx_cookie = -EINVAL; | |
1063 | } | |
1064 | ||
03895cf4 BD |
1065 | static int lpuart_config_rs485(struct uart_port *port, |
1066 | struct serial_rs485 *rs485) | |
1067 | { | |
1068 | struct lpuart_port *sport = container_of(port, | |
1069 | struct lpuart_port, port); | |
1070 | ||
1071 | u8 modem = readb(sport->port.membase + UARTMODEM) & | |
1072 | ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); | |
1073 | writeb(modem, sport->port.membase + UARTMODEM); | |
1074 | ||
68c338ea UKK |
1075 | /* clear unsupported configurations */ |
1076 | rs485->delay_rts_before_send = 0; | |
1077 | rs485->delay_rts_after_send = 0; | |
1078 | rs485->flags &= ~SER_RS485_RX_DURING_TX; | |
1079 | ||
03895cf4 BD |
1080 | if (rs485->flags & SER_RS485_ENABLED) { |
1081 | /* Enable auto RS-485 RTS mode */ | |
1082 | modem |= UARTMODEM_TXRTSE; | |
1083 | ||
1084 | /* | |
1085 | * RTS needs to be logic HIGH either during transer _or_ after | |
1086 | * transfer, other variants are not supported by the hardware. | |
1087 | */ | |
1088 | ||
1089 | if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | | |
1090 | SER_RS485_RTS_AFTER_SEND))) | |
1091 | rs485->flags |= SER_RS485_RTS_ON_SEND; | |
1092 | ||
1093 | if (rs485->flags & SER_RS485_RTS_ON_SEND && | |
1094 | rs485->flags & SER_RS485_RTS_AFTER_SEND) | |
1095 | rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; | |
1096 | ||
1097 | /* | |
1098 | * The hardware defaults to RTS logic HIGH while transfer. | |
1099 | * Switch polarity in case RTS shall be logic HIGH | |
1100 | * after transfer. | |
1101 | * Note: UART is assumed to be active high. | |
1102 | */ | |
1103 | if (rs485->flags & SER_RS485_RTS_ON_SEND) | |
1104 | modem &= ~UARTMODEM_TXRTSPOL; | |
1105 | else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) | |
1106 | modem |= UARTMODEM_TXRTSPOL; | |
1107 | } | |
1108 | ||
1109 | /* Store the new configuration */ | |
1110 | sport->port.rs485 = *rs485; | |
1111 | ||
1112 | writeb(modem, sport->port.membase + UARTMODEM); | |
1113 | return 0; | |
1114 | } | |
1115 | ||
c9e2e946 JL |
1116 | static unsigned int lpuart_get_mctrl(struct uart_port *port) |
1117 | { | |
1118 | unsigned int temp = 0; | |
1119 | unsigned char reg; | |
1120 | ||
1121 | reg = readb(port->membase + UARTMODEM); | |
1122 | if (reg & UARTMODEM_TXCTSE) | |
1123 | temp |= TIOCM_CTS; | |
1124 | ||
1125 | if (reg & UARTMODEM_RXRTSE) | |
1126 | temp |= TIOCM_RTS; | |
1127 | ||
1128 | return temp; | |
1129 | } | |
1130 | ||
380c966c JL |
1131 | static unsigned int lpuart32_get_mctrl(struct uart_port *port) |
1132 | { | |
1133 | unsigned int temp = 0; | |
1134 | unsigned long reg; | |
1135 | ||
a0204f25 | 1136 | reg = lpuart32_read(port, UARTMODIR); |
380c966c JL |
1137 | if (reg & UARTMODIR_TXCTSE) |
1138 | temp |= TIOCM_CTS; | |
1139 | ||
1140 | if (reg & UARTMODIR_RXRTSE) | |
1141 | temp |= TIOCM_RTS; | |
1142 | ||
1143 | return temp; | |
1144 | } | |
1145 | ||
c9e2e946 JL |
1146 | static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1147 | { | |
1148 | unsigned char temp; | |
03895cf4 BD |
1149 | struct lpuart_port *sport = container_of(port, |
1150 | struct lpuart_port, port); | |
c9e2e946 | 1151 | |
03895cf4 BD |
1152 | /* Make sure RXRTSE bit is not set when RS485 is enabled */ |
1153 | if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { | |
1154 | temp = readb(sport->port.membase + UARTMODEM) & | |
c9e2e946 JL |
1155 | ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); |
1156 | ||
03895cf4 BD |
1157 | if (mctrl & TIOCM_RTS) |
1158 | temp |= UARTMODEM_RXRTSE; | |
c9e2e946 | 1159 | |
03895cf4 BD |
1160 | if (mctrl & TIOCM_CTS) |
1161 | temp |= UARTMODEM_TXCTSE; | |
c9e2e946 | 1162 | |
03895cf4 BD |
1163 | writeb(temp, port->membase + UARTMODEM); |
1164 | } | |
c9e2e946 JL |
1165 | } |
1166 | ||
380c966c JL |
1167 | static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) |
1168 | { | |
1169 | unsigned long temp; | |
1170 | ||
a0204f25 | 1171 | temp = lpuart32_read(port, UARTMODIR) & |
380c966c JL |
1172 | ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); |
1173 | ||
1174 | if (mctrl & TIOCM_RTS) | |
1175 | temp |= UARTMODIR_RXRTSE; | |
1176 | ||
1177 | if (mctrl & TIOCM_CTS) | |
1178 | temp |= UARTMODIR_TXCTSE; | |
1179 | ||
a0204f25 | 1180 | lpuart32_write(port, temp, UARTMODIR); |
380c966c JL |
1181 | } |
1182 | ||
c9e2e946 JL |
1183 | static void lpuart_break_ctl(struct uart_port *port, int break_state) |
1184 | { | |
1185 | unsigned char temp; | |
1186 | ||
1187 | temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; | |
1188 | ||
1189 | if (break_state != 0) | |
1190 | temp |= UARTCR2_SBK; | |
1191 | ||
1192 | writeb(temp, port->membase + UARTCR2); | |
1193 | } | |
1194 | ||
380c966c JL |
1195 | static void lpuart32_break_ctl(struct uart_port *port, int break_state) |
1196 | { | |
1197 | unsigned long temp; | |
1198 | ||
a0204f25 | 1199 | temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; |
380c966c JL |
1200 | |
1201 | if (break_state != 0) | |
1202 | temp |= UARTCTRL_SBK; | |
1203 | ||
a0204f25 | 1204 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
1205 | } |
1206 | ||
c9e2e946 JL |
1207 | static void lpuart_setup_watermark(struct lpuart_port *sport) |
1208 | { | |
1209 | unsigned char val, cr2; | |
bc764b8f | 1210 | unsigned char cr2_saved; |
c9e2e946 JL |
1211 | |
1212 | cr2 = readb(sport->port.membase + UARTCR2); | |
bc764b8f | 1213 | cr2_saved = cr2; |
c9e2e946 JL |
1214 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | |
1215 | UARTCR2_RIE | UARTCR2_RE); | |
1216 | writeb(cr2, sport->port.membase + UARTCR2); | |
1217 | ||
c9e2e946 | 1218 | val = readb(sport->port.membase + UARTPFIFO); |
c9e2e946 JL |
1219 | writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, |
1220 | sport->port.membase + UARTPFIFO); | |
1221 | ||
1222 | /* flush Tx and Rx FIFO */ | |
1223 | writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, | |
1224 | sport->port.membase + UARTCFIFO); | |
1225 | ||
d68827c6 SA |
1226 | /* explicitly clear RDRF */ |
1227 | if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { | |
1228 | readb(sport->port.membase + UARTDR); | |
1229 | writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); | |
1230 | } | |
1231 | ||
f1cd8c87 | 1232 | writeb(0, sport->port.membase + UARTTWFIFO); |
c9e2e946 | 1233 | writeb(1, sport->port.membase + UARTRWFIFO); |
bc764b8f SG |
1234 | |
1235 | /* Restore cr2 */ | |
1236 | writeb(cr2_saved, sport->port.membase + UARTCR2); | |
c9e2e946 JL |
1237 | } |
1238 | ||
380c966c JL |
1239 | static void lpuart32_setup_watermark(struct lpuart_port *sport) |
1240 | { | |
1241 | unsigned long val, ctrl; | |
1242 | unsigned long ctrl_saved; | |
1243 | ||
a0204f25 | 1244 | ctrl = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1245 | ctrl_saved = ctrl; |
1246 | ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | | |
1247 | UARTCTRL_RIE | UARTCTRL_RE); | |
a0204f25 | 1248 | lpuart32_write(&sport->port, ctrl, UARTCTRL); |
380c966c JL |
1249 | |
1250 | /* enable FIFO mode */ | |
a0204f25 | 1251 | val = lpuart32_read(&sport->port, UARTFIFO); |
380c966c JL |
1252 | val |= UARTFIFO_TXFE | UARTFIFO_RXFE; |
1253 | val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; | |
a0204f25 | 1254 | lpuart32_write(&sport->port, val, UARTFIFO); |
380c966c JL |
1255 | |
1256 | /* set the watermark */ | |
1257 | val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); | |
a0204f25 | 1258 | lpuart32_write(&sport->port, val, UARTWATER); |
380c966c JL |
1259 | |
1260 | /* Restore cr2 */ | |
a0204f25 | 1261 | lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); |
380c966c JL |
1262 | } |
1263 | ||
5887ad43 | 1264 | static void rx_dma_timer_init(struct lpuart_port *sport) |
f1cd8c87 | 1265 | { |
e99e88a9 | 1266 | timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); |
5887ad43 BD |
1267 | sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; |
1268 | add_timer(&sport->lpuart_timer); | |
f1cd8c87 YY |
1269 | } |
1270 | ||
c9e2e946 JL |
1271 | static int lpuart_startup(struct uart_port *port) |
1272 | { | |
1273 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
c9e2e946 JL |
1274 | unsigned long flags; |
1275 | unsigned char temp; | |
1276 | ||
ed9891bf SA |
1277 | /* determine FIFO size and enable FIFO mode */ |
1278 | temp = readb(sport->port.membase + UARTPFIFO); | |
1279 | ||
1280 | sport->txfifo_size = 0x1 << (((temp >> UARTPFIFO_TXSIZE_OFF) & | |
1281 | UARTPFIFO_FIFOSIZE_MASK) + 1); | |
1282 | ||
4e8f2459 SA |
1283 | sport->port.fifosize = sport->txfifo_size; |
1284 | ||
ed9891bf SA |
1285 | sport->rxfifo_size = 0x1 << (((temp >> UARTPFIFO_RXSIZE_OFF) & |
1286 | UARTPFIFO_FIFOSIZE_MASK) + 1); | |
1287 | ||
c9e2e946 JL |
1288 | spin_lock_irqsave(&sport->port.lock, flags); |
1289 | ||
1290 | lpuart_setup_watermark(sport); | |
1291 | ||
1292 | temp = readb(sport->port.membase + UARTCR2); | |
1293 | temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); | |
1294 | writeb(temp, sport->port.membase + UARTCR2); | |
1295 | ||
5887ad43 BD |
1296 | if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) { |
1297 | /* set Rx DMA timeout */ | |
1298 | sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); | |
1299 | if (!sport->dma_rx_timeout) | |
1300 | sport->dma_rx_timeout = 1; | |
1301 | ||
1302 | sport->lpuart_dma_rx_use = true; | |
1303 | rx_dma_timer_init(sport); | |
1304 | } else { | |
1305 | sport->lpuart_dma_rx_use = false; | |
1306 | } | |
1307 | ||
1308 | if (sport->dma_tx_chan && !lpuart_dma_tx_request(port)) { | |
6250cc30 | 1309 | init_waitqueue_head(&sport->dma_wait); |
5887ad43 BD |
1310 | sport->lpuart_dma_tx_use = true; |
1311 | temp = readb(port->membase + UARTCR5); | |
1312 | writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5); | |
1313 | } else { | |
1314 | sport->lpuart_dma_tx_use = false; | |
1315 | } | |
1316 | ||
c9e2e946 | 1317 | spin_unlock_irqrestore(&sport->port.lock, flags); |
5887ad43 | 1318 | |
c9e2e946 JL |
1319 | return 0; |
1320 | } | |
1321 | ||
380c966c JL |
1322 | static int lpuart32_startup(struct uart_port *port) |
1323 | { | |
1324 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
380c966c JL |
1325 | unsigned long flags; |
1326 | unsigned long temp; | |
1327 | ||
1328 | /* determine FIFO size */ | |
a0204f25 | 1329 | temp = lpuart32_read(&sport->port, UARTFIFO); |
380c966c JL |
1330 | |
1331 | sport->txfifo_size = 0x1 << (((temp >> UARTFIFO_TXSIZE_OFF) & | |
1332 | UARTFIFO_FIFOSIZE_MASK) - 1); | |
1333 | ||
1334 | sport->rxfifo_size = 0x1 << (((temp >> UARTFIFO_RXSIZE_OFF) & | |
1335 | UARTFIFO_FIFOSIZE_MASK) - 1); | |
1336 | ||
380c966c JL |
1337 | spin_lock_irqsave(&sport->port.lock, flags); |
1338 | ||
1339 | lpuart32_setup_watermark(sport); | |
1340 | ||
a0204f25 | 1341 | temp = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1342 | temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | UARTCTRL_TE); |
1343 | temp |= UARTCTRL_ILIE; | |
a0204f25 | 1344 | lpuart32_write(&sport->port, temp, UARTCTRL); |
380c966c JL |
1345 | |
1346 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1347 | return 0; | |
1348 | } | |
1349 | ||
c9e2e946 JL |
1350 | static void lpuart_shutdown(struct uart_port *port) |
1351 | { | |
1352 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1353 | unsigned char temp; | |
1354 | unsigned long flags; | |
1355 | ||
1356 | spin_lock_irqsave(&port->lock, flags); | |
1357 | ||
1358 | /* disable Rx/Tx and interrupts */ | |
1359 | temp = readb(port->membase + UARTCR2); | |
1360 | temp &= ~(UARTCR2_TE | UARTCR2_RE | | |
1361 | UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
1362 | writeb(temp, port->membase + UARTCR2); | |
1363 | ||
1364 | spin_unlock_irqrestore(&port->lock, flags); | |
1365 | ||
4a818c43 | 1366 | if (sport->lpuart_dma_rx_use) { |
4a8588a1 | 1367 | del_timer_sync(&sport->lpuart_timer); |
5887ad43 | 1368 | lpuart_dma_rx_free(&sport->port); |
f1cd8c87 | 1369 | } |
4a818c43 | 1370 | |
6250cc30 BD |
1371 | if (sport->lpuart_dma_tx_use) { |
1372 | if (wait_event_interruptible(sport->dma_wait, | |
1373 | !sport->dma_tx_in_progress) != false) { | |
1374 | sport->dma_tx_in_progress = false; | |
1375 | dmaengine_terminate_all(sport->dma_tx_chan); | |
1376 | } | |
1377 | ||
1378 | lpuart_stop_tx(port); | |
1379 | } | |
c9e2e946 JL |
1380 | } |
1381 | ||
380c966c JL |
1382 | static void lpuart32_shutdown(struct uart_port *port) |
1383 | { | |
380c966c JL |
1384 | unsigned long temp; |
1385 | unsigned long flags; | |
1386 | ||
1387 | spin_lock_irqsave(&port->lock, flags); | |
1388 | ||
1389 | /* disable Rx/Tx and interrupts */ | |
a0204f25 | 1390 | temp = lpuart32_read(port, UARTCTRL); |
380c966c JL |
1391 | temp &= ~(UARTCTRL_TE | UARTCTRL_RE | |
1392 | UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); | |
a0204f25 | 1393 | lpuart32_write(port, temp, UARTCTRL); |
380c966c JL |
1394 | |
1395 | spin_unlock_irqrestore(&port->lock, flags); | |
380c966c JL |
1396 | } |
1397 | ||
c9e2e946 JL |
1398 | static void |
1399 | lpuart_set_termios(struct uart_port *port, struct ktermios *termios, | |
1400 | struct ktermios *old) | |
1401 | { | |
1402 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1403 | unsigned long flags; | |
aa9e7d78 | 1404 | unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; |
c9e2e946 JL |
1405 | unsigned int baud; |
1406 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
1407 | unsigned int sbr, brfa; | |
1408 | ||
1409 | cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); | |
1410 | old_cr2 = readb(sport->port.membase + UARTCR2); | |
aa9e7d78 | 1411 | cr3 = readb(sport->port.membase + UARTCR3); |
c9e2e946 JL |
1412 | cr4 = readb(sport->port.membase + UARTCR4); |
1413 | bdh = readb(sport->port.membase + UARTBDH); | |
1414 | modem = readb(sport->port.membase + UARTMODEM); | |
1415 | /* | |
1416 | * only support CS8 and CS7, and for CS7 must enable PE. | |
1417 | * supported mode: | |
1418 | * - (7,e/o,1) | |
1419 | * - (8,n,1) | |
1420 | * - (8,m/s,1) | |
1421 | * - (8,e/o,1) | |
1422 | */ | |
1423 | while ((termios->c_cflag & CSIZE) != CS8 && | |
1424 | (termios->c_cflag & CSIZE) != CS7) { | |
1425 | termios->c_cflag &= ~CSIZE; | |
1426 | termios->c_cflag |= old_csize; | |
1427 | old_csize = CS8; | |
1428 | } | |
1429 | ||
1430 | if ((termios->c_cflag & CSIZE) == CS8 || | |
1431 | (termios->c_cflag & CSIZE) == CS7) | |
1432 | cr1 = old_cr1 & ~UARTCR1_M; | |
1433 | ||
1434 | if (termios->c_cflag & CMSPAR) { | |
1435 | if ((termios->c_cflag & CSIZE) != CS8) { | |
1436 | termios->c_cflag &= ~CSIZE; | |
1437 | termios->c_cflag |= CS8; | |
1438 | } | |
1439 | cr1 |= UARTCR1_M; | |
1440 | } | |
1441 | ||
03895cf4 BD |
1442 | /* |
1443 | * When auto RS-485 RTS mode is enabled, | |
1444 | * hardware flow control need to be disabled. | |
1445 | */ | |
1446 | if (sport->port.rs485.flags & SER_RS485_ENABLED) | |
1447 | termios->c_cflag &= ~CRTSCTS; | |
1448 | ||
c9e2e946 JL |
1449 | if (termios->c_cflag & CRTSCTS) { |
1450 | modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
1451 | } else { | |
1452 | termios->c_cflag &= ~CRTSCTS; | |
1453 | modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
1454 | } | |
1455 | ||
1456 | if (termios->c_cflag & CSTOPB) | |
1457 | termios->c_cflag &= ~CSTOPB; | |
1458 | ||
1459 | /* parity must be enabled when CS7 to match 8-bits format */ | |
1460 | if ((termios->c_cflag & CSIZE) == CS7) | |
1461 | termios->c_cflag |= PARENB; | |
1462 | ||
1463 | if ((termios->c_cflag & PARENB)) { | |
1464 | if (termios->c_cflag & CMSPAR) { | |
1465 | cr1 &= ~UARTCR1_PE; | |
aa9e7d78 BD |
1466 | if (termios->c_cflag & PARODD) |
1467 | cr3 |= UARTCR3_T8; | |
1468 | else | |
1469 | cr3 &= ~UARTCR3_T8; | |
c9e2e946 JL |
1470 | } else { |
1471 | cr1 |= UARTCR1_PE; | |
1472 | if ((termios->c_cflag & CSIZE) == CS8) | |
1473 | cr1 |= UARTCR1_M; | |
1474 | if (termios->c_cflag & PARODD) | |
1475 | cr1 |= UARTCR1_PT; | |
1476 | else | |
1477 | cr1 &= ~UARTCR1_PT; | |
1478 | } | |
1479 | } | |
1480 | ||
1481 | /* ask the core to calculate the divisor */ | |
1482 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); | |
1483 | ||
54a44d54 NY |
1484 | /* |
1485 | * Need to update the Ring buffer length according to the selected | |
1486 | * baud rate and restart Rx DMA path. | |
1487 | * | |
1488 | * Since timer function acqures sport->port.lock, need to stop before | |
1489 | * acquring same lock because otherwise del_timer_sync() can deadlock. | |
1490 | */ | |
1491 | if (old && sport->lpuart_dma_rx_use) { | |
1492 | del_timer_sync(&sport->lpuart_timer); | |
1493 | lpuart_dma_rx_free(&sport->port); | |
1494 | } | |
1495 | ||
c9e2e946 JL |
1496 | spin_lock_irqsave(&sport->port.lock, flags); |
1497 | ||
1498 | sport->port.read_status_mask = 0; | |
1499 | if (termios->c_iflag & INPCK) | |
1500 | sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE); | |
ef8b9ddc | 1501 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) |
c9e2e946 JL |
1502 | sport->port.read_status_mask |= UARTSR1_FE; |
1503 | ||
1504 | /* characters to ignore */ | |
1505 | sport->port.ignore_status_mask = 0; | |
1506 | if (termios->c_iflag & IGNPAR) | |
1507 | sport->port.ignore_status_mask |= UARTSR1_PE; | |
1508 | if (termios->c_iflag & IGNBRK) { | |
1509 | sport->port.ignore_status_mask |= UARTSR1_FE; | |
1510 | /* | |
1511 | * if we're ignoring parity and break indicators, | |
1512 | * ignore overruns too (for real raw support). | |
1513 | */ | |
1514 | if (termios->c_iflag & IGNPAR) | |
1515 | sport->port.ignore_status_mask |= UARTSR1_OR; | |
1516 | } | |
1517 | ||
1518 | /* update the per-port timeout */ | |
1519 | uart_update_timeout(port, termios->c_cflag, baud); | |
1520 | ||
1521 | /* wait transmit engin complete */ | |
1522 | while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) | |
1523 | barrier(); | |
1524 | ||
1525 | /* disable transmit and receive */ | |
1526 | writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), | |
1527 | sport->port.membase + UARTCR2); | |
1528 | ||
1529 | sbr = sport->port.uartclk / (16 * baud); | |
1530 | brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; | |
1531 | bdh &= ~UARTBDH_SBR_MASK; | |
1532 | bdh |= (sbr >> 8) & 0x1F; | |
1533 | cr4 &= ~UARTCR4_BRFA_MASK; | |
1534 | brfa &= UARTCR4_BRFA_MASK; | |
1535 | writeb(cr4 | brfa, sport->port.membase + UARTCR4); | |
1536 | writeb(bdh, sport->port.membase + UARTBDH); | |
1537 | writeb(sbr & 0xFF, sport->port.membase + UARTBDL); | |
aa9e7d78 | 1538 | writeb(cr3, sport->port.membase + UARTCR3); |
c9e2e946 JL |
1539 | writeb(cr1, sport->port.membase + UARTCR1); |
1540 | writeb(modem, sport->port.membase + UARTMODEM); | |
1541 | ||
1542 | /* restore control register */ | |
1543 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
1544 | ||
54a44d54 NY |
1545 | if (old && sport->lpuart_dma_rx_use) { |
1546 | if (!lpuart_start_rx_dma(sport)) | |
5887ad43 | 1547 | rx_dma_timer_init(sport); |
54a44d54 | 1548 | else |
5887ad43 | 1549 | sport->lpuart_dma_rx_use = false; |
5887ad43 BD |
1550 | } |
1551 | ||
c9e2e946 JL |
1552 | spin_unlock_irqrestore(&sport->port.lock, flags); |
1553 | } | |
1554 | ||
a6d7514b DA |
1555 | static void |
1556 | lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate) | |
1557 | { | |
1558 | u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; | |
1559 | u32 clk = sport->port.uartclk; | |
1560 | ||
1561 | /* | |
1562 | * The idea is to use the best OSR (over-sampling rate) possible. | |
1563 | * Note, OSR is typically hard-set to 16 in other LPUART instantiations. | |
1564 | * Loop to find the best OSR value possible, one that generates minimum | |
1565 | * baud_diff iterate through the rest of the supported values of OSR. | |
1566 | * | |
1567 | * Calculation Formula: | |
1568 | * Baud Rate = baud clock / ((OSR+1) × SBR) | |
1569 | */ | |
1570 | baud_diff = baudrate; | |
1571 | osr = 0; | |
1572 | sbr = 0; | |
1573 | ||
1574 | for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { | |
1575 | /* calculate the temporary sbr value */ | |
1576 | tmp_sbr = (clk / (baudrate * tmp_osr)); | |
1577 | if (tmp_sbr == 0) | |
1578 | tmp_sbr = 1; | |
1579 | ||
1580 | /* | |
1581 | * calculate the baud rate difference based on the temporary | |
1582 | * osr and sbr values | |
1583 | */ | |
1584 | tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; | |
1585 | ||
1586 | /* select best values between sbr and sbr+1 */ | |
1587 | tmp = clk / (tmp_osr * (tmp_sbr + 1)); | |
1588 | if (tmp_diff > (baudrate - tmp)) { | |
1589 | tmp_diff = baudrate - tmp; | |
1590 | tmp_sbr++; | |
1591 | } | |
1592 | ||
1593 | if (tmp_diff <= baud_diff) { | |
1594 | baud_diff = tmp_diff; | |
1595 | osr = tmp_osr; | |
1596 | sbr = tmp_sbr; | |
1597 | ||
1598 | if (!baud_diff) | |
1599 | break; | |
1600 | } | |
1601 | } | |
1602 | ||
1603 | /* handle buadrate outside acceptable rate */ | |
1604 | if (baud_diff > ((baudrate / 100) * 3)) | |
1605 | dev_warn(sport->port.dev, | |
1606 | "unacceptable baud rate difference of more than 3%%\n"); | |
1607 | ||
1608 | tmp = lpuart32_read(&sport->port, UARTBAUD); | |
1609 | ||
1610 | if ((osr > 3) && (osr < 8)) | |
1611 | tmp |= UARTBAUD_BOTHEDGE; | |
1612 | ||
1613 | tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); | |
1614 | tmp |= (((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT); | |
1615 | ||
1616 | tmp &= ~UARTBAUD_SBR_MASK; | |
1617 | tmp |= sbr & UARTBAUD_SBR_MASK; | |
1618 | ||
1619 | tmp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE); | |
1620 | ||
1621 | lpuart32_write(&sport->port, tmp, UARTBAUD); | |
1622 | } | |
1623 | ||
380c966c JL |
1624 | static void |
1625 | lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, | |
1626 | struct ktermios *old) | |
1627 | { | |
1628 | struct lpuart_port *sport = container_of(port, struct lpuart_port, port); | |
1629 | unsigned long flags; | |
c45e2d25 | 1630 | unsigned long ctrl, old_ctrl, modem; |
380c966c JL |
1631 | unsigned int baud; |
1632 | unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; | |
380c966c | 1633 | |
a0204f25 | 1634 | ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); |
a0204f25 | 1635 | modem = lpuart32_read(&sport->port, UARTMODIR); |
380c966c JL |
1636 | /* |
1637 | * only support CS8 and CS7, and for CS7 must enable PE. | |
1638 | * supported mode: | |
1639 | * - (7,e/o,1) | |
1640 | * - (8,n,1) | |
1641 | * - (8,m/s,1) | |
1642 | * - (8,e/o,1) | |
1643 | */ | |
1644 | while ((termios->c_cflag & CSIZE) != CS8 && | |
1645 | (termios->c_cflag & CSIZE) != CS7) { | |
1646 | termios->c_cflag &= ~CSIZE; | |
1647 | termios->c_cflag |= old_csize; | |
1648 | old_csize = CS8; | |
1649 | } | |
1650 | ||
1651 | if ((termios->c_cflag & CSIZE) == CS8 || | |
1652 | (termios->c_cflag & CSIZE) == CS7) | |
1653 | ctrl = old_ctrl & ~UARTCTRL_M; | |
1654 | ||
1655 | if (termios->c_cflag & CMSPAR) { | |
1656 | if ((termios->c_cflag & CSIZE) != CS8) { | |
1657 | termios->c_cflag &= ~CSIZE; | |
1658 | termios->c_cflag |= CS8; | |
1659 | } | |
1660 | ctrl |= UARTCTRL_M; | |
1661 | } | |
1662 | ||
1663 | if (termios->c_cflag & CRTSCTS) { | |
1664 | modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
1665 | } else { | |
1666 | termios->c_cflag &= ~CRTSCTS; | |
1667 | modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); | |
1668 | } | |
1669 | ||
1670 | if (termios->c_cflag & CSTOPB) | |
1671 | termios->c_cflag &= ~CSTOPB; | |
1672 | ||
1673 | /* parity must be enabled when CS7 to match 8-bits format */ | |
1674 | if ((termios->c_cflag & CSIZE) == CS7) | |
1675 | termios->c_cflag |= PARENB; | |
1676 | ||
1677 | if ((termios->c_cflag & PARENB)) { | |
1678 | if (termios->c_cflag & CMSPAR) { | |
1679 | ctrl &= ~UARTCTRL_PE; | |
1680 | ctrl |= UARTCTRL_M; | |
1681 | } else { | |
1682 | ctrl |= UARTCR1_PE; | |
1683 | if ((termios->c_cflag & CSIZE) == CS8) | |
1684 | ctrl |= UARTCTRL_M; | |
1685 | if (termios->c_cflag & PARODD) | |
1686 | ctrl |= UARTCTRL_PT; | |
1687 | else | |
1688 | ctrl &= ~UARTCTRL_PT; | |
1689 | } | |
1690 | } | |
1691 | ||
1692 | /* ask the core to calculate the divisor */ | |
1693 | baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); | |
1694 | ||
1695 | spin_lock_irqsave(&sport->port.lock, flags); | |
1696 | ||
1697 | sport->port.read_status_mask = 0; | |
1698 | if (termios->c_iflag & INPCK) | |
1699 | sport->port.read_status_mask |= (UARTSTAT_FE | UARTSTAT_PE); | |
1700 | if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) | |
1701 | sport->port.read_status_mask |= UARTSTAT_FE; | |
1702 | ||
1703 | /* characters to ignore */ | |
1704 | sport->port.ignore_status_mask = 0; | |
1705 | if (termios->c_iflag & IGNPAR) | |
1706 | sport->port.ignore_status_mask |= UARTSTAT_PE; | |
1707 | if (termios->c_iflag & IGNBRK) { | |
1708 | sport->port.ignore_status_mask |= UARTSTAT_FE; | |
1709 | /* | |
1710 | * if we're ignoring parity and break indicators, | |
1711 | * ignore overruns too (for real raw support). | |
1712 | */ | |
1713 | if (termios->c_iflag & IGNPAR) | |
1714 | sport->port.ignore_status_mask |= UARTSTAT_OR; | |
1715 | } | |
1716 | ||
1717 | /* update the per-port timeout */ | |
1718 | uart_update_timeout(port, termios->c_cflag, baud); | |
1719 | ||
1720 | /* wait transmit engin complete */ | |
a0204f25 | 1721 | while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) |
380c966c JL |
1722 | barrier(); |
1723 | ||
1724 | /* disable transmit and receive */ | |
a0204f25 DA |
1725 | lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), |
1726 | UARTCTRL); | |
380c966c | 1727 | |
a6d7514b | 1728 | lpuart32_serial_setbrg(sport, baud); |
a0204f25 DA |
1729 | lpuart32_write(&sport->port, modem, UARTMODIR); |
1730 | lpuart32_write(&sport->port, ctrl, UARTCTRL); | |
380c966c JL |
1731 | /* restore control register */ |
1732 | ||
1733 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
1734 | } | |
1735 | ||
c9e2e946 JL |
1736 | static const char *lpuart_type(struct uart_port *port) |
1737 | { | |
1738 | return "FSL_LPUART"; | |
1739 | } | |
1740 | ||
1741 | static void lpuart_release_port(struct uart_port *port) | |
1742 | { | |
1743 | /* nothing to do */ | |
1744 | } | |
1745 | ||
1746 | static int lpuart_request_port(struct uart_port *port) | |
1747 | { | |
1748 | return 0; | |
1749 | } | |
1750 | ||
1751 | /* configure/autoconfigure the port */ | |
1752 | static void lpuart_config_port(struct uart_port *port, int flags) | |
1753 | { | |
1754 | if (flags & UART_CONFIG_TYPE) | |
1755 | port->type = PORT_LPUART; | |
1756 | } | |
1757 | ||
1758 | static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1759 | { | |
1760 | int ret = 0; | |
1761 | ||
1762 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) | |
1763 | ret = -EINVAL; | |
1764 | if (port->irq != ser->irq) | |
1765 | ret = -EINVAL; | |
1766 | if (ser->io_type != UPIO_MEM) | |
1767 | ret = -EINVAL; | |
1768 | if (port->uartclk / 16 != ser->baud_base) | |
1769 | ret = -EINVAL; | |
1770 | if (port->iobase != ser->port) | |
1771 | ret = -EINVAL; | |
1772 | if (ser->hub6 != 0) | |
1773 | ret = -EINVAL; | |
1774 | return ret; | |
1775 | } | |
1776 | ||
069a47e5 | 1777 | static const struct uart_ops lpuart_pops = { |
c9e2e946 JL |
1778 | .tx_empty = lpuart_tx_empty, |
1779 | .set_mctrl = lpuart_set_mctrl, | |
1780 | .get_mctrl = lpuart_get_mctrl, | |
1781 | .stop_tx = lpuart_stop_tx, | |
1782 | .start_tx = lpuart_start_tx, | |
1783 | .stop_rx = lpuart_stop_rx, | |
c9e2e946 JL |
1784 | .break_ctl = lpuart_break_ctl, |
1785 | .startup = lpuart_startup, | |
1786 | .shutdown = lpuart_shutdown, | |
1787 | .set_termios = lpuart_set_termios, | |
1788 | .type = lpuart_type, | |
1789 | .request_port = lpuart_request_port, | |
1790 | .release_port = lpuart_release_port, | |
1791 | .config_port = lpuart_config_port, | |
1792 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 1793 | .flush_buffer = lpuart_flush_buffer, |
2a41bc2a NR |
1794 | #if defined(CONFIG_CONSOLE_POLL) |
1795 | .poll_init = lpuart_poll_init, | |
1796 | .poll_get_char = lpuart_poll_get_char, | |
1797 | .poll_put_char = lpuart_poll_put_char, | |
1798 | #endif | |
c9e2e946 JL |
1799 | }; |
1800 | ||
069a47e5 | 1801 | static const struct uart_ops lpuart32_pops = { |
380c966c JL |
1802 | .tx_empty = lpuart32_tx_empty, |
1803 | .set_mctrl = lpuart32_set_mctrl, | |
1804 | .get_mctrl = lpuart32_get_mctrl, | |
1805 | .stop_tx = lpuart32_stop_tx, | |
1806 | .start_tx = lpuart32_start_tx, | |
1807 | .stop_rx = lpuart32_stop_rx, | |
1808 | .break_ctl = lpuart32_break_ctl, | |
1809 | .startup = lpuart32_startup, | |
1810 | .shutdown = lpuart32_shutdown, | |
1811 | .set_termios = lpuart32_set_termios, | |
1812 | .type = lpuart_type, | |
1813 | .request_port = lpuart_request_port, | |
1814 | .release_port = lpuart_release_port, | |
1815 | .config_port = lpuart_config_port, | |
1816 | .verify_port = lpuart_verify_port, | |
bfc2e07f | 1817 | .flush_buffer = lpuart_flush_buffer, |
a5fa2660 MV |
1818 | #if defined(CONFIG_CONSOLE_POLL) |
1819 | .poll_init = lpuart32_poll_init, | |
1820 | .poll_get_char = lpuart32_poll_get_char, | |
1821 | .poll_put_char = lpuart32_poll_put_char, | |
1822 | #endif | |
380c966c JL |
1823 | }; |
1824 | ||
c9e2e946 JL |
1825 | static struct lpuart_port *lpuart_ports[UART_NR]; |
1826 | ||
1827 | #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE | |
1828 | static void lpuart_console_putchar(struct uart_port *port, int ch) | |
1829 | { | |
1830 | while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE)) | |
1831 | barrier(); | |
1832 | ||
1833 | writeb(ch, port->membase + UARTDR); | |
1834 | } | |
1835 | ||
380c966c JL |
1836 | static void lpuart32_console_putchar(struct uart_port *port, int ch) |
1837 | { | |
a0204f25 | 1838 | while (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)) |
380c966c JL |
1839 | barrier(); |
1840 | ||
a0204f25 | 1841 | lpuart32_write(port, ch, UARTDATA); |
380c966c JL |
1842 | } |
1843 | ||
c9e2e946 JL |
1844 | static void |
1845 | lpuart_console_write(struct console *co, const char *s, unsigned int count) | |
1846 | { | |
1847 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
1848 | unsigned char old_cr2, cr2; | |
abf1e0a9 SA |
1849 | unsigned long flags; |
1850 | int locked = 1; | |
1851 | ||
1852 | if (sport->port.sysrq || oops_in_progress) | |
1853 | locked = spin_trylock_irqsave(&sport->port.lock, flags); | |
1854 | else | |
1855 | spin_lock_irqsave(&sport->port.lock, flags); | |
c9e2e946 JL |
1856 | |
1857 | /* first save CR2 and then disable interrupts */ | |
1858 | cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); | |
1859 | cr2 |= (UARTCR2_TE | UARTCR2_RE); | |
1860 | cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); | |
1861 | writeb(cr2, sport->port.membase + UARTCR2); | |
1862 | ||
1863 | uart_console_write(&sport->port, s, count, lpuart_console_putchar); | |
1864 | ||
1865 | /* wait for transmitter finish complete and restore CR2 */ | |
1866 | while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC)) | |
1867 | barrier(); | |
1868 | ||
1869 | writeb(old_cr2, sport->port.membase + UARTCR2); | |
abf1e0a9 SA |
1870 | |
1871 | if (locked) | |
1872 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
c9e2e946 JL |
1873 | } |
1874 | ||
380c966c JL |
1875 | static void |
1876 | lpuart32_console_write(struct console *co, const char *s, unsigned int count) | |
1877 | { | |
1878 | struct lpuart_port *sport = lpuart_ports[co->index]; | |
1879 | unsigned long old_cr, cr; | |
abf1e0a9 SA |
1880 | unsigned long flags; |
1881 | int locked = 1; | |
1882 | ||
1883 | if (sport->port.sysrq || oops_in_progress) | |
1884 | locked = spin_trylock_irqsave(&sport->port.lock, flags); | |
1885 | else | |
1886 | spin_lock_irqsave(&sport->port.lock, flags); | |
380c966c JL |
1887 | |
1888 | /* first save CR2 and then disable interrupts */ | |
a0204f25 | 1889 | cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1890 | cr |= (UARTCTRL_TE | UARTCTRL_RE); |
1891 | cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); | |
a0204f25 | 1892 | lpuart32_write(&sport->port, cr, UARTCTRL); |
380c966c JL |
1893 | |
1894 | uart_console_write(&sport->port, s, count, lpuart32_console_putchar); | |
1895 | ||
1896 | /* wait for transmitter finish complete and restore CR2 */ | |
a0204f25 | 1897 | while (!(lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_TC)) |
380c966c JL |
1898 | barrier(); |
1899 | ||
a0204f25 | 1900 | lpuart32_write(&sport->port, old_cr, UARTCTRL); |
abf1e0a9 SA |
1901 | |
1902 | if (locked) | |
1903 | spin_unlock_irqrestore(&sport->port.lock, flags); | |
380c966c JL |
1904 | } |
1905 | ||
c9e2e946 JL |
1906 | /* |
1907 | * if the port was already initialised (eg, by a boot loader), | |
1908 | * try to determine the current setup. | |
1909 | */ | |
1910 | static void __init | |
1911 | lpuart_console_get_options(struct lpuart_port *sport, int *baud, | |
1912 | int *parity, int *bits) | |
1913 | { | |
1914 | unsigned char cr, bdh, bdl, brfa; | |
1915 | unsigned int sbr, uartclk, baud_raw; | |
1916 | ||
1917 | cr = readb(sport->port.membase + UARTCR2); | |
1918 | cr &= UARTCR2_TE | UARTCR2_RE; | |
1919 | if (!cr) | |
1920 | return; | |
1921 | ||
1922 | /* ok, the port was enabled */ | |
1923 | ||
1924 | cr = readb(sport->port.membase + UARTCR1); | |
1925 | ||
1926 | *parity = 'n'; | |
1927 | if (cr & UARTCR1_PE) { | |
1928 | if (cr & UARTCR1_PT) | |
1929 | *parity = 'o'; | |
1930 | else | |
1931 | *parity = 'e'; | |
1932 | } | |
1933 | ||
1934 | if (cr & UARTCR1_M) | |
1935 | *bits = 9; | |
1936 | else | |
1937 | *bits = 8; | |
1938 | ||
1939 | bdh = readb(sport->port.membase + UARTBDH); | |
1940 | bdh &= UARTBDH_SBR_MASK; | |
1941 | bdl = readb(sport->port.membase + UARTBDL); | |
1942 | sbr = bdh; | |
1943 | sbr <<= 8; | |
1944 | sbr |= bdl; | |
1945 | brfa = readb(sport->port.membase + UARTCR4); | |
1946 | brfa &= UARTCR4_BRFA_MASK; | |
1947 | ||
1948 | uartclk = clk_get_rate(sport->clk); | |
1949 | /* | |
1950 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
1951 | */ | |
1952 | baud_raw = uartclk / (16 * (sbr + brfa / 32)); | |
1953 | ||
1954 | if (*baud != baud_raw) | |
1955 | printk(KERN_INFO "Serial: Console lpuart rounded baud rate" | |
1956 | "from %d to %d\n", baud_raw, *baud); | |
1957 | } | |
1958 | ||
380c966c JL |
1959 | static void __init |
1960 | lpuart32_console_get_options(struct lpuart_port *sport, int *baud, | |
1961 | int *parity, int *bits) | |
1962 | { | |
1963 | unsigned long cr, bd; | |
1964 | unsigned int sbr, uartclk, baud_raw; | |
1965 | ||
a0204f25 | 1966 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1967 | cr &= UARTCTRL_TE | UARTCTRL_RE; |
1968 | if (!cr) | |
1969 | return; | |
1970 | ||
1971 | /* ok, the port was enabled */ | |
1972 | ||
a0204f25 | 1973 | cr = lpuart32_read(&sport->port, UARTCTRL); |
380c966c JL |
1974 | |
1975 | *parity = 'n'; | |
1976 | if (cr & UARTCTRL_PE) { | |
1977 | if (cr & UARTCTRL_PT) | |
1978 | *parity = 'o'; | |
1979 | else | |
1980 | *parity = 'e'; | |
1981 | } | |
1982 | ||
1983 | if (cr & UARTCTRL_M) | |
1984 | *bits = 9; | |
1985 | else | |
1986 | *bits = 8; | |
1987 | ||
a0204f25 | 1988 | bd = lpuart32_read(&sport->port, UARTBAUD); |
380c966c JL |
1989 | bd &= UARTBAUD_SBR_MASK; |
1990 | sbr = bd; | |
1991 | uartclk = clk_get_rate(sport->clk); | |
1992 | /* | |
1993 | * baud = mod_clk/(16*(sbr[13]+(brfa)/32) | |
1994 | */ | |
1995 | baud_raw = uartclk / (16 * sbr); | |
1996 | ||
1997 | if (*baud != baud_raw) | |
1998 | printk(KERN_INFO "Serial: Console lpuart rounded baud rate" | |
1999 | "from %d to %d\n", baud_raw, *baud); | |
2000 | } | |
2001 | ||
c9e2e946 JL |
2002 | static int __init lpuart_console_setup(struct console *co, char *options) |
2003 | { | |
2004 | struct lpuart_port *sport; | |
2005 | int baud = 115200; | |
2006 | int bits = 8; | |
2007 | int parity = 'n'; | |
2008 | int flow = 'n'; | |
2009 | ||
2010 | /* | |
2011 | * check whether an invalid uart number has been specified, and | |
2012 | * if so, search for the first available port that does have | |
2013 | * console support. | |
2014 | */ | |
2015 | if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) | |
2016 | co->index = 0; | |
2017 | ||
2018 | sport = lpuart_ports[co->index]; | |
2019 | if (sport == NULL) | |
2020 | return -ENODEV; | |
2021 | ||
2022 | if (options) | |
2023 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2024 | else | |
3ee5447e | 2025 | if (lpuart_is_32(sport)) |
380c966c JL |
2026 | lpuart32_console_get_options(sport, &baud, &parity, &bits); |
2027 | else | |
2028 | lpuart_console_get_options(sport, &baud, &parity, &bits); | |
c9e2e946 | 2029 | |
3ee5447e | 2030 | if (lpuart_is_32(sport)) |
380c966c JL |
2031 | lpuart32_setup_watermark(sport); |
2032 | else | |
2033 | lpuart_setup_watermark(sport); | |
c9e2e946 JL |
2034 | |
2035 | return uart_set_options(&sport->port, co, baud, parity, bits, flow); | |
2036 | } | |
2037 | ||
2038 | static struct uart_driver lpuart_reg; | |
2039 | static struct console lpuart_console = { | |
2040 | .name = DEV_NAME, | |
2041 | .write = lpuart_console_write, | |
2042 | .device = uart_console_device, | |
2043 | .setup = lpuart_console_setup, | |
2044 | .flags = CON_PRINTBUFFER, | |
2045 | .index = -1, | |
2046 | .data = &lpuart_reg, | |
2047 | }; | |
2048 | ||
380c966c JL |
2049 | static struct console lpuart32_console = { |
2050 | .name = DEV_NAME, | |
2051 | .write = lpuart32_console_write, | |
2052 | .device = uart_console_device, | |
2053 | .setup = lpuart_console_setup, | |
2054 | .flags = CON_PRINTBUFFER, | |
2055 | .index = -1, | |
2056 | .data = &lpuart_reg, | |
2057 | }; | |
2058 | ||
1d59b382 SA |
2059 | static void lpuart_early_write(struct console *con, const char *s, unsigned n) |
2060 | { | |
2061 | struct earlycon_device *dev = con->data; | |
2062 | ||
2063 | uart_console_write(&dev->port, s, n, lpuart_console_putchar); | |
2064 | } | |
2065 | ||
2066 | static void lpuart32_early_write(struct console *con, const char *s, unsigned n) | |
2067 | { | |
2068 | struct earlycon_device *dev = con->data; | |
2069 | ||
2070 | uart_console_write(&dev->port, s, n, lpuart32_console_putchar); | |
2071 | } | |
2072 | ||
2073 | static int __init lpuart_early_console_setup(struct earlycon_device *device, | |
2074 | const char *opt) | |
2075 | { | |
2076 | if (!device->port.membase) | |
2077 | return -ENODEV; | |
2078 | ||
2079 | device->con->write = lpuart_early_write; | |
2080 | return 0; | |
2081 | } | |
2082 | ||
2083 | static int __init lpuart32_early_console_setup(struct earlycon_device *device, | |
2084 | const char *opt) | |
2085 | { | |
2086 | if (!device->port.membase) | |
2087 | return -ENODEV; | |
2088 | ||
f98e1fcd | 2089 | device->port.iotype = UPIO_MEM32BE; |
1d59b382 SA |
2090 | device->con->write = lpuart32_early_write; |
2091 | return 0; | |
2092 | } | |
2093 | ||
97d6f353 DA |
2094 | static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, |
2095 | const char *opt) | |
2096 | { | |
2097 | if (!device->port.membase) | |
2098 | return -ENODEV; | |
2099 | ||
2100 | device->port.iotype = UPIO_MEM32; | |
2101 | device->port.membase += IMX_REG_OFF; | |
2102 | device->con->write = lpuart32_early_write; | |
2103 | ||
2104 | return 0; | |
2105 | } | |
1d59b382 SA |
2106 | OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); |
2107 | OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); | |
97d6f353 | 2108 | OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); |
1d59b382 SA |
2109 | EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); |
2110 | EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); | |
2111 | ||
c9e2e946 | 2112 | #define LPUART_CONSOLE (&lpuart_console) |
380c966c | 2113 | #define LPUART32_CONSOLE (&lpuart32_console) |
c9e2e946 JL |
2114 | #else |
2115 | #define LPUART_CONSOLE NULL | |
380c966c | 2116 | #define LPUART32_CONSOLE NULL |
c9e2e946 JL |
2117 | #endif |
2118 | ||
2119 | static struct uart_driver lpuart_reg = { | |
2120 | .owner = THIS_MODULE, | |
2121 | .driver_name = DRIVER_NAME, | |
2122 | .dev_name = DEV_NAME, | |
2123 | .nr = ARRAY_SIZE(lpuart_ports), | |
2124 | .cons = LPUART_CONSOLE, | |
2125 | }; | |
2126 | ||
2127 | static int lpuart_probe(struct platform_device *pdev) | |
2128 | { | |
0d6fce90 DA |
2129 | const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, |
2130 | &pdev->dev); | |
2131 | const struct lpuart_soc_data *sdata = of_id->data; | |
c9e2e946 JL |
2132 | struct device_node *np = pdev->dev.of_node; |
2133 | struct lpuart_port *sport; | |
2134 | struct resource *res; | |
2135 | int ret; | |
2136 | ||
2137 | sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); | |
2138 | if (!sport) | |
2139 | return -ENOMEM; | |
2140 | ||
2141 | pdev->dev.coherent_dma_mask = 0; | |
2142 | ||
2143 | ret = of_alias_get_id(np, "serial"); | |
2144 | if (ret < 0) { | |
2145 | dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); | |
2146 | return ret; | |
2147 | } | |
2148 | sport->port.line = ret; | |
4ae612a3 | 2149 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c9e2e946 JL |
2150 | sport->port.membase = devm_ioremap_resource(&pdev->dev, res); |
2151 | if (IS_ERR(sport->port.membase)) | |
2152 | return PTR_ERR(sport->port.membase); | |
2153 | ||
24b1e5f0 | 2154 | sport->port.membase += sdata->reg_off; |
4ae612a3 | 2155 | sport->port.mapbase = res->start; |
c9e2e946 JL |
2156 | sport->port.dev = &pdev->dev; |
2157 | sport->port.type = PORT_LPUART; | |
394a9e2c JS |
2158 | ret = platform_get_irq(pdev, 0); |
2159 | if (ret < 0) { | |
2160 | dev_err(&pdev->dev, "cannot obtain irq\n"); | |
2161 | return ret; | |
2162 | } | |
2163 | sport->port.irq = ret; | |
0d6fce90 | 2164 | sport->port.iotype = sdata->iotype; |
3ee5447e | 2165 | if (lpuart_is_32(sport)) |
380c966c JL |
2166 | sport->port.ops = &lpuart32_pops; |
2167 | else | |
2168 | sport->port.ops = &lpuart_pops; | |
c9e2e946 JL |
2169 | sport->port.flags = UPF_BOOT_AUTOCONF; |
2170 | ||
03895cf4 BD |
2171 | sport->port.rs485_config = lpuart_config_rs485; |
2172 | ||
c9e2e946 JL |
2173 | sport->clk = devm_clk_get(&pdev->dev, "ipg"); |
2174 | if (IS_ERR(sport->clk)) { | |
2175 | ret = PTR_ERR(sport->clk); | |
2176 | dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret); | |
2177 | return ret; | |
2178 | } | |
2179 | ||
2180 | ret = clk_prepare_enable(sport->clk); | |
2181 | if (ret) { | |
2182 | dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret); | |
2183 | return ret; | |
2184 | } | |
2185 | ||
2186 | sport->port.uartclk = clk_get_rate(sport->clk); | |
2187 | ||
2188 | lpuart_ports[sport->port.line] = sport; | |
2189 | ||
2190 | platform_set_drvdata(pdev, &sport->port); | |
2191 | ||
9d7ee0e2 | 2192 | if (lpuart_is_32(sport)) { |
380c966c | 2193 | lpuart_reg.cons = LPUART32_CONSOLE; |
9d7ee0e2 FD |
2194 | ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, |
2195 | DRIVER_NAME, sport); | |
2196 | } else { | |
380c966c | 2197 | lpuart_reg.cons = LPUART_CONSOLE; |
9d7ee0e2 FD |
2198 | ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, |
2199 | DRIVER_NAME, sport); | |
2200 | } | |
2201 | ||
2202 | if (ret) | |
2203 | goto failed_irq_request; | |
380c966c | 2204 | |
c9e2e946 | 2205 | ret = uart_add_one_port(&lpuart_reg, &sport->port); |
9d7ee0e2 FD |
2206 | if (ret) |
2207 | goto failed_attach_port; | |
c9e2e946 | 2208 | |
dde18d53 SH |
2209 | of_get_rs485_mode(np, &sport->port.rs485); |
2210 | ||
2211 | if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) { | |
2212 | dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); | |
2213 | return -ENOSYS; | |
2214 | } | |
2215 | ||
2216 | if (sport->port.rs485.delay_rts_before_send || | |
2217 | sport->port.rs485.delay_rts_after_send) { | |
2218 | dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); | |
2219 | return -ENOSYS; | |
2220 | } | |
2221 | ||
2222 | if (sport->port.rs485.flags & SER_RS485_ENABLED) { | |
2223 | sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; | |
2224 | writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); | |
2225 | } | |
2226 | ||
4a818c43 SA |
2227 | sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx"); |
2228 | if (!sport->dma_tx_chan) | |
2229 | dev_info(sport->port.dev, "DMA tx channel request failed, " | |
2230 | "operating without tx DMA\n"); | |
2231 | ||
2232 | sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx"); | |
2233 | if (!sport->dma_rx_chan) | |
2234 | dev_info(sport->port.dev, "DMA rx channel request failed, " | |
2235 | "operating without rx DMA\n"); | |
2236 | ||
c9e2e946 | 2237 | return 0; |
9d7ee0e2 FD |
2238 | |
2239 | failed_attach_port: | |
2240 | failed_irq_request: | |
2241 | clk_disable_unprepare(sport->clk); | |
2242 | return ret; | |
c9e2e946 JL |
2243 | } |
2244 | ||
2245 | static int lpuart_remove(struct platform_device *pdev) | |
2246 | { | |
2247 | struct lpuart_port *sport = platform_get_drvdata(pdev); | |
2248 | ||
2249 | uart_remove_one_port(&lpuart_reg, &sport->port); | |
2250 | ||
2251 | clk_disable_unprepare(sport->clk); | |
2252 | ||
4a818c43 SA |
2253 | if (sport->dma_tx_chan) |
2254 | dma_release_channel(sport->dma_tx_chan); | |
2255 | ||
2256 | if (sport->dma_rx_chan) | |
2257 | dma_release_channel(sport->dma_rx_chan); | |
2258 | ||
c9e2e946 JL |
2259 | return 0; |
2260 | } | |
2261 | ||
2262 | #ifdef CONFIG_PM_SLEEP | |
2263 | static int lpuart_suspend(struct device *dev) | |
2264 | { | |
2265 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
2fe605df | 2266 | unsigned long temp; |
3d6bcddf | 2267 | bool irq_wake; |
2fe605df | 2268 | |
3ee5447e | 2269 | if (lpuart_is_32(sport)) { |
2fe605df | 2270 | /* disable Rx/Tx and interrupts */ |
a0204f25 | 2271 | temp = lpuart32_read(&sport->port, UARTCTRL); |
2fe605df | 2272 | temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); |
a0204f25 | 2273 | lpuart32_write(&sport->port, temp, UARTCTRL); |
2fe605df YY |
2274 | } else { |
2275 | /* disable Rx/Tx and interrupts */ | |
2276 | temp = readb(sport->port.membase + UARTCR2); | |
2277 | temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); | |
2278 | writeb(temp, sport->port.membase + UARTCR2); | |
2279 | } | |
c9e2e946 JL |
2280 | |
2281 | uart_suspend_port(&lpuart_reg, &sport->port); | |
c05efd69 | 2282 | |
3d6bcddf AS |
2283 | /* uart_suspend_port() might set wakeup flag */ |
2284 | irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); | |
2285 | ||
c05efd69 BD |
2286 | if (sport->lpuart_dma_rx_use) { |
2287 | /* | |
2288 | * EDMA driver during suspend will forcefully release any | |
2289 | * non-idle DMA channels. If port wakeup is enabled or if port | |
2290 | * is console port or 'no_console_suspend' is set the Rx DMA | |
2291 | * cannot resume as as expected, hence gracefully release the | |
2292 | * Rx DMA path before suspend and start Rx DMA path on resume. | |
2293 | */ | |
3d6bcddf | 2294 | if (irq_wake) { |
c05efd69 BD |
2295 | del_timer_sync(&sport->lpuart_timer); |
2296 | lpuart_dma_rx_free(&sport->port); | |
2297 | } | |
2298 | ||
2299 | /* Disable Rx DMA to use UART port as wakeup source */ | |
2300 | writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_RDMAS, | |
2301 | sport->port.membase + UARTCR5); | |
2302 | } | |
2303 | ||
2304 | if (sport->lpuart_dma_tx_use) { | |
2305 | sport->dma_tx_in_progress = false; | |
2306 | dmaengine_terminate_all(sport->dma_tx_chan); | |
2307 | } | |
2308 | ||
3d6bcddf | 2309 | if (sport->port.suspended && !irq_wake) |
d6b0d2f2 | 2310 | clk_disable_unprepare(sport->clk); |
c9e2e946 JL |
2311 | |
2312 | return 0; | |
2313 | } | |
2314 | ||
2315 | static int lpuart_resume(struct device *dev) | |
2316 | { | |
2317 | struct lpuart_port *sport = dev_get_drvdata(dev); | |
3d6bcddf | 2318 | bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); |
08de1014 JL |
2319 | unsigned long temp; |
2320 | ||
3d6bcddf | 2321 | if (sport->port.suspended && !irq_wake) |
d6b0d2f2 SA |
2322 | clk_prepare_enable(sport->clk); |
2323 | ||
3ee5447e | 2324 | if (lpuart_is_32(sport)) { |
08de1014 | 2325 | lpuart32_setup_watermark(sport); |
a0204f25 | 2326 | temp = lpuart32_read(&sport->port, UARTCTRL); |
08de1014 JL |
2327 | temp |= (UARTCTRL_RIE | UARTCTRL_TIE | UARTCTRL_RE | |
2328 | UARTCTRL_TE | UARTCTRL_ILIE); | |
a0204f25 | 2329 | lpuart32_write(&sport->port, temp, UARTCTRL); |
08de1014 JL |
2330 | } else { |
2331 | lpuart_setup_watermark(sport); | |
2332 | temp = readb(sport->port.membase + UARTCR2); | |
2333 | temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE); | |
2334 | writeb(temp, sport->port.membase + UARTCR2); | |
2335 | } | |
c9e2e946 | 2336 | |
c05efd69 | 2337 | if (sport->lpuart_dma_rx_use) { |
3d6bcddf | 2338 | if (irq_wake) { |
54a44d54 | 2339 | if (!lpuart_start_rx_dma(sport)) |
c05efd69 | 2340 | rx_dma_timer_init(sport); |
54a44d54 | 2341 | else |
c05efd69 | 2342 | sport->lpuart_dma_rx_use = false; |
c05efd69 BD |
2343 | } |
2344 | } | |
2345 | ||
2346 | if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) { | |
2347 | init_waitqueue_head(&sport->dma_wait); | |
2348 | sport->lpuart_dma_tx_use = true; | |
2349 | writeb(readb(sport->port.membase + UARTCR5) | | |
2350 | UARTCR5_TDMAS, sport->port.membase + UARTCR5); | |
2351 | } else { | |
2352 | sport->lpuart_dma_tx_use = false; | |
2353 | } | |
2354 | ||
c9e2e946 JL |
2355 | uart_resume_port(&lpuart_reg, &sport->port); |
2356 | ||
2357 | return 0; | |
2358 | } | |
2359 | #endif | |
2360 | ||
2361 | static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); | |
2362 | ||
2363 | static struct platform_driver lpuart_driver = { | |
2364 | .probe = lpuart_probe, | |
2365 | .remove = lpuart_remove, | |
2366 | .driver = { | |
2367 | .name = "fsl-lpuart", | |
c9e2e946 JL |
2368 | .of_match_table = lpuart_dt_ids, |
2369 | .pm = &lpuart_pm_ops, | |
2370 | }, | |
2371 | }; | |
2372 | ||
2373 | static int __init lpuart_serial_init(void) | |
2374 | { | |
144c29ed | 2375 | int ret = uart_register_driver(&lpuart_reg); |
c9e2e946 | 2376 | |
c9e2e946 JL |
2377 | if (ret) |
2378 | return ret; | |
2379 | ||
2380 | ret = platform_driver_register(&lpuart_driver); | |
2381 | if (ret) | |
2382 | uart_unregister_driver(&lpuart_reg); | |
2383 | ||
39c34b09 | 2384 | return ret; |
c9e2e946 JL |
2385 | } |
2386 | ||
2387 | static void __exit lpuart_serial_exit(void) | |
2388 | { | |
2389 | platform_driver_unregister(&lpuart_driver); | |
2390 | uart_unregister_driver(&lpuart_reg); | |
2391 | } | |
2392 | ||
2393 | module_init(lpuart_serial_init); | |
2394 | module_exit(lpuart_serial_exit); | |
2395 | ||
2396 | MODULE_DESCRIPTION("Freescale lpuart serial port driver"); | |
2397 | MODULE_LICENSE("GPL v2"); |