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e3b3d0f5 1// SPDX-License-Identifier: GPL-2.0
1da177e4 2/*
1da177e4
LT		 3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
f43dc23d 5 * Copyright (C) 2002 - 2011 Paul Mundt
f4998e55 6 * Copyright (C) 2015 Glider bvba
3ea6bc3d 7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
1da177e4
LT		 8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
d89ddd1c 16 * Removed SH7300 support (Jul 2007).
1da177e4 17 */
0b3d4ef6
PM		 18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
1da177e4
LT		 21
22#undef DEBUG
23
8fb9631c
LP		 24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
1da177e4 32#include <linux/errno.h>
8fb9631c 33#include <linux/init.h>
1da177e4 34#include <linux/interrupt.h>
1da177e4 35#include <linux/ioport.h>
8fb9631c
LP		 36#include <linux/major.h>
37#include <linux/module.h>
1da177e4 38#include <linux/mm.h>
20bdcab8 39#include <linux/of.h>
6e605a01 40#include <linux/of_device.h>
8fb9631c 41#include <linux/platform_device.h>
5e50d2d6 42#include <linux/pm_runtime.h>
73a19e4c 43#include <linux/scatterlist.h>
8fb9631c
LP		 44#include <linux/serial.h>
45#include <linux/serial_sci.h>
46#include <linux/sh_dma.h>
5a0e3ad6 47#include <linux/slab.h>
8fb9631c
LP		 48#include <linux/string.h>
49#include <linux/sysrq.h>
50#include <linux/timer.h>
51#include <linux/tty.h>
52#include <linux/tty_flip.h>
85f094ec
PM		 53
54#ifdef CONFIG_SUPERH
1da177e4
LT		 55#include <asm/sh_bios.h>
56#endif
57
f907c9ea 58#include "serial_mctrl_gpio.h"
1da177e4
LT		 59#include "sh-sci.h"
60
89b5c1ab
LP		 61/* Offsets into the sci_port->irqs array */
62enum {
63 SCIx_ERI_IRQ,
64 SCIx_RXI_IRQ,
65 SCIx_TXI_IRQ,
66 SCIx_BRI_IRQ,
67 SCIx_NR_IRQS,
68
69 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
70};
71
72#define SCIx_IRQ_IS_MUXED(port) \
73 ((port)->irqs[SCIx_ERI_IRQ] == \
74 (port)->irqs[SCIx_RXI_IRQ]) || \
75 ((port)->irqs[SCIx_ERI_IRQ] && \
76 ((port)->irqs[SCIx_RXI_IRQ] < 0))
77
f4998e55
GU		 78enum SCI_CLKS {
79 SCI_FCK, /* Functional Clock */
6af27bf2 80 SCI_SCK, /* Optional External Clock */
1270f865
GU		 81 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
82 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
f4998e55
GU		 83 SCI_NUM_CLKS
84};
85
69eee8e9
GU		 86/* Bit x set means sampling rate x + 1 is supported */
87#define SCI_SR(x) BIT((x) - 1)
88#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
89
92a05748
GU		 90#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
91 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
92 SCI_SR(19) | SCI_SR(27)
93
69eee8e9
GU		 94#define min_sr(_port) ffs((_port)->sampling_rate_mask)
95#define max_sr(_port) fls((_port)->sampling_rate_mask)
96
97/* Iterate over all supported sampling rates, from high to low */
98#define for_each_sr(_sr, _port) \
99 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
100 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
101
e095ee6b
LP		 102struct plat_sci_reg {
103 u8 offset, size;
104};
105
106struct sci_port_params {
107 const struct plat_sci_reg regs[SCIx_NR_REGS];
b2f20ed9
LP		 108 unsigned int fifosize;
109 unsigned int overrun_reg;
110 unsigned int overrun_mask;
111 unsigned int sampling_rate_mask;
112 unsigned int error_mask;
113 unsigned int error_clear;
e095ee6b
LP		 114};
115
e108b2ca
PM		 116struct sci_port {
117 struct uart_port port;
118
ce6738b6 119 /* Platform configuration */
e095ee6b 120 const struct sci_port_params *params;
daf5a895 121 const struct plat_sci_port *cfg;
69eee8e9 122 unsigned int sampling_rate_mask;
e4d6f911 123 resource_size_t reg_size;
f907c9ea 124 struct mctrl_gpios *gpios;
e108b2ca 125
f4998e55
GU		 126 /* Clocks */
127 struct clk *clks[SCI_NUM_CLKS];
128 unsigned long clk_rates[SCI_NUM_CLKS];
edad1f20 129
1fcc91a6 130 int irqs[SCIx_NR_IRQS];
9174fc8f
PM		 131 char *irqstr[SCIx_NR_IRQS];
132
73a19e4c
GL		 133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
f43dc23d 135
73a19e4c 136#ifdef CONFIG_SERIAL_SH_SCI_DMA
73a19e4c
GL		 137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx[2];
139 dma_cookie_t active_rx;
79904420
GU		 140 dma_addr_t tx_dma_addr;
141 unsigned int tx_dma_len;
73a19e4c 142 struct scatterlist sg_rx[2];
7b39d901 143 void *rx_buf[2];
73a19e4c 144 size_t buf_len_rx;
73a19e4c 145 struct work_struct work_tx;
73a19e4c 146 struct timer_list rx_timer;
3089f381 147 unsigned int rx_timeout;
73a19e4c 148#endif
03940376 149 unsigned int rx_frame;
18e8cf15 150 int rx_trigger;
03940376
UH		 151 struct timer_list rx_fifo_timer;
152 int rx_fifo_timeout;
fa2abb03 153 u16 hscif_tot;
33f50ffc 154
97ed9790 155 bool has_rtscts;
33f50ffc 156 bool autorts;
e108b2ca
PM		 157};
158
e108b2ca 159#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
b7a76e4b 160
e108b2ca
PM		 161static struct sci_port sci_ports[SCI_NPORTS];
162static struct uart_driver sci_uart_driver;
1da177e4 163
e7c98dc7
MT		 164static inline struct sci_port *
165to_sci_port(struct uart_port *uart)
166{
167 return container_of(uart, struct sci_port, port);
168}
169
e095ee6b 170static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
61a6976b
PM		 171 /*
172 * Common SCI definitions, dependent on the port's regshift
173 * value.
174 */
175 [SCIx_SCI_REGTYPE] = {
e095ee6b
LP		 176 .regs = {
177 [SCSMR] = { 0x00, 8 },
178 [SCBRR] = { 0x01, 8 },
179 [SCSCR] = { 0x02, 8 },
180 [SCxTDR] = { 0x03, 8 },
181 [SCxSR] = { 0x04, 8 },
182 [SCxRDR] = { 0x05, 8 },
183 },
b2f20ed9
LP		 184 .fifosize = 1,
185 .overrun_reg = SCxSR,
186 .overrun_mask = SCI_ORER,
187 .sampling_rate_mask = SCI_SR(32),
188 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
189 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 190 },
191
192 /*
a752ba18 193 * Common definitions for legacy IrDA ports.
61a6976b
PM		 194 */
195 [SCIx_IRDA_REGTYPE] = {
e095ee6b
LP		 196 .regs = {
197 [SCSMR] = { 0x00, 8 },
198 [SCBRR] = { 0x02, 8 },
199 [SCSCR] = { 0x04, 8 },
200 [SCxTDR] = { 0x06, 8 },
201 [SCxSR] = { 0x08, 16 },
202 [SCxRDR] = { 0x0a, 8 },
203 [SCFCR] = { 0x0c, 8 },
204 [SCFDR] = { 0x0e, 16 },
205 },
b2f20ed9
LP		 206 .fifosize = 1,
207 .overrun_reg = SCxSR,
208 .overrun_mask = SCI_ORER,
209 .sampling_rate_mask = SCI_SR(32),
210 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
211 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
61a6976b
PM		 212 },
213
214 /*
215 * Common SCIFA definitions.
216 */
217 [SCIx_SCIFA_REGTYPE] = {
e095ee6b
LP		 218 .regs = {
219 [SCSMR] = { 0x00, 16 },
220 [SCBRR] = { 0x04, 8 },
221 [SCSCR] = { 0x08, 16 },
222 [SCxTDR] = { 0x20, 8 },
223 [SCxSR] = { 0x14, 16 },
224 [SCxRDR] = { 0x24, 8 },
225 [SCFCR] = { 0x18, 16 },
226 [SCFDR] = { 0x1c, 16 },
227 [SCPCR] = { 0x30, 16 },
228 [SCPDR] = { 0x34, 16 },
229 },
b2f20ed9
LP		 230 .fifosize = 64,
231 .overrun_reg = SCxSR,
232 .overrun_mask = SCIFA_ORER,
233 .sampling_rate_mask = SCI_SR_SCIFAB,
234 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
235 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 236 },
237
238 /*
239 * Common SCIFB definitions.
240 */
241 [SCIx_SCIFB_REGTYPE] = {
e095ee6b
LP		 242 .regs = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x40, 8 },
247 [SCxSR] = { 0x14, 16 },
248 [SCxRDR] = { 0x60, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCTFDR] = { 0x38, 16 },
251 [SCRFDR] = { 0x3c, 16 },
252 [SCPCR] = { 0x30, 16 },
253 [SCPDR] = { 0x34, 16 },
254 },
b2f20ed9
LP		 255 .fifosize = 256,
256 .overrun_reg = SCxSR,
257 .overrun_mask = SCIFA_ORER,
258 .sampling_rate_mask = SCI_SR_SCIFAB,
259 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
260 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 261 },
262
3af1f8a4
PE		 263 /*
264 * Common SH-2(A) SCIF definitions for ports with FIFO data
265 * count registers.
266 */
267 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 268 .regs = {
269 [SCSMR] = { 0x00, 16 },
270 [SCBRR] = { 0x04, 8 },
271 [SCSCR] = { 0x08, 16 },
272 [SCxTDR] = { 0x0c, 8 },
273 [SCxSR] = { 0x10, 16 },
274 [SCxRDR] = { 0x14, 8 },
275 [SCFCR] = { 0x18, 16 },
276 [SCFDR] = { 0x1c, 16 },
277 [SCSPTR] = { 0x20, 16 },
278 [SCLSR] = { 0x24, 16 },
279 },
b2f20ed9
LP		 280 .fifosize = 16,
281 .overrun_reg = SCLSR,
282 .overrun_mask = SCLSR_ORER,
283 .sampling_rate_mask = SCI_SR(32),
284 .error_mask = SCIF_DEFAULT_ERROR_MASK,
285 .error_clear = SCIF_ERROR_CLEAR,
3af1f8a4
PE		 286 },
287
61a6976b
PM		 288 /*
289 * Common SH-3 SCIF definitions.
290 */
291 [SCIx_SH3_SCIF_REGTYPE] = {
e095ee6b
LP		 292 .regs = {
293 [SCSMR] = { 0x00, 8 },
294 [SCBRR] = { 0x02, 8 },
295 [SCSCR] = { 0x04, 8 },
296 [SCxTDR] = { 0x06, 8 },
297 [SCxSR] = { 0x08, 16 },
298 [SCxRDR] = { 0x0a, 8 },
299 [SCFCR] = { 0x0c, 8 },
300 [SCFDR] = { 0x0e, 16 },
301 },
b2f20ed9
LP		 302 .fifosize = 16,
303 .overrun_reg = SCLSR,
304 .overrun_mask = SCLSR_ORER,
305 .sampling_rate_mask = SCI_SR(32),
306 .error_mask = SCIF_DEFAULT_ERROR_MASK,
307 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 308 },
309
310 /*
311 * Common SH-4(A) SCIF(B) definitions.
312 */
313 [SCIx_SH4_SCIF_REGTYPE] = {
e095ee6b
LP		 314 .regs = {
315 [SCSMR] = { 0x00, 16 },
316 [SCBRR] = { 0x04, 8 },
317 [SCSCR] = { 0x08, 16 },
318 [SCxTDR] = { 0x0c, 8 },
319 [SCxSR] = { 0x10, 16 },
320 [SCxRDR] = { 0x14, 8 },
321 [SCFCR] = { 0x18, 16 },
322 [SCFDR] = { 0x1c, 16 },
323 [SCSPTR] = { 0x20, 16 },
324 [SCLSR] = { 0x24, 16 },
325 },
b2f20ed9
LP		 326 .fifosize = 16,
327 .overrun_reg = SCLSR,
328 .overrun_mask = SCLSR_ORER,
329 .sampling_rate_mask = SCI_SR(32),
330 .error_mask = SCIF_DEFAULT_ERROR_MASK,
331 .error_clear = SCIF_ERROR_CLEAR,
b8bbd6b2
GU		 332 },
333
334 /*
335 * Common SCIF definitions for ports with a Baud Rate Generator for
336 * External Clock (BRG).
337 */
338 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
e095ee6b
LP		 339 .regs = {
340 [SCSMR] = { 0x00, 16 },
341 [SCBRR] = { 0x04, 8 },
342 [SCSCR] = { 0x08, 16 },
343 [SCxTDR] = { 0x0c, 8 },
344 [SCxSR] = { 0x10, 16 },
345 [SCxRDR] = { 0x14, 8 },
346 [SCFCR] = { 0x18, 16 },
347 [SCFDR] = { 0x1c, 16 },
348 [SCSPTR] = { 0x20, 16 },
349 [SCLSR] = { 0x24, 16 },
350 [SCDL] = { 0x30, 16 },
351 [SCCKS] = { 0x34, 16 },
352 },
b2f20ed9
LP		 353 .fifosize = 16,
354 .overrun_reg = SCLSR,
355 .overrun_mask = SCLSR_ORER,
356 .sampling_rate_mask = SCI_SR(32),
357 .error_mask = SCIF_DEFAULT_ERROR_MASK,
358 .error_clear = SCIF_ERROR_CLEAR,
f303b364
UH		 359 },
360
361 /*
362 * Common HSCIF definitions.
363 */
364 [SCIx_HSCIF_REGTYPE] = {
e095ee6b
LP		 365 .regs = {
366 [SCSMR] = { 0x00, 16 },
367 [SCBRR] = { 0x04, 8 },
368 [SCSCR] = { 0x08, 16 },
369 [SCxTDR] = { 0x0c, 8 },
370 [SCxSR] = { 0x10, 16 },
371 [SCxRDR] = { 0x14, 8 },
372 [SCFCR] = { 0x18, 16 },
373 [SCFDR] = { 0x1c, 16 },
374 [SCSPTR] = { 0x20, 16 },
375 [SCLSR] = { 0x24, 16 },
376 [HSSRR] = { 0x40, 16 },
377 [SCDL] = { 0x30, 16 },
378 [SCCKS] = { 0x34, 16 },
54e14ae2
UH		 379 [HSRTRGR] = { 0x54, 16 },
380 [HSTTRGR] = { 0x58, 16 },
e095ee6b 381 },
b2f20ed9
LP		 382 .fifosize = 128,
383 .overrun_reg = SCLSR,
384 .overrun_mask = SCLSR_ORER,
385 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
386 .error_mask = SCIF_DEFAULT_ERROR_MASK,
387 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 388 },
389
390 /*
391 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
392 * register.
393 */
394 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
e095ee6b
LP		 395 .regs = {
396 [SCSMR] = { 0x00, 16 },
397 [SCBRR] = { 0x04, 8 },
398 [SCSCR] = { 0x08, 16 },
399 [SCxTDR] = { 0x0c, 8 },
400 [SCxSR] = { 0x10, 16 },
401 [SCxRDR] = { 0x14, 8 },
402 [SCFCR] = { 0x18, 16 },
403 [SCFDR] = { 0x1c, 16 },
404 [SCLSR] = { 0x24, 16 },
405 },
b2f20ed9
LP		 406 .fifosize = 16,
407 .overrun_reg = SCLSR,
408 .overrun_mask = SCLSR_ORER,
409 .sampling_rate_mask = SCI_SR(32),
410 .error_mask = SCIF_DEFAULT_ERROR_MASK,
411 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 412 },
413
414 /*
415 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
416 * count registers.
417 */
418 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
e095ee6b
LP		 419 .regs = {
420 [SCSMR] = { 0x00, 16 },
421 [SCBRR] = { 0x04, 8 },
422 [SCSCR] = { 0x08, 16 },
423 [SCxTDR] = { 0x0c, 8 },
424 [SCxSR] = { 0x10, 16 },
425 [SCxRDR] = { 0x14, 8 },
426 [SCFCR] = { 0x18, 16 },
427 [SCFDR] = { 0x1c, 16 },
428 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
429 [SCRFDR] = { 0x20, 16 },
430 [SCSPTR] = { 0x24, 16 },
431 [SCLSR] = { 0x28, 16 },
432 },
b2f20ed9
LP		 433 .fifosize = 16,
434 .overrun_reg = SCLSR,
435 .overrun_mask = SCLSR_ORER,
436 .sampling_rate_mask = SCI_SR(32),
437 .error_mask = SCIF_DEFAULT_ERROR_MASK,
438 .error_clear = SCIF_ERROR_CLEAR,
61a6976b
PM		 439 },
440
441 /*
442 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
443 * registers.
444 */
445 [SCIx_SH7705_SCIF_REGTYPE] = {
e095ee6b
LP		 446 .regs = {
447 [SCSMR] = { 0x00, 16 },
448 [SCBRR] = { 0x04, 8 },
449 [SCSCR] = { 0x08, 16 },
450 [SCxTDR] = { 0x20, 8 },
451 [SCxSR] = { 0x14, 16 },
452 [SCxRDR] = { 0x24, 8 },
453 [SCFCR] = { 0x18, 16 },
454 [SCFDR] = { 0x1c, 16 },
455 },
18e8cf15 456 .fifosize = 64,
b2f20ed9
LP		 457 .overrun_reg = SCxSR,
458 .overrun_mask = SCIFA_ORER,
459 .sampling_rate_mask = SCI_SR(16),
460 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
461 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
61a6976b
PM		 462 },
463};
464
e095ee6b 465#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
72b294cf 466
61a6976b
PM		 467/*
468 * The "offset" here is rather misleading, in that it refers to an enum
469 * value relative to the port mapping rather than the fixed offset
470 * itself, which needs to be manually retrieved from the platform's
471 * register map for the given port.
472 */
473static unsigned int sci_serial_in(struct uart_port *p, int offset)
474{
d3184e68 475 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 476
477 if (reg->size == 8)
478 return ioread8(p->membase + (reg->offset << p->regshift));
479 else if (reg->size == 16)
480 return ioread16(p->membase + (reg->offset << p->regshift));
481 else
482 WARN(1, "Invalid register access\n");
483
484 return 0;
485}
486
487static void sci_serial_out(struct uart_port *p, int offset, int value)
488{
d3184e68 489 const struct plat_sci_reg *reg = sci_getreg(p, offset);
61a6976b
PM		 490
491 if (reg->size == 8)
492 iowrite8(value, p->membase + (reg->offset << p->regshift));
493 else if (reg->size == 16)
494 iowrite16(value, p->membase + (reg->offset << p->regshift));
495 else
496 WARN(1, "Invalid register access\n");
497}
498
23241d43
PM		 499static void sci_port_enable(struct sci_port *sci_port)
500{
f4998e55
GU		 501 unsigned int i;
502
23241d43
PM		 503 if (!sci_port->port.dev)
504 return;
505
506 pm_runtime_get_sync(sci_port->port.dev);
507
f4998e55
GU		 508 for (i = 0; i < SCI_NUM_CLKS; i++) {
509 clk_prepare_enable(sci_port->clks[i]);
510 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
511 }
512 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
23241d43
PM		 513}
514
515static void sci_port_disable(struct sci_port *sci_port)
516{
f4998e55
GU		 517 unsigned int i;
518
23241d43
PM		 519 if (!sci_port->port.dev)
520 return;
521
f4998e55
GU		 522 for (i = SCI_NUM_CLKS; i-- > 0; )
523 clk_disable_unprepare(sci_port->clks[i]);
23241d43
PM		 524
525 pm_runtime_put_sync(sci_port->port.dev);
526}
527
e1910fcd
GU		 528static inline unsigned long port_rx_irq_mask(struct uart_port *port)
529{
530 /*
531 * Not all ports (such as SCIFA) will support REIE. Rather than
532 * special-casing the port type, we check the port initialization
533 * IRQ enable mask to see whether the IRQ is desired at all. If
534 * it's unset, it's logically inferred that there's no point in
535 * testing for it.
536 */
537 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
538}
539
540static void sci_start_tx(struct uart_port *port)
541{
542 struct sci_port *s = to_sci_port(port);
543 unsigned short ctrl;
544
545#ifdef CONFIG_SERIAL_SH_SCI_DMA
546 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
547 u16 new, scr = serial_port_in(port, SCSCR);
548 if (s->chan_tx)
549 new = scr | SCSCR_TDRQE;
550 else
551 new = scr & ~SCSCR_TDRQE;
552 if (new != scr)
553 serial_port_out(port, SCSCR, new);
554 }
555
556 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
557 dma_submit_error(s->cookie_tx)) {
558 s->cookie_tx = 0;
559 schedule_work(&s->work_tx);
560 }
561#endif
562
563 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
564 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
565 ctrl = serial_port_in(port, SCSCR);
566 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
567 }
568}
569
570static void sci_stop_tx(struct uart_port *port)
571{
572 unsigned short ctrl;
573
574 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
575 ctrl = serial_port_in(port, SCSCR);
576
577 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
578 ctrl &= ~SCSCR_TDRQE;
579
580 ctrl &= ~SCSCR_TIE;
581
582 serial_port_out(port, SCSCR, ctrl);
583}
584
585static void sci_start_rx(struct uart_port *port)
586{
587 unsigned short ctrl;
588
589 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
590
591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
592 ctrl &= ~SCSCR_RDRQE;
593
594 serial_port_out(port, SCSCR, ctrl);
595}
596
597static void sci_stop_rx(struct uart_port *port)
598{
599 unsigned short ctrl;
600
601 ctrl = serial_port_in(port, SCSCR);
602
603 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
604 ctrl &= ~SCSCR_RDRQE;
605
606 ctrl &= ~port_rx_irq_mask(port);
607
608 serial_port_out(port, SCSCR, ctrl);
609}
610
a1b5b43f
GU		 611static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
612{
613 if (port->type == PORT_SCI) {
614 /* Just store the mask */
615 serial_port_out(port, SCxSR, mask);
b2f20ed9 616 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
a1b5b43f
GU		 617 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
618 /* Only clear the status bits we want to clear */
619 serial_port_out(port, SCxSR,
620 serial_port_in(port, SCxSR) & mask);
621 } else {
622 /* Store the mask, clear parity/framing errors */
623 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
624 }
625}
626
0b0cced1
YS		 627#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
628 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
1f6fd5c9
PM		 629
630#ifdef CONFIG_CONSOLE_POLL
07d2a1a1 631static int sci_poll_get_char(struct uart_port *port)
1da177e4 632{
1da177e4
LT		 633 unsigned short status;
634 int c;
635
e108b2ca 636 do {
b12bb29f 637 status = serial_port_in(port, SCxSR);
1da177e4 638 if (status & SCxSR_ERRORS(port)) {
a1b5b43f 639 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1da177e4
LT		 640 continue;
641 }
3f255eb3
JW		 642 break;
643 } while (1);
644
645 if (!(status & SCxSR_RDxF(port)))
646 return NO_POLL_CHAR;
07d2a1a1 647
b12bb29f 648 c = serial_port_in(port, SCxRDR);
07d2a1a1 649
e7c98dc7 650 /* Dummy read */
b12bb29f 651 serial_port_in(port, SCxSR);
a1b5b43f 652 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 653
654 return c;
655}
1f6fd5c9 656#endif
1da177e4 657
07d2a1a1 658static void sci_poll_put_char(struct uart_port *port, unsigned char c)
1da177e4 659{
1da177e4
LT		 660 unsigned short status;
661
1da177e4 662 do {
b12bb29f 663 status = serial_port_in(port, SCxSR);
1da177e4
LT		 664 } while (!(status & SCxSR_TDxE(port)));
665
b12bb29f 666 serial_port_out(port, SCxTDR, c);
a1b5b43f 667 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
1da177e4 668}
0b0cced1
YS		 669#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
670 CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 671
61a6976b 672static void sci_init_pins(struct uart_port *port, unsigned int cflag)
1da177e4 673{
61a6976b 674 struct sci_port *s = to_sci_port(port);
1da177e4 675
61a6976b
PM		 676 /*
677 * Use port-specific handler if provided.
678 */
679 if (s->cfg->ops && s->cfg->ops->init_pins) {
680 s->cfg->ops->init_pins(port, cflag);
681 return;
1da177e4 682 }
41504c39 683
e9d7a45a 684 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
cfa6eb23 685 u16 data = serial_port_in(port, SCPDR);
e9d7a45a
GU		 686 u16 ctrl = serial_port_in(port, SCPCR);
687
688 /* Enable RXD and TXD pin functions */
689 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
97ed9790 690 if (to_sci_port(port)->has_rtscts) {
cfa6eb23
GU		 691 /* RTS# is output, active low, unless autorts */
692 if (!(port->mctrl & TIOCM_RTS)) {
693 ctrl |= SCPCR_RTSC;
694 data |= SCPDR_RTSD;
695 } else if (!s->autorts) {
696 ctrl |= SCPCR_RTSC;
697 data &= ~SCPDR_RTSD;
698 } else {
699 /* Enable RTS# pin function */
700 ctrl &= ~SCPCR_RTSC;
701 }
e9d7a45a
GU		 702 /* Enable CTS# pin function */
703 ctrl &= ~SCPCR_CTSC;
704 }
cfa6eb23 705 serial_port_out(port, SCPDR, data);
e9d7a45a
GU		 706 serial_port_out(port, SCPCR, ctrl);
707 } else if (sci_getreg(port, SCSPTR)->size) {
d2b9775d
GU		 708 u16 status = serial_port_in(port, SCSPTR);
709
cfa6eb23
GU		 710 /* RTS# is always output; and active low, unless autorts */
711 status |= SCSPTR_RTSIO;
712 if (!(port->mctrl & TIOCM_RTS))
713 status |= SCSPTR_RTSDT;
714 else if (!s->autorts)
715 status &= ~SCSPTR_RTSDT;
d2b9775d
GU		 716 /* CTS# and SCK are inputs */
717 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
718 serial_port_out(port, SCSPTR, status);
faf02f8f 719 }
d5701647 720}
e108b2ca 721
72b294cf 722static int sci_txfill(struct uart_port *port)
e108b2ca 723{
b2f20ed9
LP		 724 struct sci_port *s = to_sci_port(port);
725 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 726 const struct plat_sci_reg *reg;
e108b2ca 727
72b294cf
PM		 728 reg = sci_getreg(port, SCTFDR);
729 if (reg->size)
b2f20ed9 730 return serial_port_in(port, SCTFDR) & fifo_mask;
c63847a3 731
72b294cf
PM		 732 reg = sci_getreg(port, SCFDR);
733 if (reg->size)
b12bb29f 734 return serial_port_in(port, SCFDR) >> 8;
d1d4b10c 735
b12bb29f 736 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
e108b2ca
PM		 737}
738
73a19e4c
GL		 739static int sci_txroom(struct uart_port *port)
740{
72b294cf 741 return port->fifosize - sci_txfill(port);
73a19e4c
GL		 742}
743
744static int sci_rxfill(struct uart_port *port)
e108b2ca 745{
b2f20ed9
LP		 746 struct sci_port *s = to_sci_port(port);
747 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
d3184e68 748 const struct plat_sci_reg *reg;
72b294cf
PM		 749
750 reg = sci_getreg(port, SCRFDR);
751 if (reg->size)
b2f20ed9 752 return serial_port_in(port, SCRFDR) & fifo_mask;
72b294cf
PM		 753
754 reg = sci_getreg(port, SCFDR);
755 if (reg->size)
b2f20ed9 756 return serial_port_in(port, SCFDR) & fifo_mask;
72b294cf 757
b12bb29f 758 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
e108b2ca
PM		 759}
760
1da177e4
LT		 761/* ********************************************************************** *
762 * the interrupt related routines *
763 * ********************************************************************** */
764
765static void sci_transmit_chars(struct uart_port *port)
766{
ebd2c8f6 767 struct circ_buf *xmit = &port->state->xmit;
1da177e4 768 unsigned int stopped = uart_tx_stopped(port);
1da177e4
LT		 769 unsigned short status;
770 unsigned short ctrl;
e108b2ca 771 int count;
1da177e4 772
b12bb29f 773 status = serial_port_in(port, SCxSR);
1da177e4 774 if (!(status & SCxSR_TDxE(port))) {
b12bb29f 775 ctrl = serial_port_in(port, SCSCR);
e7c98dc7 776 if (uart_circ_empty(xmit))
8e698614 777 ctrl &= ~SCSCR_TIE;
e7c98dc7 778 else
8e698614 779 ctrl |= SCSCR_TIE;
b12bb29f 780 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 781 return;
782 }
783
72b294cf 784 count = sci_txroom(port);
1da177e4
LT		 785
786 do {
787 unsigned char c;
788
789 if (port->x_char) {
790 c = port->x_char;
791 port->x_char = 0;
792 } else if (!uart_circ_empty(xmit) && !stopped) {
793 c = xmit->buf[xmit->tail];
794 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
795 } else {
796 break;
797 }
798
b12bb29f 799 serial_port_out(port, SCxTDR, c);
1da177e4
LT		 800
801 port->icount.tx++;
802 } while (--count > 0);
803
a1b5b43f 804 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4
LT		 805
806 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
807 uart_write_wakeup(port);
808 if (uart_circ_empty(xmit)) {
b129a8cc 809 sci_stop_tx(port);
1da177e4 810 } else {
b12bb29f 811 ctrl = serial_port_in(port, SCSCR);
1da177e4 812
1a22f08d 813 if (port->type != PORT_SCI) {
b12bb29f 814 serial_port_in(port, SCxSR); /* Dummy read */
a1b5b43f 815 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
1da177e4 816 }
1da177e4 817
8e698614 818 ctrl |= SCSCR_TIE;
b12bb29f 819 serial_port_out(port, SCSCR, ctrl);
1da177e4
LT		 820 }
821}
822
823/* On SH3, SCIF may read end-of-break as a space->mark char */
e7c98dc7 824#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
1da177e4 825
94c8b6db 826static void sci_receive_chars(struct uart_port *port)
1da177e4 827{
227434f8 828 struct tty_port *tport = &port->state->port;
1da177e4
LT		 829 int i, count, copied = 0;
830 unsigned short status;
33f0f88f 831 unsigned char flag;
1da177e4 832
b12bb29f 833 status = serial_port_in(port, SCxSR);
1da177e4
LT		 834 if (!(status & SCxSR_RDxF(port)))
835 return;
836
837 while (1) {
1da177e4 838 /* Don't copy more bytes than there is room for in the buffer */
227434f8 839 count = tty_buffer_request_room(tport, sci_rxfill(port));
1da177e4
LT		 840
841 /* If for any reason we can't copy more data, we're done! */
842 if (count == 0)
843 break;
844
845 if (port->type == PORT_SCI) {
b12bb29f 846 char c = serial_port_in(port, SCxRDR);
d5cb1319 847 if (uart_handle_sysrq_char(port, c))
1da177e4 848 count = 0;
e7c98dc7 849 else
92a19f9c 850 tty_insert_flip_char(tport, c, TTY_NORMAL);
1da177e4 851 } else {
e7c98dc7 852 for (i = 0; i < count; i++) {
b12bb29f 853 char c = serial_port_in(port, SCxRDR);
d97fbbed 854
b12bb29f 855 status = serial_port_in(port, SCxSR);
7d12e780 856 if (uart_handle_sysrq_char(port, c)) {
1da177e4
LT		 857 count--; i--;
858 continue;
859 }
860
861 /* Store data and status */
73a19e4c 862 if (status & SCxSR_FER(port)) {
33f0f88f 863 flag = TTY_FRAME;
d97fbbed 864 port->icount.frame++;
762c69e3 865 dev_notice(port->dev, "frame error\n");
73a19e4c 866 } else if (status & SCxSR_PER(port)) {
33f0f88f 867 flag = TTY_PARITY;
d97fbbed 868 port->icount.parity++;
762c69e3 869 dev_notice(port->dev, "parity error\n");
33f0f88f
AC		 870 } else
871 flag = TTY_NORMAL;
762c69e3 872
92a19f9c 873 tty_insert_flip_char(tport, c, flag);
1da177e4
LT		 874 }
875 }
876
b12bb29f 877 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 878 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4 879
1da177e4
LT		 880 copied += count;
881 port->icount.rx += count;
882 }
883
884 if (copied) {
885 /* Tell the rest of the system the news. New characters! */
2e124b4a 886 tty_flip_buffer_push(tport);
1da177e4 887 } else {
b12bb29f 888 serial_port_in(port, SCxSR); /* dummy read */
a1b5b43f 889 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1da177e4
LT		 890 }
891}
892
94c8b6db 893static int sci_handle_errors(struct uart_port *port)
1da177e4
LT		 894{
895 int copied = 0;
b12bb29f 896 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 897 struct tty_port *tport = &port->state->port;
debf9507 898 struct sci_port *s = to_sci_port(port);
1da177e4 899
3ae988d9 900 /* Handle overruns */
b2f20ed9 901 if (status & s->params->overrun_mask) {
3ae988d9 902 port->icount.overrun++;
d97fbbed 903
3ae988d9
LP		 904 /* overrun error */
905 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
906 copied++;
762c69e3 907
9b971cd2 908 dev_notice(port->dev, "overrun error\n");
1da177e4
LT		 909 }
910
e108b2ca 911 if (status & SCxSR_FER(port)) {
d5cb1319
LP		 912 /* frame error */
913 port->icount.frame++;
d97fbbed 914
d5cb1319
LP		 915 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
916 copied++;
762c69e3 917
d5cb1319 918 dev_notice(port->dev, "frame error\n");
1da177e4
LT		 919 }
920
e108b2ca 921 if (status & SCxSR_PER(port)) {
1da177e4 922 /* parity error */
d97fbbed
PM		 923 port->icount.parity++;
924
92a19f9c 925 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
e108b2ca 926 copied++;
762c69e3 927
9b971cd2 928 dev_notice(port->dev, "parity error\n");
1da177e4
LT		 929 }
930
33f0f88f 931 if (copied)
2e124b4a 932 tty_flip_buffer_push(tport);
1da177e4
LT		 933
934 return copied;
935}
936
94c8b6db 937static int sci_handle_fifo_overrun(struct uart_port *port)
d830fa45 938{
92a19f9c 939 struct tty_port *tport = &port->state->port;
debf9507 940 struct sci_port *s = to_sci_port(port);
d3184e68 941 const struct plat_sci_reg *reg;
2e0842a1 942 int copied = 0;
75c249fd 943 u16 status;
d830fa45 944
b2f20ed9 945 reg = sci_getreg(port, s->params->overrun_reg);
4b8c59a3 946 if (!reg->size)
d830fa45
PM		 947 return 0;
948
b2f20ed9
LP		 949 status = serial_port_in(port, s->params->overrun_reg);
950 if (status & s->params->overrun_mask) {
951 status &= ~s->params->overrun_mask;
952 serial_port_out(port, s->params->overrun_reg, status);
d830fa45 953
d97fbbed
PM		 954 port->icount.overrun++;
955
92a19f9c 956 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
2e124b4a 957 tty_flip_buffer_push(tport);
d830fa45 958
51b31f1c 959 dev_dbg(port->dev, "overrun error\n");
d830fa45
PM		 960 copied++;
961 }
962
963 return copied;
964}
965
94c8b6db 966static int sci_handle_breaks(struct uart_port *port)
1da177e4
LT		 967{
968 int copied = 0;
b12bb29f 969 unsigned short status = serial_port_in(port, SCxSR);
92a19f9c 970 struct tty_port *tport = &port->state->port;
1da177e4 971
0b3d4ef6
PM		 972 if (uart_handle_break(port))
973 return 0;
974
d5cb1319 975 if (status & SCxSR_BRK(port)) {
d97fbbed
PM		 976 port->icount.brk++;
977
1da177e4 978 /* Notify of BREAK */
92a19f9c 979 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
33f0f88f 980 copied++;
762c69e3
PM		 981
982 dev_dbg(port->dev, "BREAK detected\n");
1da177e4
LT		 983 }
984
33f0f88f 985 if (copied)
2e124b4a 986 tty_flip_buffer_push(tport);
e108b2ca 987
d830fa45
PM		 988 copied += sci_handle_fifo_overrun(port);
989
1da177e4
LT		 990 return copied;
991}
992
a380ed46
UH		 993static int scif_set_rtrg(struct uart_port *port, int rx_trig)
994{
995 unsigned int bits;
996
997 if (rx_trig < 1)
998 rx_trig = 1;
999 if (rx_trig >= port->fifosize)
1000 rx_trig = port->fifosize;
1001
1002 /* HSCIF can be set to an arbitrary level. */
1003 if (sci_getreg(port, HSRTRGR)->size) {
1004 serial_port_out(port, HSRTRGR, rx_trig);
1005 return rx_trig;
1006 }
1007
1008 switch (port->type) {
1009 case PORT_SCIF:
1010 if (rx_trig < 4) {
1011 bits = 0;
1012 rx_trig = 1;
1013 } else if (rx_trig < 8) {
1014 bits = SCFCR_RTRG0;
1015 rx_trig = 4;
1016 } else if (rx_trig < 14) {
1017 bits = SCFCR_RTRG1;
1018 rx_trig = 8;
1019 } else {
1020 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1021 rx_trig = 14;
1022 }
1023 break;
1024 case PORT_SCIFA:
1025 case PORT_SCIFB:
1026 if (rx_trig < 16) {
1027 bits = 0;
1028 rx_trig = 1;
1029 } else if (rx_trig < 32) {
1030 bits = SCFCR_RTRG0;
1031 rx_trig = 16;
1032 } else if (rx_trig < 48) {
1033 bits = SCFCR_RTRG1;
1034 rx_trig = 32;
1035 } else {
1036 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1037 rx_trig = 48;
1038 }
1039 break;
1040 default:
1041 WARN(1, "unknown FIFO configuration");
1042 return 1;
1043 }
1044
1045 serial_port_out(port, SCFCR,
1046 (serial_port_in(port, SCFCR) &
1047 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1048
1049 return rx_trig;
1050}
1051
03940376
UH		 1052static int scif_rtrg_enabled(struct uart_port *port)
1053{
1054 if (sci_getreg(port, HSRTRGR)->size)
1055 return serial_port_in(port, HSRTRGR) != 0;
1056 else
1057 return (serial_port_in(port, SCFCR) &
1058 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1059}
1060
e99e88a9 1061static void rx_fifo_timer_fn(struct timer_list *t)
03940376 1062{
e99e88a9 1063 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
03940376
UH		 1064 struct uart_port *port = &s->port;
1065
1066 dev_dbg(port->dev, "Rx timed out\n");
1067 scif_set_rtrg(port, 1);
1068}
1069
5d23188a
UH		 1070static ssize_t rx_trigger_show(struct device *dev,
1071 struct device_attribute *attr,
1072 char *buf)
1073{
1074 struct uart_port *port = dev_get_drvdata(dev);
1075 struct sci_port *sci = to_sci_port(port);
1076
1077 return sprintf(buf, "%d\n", sci->rx_trigger);
1078}
1079
1080static ssize_t rx_trigger_store(struct device *dev,
1081 struct device_attribute *attr,
1082 const char *buf,
1083 size_t count)
1084{
1085 struct uart_port *port = dev_get_drvdata(dev);
1086 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1087 int ret;
5d23188a
UH		 1088 long r;
1089
4ab3c51e
DC		 1090 ret = kstrtol(buf, 0, &r);
1091 if (ret)
1092 return ret;
90afa525 1093
5d23188a 1094 sci->rx_trigger = scif_set_rtrg(port, r);
90afa525
UH		 1095 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1096 scif_set_rtrg(port, 1);
1097
5d23188a
UH		 1098 return count;
1099}
1100
1101static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1102
1103static ssize_t rx_fifo_timeout_show(struct device *dev,
1104 struct device_attribute *attr,
1105 char *buf)
1106{
1107 struct uart_port *port = dev_get_drvdata(dev);
1108 struct sci_port *sci = to_sci_port(port);
fa2abb03 1109 int v;
5d23188a 1110
fa2abb03
UH		 1111 if (port->type == PORT_HSCIF)
1112 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1113 else
1114 v = sci->rx_fifo_timeout;
1115
1116 return sprintf(buf, "%d\n", v);
5d23188a
UH		 1117}
1118
1119static ssize_t rx_fifo_timeout_store(struct device *dev,
1120 struct device_attribute *attr,
1121 const char *buf,
1122 size_t count)
1123{
1124 struct uart_port *port = dev_get_drvdata(dev);
1125 struct sci_port *sci = to_sci_port(port);
4ab3c51e 1126 int ret;
5d23188a
UH		 1127 long r;
1128
4ab3c51e
DC		 1129 ret = kstrtol(buf, 0, &r);
1130 if (ret)
1131 return ret;
fa2abb03
UH		 1132
1133 if (port->type == PORT_HSCIF) {
1134 if (r < 0 || r > 3)
1135 return -EINVAL;
1136 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1137 } else {
1138 sci->rx_fifo_timeout = r;
1139 scif_set_rtrg(port, 1);
1140 if (r > 0)
e99e88a9 1141 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
fa2abb03
UH		 1142 }
1143
5d23188a
UH		 1144 return count;
1145}
1146
69d725f4 1147static DEVICE_ATTR_RW(rx_fifo_timeout);
5d23188a
UH		 1148
1149
73a19e4c 1150#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1151static void sci_dma_tx_complete(void *arg)
1152{
1153 struct sci_port *s = arg;
1154 struct uart_port *port = &s->port;
1155 struct circ_buf *xmit = &port->state->xmit;
1156 unsigned long flags;
73a19e4c 1157
e1910fcd 1158 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
73a19e4c 1159
e1910fcd 1160 spin_lock_irqsave(&port->lock, flags);
73a19e4c 1161
e1910fcd
GU		 1162 xmit->tail += s->tx_dma_len;
1163 xmit->tail &= UART_XMIT_SIZE - 1;
73a19e4c 1164
e1910fcd 1165 port->icount.tx += s->tx_dma_len;
1da177e4 1166
e1910fcd
GU		 1167 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1168 uart_write_wakeup(port);
1da177e4 1169
e1910fcd
GU		 1170 if (!uart_circ_empty(xmit)) {
1171 s->cookie_tx = 0;
1172 schedule_work(&s->work_tx);
1173 } else {
1174 s->cookie_tx = -EINVAL;
1175 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1176 u16 ctrl = serial_port_in(port, SCSCR);
1177 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1178 }
1179 }
1da177e4 1180
fd78a76a 1181 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1182}
1183
e1910fcd
GU		 1184/* Locking: called with port lock held */
1185static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1da177e4 1186{
e1910fcd
GU		 1187 struct uart_port *port = &s->port;
1188 struct tty_port *tport = &port->state->port;
1189 int copied;
1da177e4 1190
e1910fcd 1191 copied = tty_insert_flip_string(tport, buf, count);
6fc5a520 1192 if (copied < count)
e1910fcd 1193 port->icount.buf_overrun++;
1da177e4 1194
e1910fcd 1195 port->icount.rx += copied;
1da177e4 1196
e1910fcd 1197 return copied;
1da177e4
LT		 1198}
1199
e1910fcd 1200static int sci_dma_rx_find_active(struct sci_port *s)
1da177e4 1201{
e1910fcd 1202 unsigned int i;
1da177e4 1203
e1910fcd
GU		 1204 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1205 if (s->active_rx == s->cookie_rx[i])
1206 return i;
1da177e4 1207
e1910fcd 1208 return -1;
1da177e4
LT		 1209}
1210
e1910fcd 1211static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
f43dc23d 1212{
e1910fcd
GU		 1213 struct dma_chan *chan = s->chan_rx;
1214 struct uart_port *port = &s->port;
1215 unsigned long flags;
1216
1217 spin_lock_irqsave(&port->lock, flags);
1218 s->chan_rx = NULL;
1219 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1220 spin_unlock_irqrestore(&port->lock, flags);
1221 dmaengine_terminate_all(chan);
1222 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1223 sg_dma_address(&s->sg_rx[0]));
1224 dma_release_channel(chan);
1be22663
TA		 1225 if (enable_pio) {
1226 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1227 sci_start_rx(port);
1be22663
TA		 1228 spin_unlock_irqrestore(&port->lock, flags);
1229 }
f43dc23d
PM		 1230}
1231
e1910fcd 1232static void sci_dma_rx_complete(void *arg)
1da177e4 1233{
e1910fcd 1234 struct sci_port *s = arg;
1d3db608 1235 struct dma_chan *chan = s->chan_rx;
e1910fcd 1236 struct uart_port *port = &s->port;
67f462b0 1237 struct dma_async_tx_descriptor *desc;
e1910fcd
GU		 1238 unsigned long flags;
1239 int active, count = 0;
1da177e4 1240
e1910fcd
GU		 1241 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1242 s->active_rx);
cb772fe7 1243
e1910fcd 1244 spin_lock_irqsave(&port->lock, flags);
1da177e4 1245
e1910fcd
GU		 1246 active = sci_dma_rx_find_active(s);
1247 if (active >= 0)
1248 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
f43dc23d 1249
e1910fcd 1250 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
f43dc23d 1251
e1910fcd
GU		 1252 if (count)
1253 tty_flip_buffer_push(&port->state->port);
8b6ff84c 1254
67f462b0
GU		 1255 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1256 DMA_DEV_TO_MEM,
1257 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1258 if (!desc)
1259 goto fail;
1260
1261 desc->callback = sci_dma_rx_complete;
1262 desc->callback_param = s;
1263 s->cookie_rx[active] = dmaengine_submit(desc);
1264 if (dma_submit_error(s->cookie_rx[active]))
1265 goto fail;
1266
1267 s->active_rx = s->cookie_rx[!active];
1268
1d3db608
MHF		 1269 dma_async_issue_pending(chan);
1270
6fc5a520 1271 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1272 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1273 __func__, s->cookie_rx[active], active, s->active_rx);
67f462b0
GU		 1274 return;
1275
1276fail:
1277 spin_unlock_irqrestore(&port->lock, flags);
1278 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1279 sci_rx_dma_release(s, true);
1da177e4
LT		 1280}
1281
e1910fcd 1282static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1da177e4 1283{
e1910fcd
GU		 1284 struct dma_chan *chan = s->chan_tx;
1285 struct uart_port *port = &s->port;
e552de24 1286 unsigned long flags;
1da177e4 1287
e1910fcd
GU		 1288 spin_lock_irqsave(&port->lock, flags);
1289 s->chan_tx = NULL;
1290 s->cookie_tx = -EINVAL;
1291 spin_unlock_irqrestore(&port->lock, flags);
1292 dmaengine_terminate_all(chan);
1293 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1294 DMA_TO_DEVICE);
1295 dma_release_channel(chan);
1be22663
TA		 1296 if (enable_pio) {
1297 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1298 sci_start_tx(port);
1be22663
TA		 1299 spin_unlock_irqrestore(&port->lock, flags);
1300 }
e1910fcd 1301}
d535a230 1302
e1910fcd
GU		 1303static void sci_submit_rx(struct sci_port *s)
1304{
1305 struct dma_chan *chan = s->chan_rx;
1306 int i;
073e84c9 1307
e1910fcd
GU		 1308 for (i = 0; i < 2; i++) {
1309 struct scatterlist *sg = &s->sg_rx[i];
1310 struct dma_async_tx_descriptor *desc;
1da177e4 1311
e1910fcd
GU		 1312 desc = dmaengine_prep_slave_sg(chan,
1313 sg, 1, DMA_DEV_TO_MEM,
1314 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1315 if (!desc)
1316 goto fail;
501b825d 1317
e1910fcd
GU		 1318 desc->callback = sci_dma_rx_complete;
1319 desc->callback_param = s;
1320 s->cookie_rx[i] = dmaengine_submit(desc);
1321 if (dma_submit_error(s->cookie_rx[i]))
1322 goto fail;
9174fc8f 1323
e1910fcd 1324 }
9174fc8f 1325
e1910fcd 1326 s->active_rx = s->cookie_rx[0];
9174fc8f 1327
e1910fcd
GU		 1328 dma_async_issue_pending(chan);
1329 return;
9174fc8f 1330
e1910fcd
GU		 1331fail:
1332 if (i)
1333 dmaengine_terminate_all(chan);
1334 for (i = 0; i < 2; i++)
1335 s->cookie_rx[i] = -EINVAL;
1336 s->active_rx = -EINVAL;
e1910fcd
GU		 1337 sci_rx_dma_release(s, true);
1338}
9174fc8f 1339
e1910fcd 1340static void work_fn_tx(struct work_struct *work)
1da177e4 1341{
e1910fcd
GU		 1342 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1343 struct dma_async_tx_descriptor *desc;
1344 struct dma_chan *chan = s->chan_tx;
1345 struct uart_port *port = &s->port;
1346 struct circ_buf *xmit = &port->state->xmit;
1347 dma_addr_t buf;
1da177e4 1348
9174fc8f 1349 /*
e1910fcd
GU		 1350 * DMA is idle now.
1351 * Port xmit buffer is already mapped, and it is one page... Just adjust
1352 * offsets and lengths. Since it is a circular buffer, we have to
1353 * transmit till the end, and then the rest. Take the port lock to get a
1354 * consistent xmit buffer state.
9174fc8f 1355 */
e1910fcd
GU		 1356 spin_lock_irq(&port->lock);
1357 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1358 s->tx_dma_len = min_t(unsigned int,
1359 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1360 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1361 spin_unlock_irq(&port->lock);
0e8963de 1362
e1910fcd
GU		 1363 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1364 DMA_MEM_TO_DEV,
1365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1366 if (!desc) {
1367 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1368 /* switch to PIO */
1369 sci_tx_dma_release(s, true);
1370 return;
1371 }
0e8963de 1372
e1910fcd
GU		 1373 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1374 DMA_TO_DEVICE);
1da177e4 1375
e1910fcd
GU		 1376 spin_lock_irq(&port->lock);
1377 desc->callback = sci_dma_tx_complete;
1378 desc->callback_param = s;
1379 spin_unlock_irq(&port->lock);
1380 s->cookie_tx = dmaengine_submit(desc);
1381 if (dma_submit_error(s->cookie_tx)) {
1382 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1383 /* switch to PIO */
1384 sci_tx_dma_release(s, true);
1385 return;
1da177e4 1386 }
1da177e4 1387
e1910fcd
GU		 1388 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1389 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
73a19e4c 1390
e1910fcd 1391 dma_async_issue_pending(chan);
1da177e4
LT		 1392}
1393
e99e88a9 1394static void rx_timer_fn(struct timer_list *t)
1da177e4 1395{
e99e88a9 1396 struct sci_port *s = from_timer(s, t, rx_timer);
e7327c09 1397 struct dma_chan *chan = s->chan_rx;
e1910fcd 1398 struct uart_port *port = &s->port;
67f462b0
GU		 1399 struct dma_tx_state state;
1400 enum dma_status status;
1401 unsigned long flags;
1402 unsigned int read;
1403 int active, count;
1404 u16 scr;
1405
67f462b0 1406 dev_dbg(port->dev, "DMA Rx timed out\n");
67f462b0 1407
6fc5a520
TA		 1408 spin_lock_irqsave(&port->lock, flags);
1409
67f462b0
GU		 1410 active = sci_dma_rx_find_active(s);
1411 if (active < 0) {
1412 spin_unlock_irqrestore(&port->lock, flags);
1413 return;
1414 }
1415
1416 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
3b963042 1417 if (status == DMA_COMPLETE) {
6fc5a520 1418 spin_unlock_irqrestore(&port->lock, flags);
67f462b0
GU		 1419 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1420 s->active_rx, active);
3b963042
MHF		 1421
1422 /* Let packet complete handler take care of the packet */
1423 return;
1424 }
67f462b0 1425
e7327c09
MHF		 1426 dmaengine_pause(chan);
1427
1428 /*
1429 * sometimes DMA transfer doesn't stop even if it is stopped and
1430 * data keeps on coming until transaction is complete so check
1431 * for DMA_COMPLETE again
1432 * Let packet complete handler take care of the packet
1433 */
1434 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1435 if (status == DMA_COMPLETE) {
1436 spin_unlock_irqrestore(&port->lock, flags);
1437 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1438 return;
1439 }
1440
67f462b0
GU		 1441 /* Handle incomplete DMA receive */
1442 dmaengine_terminate_all(s->chan_rx);
1443 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
67f462b0
GU		 1444
1445 if (read) {
1446 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1447 if (count)
1448 tty_flip_buffer_push(&port->state->port);
1449 }
1450
756981be
GU		 1451 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1452 sci_submit_rx(s);
371cfed3
MHF		 1453
1454 /* Direct new serial port interrupts back to CPU */
1455 scr = serial_port_in(port, SCSCR);
1456 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1457 scr &= ~SCSCR_RDRQE;
1458 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1459 }
1460 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1461
1462 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 1463}
1464
ff441129 1465static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
219fb0c1 1466 enum dma_transfer_direction dir)
ff441129 1467{
ff441129
GU		 1468 struct dma_chan *chan;
1469 struct dma_slave_config cfg;
1470 int ret;
1471
219fb0c1
LP		 1472 chan = dma_request_slave_channel(port->dev,
1473 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
ff441129 1474 if (!chan) {
9b7becf1 1475 dev_warn(port->dev, "dma_request_slave_channel failed\n");
ff441129
GU		 1476 return NULL;
1477 }
1478
1479 memset(&cfg, 0, sizeof(cfg));
1480 cfg.direction = dir;
1481 if (dir == DMA_MEM_TO_DEV) {
1482 cfg.dst_addr = port->mapbase +
1483 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1484 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1485 } else {
1486 cfg.src_addr = port->mapbase +
1487 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1488 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1489 }
1490
1491 ret = dmaengine_slave_config(chan, &cfg);
1492 if (ret) {
1493 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1494 dma_release_channel(chan);
1495 return NULL;
1496 }
1497
1498 return chan;
1499}
1500
e1910fcd 1501static void sci_request_dma(struct uart_port *port)
73a19e4c 1502{
e1910fcd 1503 struct sci_port *s = to_sci_port(port);
e1910fcd 1504 struct dma_chan *chan;
73a19e4c 1505
e1910fcd 1506 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
73a19e4c 1507
219fb0c1 1508 if (!port->dev->of_node)
e1910fcd 1509 return;
73a19e4c 1510
e1910fcd 1511 s->cookie_tx = -EINVAL;
7464779f
AL		 1512
1513 /*
1514 * Don't request a dma channel if no channel was specified
1515 * in the device tree.
1516 */
1517 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1518 return;
1519
219fb0c1 1520 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
e1910fcd
GU		 1521 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1522 if (chan) {
1523 s->chan_tx = chan;
1524 /* UART circular tx buffer is an aligned page. */
1525 s->tx_dma_addr = dma_map_single(chan->device->dev,
1526 port->state->xmit.buf,
1527 UART_XMIT_SIZE,
1528 DMA_TO_DEVICE);
1529 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1530 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1531 dma_release_channel(chan);
1532 s->chan_tx = NULL;
1533 } else {
1534 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1535 __func__, UART_XMIT_SIZE,
1536 port->state->xmit.buf, &s->tx_dma_addr);
49d4bcad 1537 }
e1910fcd
GU		 1538
1539 INIT_WORK(&s->work_tx, work_fn_tx);
3089f381
GL		 1540 }
1541
219fb0c1 1542 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
e1910fcd
GU		 1543 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1544 if (chan) {
1545 unsigned int i;
1546 dma_addr_t dma;
1547 void *buf;
73a19e4c 1548
e1910fcd 1549 s->chan_rx = chan;
73a19e4c 1550
e1910fcd
GU		 1551 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1552 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1553 &dma, GFP_KERNEL);
1554 if (!buf) {
1555 dev_warn(port->dev,
1556 "Failed to allocate Rx dma buffer, using PIO\n");
1557 dma_release_channel(chan);
1558 s->chan_rx = NULL;
e1910fcd
GU		 1559 return;
1560 }
73a19e4c 1561
e1910fcd
GU		 1562 for (i = 0; i < 2; i++) {
1563 struct scatterlist *sg = &s->sg_rx[i];
0533502d 1564
e1910fcd
GU		 1565 sg_init_table(sg, 1);
1566 s->rx_buf[i] = buf;
1567 sg_dma_address(sg) = dma;
d09959e7 1568 sg_dma_len(sg) = s->buf_len_rx;
0533502d 1569
e1910fcd
GU		 1570 buf += s->buf_len_rx;
1571 dma += s->buf_len_rx;
1572 }
1573
e99e88a9 1574 timer_setup(&s->rx_timer, rx_timer_fn, 0);
e1910fcd 1575
756981be
GU		 1576 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1577 sci_submit_rx(s);
e1910fcd 1578 }
0533502d
GU		 1579}
1580
e1910fcd 1581static void sci_free_dma(struct uart_port *port)
73a19e4c 1582{
e1910fcd 1583 struct sci_port *s = to_sci_port(port);
73a19e4c 1584
e1910fcd
GU		 1585 if (s->chan_tx)
1586 sci_tx_dma_release(s, false);
1587 if (s->chan_rx)
1588 sci_rx_dma_release(s, false);
1589}
1cf4a7ef
GU		 1590
1591static void sci_flush_buffer(struct uart_port *port)
1592{
1593 /*
1594 * In uart_flush_buffer(), the xmit circular buffer has just been
1595 * cleared, so we have to reset tx_dma_len accordingly.
1596 */
1597 to_sci_port(port)->tx_dma_len = 0;
1598}
1599#else /* !CONFIG_SERIAL_SH_SCI_DMA */
e1910fcd
GU		 1600static inline void sci_request_dma(struct uart_port *port)
1601{
1602}
73a19e4c 1603
e1910fcd
GU		 1604static inline void sci_free_dma(struct uart_port *port)
1605{
1606}
1cf4a7ef
GU		 1607
1608#define sci_flush_buffer NULL
1609#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
73a19e4c 1610
e1910fcd
GU		 1611static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1612{
e1910fcd
GU		 1613 struct uart_port *port = ptr;
1614 struct sci_port *s = to_sci_port(port);
73a19e4c 1615
03940376 1616#ifdef CONFIG_SERIAL_SH_SCI_DMA
e1910fcd
GU		 1617 if (s->chan_rx) {
1618 u16 scr = serial_port_in(port, SCSCR);
1619 u16 ssr = serial_port_in(port, SCxSR);
73a19e4c 1620
e1910fcd
GU		 1621 /* Disable future Rx interrupts */
1622 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1623 disable_irq_nosync(irq);
1624 scr |= SCSCR_RDRQE;
1625 } else {
1626 scr &= ~SCSCR_RIE;
756981be 1627 sci_submit_rx(s);
e1910fcd
GU		 1628 }
1629 serial_port_out(port, SCSCR, scr);
1630 /* Clear current interrupt */
1631 serial_port_out(port, SCxSR,
1632 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1633 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1634 jiffies, s->rx_timeout);
1635 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
73a19e4c 1636
e1910fcd
GU		 1637 return IRQ_HANDLED;
1638 }
1639#endif
73a19e4c 1640
03940376
UH		 1641 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1642 if (!scif_rtrg_enabled(port))
1643 scif_set_rtrg(port, s->rx_trigger);
1644
1645 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1646 s->rx_frame * s->rx_fifo_timeout, 1000));
1647 }
1648
e1910fcd
GU		 1649 /* I think sci_receive_chars has to be called irrespective
1650 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1651 * to be disabled?
1652 */
1653 sci_receive_chars(ptr);
1654
1655 return IRQ_HANDLED;
73a19e4c
GL		 1656}
1657
e1910fcd 1658static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
73a19e4c 1659{
e1910fcd 1660 struct uart_port *port = ptr;
04928b79 1661 unsigned long flags;
73a19e4c 1662
04928b79 1663 spin_lock_irqsave(&port->lock, flags);
e1910fcd 1664 sci_transmit_chars(port);
04928b79 1665 spin_unlock_irqrestore(&port->lock, flags);
e1910fcd
GU		 1666
1667 return IRQ_HANDLED;
73a19e4c
GL		 1668}
1669
e1910fcd 1670static irqreturn_t sci_er_interrupt(int irq, void *ptr)
73a19e4c 1671{
e1910fcd
GU		 1672 struct uart_port *port = ptr;
1673 struct sci_port *s = to_sci_port(port);
73a19e4c 1674
e1910fcd
GU		 1675 /* Handle errors */
1676 if (port->type == PORT_SCI) {
1677 if (sci_handle_errors(port)) {
1678 /* discard character in rx buffer */
1679 serial_port_in(port, SCxSR);
1680 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1681 }
1682 } else {
1683 sci_handle_fifo_overrun(port);
1684 if (!s->chan_rx)
1685 sci_receive_chars(ptr);
1686 }
1687
1688 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1689
1690 /* Kick the transmission */
1691 if (!s->chan_tx)
1692 sci_tx_interrupt(irq, ptr);
1693
1694 return IRQ_HANDLED;
73a19e4c
GL		 1695}
1696
e1910fcd 1697static irqreturn_t sci_br_interrupt(int irq, void *ptr)
73a19e4c 1698{
e1910fcd 1699 struct uart_port *port = ptr;
73a19e4c 1700
e1910fcd
GU		 1701 /* Handle BREAKs */
1702 sci_handle_breaks(port);
1703 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
73a19e4c 1704
e1910fcd
GU		 1705 return IRQ_HANDLED;
1706}
73a19e4c 1707
e1910fcd
GU		 1708static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1709{
1710 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1711 struct uart_port *port = ptr;
1712 struct sci_port *s = to_sci_port(port);
1713 irqreturn_t ret = IRQ_NONE;
73a19e4c 1714
e1910fcd
GU		 1715 ssr_status = serial_port_in(port, SCxSR);
1716 scr_status = serial_port_in(port, SCSCR);
b2f20ed9 1717 if (s->params->overrun_reg == SCxSR)
e1910fcd 1718 orer_status = ssr_status;
b2f20ed9
LP		 1719 else if (sci_getreg(port, s->params->overrun_reg)->size)
1720 orer_status = serial_port_in(port, s->params->overrun_reg);
73a19e4c 1721
e1910fcd 1722 err_enabled = scr_status & port_rx_irq_mask(port);
73a19e4c 1723
e1910fcd
GU		 1724 /* Tx Interrupt */
1725 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1726 !s->chan_tx)
1727 ret = sci_tx_interrupt(irq, ptr);
658daa95 1728
e1910fcd
GU		 1729 /*
1730 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1731 * DR flags
1732 */
1733 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1734 (scr_status & SCSCR_RIE))
1735 ret = sci_rx_interrupt(irq, ptr);
73a19e4c 1736
e1910fcd
GU		 1737 /* Error Interrupt */
1738 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1739 ret = sci_er_interrupt(irq, ptr);
73a19e4c 1740
e1910fcd
GU		 1741 /* Break Interrupt */
1742 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1743 ret = sci_br_interrupt(irq, ptr);
1744
1745 /* Overrun Interrupt */
b2f20ed9 1746 if (orer_status & s->params->overrun_mask) {
e1910fcd
GU		 1747 sci_handle_fifo_overrun(port);
1748 ret = IRQ_HANDLED;
73a19e4c 1749 }
73a19e4c 1750
e1910fcd
GU		 1751 return ret;
1752}
73a19e4c 1753
e1910fcd
GU		 1754static const struct sci_irq_desc {
1755 const char *desc;
1756 irq_handler_t handler;
1757} sci_irq_desc[] = {
1758 /*
1759 * Split out handlers, the default case.
1760 */
1761 [SCIx_ERI_IRQ] = {
1762 .desc = "rx err",
1763 .handler = sci_er_interrupt,
1764 },
3089f381 1765
e1910fcd
GU		 1766 [SCIx_RXI_IRQ] = {
1767 .desc = "rx full",
1768 .handler = sci_rx_interrupt,
1769 },
47aceb92 1770
e1910fcd
GU		 1771 [SCIx_TXI_IRQ] = {
1772 .desc = "tx empty",
1773 .handler = sci_tx_interrupt,
1774 },
73a19e4c 1775
e1910fcd
GU		 1776 [SCIx_BRI_IRQ] = {
1777 .desc = "break",
1778 .handler = sci_br_interrupt,
1779 },
73a19e4c
GL		 1780
1781 /*
e1910fcd 1782 * Special muxed handler.
73a19e4c 1783 */
e1910fcd
GU		 1784 [SCIx_MUX_IRQ] = {
1785 .desc = "mux",
1786 .handler = sci_mpxed_interrupt,
1787 },
1788};
73a19e4c 1789
e1910fcd
GU		 1790static int sci_request_irq(struct sci_port *port)
1791{
1792 struct uart_port *up = &port->port;
1793 int i, j, ret = 0;
73a19e4c 1794
e1910fcd
GU		 1795 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1796 const struct sci_irq_desc *desc;
1797 int irq;
73a19e4c 1798
e1910fcd
GU		 1799 if (SCIx_IRQ_IS_MUXED(port)) {
1800 i = SCIx_MUX_IRQ;
1801 irq = up->irq;
1802 } else {
1803 irq = port->irqs[i];
1804
1805 /*
1806 * Certain port types won't support all of the
1807 * available interrupt sources.
1808 */
1809 if (unlikely(irq < 0))
1810 continue;
1811 }
1812
1813 desc = sci_irq_desc + i;
1814 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1815 dev_name(up->dev), desc->desc);
623ac1d4
PB		 1816 if (!port->irqstr[j]) {
1817 ret = -ENOMEM;
e1910fcd 1818 goto out_nomem;
623ac1d4 1819 }
e1910fcd
GU		 1820
1821 ret = request_irq(irq, desc->handler, up->irqflags,
1822 port->irqstr[j], port);
1823 if (unlikely(ret)) {
1824 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1825 goto out_noirq;
1826 }
73a19e4c
GL		 1827 }
1828
e1910fcd 1829 return 0;
1da177e4 1830
e1910fcd
GU		 1831out_noirq:
1832 while (--i >= 0)
1833 free_irq(port->irqs[i], port);
f43dc23d 1834
e1910fcd
GU		 1835out_nomem:
1836 while (--j >= 0)
1837 kfree(port->irqstr[j]);
f43dc23d 1838
e1910fcd 1839 return ret;
1da177e4
LT		 1840}
1841
e1910fcd 1842static void sci_free_irq(struct sci_port *port)
1da177e4 1843{
e1910fcd 1844 int i;
1da177e4 1845
e1910fcd
GU		 1846 /*
1847 * Intentionally in reverse order so we iterate over the muxed
1848 * IRQ first.
1849 */
1850 for (i = 0; i < SCIx_NR_IRQS; i++) {
1851 int irq = port->irqs[i];
f43dc23d 1852
e1910fcd
GU		 1853 /*
1854 * Certain port types won't support all of the available
1855 * interrupt sources.
1856 */
1857 if (unlikely(irq < 0))
1858 continue;
f43dc23d 1859
e1910fcd
GU		 1860 free_irq(port->irqs[i], port);
1861 kfree(port->irqstr[i]);
f43dc23d 1862
e1910fcd
GU		 1863 if (SCIx_IRQ_IS_MUXED(port)) {
1864 /* If there's only one IRQ, we're done. */
1865 return;
1866 }
1867 }
1da177e4
LT		 1868}
1869
e1910fcd 1870static unsigned int sci_tx_empty(struct uart_port *port)
1da177e4 1871{
e1910fcd
GU		 1872 unsigned short status = serial_port_in(port, SCxSR);
1873 unsigned short in_tx_fifo = sci_txfill(port);
f43dc23d 1874
e1910fcd 1875 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1da177e4
LT		 1876}
1877
33f50ffc
GU		 1878static void sci_set_rts(struct uart_port *port, bool state)
1879{
1880 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1881 u16 data = serial_port_in(port, SCPDR);
1882
1883 /* Active low */
1884 if (state)
1885 data &= ~SCPDR_RTSD;
1886 else
1887 data |= SCPDR_RTSD;
1888 serial_port_out(port, SCPDR, data);
1889
1890 /* RTS# is output */
1891 serial_port_out(port, SCPCR,
1892 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1893 } else if (sci_getreg(port, SCSPTR)->size) {
1894 u16 ctrl = serial_port_in(port, SCSPTR);
1895
1896 /* Active low */
1897 if (state)
1898 ctrl &= ~SCSPTR_RTSDT;
1899 else
1900 ctrl |= SCSPTR_RTSDT;
1901 serial_port_out(port, SCSPTR, ctrl);
1902 }
1903}
1904
1905static bool sci_get_cts(struct uart_port *port)
1906{
1907 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1908 /* Active low */
1909 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1910 } else if (sci_getreg(port, SCSPTR)->size) {
1911 /* Active low */
1912 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1913 }
1914
1915 return true;
1916}
1917
e1910fcd
GU		 1918/*
1919 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1920 * CTS/RTS is supported in hardware by at least one port and controlled
1921 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1922 * handled via the ->init_pins() op, which is a bit of a one-way street,
1923 * lacking any ability to defer pin control -- this will later be
1924 * converted over to the GPIO framework).
1925 *
1926 * Other modes (such as loopback) are supported generically on certain
1927 * port types, but not others. For these it's sufficient to test for the
1928 * existence of the support register and simply ignore the port type.
1929 */
1930static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1da177e4 1931{
f907c9ea
GU		 1932 struct sci_port *s = to_sci_port(port);
1933
e1910fcd
GU		 1934 if (mctrl & TIOCM_LOOP) {
1935 const struct plat_sci_reg *reg;
f43dc23d 1936
e1910fcd
GU		 1937 /*
1938 * Standard loopback mode for SCFCR ports.
1939 */
1940 reg = sci_getreg(port, SCFCR);
1941 if (reg->size)
1942 serial_port_out(port, SCFCR,
1943 serial_port_in(port, SCFCR) |
1944 SCFCR_LOOP);
1945 }
f907c9ea
GU		 1946
1947 mctrl_gpio_set(s->gpios, mctrl);
33f50ffc 1948
97ed9790 1949 if (!s->has_rtscts)
33f50ffc
GU		 1950 return;
1951
1952 if (!(mctrl & TIOCM_RTS)) {
1953 /* Disable Auto RTS */
1954 serial_port_out(port, SCFCR,
1955 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1956
1957 /* Clear RTS */
1958 sci_set_rts(port, 0);
1959 } else if (s->autorts) {
1960 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1961 /* Enable RTS# pin function */
1962 serial_port_out(port, SCPCR,
1963 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1964 }
1965
1966 /* Enable Auto RTS */
1967 serial_port_out(port, SCFCR,
1968 serial_port_in(port, SCFCR) | SCFCR_MCE);
1969 } else {
1970 /* Set RTS */
1971 sci_set_rts(port, 1);
1972 }
e1910fcd 1973}
f43dc23d 1974
e1910fcd
GU		 1975static unsigned int sci_get_mctrl(struct uart_port *port)
1976{
f907c9ea
GU		 1977 struct sci_port *s = to_sci_port(port);
1978 struct mctrl_gpios *gpios = s->gpios;
1979 unsigned int mctrl = 0;
1980
1981 mctrl_gpio_get(gpios, &mctrl);
1982
e1910fcd
GU		 1983 /*
1984 * CTS/RTS is handled in hardware when supported, while nothing
33f50ffc 1985 * else is wired up.
e1910fcd 1986 */
33f50ffc
GU		 1987 if (s->autorts) {
1988 if (sci_get_cts(port))
1989 mctrl |= TIOCM_CTS;
1990 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
f907c9ea 1991 mctrl |= TIOCM_CTS;
33f50ffc 1992 }
f907c9ea
GU		 1993 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
1994 mctrl |= TIOCM_DSR;
1995 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
1996 mctrl |= TIOCM_CAR;
1997
1998 return mctrl;
1999}
2000
2001static void sci_enable_ms(struct uart_port *port)
2002{
2003 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
1da177e4
LT		 2004}
2005
1da177e4
LT		 2006static void sci_break_ctl(struct uart_port *port, int break_state)
2007{
bbb4ce50 2008 unsigned short scscr, scsptr;
1be22663 2009 unsigned long flags;
bbb4ce50 2010
a4e02f6d 2011 /* check wheter the port has SCSPTR */
abbf121f 2012 if (!sci_getreg(port, SCSPTR)->size) {
bbb4ce50
SY		 2013 /*
2014 * Not supported by hardware. Most parts couple break and rx
2015 * interrupts together, with break detection always enabled.
2016 */
a4e02f6d 2017 return;
bbb4ce50 2018 }
a4e02f6d 2019
1be22663 2020 spin_lock_irqsave(&port->lock, flags);
a4e02f6d
SY		 2021 scsptr = serial_port_in(port, SCSPTR);
2022 scscr = serial_port_in(port, SCSCR);
2023
2024 if (break_state == -1) {
2025 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2026 scscr &= ~SCSCR_TE;
2027 } else {
2028 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2029 scscr |= SCSCR_TE;
2030 }
2031
2032 serial_port_out(port, SCSPTR, scsptr);
2033 serial_port_out(port, SCSCR, scscr);
1be22663 2034 spin_unlock_irqrestore(&port->lock, flags);
1da177e4
LT		 2035}
2036
2037static int sci_startup(struct uart_port *port)
2038{
a5660ada 2039 struct sci_port *s = to_sci_port(port);
073e84c9 2040 int ret;
1da177e4 2041
73a19e4c
GL		 2042 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2043
3c910176
TA		 2044 sci_request_dma(port);
2045
073e84c9 2046 ret = sci_request_irq(s);
3c910176
TA		 2047 if (unlikely(ret < 0)) {
2048 sci_free_dma(port);
073e84c9 2049 return ret;
3c910176 2050 }
073e84c9 2051
1da177e4
LT		 2052 return 0;
2053}
2054
2055static void sci_shutdown(struct uart_port *port)
2056{
a5660ada 2057 struct sci_port *s = to_sci_port(port);
33b48e16 2058 unsigned long flags;
5fd2b6ee 2059 u16 scr;
1da177e4 2060
73a19e4c
GL		 2061 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2062
33f50ffc 2063 s->autorts = false;
f907c9ea
GU		 2064 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2065
33b48e16 2066 spin_lock_irqsave(&port->lock, flags);
1da177e4 2067 sci_stop_rx(port);
b129a8cc 2068 sci_stop_tx(port);
fa2abb03
UH		 2069 /*
2070 * Stop RX and TX, disable related interrupts, keep clock source
2071 * and HSCIF TOT bits
2072 */
5fd2b6ee 2073 scr = serial_port_in(port, SCSCR);
fa2abb03
UH		 2074 serial_port_out(port, SCSCR, scr &
2075 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
33b48e16 2076 spin_unlock_irqrestore(&port->lock, flags);
073e84c9 2077
9ab76556
AM		 2078#ifdef CONFIG_SERIAL_SH_SCI_DMA
2079 if (s->chan_rx) {
2080 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2081 port->line);
2082 del_timer_sync(&s->rx_timer);
2083 }
2084#endif
2085
1da177e4 2086 sci_free_irq(s);
3c910176 2087 sci_free_dma(port);
1da177e4
LT		 2088}
2089
6af27bf2
GU		 2090static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2091 unsigned int *srr)
26c92f37 2092{
6af27bf2 2093 unsigned long freq = s->clk_rates[SCI_SCK];
6af27bf2 2094 int err, min_err = INT_MAX;
69eee8e9 2095 unsigned int sr;
6af27bf2 2096
7b5c0c08
GU		 2097 if (s->port.type != PORT_HSCIF)
2098 freq *= 2;
6af27bf2 2099
69eee8e9 2100 for_each_sr(sr, s) {
6af27bf2
GU		 2101 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2102 if (abs(err) >= abs(min_err))
2103 continue;
2104
2105 min_err = err;
2106 *srr = sr - 1;
ec09c5eb 2107
6af27bf2
GU		 2108 if (!err)
2109 break;
2110 }
e8183a6c 2111
6af27bf2
GU		 2112 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2113 *srr + 1);
2114 return min_err;
26c92f37
PM		 2115}
2116
1270f865
GU		 2117static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2118 unsigned long freq, unsigned int *dlr,
2119 unsigned int *srr)
730c4e78 2120{
1270f865 2121 int err, min_err = INT_MAX;
69eee8e9 2122 unsigned int sr, dl;
730c4e78 2123
7b5c0c08
GU		 2124 if (s->port.type != PORT_HSCIF)
2125 freq *= 2;
730c4e78 2126
69eee8e9 2127 for_each_sr(sr, s) {
1270f865
GU		 2128 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2129 dl = clamp(dl, 1U, 65535U);
2130
2131 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2132 if (abs(err) >= abs(min_err))
2133 continue;
2134
2135 min_err = err;
2136 *dlr = dl;
2137 *srr = sr - 1;
2138
2139 if (!err)
2140 break;
2141 }
730c4e78 2142
1270f865
GU		 2143 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2144 min_err, *dlr, *srr + 1);
2145 return min_err;
2146}
730c4e78 2147
b4a5c459 2148/* calculate sample rate, BRR, and clock select */
f4998e55
GU		 2149static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2150 unsigned int *brr, unsigned int *srr,
2151 unsigned int *cks)
f303b364 2152{
f4998e55 2153 unsigned long freq = s->clk_rates[SCI_FCK];
69eee8e9 2154 unsigned int sr, br, prediv, scrate, c;
6c51332d 2155 int err, min_err = INT_MAX;
f303b364 2156
7b5c0c08
GU		 2157 if (s->port.type != PORT_HSCIF)
2158 freq *= 2;
b4a5c459 2159
6c51332d
GU		 2160 /*
2161 * Find the combination of sample rate and clock select with the
2162 * smallest deviation from the desired baud rate.
2163 * Prefer high sample rates to maximise the receive margin.
2164 *
2165 * M: Receive margin (%)
2166 * N: Ratio of bit rate to clock (N = sampling rate)
2167 * D: Clock duty (D = 0 to 1.0)
2168 * L: Frame length (L = 9 to 12)
2169 * F: Absolute value of clock frequency deviation
2170 *
2171 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2172 * (|D - 0.5| / N * (1 + F))|
2173 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2174 */
69eee8e9 2175 for_each_sr(sr, s) {
f303b364
UH		 2176 for (c = 0; c <= 3; c++) {
2177 /* integerized formulas from HSCIF documentation */
7b5c0c08 2178 prediv = sr * (1 << (2 * c + 1));
de01e6cd
GU		 2179
2180 /*
2181 * We need to calculate:
2182 *
2183 * br = freq / (prediv * bps) clamped to [1..256]
881a7489 2184 * err = freq / (br * prediv) - bps
730c4e78 2185 *
de01e6cd
GU		 2186 * Watch out for overflow when calculating the desired
2187 * sampling clock rate!
730c4e78 2188 */
de01e6cd
GU		 2189 if (bps > UINT_MAX / prediv)
2190 break;
2191
2192 scrate = prediv * bps;
2193 br = DIV_ROUND_CLOSEST(freq, scrate);
95a2703e 2194 br = clamp(br, 1U, 256U);
6c51332d 2195
881a7489 2196 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
6c51332d 2197 if (abs(err) >= abs(min_err))
730c4e78
NI		 2198 continue;
2199
6c51332d 2200 min_err = err;
95a2703e 2201 *brr = br - 1;
730c4e78
NI		 2202 *srr = sr - 1;
2203 *cks = c;
6c51332d
GU		 2204
2205 if (!err)
2206 goto found;
f303b364
UH		 2207 }
2208 }
2209
6c51332d 2210found:
881a7489
GU		 2211 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2212 min_err, *brr, *srr + 1, *cks);
f4998e55 2213 return min_err;
f303b364
UH		 2214}
2215
1ba76220
MD		 2216static void sci_reset(struct uart_port *port)
2217{
d3184e68 2218 const struct plat_sci_reg *reg;
1ba76220 2219 unsigned int status;
18e8cf15 2220 struct sci_port *s = to_sci_port(port);
1ba76220 2221
fa2abb03 2222 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
1ba76220 2223
0979e0e6
PM		 2224 reg = sci_getreg(port, SCFCR);
2225 if (reg->size)
b12bb29f 2226 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2768cf42
GU		 2227
2228 sci_clear_SCxSR(port,
2229 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2230 SCxSR_BREAK_CLEAR(port));
fc2af334
GU		 2231 if (sci_getreg(port, SCLSR)->size) {
2232 status = serial_port_in(port, SCLSR);
2233 status &= ~(SCLSR_TO | SCLSR_ORER);
2234 serial_port_out(port, SCLSR, status);
2235 }
18e8cf15 2236
03940376
UH		 2237 if (s->rx_trigger > 1) {
2238 if (s->rx_fifo_timeout) {
2239 scif_set_rtrg(port, 1);
e99e88a9 2240 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
03940376 2241 } else {
90afa525
UH		 2242 if (port->type == PORT_SCIFA ||
2243 port->type == PORT_SCIFB)
2244 scif_set_rtrg(port, 1);
2245 else
2246 scif_set_rtrg(port, s->rx_trigger);
03940376
UH		 2247 }
2248 }
1ba76220
MD		 2249}
2250
606d099c
AC		 2251static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2252 struct ktermios *old)
1da177e4 2253{
03940376 2254 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
1270f865
GU		 2255 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2256 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
00b9de9c 2257 struct sci_port *s = to_sci_port(port);
d3184e68 2258 const struct plat_sci_reg *reg;
f4998e55
GU		 2259 int min_err = INT_MAX, err;
2260 unsigned long max_freq = 0;
2261 int best_clk = -1;
1be22663 2262 unsigned long flags;
1da177e4 2263
730c4e78
NI		 2264 if ((termios->c_cflag & CSIZE) == CS7)
2265 smr_val |= SCSMR_CHR;
2266 if (termios->c_cflag & PARENB)
2267 smr_val |= SCSMR_PE;
2268 if (termios->c_cflag & PARODD)
2269 smr_val |= SCSMR_PE | SCSMR_ODD;
2270 if (termios->c_cflag & CSTOPB)
2271 smr_val |= SCSMR_STOP;
2272
154280fd
MD		 2273 /*
2274 * earlyprintk comes here early on with port->uartclk set to zero.
2275 * the clock framework is not up and running at this point so here
2276 * we assume that 115200 is the maximum baud rate. please note that
2277 * the baud rate is not programmed during earlyprintk - it is assumed
2278 * that the previous boot loader has enabled required clocks and
2279 * setup the baud rate generator hardware for us already.
2280 */
f4998e55
GU		 2281 if (!port->uartclk) {
2282 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2283 goto done;
2284 }
1da177e4 2285
f4998e55
GU		 2286 for (i = 0; i < SCI_NUM_CLKS; i++)
2287 max_freq = max(max_freq, s->clk_rates[i]);
2288
69eee8e9 2289 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
f4998e55
GU		 2290 if (!baud)
2291 goto done;
2292
2293 /*
2294 * There can be multiple sources for the sampling clock. Find the one
2295 * that gives us the smallest deviation from the desired baud rate.
2296 */
2297
6af27bf2
GU		 2298 /* Optional Undivided External Clock */
2299 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2300 port->type != PORT_SCIFB) {
2301 err = sci_sck_calc(s, baud, &srr1);
2302 if (abs(err) < abs(min_err)) {
2303 best_clk = SCI_SCK;
2304 scr_val = SCSCR_CKE1;
2305 sccks = SCCKS_CKS;
2306 min_err = err;
2307 srr = srr1;
2308 if (!err)
2309 goto done;
2310 }
2311 }
2312
1270f865
GU		 2313 /* Optional BRG Frequency Divided External Clock */
2314 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2315 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2316 &srr1);
2317 if (abs(err) < abs(min_err)) {
2318 best_clk = SCI_SCIF_CLK;
2319 scr_val = SCSCR_CKE1;
2320 sccks = 0;
2321 min_err = err;
2322 dl = dl1;
2323 srr = srr1;
2324 if (!err)
2325 goto done;
2326 }
2327 }
2328
2329 /* Optional BRG Frequency Divided Internal Clock */
2330 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2331 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2332 &srr1);
2333 if (abs(err) < abs(min_err)) {
2334 best_clk = SCI_BRG_INT;
2335 scr_val = SCSCR_CKE1;
2336 sccks = SCCKS_XIN;
2337 min_err = err;
2338 dl = dl1;
2339 srr = srr1;
2340 if (!min_err)
2341 goto done;
f303b364
UH		 2342 }
2343 }
e108b2ca 2344
f4998e55
GU		 2345 /* Divided Functional Clock using standard Bit Rate Register */
2346 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2347 if (abs(err) < abs(min_err)) {
2348 best_clk = SCI_FCK;
6af27bf2 2349 scr_val = 0;
f4998e55
GU		 2350 min_err = err;
2351 brr = brr1;
2352 srr = srr1;
2353 cks = cks1;
2354 }
2355
2356done:
2357 if (best_clk >= 0)
2358 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2359 s->clks[best_clk], baud, min_err);
e108b2ca 2360
23241d43 2361 sci_port_enable(s);
36003386 2362
6af27bf2
GU		 2363 /*
2364 * Program the optional External Baud Rate Generator (BRG) first.
2365 * It controls the mux to select (H)SCK or frequency divided clock.
2366 */
1270f865
GU		 2367 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2368 serial_port_out(port, SCDL, dl);
6af27bf2 2369 serial_port_out(port, SCCKS, sccks);
1270f865 2370 }
1da177e4 2371
1be22663
TA		 2372 spin_lock_irqsave(&port->lock, flags);
2373
1ba76220 2374 sci_reset(port);
1da177e4
LT		 2375
2376 uart_update_timeout(port, termios->c_cflag, baud);
2377
f4998e55 2378 if (best_clk >= 0) {
92a05748
GU		 2379 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2380 switch (srr + 1) {
2381 case 5: smr_val |= SCSMR_SRC_5; break;
2382 case 7: smr_val |= SCSMR_SRC_7; break;
2383 case 11: smr_val |= SCSMR_SRC_11; break;
2384 case 13: smr_val |= SCSMR_SRC_13; break;
2385 case 16: smr_val |= SCSMR_SRC_16; break;
2386 case 17: smr_val |= SCSMR_SRC_17; break;
2387 case 19: smr_val |= SCSMR_SRC_19; break;
2388 case 27: smr_val |= SCSMR_SRC_27; break;
2389 }
f4998e55 2390 smr_val |= cks;
fa2abb03 2391 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
f4998e55
GU		 2392 serial_port_out(port, SCSMR, smr_val);
2393 serial_port_out(port, SCBRR, brr);
2394 if (sci_getreg(port, HSSRR)->size)
f303b364 2395 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
f4998e55
GU		 2396
2397 /* Wait one bit interval */
2398 udelay((1000000 + (baud - 1)) / baud);
2399 } else {
2400 /* Don't touch the bit rate configuration */
2401 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
3a964abe
GU		 2402 smr_val |= serial_port_in(port, SCSMR) &
2403 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
fa2abb03 2404 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
9d482cc3 2405 serial_port_out(port, SCSMR, smr_val);
f4998e55 2406 }
1da177e4 2407
d5701647 2408 sci_init_pins(port, termios->c_cflag);
0979e0e6 2409
33f50ffc
GU		 2410 port->status &= ~UPSTAT_AUTOCTS;
2411 s->autorts = false;
73c3d53f
PM		 2412 reg = sci_getreg(port, SCFCR);
2413 if (reg->size) {
b12bb29f 2414 unsigned short ctrl = serial_port_in(port, SCFCR);
0979e0e6 2415
33f50ffc
GU		 2416 if ((port->flags & UPF_HARD_FLOW) &&
2417 (termios->c_cflag & CRTSCTS)) {
2418 /* There is no CTS interrupt to restart the hardware */
2419 port->status |= UPSTAT_AUTOCTS;
2420 /* MCE is enabled when RTS is raised */
2421 s->autorts = true;
faf02f8f 2422 }
73c3d53f
PM		 2423
2424 /*
2425 * As we've done a sci_reset() above, ensure we don't
2426 * interfere with the FIFOs while toggling MCE. As the
2427 * reset values could still be set, simply mask them out.
2428 */
2429 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2430
b12bb29f 2431 serial_port_out(port, SCFCR, ctrl);
0979e0e6 2432 }
5f76895e
GU		 2433 if (port->flags & UPF_HARD_FLOW) {
2434 /* Refresh (Auto) RTS */
2435 sci_set_mctrl(port, port->mctrl);
2436 }
b7a76e4b 2437
9f8325b3
LP		 2438 scr_val |= SCSCR_RE | SCSCR_TE |
2439 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2440 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
92a05748
GU		 2441 if ((srr + 1 == 5) &&
2442 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2443 /*
2444 * In asynchronous mode, when the sampling rate is 1/5, first
2445 * received data may become invalid on some SCIFA and SCIFB.
2446 * To avoid this problem wait more than 1 serial data time (1
2447 * bit time x serial data number) after setting SCSCR.RE = 1.
2448 */
2449 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2450 }
1da177e4 2451
3089f381 2452 /*
5f6d8515 2453 * Calculate delay for 2 DMA buffers (4 FIFO).
f5835c1d
GU		 2454 * See serial_core.c::uart_update_timeout().
2455 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2456 * function calculates 1 jiffie for the data plus 5 jiffies for the
2457 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2458 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2459 * value obtained by this formula is too small. Therefore, if the value
2460 * is smaller than 20ms, use 20ms as the timeout value for DMA.
3089f381 2461 */
03940376
UH		 2462 /* byte size and parity */
2463 switch (termios->c_cflag & CSIZE) {
2464 case CS5:
2465 bits = 7;
2466 break;
2467 case CS6:
2468 bits = 8;
2469 break;
2470 case CS7:
2471 bits = 9;
2472 break;
2473 default:
2474 bits = 10;
2475 break;
2476 }
5f6d8515 2477
03940376
UH		 2478 if (termios->c_cflag & CSTOPB)
2479 bits++;
2480 if (termios->c_cflag & PARENB)
2481 bits++;
5f6d8515 2482
03940376
UH		 2483 s->rx_frame = (100 * bits * HZ) / (baud / 10);
2484#ifdef CONFIG_SERIAL_SH_SCI_DMA
2485 s->rx_timeout = DIV_ROUND_UP(s->buf_len_rx * 2 * s->rx_frame, 1000);
03940376
UH		 2486 if (s->rx_timeout < msecs_to_jiffies(20))
2487 s->rx_timeout = msecs_to_jiffies(20);
3089f381
GL		 2488#endif
2489
1da177e4 2490 if ((termios->c_cflag & CREAD) != 0)
73a19e4c 2491 sci_start_rx(port);
36003386 2492
1be22663
TA		 2493 spin_unlock_irqrestore(&port->lock, flags);
2494
23241d43 2495 sci_port_disable(s);
f907c9ea
GU		 2496
2497 if (UART_ENABLE_MS(port, termios->c_cflag))
2498 sci_enable_ms(port);
1da177e4
LT		 2499}
2500
0174e5ca
TK		 2501static void sci_pm(struct uart_port *port, unsigned int state,
2502 unsigned int oldstate)
2503{
2504 struct sci_port *sci_port = to_sci_port(port);
2505
2506 switch (state) {
d3dfe5d9 2507 case UART_PM_STATE_OFF:
0174e5ca
TK		 2508 sci_port_disable(sci_port);
2509 break;
2510 default:
2511 sci_port_enable(sci_port);
2512 break;
2513 }
2514}
2515
1da177e4
LT		 2516static const char *sci_type(struct uart_port *port)
2517{
2518 switch (port->type) {
e7c98dc7
MT		 2519 case PORT_IRDA:
2520 return "irda";
2521 case PORT_SCI:
2522 return "sci";
2523 case PORT_SCIF:
2524 return "scif";
2525 case PORT_SCIFA:
2526 return "scifa";
d1d4b10c
GL		 2527 case PORT_SCIFB:
2528 return "scifb";
f303b364
UH		 2529 case PORT_HSCIF:
2530 return "hscif";
1da177e4
LT		 2531 }
2532
fa43972f 2533 return NULL;
1da177e4
LT		 2534}
2535
f6e9495d
PM		 2536static int sci_remap_port(struct uart_port *port)
2537{
e4d6f911 2538 struct sci_port *sport = to_sci_port(port);
f6e9495d
PM		 2539
2540 /*
2541 * Nothing to do if there's already an established membase.
2542 */
2543 if (port->membase)
2544 return 0;
2545
3d73f32b 2546 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e4d6f911 2547 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
f6e9495d
PM		 2548 if (unlikely(!port->membase)) {
2549 dev_err(port->dev, "can't remap port#%d\n", port->line);
2550 return -ENXIO;
2551 }
2552 } else {
2553 /*
2554 * For the simple (and majority of) cases where we don't
2555 * need to do any remapping, just cast the cookie
2556 * directly.
2557 */
3af4e960 2558 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
f6e9495d
PM		 2559 }
2560
2561 return 0;
2562}
2563
e2651647 2564static void sci_release_port(struct uart_port *port)
1da177e4 2565{
e4d6f911
YS		 2566 struct sci_port *sport = to_sci_port(port);
2567
3d73f32b 2568 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
e2651647
PM		 2569 iounmap(port->membase);
2570 port->membase = NULL;
2571 }
2572
e4d6f911 2573 release_mem_region(port->mapbase, sport->reg_size);
1da177e4
LT		 2574}
2575
e2651647 2576static int sci_request_port(struct uart_port *port)
1da177e4 2577{
e2651647 2578 struct resource *res;
e4d6f911 2579 struct sci_port *sport = to_sci_port(port);
f6e9495d 2580 int ret;
1da177e4 2581
e4d6f911
YS		 2582 res = request_mem_region(port->mapbase, sport->reg_size,
2583 dev_name(port->dev));
2584 if (unlikely(res == NULL)) {
2585 dev_err(port->dev, "request_mem_region failed.");
e2651647 2586 return -EBUSY;
e4d6f911 2587 }
1da177e4 2588
f6e9495d
PM		 2589 ret = sci_remap_port(port);
2590 if (unlikely(ret != 0)) {
2591 release_resource(res);
2592 return ret;
7ff731ae 2593 }
e2651647
PM		 2594
2595 return 0;
2596}
2597
2598static void sci_config_port(struct uart_port *port, int flags)
2599{
2600 if (flags & UART_CONFIG_TYPE) {
2601 struct sci_port *sport = to_sci_port(port);
2602
2603 port->type = sport->cfg->type;
2604 sci_request_port(port);
2605 }
1da177e4
LT		 2606}
2607
2608static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2609{
1da177e4
LT		 2610 if (ser->baud_base < 2400)
2611 /* No paper tape reader for Mitch.. */
2612 return -EINVAL;
2613
2614 return 0;
2615}
2616
069a47e5 2617static const struct uart_ops sci_uart_ops = {
1da177e4
LT		 2618 .tx_empty = sci_tx_empty,
2619 .set_mctrl = sci_set_mctrl,
2620 .get_mctrl = sci_get_mctrl,
2621 .start_tx = sci_start_tx,
2622 .stop_tx = sci_stop_tx,
2623 .stop_rx = sci_stop_rx,
f907c9ea 2624 .enable_ms = sci_enable_ms,
1da177e4
LT		 2625 .break_ctl = sci_break_ctl,
2626 .startup = sci_startup,
2627 .shutdown = sci_shutdown,
1cf4a7ef 2628 .flush_buffer = sci_flush_buffer,
1da177e4 2629 .set_termios = sci_set_termios,
0174e5ca 2630 .pm = sci_pm,
1da177e4
LT		 2631 .type = sci_type,
2632 .release_port = sci_release_port,
2633 .request_port = sci_request_port,
2634 .config_port = sci_config_port,
2635 .verify_port = sci_verify_port,
07d2a1a1
PM		 2636#ifdef CONFIG_CONSOLE_POLL
2637 .poll_get_char = sci_poll_get_char,
2638 .poll_put_char = sci_poll_put_char,
2639#endif
1da177e4
LT		 2640};
2641
a9ec81f4
LP		 2642static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2643{
f4998e55
GU		 2644 const char *clk_names[] = {
2645 [SCI_FCK] = "fck",
6af27bf2 2646 [SCI_SCK] = "sck",
1270f865
GU		 2647 [SCI_BRG_INT] = "brg_int",
2648 [SCI_SCIF_CLK] = "scif_clk",
f4998e55
GU		 2649 };
2650 struct clk *clk;
2651 unsigned int i;
a9ec81f4 2652
6af27bf2
GU		 2653 if (sci_port->cfg->type == PORT_HSCIF)
2654 clk_names[SCI_SCK] = "hsck";
2655
f4998e55
GU		 2656 for (i = 0; i < SCI_NUM_CLKS; i++) {
2657 clk = devm_clk_get(dev, clk_names[i]);
2658 if (PTR_ERR(clk) == -EPROBE_DEFER)
2659 return -EPROBE_DEFER;
a9ec81f4 2660
f4998e55
GU		 2661 if (IS_ERR(clk) && i == SCI_FCK) {
2662 /*
2663 * "fck" used to be called "sci_ick", and we need to
2664 * maintain DT backward compatibility.
2665 */
2666 clk = devm_clk_get(dev, "sci_ick");
2667 if (PTR_ERR(clk) == -EPROBE_DEFER)
2668 return -EPROBE_DEFER;
a9ec81f4 2669
f4998e55
GU		 2670 if (!IS_ERR(clk))
2671 goto found;
a9ec81f4 2672
f4998e55
GU		 2673 /*
2674 * Not all SH platforms declare a clock lookup entry
2675 * for SCI devices, in which case we need to get the
2676 * global "peripheral_clk" clock.
2677 */
2678 clk = devm_clk_get(dev, "peripheral_clk");
2679 if (!IS_ERR(clk))
2680 goto found;
2681
2682 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2683 PTR_ERR(clk));
2684 return PTR_ERR(clk);
2685 }
2686
2687found:
2688 if (IS_ERR(clk))
2689 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2690 PTR_ERR(clk));
2691 else
2692 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2693 clk, clk);
2694 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2695 }
2696 return 0;
a9ec81f4
LP		 2697}
2698
daf5a895
LP		 2699static const struct sci_port_params *
2700sci_probe_regmap(const struct plat_sci_port *cfg)
2701{
2702 unsigned int regtype;
2703
2704 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2705 return &sci_port_params[cfg->regtype];
2706
2707 switch (cfg->type) {
2708 case PORT_SCI:
2709 regtype = SCIx_SCI_REGTYPE;
2710 break;
2711 case PORT_IRDA:
2712 regtype = SCIx_IRDA_REGTYPE;
2713 break;
2714 case PORT_SCIFA:
2715 regtype = SCIx_SCIFA_REGTYPE;
2716 break;
2717 case PORT_SCIFB:
2718 regtype = SCIx_SCIFB_REGTYPE;
2719 break;
2720 case PORT_SCIF:
2721 /*
2722 * The SH-4 is a bit of a misnomer here, although that's
2723 * where this particular port layout originated. This
2724 * configuration (or some slight variation thereof)
2725 * remains the dominant model for all SCIFs.
2726 */
2727 regtype = SCIx_SH4_SCIF_REGTYPE;
2728 break;
2729 case PORT_HSCIF:
2730 regtype = SCIx_HSCIF_REGTYPE;
2731 break;
2732 default:
2733 pr_err("Can't probe register map for given port\n");
2734 return NULL;
2735 }
2736
2737 return &sci_port_params[regtype];
2738}
2739
9671f099 2740static int sci_init_single(struct platform_device *dev,
1fcc91a6 2741 struct sci_port *sci_port, unsigned int index,
daf5a895 2742 const struct plat_sci_port *p, bool early)
e108b2ca 2743{
73a19e4c 2744 struct uart_port *port = &sci_port->port;
1fcc91a6
LP		 2745 const struct resource *res;
2746 unsigned int i;
3127c6b2 2747 int ret;
e108b2ca 2748
50f0959a
PM		 2749 sci_port->cfg = p;
2750
73a19e4c
GL		 2751 port->ops = &sci_uart_ops;
2752 port->iotype = UPIO_MEM;
2753 port->line = index;
75136d48 2754
89b5c1ab
LP		 2755 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2756 if (res == NULL)
2757 return -ENOMEM;
1fcc91a6 2758
89b5c1ab 2759 port->mapbase = res->start;
e4d6f911 2760 sci_port->reg_size = resource_size(res);
1fcc91a6 2761
89b5c1ab
LP		 2762 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2763 sci_port->irqs[i] = platform_get_irq(dev, i);
1fcc91a6 2764
89b5c1ab
LP		 2765 /* The SCI generates several interrupts. They can be muxed together or
2766 * connected to different interrupt lines. In the muxed case only one
2767 * interrupt resource is specified. In the non-muxed case three or four
2768 * interrupt resources are specified, as the BRI interrupt is optional.
2769 */
2770 if (sci_port->irqs[0] < 0)
2771 return -ENXIO;
1fcc91a6 2772
89b5c1ab
LP		 2773 if (sci_port->irqs[1] < 0) {
2774 sci_port->irqs[1] = sci_port->irqs[0];
2775 sci_port->irqs[2] = sci_port->irqs[0];
2776 sci_port->irqs[3] = sci_port->irqs[0];
1fcc91a6
LP		 2777 }
2778
daf5a895
LP		 2779 sci_port->params = sci_probe_regmap(p);
2780 if (unlikely(sci_port->params == NULL))
2781 return -EINVAL;
e095ee6b 2782
18e8cf15
UH		 2783 switch (p->type) {
2784 case PORT_SCIFB:
2785 sci_port->rx_trigger = 48;
2786 break;
2787 case PORT_HSCIF:
2788 sci_port->rx_trigger = 64;
2789 break;
2790 case PORT_SCIFA:
2791 sci_port->rx_trigger = 32;
2792 break;
2793 case PORT_SCIF:
2794 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2795 /* RX triggering not implemented for this IP */
2796 sci_port->rx_trigger = 1;
2797 else
2798 sci_port->rx_trigger = 8;
2799 break;
2800 default:
2801 sci_port->rx_trigger = 1;
2802 break;
2803 }
2804
03940376 2805 sci_port->rx_fifo_timeout = 0;
fa2abb03 2806 sci_port->hscif_tot = 0;
03940376 2807
878fbb91
LP		 2808 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2809 * match the SoC datasheet, this should be investigated. Let platform
2810 * data override the sampling rate for now.
ec09c5eb 2811 */
b2f20ed9
LP		 2812 sci_port->sampling_rate_mask = p->sampling_rate
2813 ? SCI_SR(p->sampling_rate)
2814 : sci_port->params->sampling_rate_mask;
ec09c5eb 2815
1fcc91a6 2816 if (!early) {
a9ec81f4
LP		 2817 ret = sci_init_clocks(sci_port, &dev->dev);
2818 if (ret < 0)
2819 return ret;
c7ed1ab3 2820
73a19e4c 2821 port->dev = &dev->dev;
5e50d2d6
MD		 2822
2823 pm_runtime_enable(&dev->dev);
7b6fd3bf 2824 }
e108b2ca 2825
ce6738b6 2826 port->type = p->type;
3d73f32b 2827 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
b2f20ed9 2828 port->fifosize = sci_port->params->fifosize;
73a19e4c 2829
dfc80387
LP		 2830 if (port->type == PORT_SCI) {
2831 if (sci_port->reg_size >= 0x20)
2832 port->regshift = 2;
2833 else
2834 port->regshift = 1;
2835 }
2836
ce6738b6 2837 /*
61a6976b 2838 * The UART port needs an IRQ value, so we peg this to the RX IRQ
ce6738b6
PM		 2839 * for the multi-IRQ ports, which is where we are primarily
2840 * concerned with the shutdown path synchronization.
2841 *
2842 * For the muxed case there's nothing more to do.
2843 */
1fcc91a6 2844 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
9cfb5c05 2845 port->irqflags = 0;
73a19e4c 2846
61a6976b
PM		 2847 port->serial_in = sci_serial_in;
2848 port->serial_out = sci_serial_out;
2849
c7ed1ab3 2850 return 0;
e108b2ca
PM		 2851}
2852
6dae1421
LP		 2853static void sci_cleanup_single(struct sci_port *port)
2854{
6dae1421
LP		 2855 pm_runtime_disable(port->port.dev);
2856}
2857
0b0cced1
YS		 2858#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2859 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
dc8e6f5b
MD		 2860static void serial_console_putchar(struct uart_port *port, int ch)
2861{
2862 sci_poll_put_char(port, ch);
2863}
2864
1da177e4
LT		 2865/*
2866 * Print a string to the serial port trying not to disturb
2867 * any possible real use of the port...
2868 */
2869static void serial_console_write(struct console *co, const char *s,
2870 unsigned count)
2871{
906b17dc
PM		 2872 struct sci_port *sci_port = &sci_ports[co->index];
2873 struct uart_port *port = &sci_port->port;
a67969b5 2874 unsigned short bits, ctrl, ctrl_temp;
40f70c03
SK		 2875 unsigned long flags;
2876 int locked = 1;
2877
2878 local_irq_save(flags);
0b0cced1 2879#if defined(SUPPORT_SYSRQ)
40f70c03
SK		 2880 if (port->sysrq)
2881 locked = 0;
0b0cced1
YS		 2882 else
2883#endif
2884 if (oops_in_progress)
40f70c03
SK		 2885 locked = spin_trylock(&port->lock);
2886 else
2887 spin_lock(&port->lock);
2888
a67969b5 2889 /* first save SCSCR then disable interrupts, keep clock source */
40f70c03 2890 ctrl = serial_port_in(port, SCSCR);
9f8325b3
LP		 2891 ctrl_temp = SCSCR_RE | SCSCR_TE |
2892 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
a67969b5 2893 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
fa2abb03 2894 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
07d2a1a1 2895
501b825d 2896 uart_console_write(port, s, count, serial_console_putchar);
973e5d52
MD		 2897
2898 /* wait until fifo is empty and last bit has been transmitted */
2899 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
b12bb29f 2900 while ((serial_port_in(port, SCxSR) & bits) != bits)
973e5d52 2901 cpu_relax();
40f70c03
SK		 2902
2903 /* restore the SCSCR */
2904 serial_port_out(port, SCSCR, ctrl);
2905
2906 if (locked)
2907 spin_unlock(&port->lock);
2908 local_irq_restore(flags);
1da177e4
LT		 2909}
2910
9671f099 2911static int serial_console_setup(struct console *co, char *options)
1da177e4 2912{
dc8e6f5b 2913 struct sci_port *sci_port;
1da177e4
LT		 2914 struct uart_port *port;
2915 int baud = 115200;
2916 int bits = 8;
2917 int parity = 'n';
2918 int flow = 'n';
2919 int ret;
2920
e108b2ca 2921 /*
906b17dc 2922 * Refuse to handle any bogus ports.
1da177e4 2923 */
906b17dc 2924 if (co->index < 0 || co->index >= SCI_NPORTS)
e108b2ca 2925 return -ENODEV;
e108b2ca 2926
906b17dc
PM		 2927 sci_port = &sci_ports[co->index];
2928 port = &sci_port->port;
2929
b2267a6b
AC		 2930 /*
2931 * Refuse to handle uninitialized ports.
2932 */
2933 if (!port->ops)
2934 return -ENODEV;
2935
f6e9495d
PM		 2936 ret = sci_remap_port(port);
2937 if (unlikely(ret != 0))
2938 return ret;
e108b2ca 2939
1da177e4
LT		 2940 if (options)
2941 uart_parse_options(options, &baud, &parity, &bits, &flow);
2942
ab7cfb55 2943 return uart_set_options(port, co, baud, parity, bits, flow);
1da177e4
LT		 2944}
2945
2946static struct console serial_console = {
2947 .name = "ttySC",
906b17dc 2948 .device = uart_console_device,
1da177e4
LT		 2949 .write = serial_console_write,
2950 .setup = serial_console_setup,
fa5da2f7 2951 .flags = CON_PRINTBUFFER,
1da177e4 2952 .index = -1,
906b17dc 2953 .data = &sci_uart_driver,
1da177e4
LT		 2954};
2955
7b6fd3bf
MD		 2956static struct console early_serial_console = {
2957 .name = "early_ttySC",
2958 .write = serial_console_write,
2959 .flags = CON_PRINTBUFFER,
906b17dc 2960 .index = -1,
7b6fd3bf 2961};
ecdf8a46 2962
7b6fd3bf
MD		 2963static char early_serial_buf[32];
2964
9671f099 2965static int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46 2966{
daf5a895 2967 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
ecdf8a46
PM		 2968
2969 if (early_serial_console.data)
2970 return -EEXIST;
2971
2972 early_serial_console.index = pdev->id;
ecdf8a46 2973
1fcc91a6 2974 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
ecdf8a46
PM		 2975
2976 serial_console_setup(&early_serial_console, early_serial_buf);
2977
2978 if (!strstr(early_serial_buf, "keep"))
2979 early_serial_console.flags |= CON_BOOT;
2980
2981 register_console(&early_serial_console);
2982 return 0;
2983}
6a8c9799
NI		 2984
2985#define SCI_CONSOLE (&serial_console)
2986
ecdf8a46 2987#else
9671f099 2988static inline int sci_probe_earlyprintk(struct platform_device *pdev)
ecdf8a46
PM		 2989{
2990 return -EINVAL;
2991}
1da177e4 2992
6a8c9799
NI		 2993#define SCI_CONSOLE NULL
2994
0b0cced1 2995#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
1da177e4 2996
6c13d5d2 2997static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
1da177e4 2998
352b9266 2999static DEFINE_MUTEX(sci_uart_registration_lock);
1da177e4
LT		 3000static struct uart_driver sci_uart_driver = {
3001 .owner = THIS_MODULE,
3002 .driver_name = "sci",
1da177e4
LT		 3003 .dev_name = "ttySC",
3004 .major = SCI_MAJOR,
3005 .minor = SCI_MINOR_START,
e108b2ca 3006 .nr = SCI_NPORTS,
1da177e4
LT		 3007 .cons = SCI_CONSOLE,
3008};
3009
54507f6e 3010static int sci_remove(struct platform_device *dev)
e552de24 3011{
d535a230 3012 struct sci_port *port = platform_get_drvdata(dev);
e552de24 3013
d535a230
PM		 3014 uart_remove_one_port(&sci_uart_driver, &port->port);
3015
6dae1421 3016 sci_cleanup_single(port);
e552de24 3017
5d23188a
UH		 3018 if (port->port.fifosize > 1) {
3019 sysfs_remove_file(&dev->dev.kobj,
3020 &dev_attr_rx_fifo_trigger.attr);
3021 }
fa2abb03
UH		 3022 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3023 port->port.type == PORT_HSCIF) {
5d23188a
UH		 3024 sysfs_remove_file(&dev->dev.kobj,
3025 &dev_attr_rx_fifo_timeout.attr);
3026 }
3027
e552de24
MD		 3028 return 0;
3029}
3030
bd2238fb
GU		 3031
3032#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3033#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3034#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
20bdcab8
BH		 3035
3036static const struct of_device_id of_sci_match[] = {
f443ff80
GU		 3037 /* SoC-specific types */
3038 {
3039 .compatible = "renesas,scif-r7s72100",
3040 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3041 },
9ed44bb2
GU		 3042 /* Family-specific types */
3043 {
3044 .compatible = "renesas,rcar-gen1-scif",
3045 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3046 }, {
3047 .compatible = "renesas,rcar-gen2-scif",
3048 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3049 }, {
3050 .compatible = "renesas,rcar-gen3-scif",
3051 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3052 },
f443ff80 3053 /* Generic types */
20bdcab8
BH		 3054 {
3055 .compatible = "renesas,scif",
bd2238fb 3056 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
20bdcab8
BH		 3057 }, {
3058 .compatible = "renesas,scifa",
bd2238fb 3059 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
20bdcab8
BH		 3060 }, {
3061 .compatible = "renesas,scifb",
bd2238fb 3062 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
20bdcab8
BH		 3063 }, {
3064 .compatible = "renesas,hscif",
bd2238fb 3065 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
e1d0be61
YS		 3066 }, {
3067 .compatible = "renesas,sci",
bd2238fb 3068 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
20bdcab8
BH		 3069 }, {
3070 /* Terminator */
3071 },
3072};
3073MODULE_DEVICE_TABLE(of, of_sci_match);
3074
54b12c48
GU		 3075static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3076 unsigned int *dev_id)
20bdcab8
BH		 3077{
3078 struct device_node *np = pdev->dev.of_node;
20bdcab8 3079 struct plat_sci_port *p;
97ed9790 3080 struct sci_port *sp;
6e605a01 3081 const void *data;
20bdcab8
BH		 3082 int id;
3083
3084 if (!IS_ENABLED(CONFIG_OF) || !np)
3085 return NULL;
3086
6e605a01 3087 data = of_device_get_match_data(&pdev->dev);
20bdcab8 3088
20bdcab8 3089 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
4205463c 3090 if (!p)
20bdcab8 3091 return NULL;
20bdcab8 3092
2095fc76 3093 /* Get the line number from the aliases node. */
20bdcab8
BH		 3094 id = of_alias_get_id(np, "serial");
3095 if (id < 0) {
3096 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3097 return NULL;
3098 }
3099
97ed9790 3100 sp = &sci_ports[id];
20bdcab8
BH		 3101 *dev_id = id;
3102
6e605a01
GU		 3103 p->type = SCI_OF_TYPE(data);
3104 p->regtype = SCI_OF_REGTYPE(data);
20bdcab8 3105
43c61286 3106 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
861a70ab 3107
20bdcab8
BH		 3108 return p;
3109}
3110
9671f099 3111static int sci_probe_single(struct platform_device *dev,
0ee70712
MD		 3112 unsigned int index,
3113 struct plat_sci_port *p,
3114 struct sci_port *sciport)
3115{
0ee70712
MD		 3116 int ret;
3117
3118 /* Sanity check */
3119 if (unlikely(index >= SCI_NPORTS)) {
9b971cd2 3120 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
0ee70712 3121 index+1, SCI_NPORTS);
9b971cd2 3122 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
b6c5ef6f 3123 return -EINVAL;
0ee70712
MD		 3124 }
3125
352b9266
SS		 3126 mutex_lock(&sci_uart_registration_lock);
3127 if (!sci_uart_driver.state) {
3128 ret = uart_register_driver(&sci_uart_driver);
3129 if (ret) {
3130 mutex_unlock(&sci_uart_registration_lock);
3131 return ret;
3132 }
3133 }
3134 mutex_unlock(&sci_uart_registration_lock);
3135
1fcc91a6 3136 ret = sci_init_single(dev, sciport, index, p, false);
c7ed1ab3
PM		 3137 if (ret)
3138 return ret;
0ee70712 3139
f907c9ea
GU		 3140 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3141 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3142 return PTR_ERR(sciport->gpios);
3143
97ed9790 3144 if (sciport->has_rtscts) {
f907c9ea
GU		 3145 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3146 UART_GPIO_CTS)) ||
3147 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3148 UART_GPIO_RTS))) {
3149 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3150 return -EINVAL;
3151 }
33f50ffc 3152 sciport->port.flags |= UPF_HARD_FLOW;
f907c9ea
GU		 3153 }
3154
6dae1421
LP		 3155 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3156 if (ret) {
3157 sci_cleanup_single(sciport);
3158 return ret;
3159 }
3160
3161 return 0;
0ee70712
MD		 3162}
3163
9671f099 3164static int sci_probe(struct platform_device *dev)
1da177e4 3165{
20bdcab8
BH		 3166 struct plat_sci_port *p;
3167 struct sci_port *sp;
3168 unsigned int dev_id;
ecdf8a46 3169 int ret;
d535a230 3170
ecdf8a46
PM		 3171 /*
3172 * If we've come here via earlyprintk initialization, head off to
3173 * the special early probe. We don't have sufficient device state
3174 * to make it beyond this yet.
3175 */
3176 if (is_early_platform_device(dev))
3177 return sci_probe_earlyprintk(dev);
7b6fd3bf 3178
20bdcab8
BH		 3179 if (dev->dev.of_node) {
3180 p = sci_parse_dt(dev, &dev_id);
3181 if (p == NULL)
3182 return -EINVAL;
3183 } else {
3184 p = dev->dev.platform_data;
3185 if (p == NULL) {
3186 dev_err(&dev->dev, "no platform data supplied\n");
3187 return -EINVAL;
3188 }
3189
3190 dev_id = dev->id;
3191 }
3192
3193 sp = &sci_ports[dev_id];
d535a230 3194 platform_set_drvdata(dev, sp);
e552de24 3195
20bdcab8 3196 ret = sci_probe_single(dev, dev_id, p, sp);
d535a230 3197 if (ret)
6dae1421 3198 return ret;
e552de24 3199
5d23188a
UH		 3200 if (sp->port.fifosize > 1) {
3201 ret = sysfs_create_file(&dev->dev.kobj,
3202 &dev_attr_rx_fifo_trigger.attr);
3203 if (ret)
3204 return ret;
3205 }
fa2abb03
UH		 3206 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3207 sp->port.type == PORT_HSCIF) {
5d23188a
UH		 3208 ret = sysfs_create_file(&dev->dev.kobj,
3209 &dev_attr_rx_fifo_timeout.attr);
3210 if (ret) {
3211 if (sp->port.fifosize > 1) {
3212 sysfs_remove_file(&dev->dev.kobj,
3213 &dev_attr_rx_fifo_trigger.attr);
3214 }
3215 return ret;
3216 }
3217 }
3218
1da177e4
LT		 3219#ifdef CONFIG_SH_STANDARD_BIOS
3220 sh_bios_gdb_detach();
3221#endif
3222
e108b2ca 3223 return 0;
1da177e4
LT		 3224}
3225
cb876341 3226static __maybe_unused int sci_suspend(struct device *dev)
1da177e4 3227{
d535a230 3228 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3229
d535a230
PM		 3230 if (sport)
3231 uart_suspend_port(&sci_uart_driver, &sport->port);
1da177e4 3232
e108b2ca
PM		 3233 return 0;
3234}
1da177e4 3235
cb876341 3236static __maybe_unused int sci_resume(struct device *dev)
e108b2ca 3237{
d535a230 3238 struct sci_port *sport = dev_get_drvdata(dev);
e108b2ca 3239
d535a230
PM		 3240 if (sport)
3241 uart_resume_port(&sci_uart_driver, &sport->port);
e108b2ca
PM		 3242
3243 return 0;
3244}
3245
cb876341 3246static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
6daa79b3 3247
e108b2ca
PM		 3248static struct platform_driver sci_driver = {
3249 .probe = sci_probe,
b9e39c89 3250 .remove = sci_remove,
e108b2ca
PM		 3251 .driver = {
3252 .name = "sh-sci",
6daa79b3 3253 .pm = &sci_dev_pm_ops,
20bdcab8 3254 .of_match_table = of_match_ptr(of_sci_match),
e108b2ca
PM		 3255 },
3256};
3257
3258static int __init sci_init(void)
3259{
6c13d5d2 3260 pr_info("%s\n", banner);
e108b2ca 3261
352b9266 3262 return platform_driver_register(&sci_driver);
e108b2ca
PM		 3263}
3264
3265static void __exit sci_exit(void)
3266{
3267 platform_driver_unregister(&sci_driver);
352b9266
SS		 3268
3269 if (sci_uart_driver.state)
3270 uart_unregister_driver(&sci_uart_driver);
1da177e4
LT		 3271}
3272
7b6fd3bf
MD		 3273#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3274early_platform_init_buffer("earlyprintk", &sci_driver,
3275 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3276#endif
0b0cced1 3277#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
dd076cff 3278static struct plat_sci_port port_cfg __initdata;
0b0cced1
YS		 3279
3280static int __init early_console_setup(struct earlycon_device *device,
3281 int type)
3282{
3283 if (!device->port.membase)
3284 return -ENODEV;
3285
3286 device->port.serial_in = sci_serial_in;
3287 device->port.serial_out = sci_serial_out;
3288 device->port.type = type;
3289 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
daf5a895 3290 port_cfg.type = type;
0b0cced1 3291 sci_ports[0].cfg = &port_cfg;
daf5a895 3292 sci_ports[0].params = sci_probe_regmap(&port_cfg);
9f8325b3
LP		 3293 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3294 sci_serial_out(&sci_ports[0].port, SCSCR,
3295 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
0b0cced1
YS		 3296
3297 device->con->write = serial_console_write;
3298 return 0;
3299}
3300static int __init sci_early_console_setup(struct earlycon_device *device,
3301 const char *opt)
3302{
3303 return early_console_setup(device, PORT_SCI);
3304}
3305static int __init scif_early_console_setup(struct earlycon_device *device,
3306 const char *opt)
3307{
3308 return early_console_setup(device, PORT_SCIF);
3309}
3310static int __init scifa_early_console_setup(struct earlycon_device *device,
3311 const char *opt)
3312{
3313 return early_console_setup(device, PORT_SCIFA);
3314}
3315static int __init scifb_early_console_setup(struct earlycon_device *device,
3316 const char *opt)
3317{
3318 return early_console_setup(device, PORT_SCIFB);
3319}
3320static int __init hscif_early_console_setup(struct earlycon_device *device,
3321 const char *opt)
3322{
3323 return early_console_setup(device, PORT_HSCIF);
3324}
3325
0b0cced1 3326OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
0b0cced1 3327OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
0b0cced1 3328OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
0b0cced1 3329OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
0b0cced1
YS		 3330OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3331#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3332
1da177e4
LT		 3333module_init(sci_init);
3334module_exit(sci_exit);
3335
e108b2ca 3336MODULE_LICENSE("GPL");
e169c139 3337MODULE_ALIAS("platform:sh-sci");
7f405f9c 3338MODULE_AUTHOR("Paul Mundt");
f303b364 3339MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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