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5fd54ace | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * Universal Host Controller Interface driver for USB. | |
4 | * | |
5 | * Maintainer: Alan Stern <stern@rowland.harvard.edu> | |
6 | * | |
7 | * (C) Copyright 1999 Linus Torvalds | |
8 | * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com | |
9 | * (C) Copyright 1999 Randy Dunlap | |
10 | * (C) Copyright 1999 Georg Acher, acher@in.tum.de | |
11 | * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de | |
12 | * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch | |
13 | * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at | |
14 | * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface | |
15 | * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com). | |
16 | * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c) | |
17230acd | 17 | * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu |
1da177e4 LT |
18 | * |
19 | * Intel documents this fairly well, and as far as I know there | |
20 | * are no royalties or anything like that, but even so there are | |
21 | * people who decided that they want to do the same thing in a | |
22 | * completely different way. | |
23 | * | |
1da177e4 LT |
24 | */ |
25 | ||
1da177e4 LT |
26 | #include <linux/module.h> |
27 | #include <linux/pci.h> | |
28 | #include <linux/kernel.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/ioport.h> | |
1da177e4 | 32 | #include <linux/slab.h> |
1da177e4 LT |
33 | #include <linux/errno.h> |
34 | #include <linux/unistd.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/debugfs.h> | |
38 | #include <linux/pm.h> | |
39 | #include <linux/dmapool.h> | |
40 | #include <linux/dma-mapping.h> | |
41 | #include <linux/usb.h> | |
27729aad | 42 | #include <linux/usb/hcd.h> |
1da177e4 | 43 | #include <linux/bitops.h> |
b62df451 | 44 | #include <linux/dmi.h> |
1da177e4 | 45 | |
7c0f6ba6 | 46 | #include <linux/uaccess.h> |
1da177e4 LT |
47 | #include <asm/io.h> |
48 | #include <asm/irq.h> | |
1da177e4 | 49 | |
1da177e4 LT |
50 | #include "uhci-hcd.h" |
51 | ||
52 | /* | |
53 | * Version Information | |
54 | */ | |
85ee7a1d JP |
55 | #define DRIVER_AUTHOR \ |
56 | "Linus 'Frodo Rabbit' Torvalds, Johannes Erdfelt, " \ | |
57 | "Randy Dunlap, Georg Acher, Deti Fliegl, Thomas Sailer, " \ | |
58 | "Roman Weissgaerber, Alan Stern" | |
1da177e4 LT |
59 | #define DRIVER_DESC "USB Universal Host Controller Interface driver" |
60 | ||
5f8364b7 | 61 | /* for flakey hardware, ignore overcurrent indicators */ |
90ab5ee9 | 62 | static bool ignore_oc; |
5f8364b7 AS |
63 | module_param(ignore_oc, bool, S_IRUGO); |
64 | MODULE_PARM_DESC(ignore_oc, "ignore hardware overcurrent indications"); | |
65 | ||
1da177e4 LT |
66 | /* |
67 | * debug = 0, no debugging messages | |
687f5f34 AS |
68 | * debug = 1, dump failed URBs except for stalls |
69 | * debug = 2, dump all failed URBs (including stalls) | |
837cbb07 | 70 | * show all queues in /sys/kernel/debug/uhci/[pci_addr] |
687f5f34 | 71 | * debug = 3, show all TDs in URBs when dumping |
1da177e4 | 72 | */ |
1c20163d | 73 | #ifdef CONFIG_DYNAMIC_DEBUG |
cadb3756 | 74 | |
1da177e4 | 75 | static int debug = 1; |
1da177e4 LT |
76 | module_param(debug, int, S_IRUGO | S_IWUSR); |
77 | MODULE_PARM_DESC(debug, "Debug level"); | |
cadb3756 | 78 | static char *errbuf; |
8d402e1a AS |
79 | |
80 | #else | |
cadb3756 ON |
81 | |
82 | #define debug 0 | |
83 | #define errbuf NULL | |
84 | ||
8d402e1a AS |
85 | #endif |
86 | ||
cadb3756 | 87 | |
1da177e4 LT |
88 | #define ERRBUF_LEN (32 * 1024) |
89 | ||
e18b890b | 90 | static struct kmem_cache *uhci_up_cachep; /* urb_priv */ |
1da177e4 | 91 | |
6c1b445c AS |
92 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state); |
93 | static void wakeup_rh(struct uhci_hcd *uhci); | |
1da177e4 | 94 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci); |
1da177e4 | 95 | |
f3fe239b AS |
96 | /* |
97 | * Calculate the link pointer DMA value for the first Skeleton QH in a frame. | |
98 | */ | |
51e2f62f | 99 | static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame) |
f3fe239b AS |
100 | { |
101 | int skelnum; | |
102 | ||
103 | /* | |
104 | * The interrupt queues will be interleaved as evenly as possible. | |
105 | * There's not much to be done about period-1 interrupts; they have | |
106 | * to occur in every frame. But we can schedule period-2 interrupts | |
107 | * in odd-numbered frames, period-4 interrupts in frames congruent | |
108 | * to 2 (mod 4), and so on. This way each frame only has two | |
109 | * interrupt QHs, which will help spread out bandwidth utilization. | |
110 | * | |
111 | * ffs (Find First bit Set) does exactly what we need: | |
17230acd AS |
112 | * 1,3,5,... => ffs = 0 => use period-2 QH = skelqh[8], |
113 | * 2,6,10,... => ffs = 1 => use period-4 QH = skelqh[7], etc. | |
f3fe239b | 114 | * ffs >= 7 => not on any high-period queue, so use |
17230acd | 115 | * period-1 QH = skelqh[9]. |
f3fe239b AS |
116 | * Add in UHCI_NUMFRAMES to insure at least one bit is set. |
117 | */ | |
118 | skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES); | |
119 | if (skelnum <= 1) | |
120 | skelnum = 9; | |
51e2f62f | 121 | return LINK_TO_QH(uhci, uhci->skelqh[skelnum]); |
f3fe239b AS |
122 | } |
123 | ||
1da177e4 LT |
124 | #include "uhci-debug.c" |
125 | #include "uhci-q.c" | |
1f09df8b | 126 | #include "uhci-hub.c" |
1da177e4 | 127 | |
a8bed8b6 | 128 | /* |
bb200f6e | 129 | * Finish up a host controller reset and update the recorded state. |
a8bed8b6 | 130 | */ |
bb200f6e | 131 | static void finish_reset(struct uhci_hcd *uhci) |
1da177e4 | 132 | { |
c074b416 AS |
133 | int port; |
134 | ||
c074b416 AS |
135 | /* HCRESET doesn't affect the Suspend, Reset, and Resume Detect |
136 | * bits in the port status and control registers. | |
137 | * We have to clear them by hand. | |
138 | */ | |
139 | for (port = 0; port < uhci->rh_numports; ++port) | |
9faa091a | 140 | uhci_writew(uhci, 0, USBPORTSC1 + (port * 2)); |
c074b416 | 141 | |
8e326406 | 142 | uhci->port_c_suspend = uhci->resuming_ports = 0; |
c8f4fe43 | 143 | uhci->rh_state = UHCI_RH_RESET; |
a8bed8b6 | 144 | uhci->is_stopped = UHCI_IS_STOPPED; |
541c7d43 | 145 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
1da177e4 LT |
146 | } |
147 | ||
4daaa87c AS |
148 | /* |
149 | * Last rites for a defunct/nonfunctional controller | |
02597d2d | 150 | * or one we don't want to use any more. |
4daaa87c | 151 | */ |
e323de46 | 152 | static void uhci_hc_died(struct uhci_hcd *uhci) |
4daaa87c | 153 | { |
e323de46 | 154 | uhci_get_current_frame_number(uhci); |
e7652e1e | 155 | uhci->reset_hc(uhci); |
bb200f6e | 156 | finish_reset(uhci); |
e323de46 AS |
157 | uhci->dead = 1; |
158 | ||
159 | /* The current frame may already be partway finished */ | |
160 | ++uhci->frame_number; | |
4daaa87c AS |
161 | } |
162 | ||
a8bed8b6 | 163 | /* |
be3cbc5f DB |
164 | * Initialize a controller that was newly discovered or has lost power |
165 | * or otherwise been reset while it was suspended. In none of these cases | |
166 | * can we be sure of its previous state. | |
a8bed8b6 AS |
167 | */ |
168 | static void check_and_reset_hc(struct uhci_hcd *uhci) | |
169 | { | |
e7652e1e | 170 | if (uhci->check_and_reset_hc(uhci)) |
bb200f6e | 171 | finish_reset(uhci); |
a8bed8b6 AS |
172 | } |
173 | ||
d3219d1c JA |
174 | #if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC) |
175 | /* | |
176 | * The two functions below are generic reset functions that are used on systems | |
177 | * that do not have keyboard and mouse legacy support. We assume that we are | |
178 | * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined. | |
179 | */ | |
180 | ||
181 | /* | |
182 | * Make sure the controller is completely inactive, unable to | |
183 | * generate interrupts or do DMA. | |
184 | */ | |
185 | static void uhci_generic_reset_hc(struct uhci_hcd *uhci) | |
186 | { | |
187 | /* Reset the HC - this will force us to get a | |
188 | * new notification of any already connected | |
189 | * ports due to the virtual disconnect that it | |
190 | * implies. | |
191 | */ | |
192 | uhci_writew(uhci, USBCMD_HCRESET, USBCMD); | |
193 | mb(); | |
194 | udelay(5); | |
195 | if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET) | |
196 | dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n"); | |
197 | ||
198 | /* Just to be safe, disable interrupt requests and | |
199 | * make sure the controller is stopped. | |
200 | */ | |
201 | uhci_writew(uhci, 0, USBINTR); | |
202 | uhci_writew(uhci, 0, USBCMD); | |
203 | } | |
204 | ||
205 | /* | |
206 | * Initialize a controller that was newly discovered or has just been | |
207 | * resumed. In either case we can't be sure of its previous state. | |
208 | * | |
209 | * Returns: 1 if the controller was reset, 0 otherwise. | |
210 | */ | |
211 | static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci) | |
212 | { | |
213 | unsigned int cmd, intr; | |
214 | ||
215 | /* | |
216 | * When restarting a suspended controller, we expect all the | |
217 | * settings to be the same as we left them: | |
218 | * | |
219 | * Controller is stopped and configured with EGSM set; | |
220 | * No interrupts enabled except possibly Resume Detect. | |
221 | * | |
222 | * If any of these conditions are violated we do a complete reset. | |
223 | */ | |
224 | ||
225 | cmd = uhci_readw(uhci, USBCMD); | |
226 | if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) { | |
227 | dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n", | |
228 | __func__, cmd); | |
229 | goto reset_needed; | |
230 | } | |
231 | ||
232 | intr = uhci_readw(uhci, USBINTR); | |
233 | if (intr & (~USBINTR_RESUME)) { | |
234 | dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n", | |
235 | __func__, intr); | |
236 | goto reset_needed; | |
237 | } | |
238 | return 0; | |
239 | ||
240 | reset_needed: | |
241 | dev_dbg(uhci_dev(uhci), "Performing full reset\n"); | |
242 | uhci_generic_reset_hc(uhci); | |
243 | return 1; | |
244 | } | |
245 | #endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */ | |
246 | ||
a8bed8b6 AS |
247 | /* |
248 | * Store the basic register settings needed by the controller. | |
249 | */ | |
250 | static void configure_hc(struct uhci_hcd *uhci) | |
251 | { | |
252 | /* Set the frame length to the default: 1 ms exactly */ | |
9faa091a | 253 | uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF); |
a8bed8b6 AS |
254 | |
255 | /* Store the frame list base address */ | |
9faa091a | 256 | uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD); |
a8bed8b6 AS |
257 | |
258 | /* Set the current frame number */ | |
9faa091a JA |
259 | uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER, |
260 | USBFRNUM); | |
0d436b42 | 261 | |
e7652e1e JA |
262 | /* perform any arch/bus specific configuration */ |
263 | if (uhci->configure_hc) | |
264 | uhci->configure_hc(uhci); | |
a8bed8b6 AS |
265 | } |
266 | ||
c8f4fe43 | 267 | static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci) |
1da177e4 | 268 | { |
4642d34a BH |
269 | /* |
270 | * If we have to ignore overcurrent events then almost by definition | |
271 | * we can't depend on resume-detect interrupts. | |
272 | * | |
273 | * Those interrupts also don't seem to work on ASpeed SoCs. | |
274 | */ | |
275 | if (ignore_oc || uhci_is_aspeed(uhci)) | |
5f8364b7 AS |
276 | return 1; |
277 | ||
e7652e1e JA |
278 | return uhci->resume_detect_interrupts_are_broken ? |
279 | uhci->resume_detect_interrupts_are_broken(uhci) : 0; | |
c8f4fe43 AS |
280 | } |
281 | ||
d8f12ab5 | 282 | static int global_suspend_mode_is_broken(struct uhci_hcd *uhci) |
b62df451 | 283 | { |
e7652e1e JA |
284 | return uhci->global_suspend_mode_is_broken ? |
285 | uhci->global_suspend_mode_is_broken(uhci) : 0; | |
b62df451 AS |
286 | } |
287 | ||
a8bed8b6 | 288 | static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state) |
c8f4fe43 AS |
289 | __releases(uhci->lock) |
290 | __acquires(uhci->lock) | |
291 | { | |
292 | int auto_stop; | |
d8f12ab5 | 293 | int int_enable, egsm_enable, wakeup_enable; |
58a97ffe | 294 | struct usb_device *rhdev = uhci_to_hcd(uhci)->self.root_hub; |
c8f4fe43 AS |
295 | |
296 | auto_stop = (new_state == UHCI_RH_AUTO_STOPPED); | |
58a97ffe | 297 | dev_dbg(&rhdev->dev, "%s%s\n", __func__, |
c8f4fe43 AS |
298 | (auto_stop ? " (auto-stop)" : "")); |
299 | ||
d8f12ab5 AS |
300 | /* Start off by assuming Resume-Detect interrupts and EGSM work |
301 | * and that remote wakeups should be enabled. | |
c8f4fe43 | 302 | */ |
b62df451 | 303 | egsm_enable = USBCMD_EGSM; |
1f09df8b | 304 | int_enable = USBINTR_RESUME; |
d8f12ab5 AS |
305 | wakeup_enable = 1; |
306 | ||
5c12e785 AS |
307 | /* |
308 | * In auto-stop mode, we must be able to detect new connections. | |
309 | * The user can force us to poll by disabling remote wakeup; | |
310 | * otherwise we will use the EGSM/RD mechanism. | |
d8f12ab5 AS |
311 | */ |
312 | if (auto_stop) { | |
313 | if (!device_may_wakeup(&rhdev->dev)) | |
5c12e785 AS |
314 | egsm_enable = int_enable = 0; |
315 | } | |
d8f12ab5 | 316 | |
58a97ffe | 317 | #ifdef CONFIG_PM |
5c12e785 AS |
318 | /* |
319 | * In bus-suspend mode, we use the wakeup setting specified | |
320 | * for the root hub. | |
321 | */ | |
322 | else { | |
d8f12ab5 AS |
323 | if (!rhdev->do_remote_wakeup) |
324 | wakeup_enable = 0; | |
d8f12ab5 | 325 | } |
5c12e785 | 326 | #endif |
d8f12ab5 | 327 | |
5c12e785 AS |
328 | /* |
329 | * UHCI doesn't distinguish between wakeup requests from downstream | |
330 | * devices and local connect/disconnect events. There's no way to | |
331 | * enable one without the other; both are controlled by EGSM. Thus | |
332 | * if wakeups are disallowed then EGSM must be turned off -- in which | |
333 | * case remote wakeup requests from downstream during system sleep | |
334 | * will be lost. | |
335 | * | |
336 | * In addition, if EGSM is broken then we can't use it. Likewise, | |
337 | * if Resume-Detect interrupts are broken then we can't use them. | |
d8f12ab5 | 338 | * |
5c12e785 AS |
339 | * Finally, neither EGSM nor RD is useful by itself. Without EGSM, |
340 | * the RD status bit will never get set. Without RD, the controller | |
341 | * won't generate interrupts to tell the system about wakeup events. | |
d8f12ab5 | 342 | */ |
5c12e785 AS |
343 | if (!wakeup_enable || global_suspend_mode_is_broken(uhci) || |
344 | resume_detect_interrupts_are_broken(uhci)) | |
345 | egsm_enable = int_enable = 0; | |
b62df451 | 346 | |
5c12e785 | 347 | uhci->RD_enable = !!int_enable; |
9faa091a JA |
348 | uhci_writew(uhci, int_enable, USBINTR); |
349 | uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD); | |
a8bed8b6 | 350 | mb(); |
c8f4fe43 AS |
351 | udelay(5); |
352 | ||
353 | /* If we're auto-stopping then no devices have been attached | |
354 | * for a while, so there shouldn't be any active URBs and the | |
355 | * controller should stop after a few microseconds. Otherwise | |
356 | * we will give the controller one frame to stop. | |
357 | */ | |
9faa091a | 358 | if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) { |
c8f4fe43 AS |
359 | uhci->rh_state = UHCI_RH_SUSPENDING; |
360 | spin_unlock_irq(&uhci->lock); | |
361 | msleep(1); | |
362 | spin_lock_irq(&uhci->lock); | |
e323de46 | 363 | if (uhci->dead) |
4daaa87c | 364 | return; |
c8f4fe43 | 365 | } |
9faa091a | 366 | if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) |
58a97ffe | 367 | dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n"); |
1da177e4 | 368 | |
1da177e4 | 369 | uhci_get_current_frame_number(uhci); |
c8f4fe43 AS |
370 | |
371 | uhci->rh_state = new_state; | |
1da177e4 | 372 | uhci->is_stopped = UHCI_IS_STOPPED; |
d8f12ab5 | 373 | |
5c12e785 AS |
374 | /* |
375 | * If remote wakeup is enabled but either EGSM or RD interrupts | |
376 | * doesn't work, then we won't get an interrupt when a wakeup event | |
377 | * occurs. Thus the suspended root hub needs to be polled. | |
d8f12ab5 | 378 | */ |
5c12e785 | 379 | if (wakeup_enable && (!int_enable || !egsm_enable)) |
541c7d43 AS |
380 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
381 | else | |
382 | clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); | |
1da177e4 | 383 | |
7d12e780 | 384 | uhci_scan_schedule(uhci); |
84afddd7 | 385 | uhci_fsbr_off(uhci); |
1da177e4 LT |
386 | } |
387 | ||
a8bed8b6 AS |
388 | static void start_rh(struct uhci_hcd *uhci) |
389 | { | |
a8bed8b6 | 390 | uhci->is_stopped = 0; |
a8bed8b6 | 391 | |
4642d34a BH |
392 | /* |
393 | * Clear stale status bits on Aspeed as we get a stale HCH | |
394 | * which causes problems later on | |
395 | */ | |
396 | if (uhci_is_aspeed(uhci)) | |
397 | uhci_writew(uhci, uhci_readw(uhci, USBSTS), USBSTS); | |
398 | ||
a8bed8b6 AS |
399 | /* Mark it configured and running with a 64-byte max packet. |
400 | * All interrupts are enabled, even though RESUME won't do anything. | |
401 | */ | |
9faa091a JA |
402 | uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD); |
403 | uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME | | |
404 | USBINTR_IOC | USBINTR_SP, USBINTR); | |
a8bed8b6 | 405 | mb(); |
6c1b445c | 406 | uhci->rh_state = UHCI_RH_RUNNING; |
541c7d43 | 407 | set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags); |
a8bed8b6 AS |
408 | } |
409 | ||
410 | static void wakeup_rh(struct uhci_hcd *uhci) | |
c8f4fe43 AS |
411 | __releases(uhci->lock) |
412 | __acquires(uhci->lock) | |
1da177e4 | 413 | { |
be3cbc5f | 414 | dev_dbg(&uhci_to_hcd(uhci)->self.root_hub->dev, |
441b62c1 | 415 | "%s%s\n", __func__, |
c8f4fe43 AS |
416 | uhci->rh_state == UHCI_RH_AUTO_STOPPED ? |
417 | " (auto-start)" : ""); | |
1da177e4 | 418 | |
c8f4fe43 AS |
419 | /* If we are auto-stopped then no devices are attached so there's |
420 | * no need for wakeup signals. Otherwise we send Global Resume | |
421 | * for 20 ms. | |
422 | */ | |
423 | if (uhci->rh_state == UHCI_RH_SUSPENDED) { | |
d8f12ab5 AS |
424 | unsigned egsm; |
425 | ||
426 | /* Keep EGSM on if it was set before */ | |
9faa091a | 427 | egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM; |
c8f4fe43 | 428 | uhci->rh_state = UHCI_RH_RESUMING; |
9faa091a | 429 | uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD); |
c8f4fe43 AS |
430 | spin_unlock_irq(&uhci->lock); |
431 | msleep(20); | |
432 | spin_lock_irq(&uhci->lock); | |
e323de46 | 433 | if (uhci->dead) |
4daaa87c | 434 | return; |
1da177e4 | 435 | |
c8f4fe43 | 436 | /* End Global Resume and wait for EOP to be sent */ |
9faa091a | 437 | uhci_writew(uhci, USBCMD_CF, USBCMD); |
a8bed8b6 | 438 | mb(); |
c8f4fe43 | 439 | udelay(4); |
9faa091a | 440 | if (uhci_readw(uhci, USBCMD) & USBCMD_FGR) |
c8f4fe43 AS |
441 | dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n"); |
442 | } | |
1da177e4 | 443 | |
a8bed8b6 | 444 | start_rh(uhci); |
c8f4fe43 | 445 | |
6c1b445c AS |
446 | /* Restart root hub polling */ |
447 | mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies); | |
1da177e4 LT |
448 | } |
449 | ||
7d12e780 | 450 | static irqreturn_t uhci_irq(struct usb_hcd *hcd) |
014e73c9 AS |
451 | { |
452 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
014e73c9 | 453 | unsigned short status; |
1da177e4 LT |
454 | |
455 | /* | |
014e73c9 AS |
456 | * Read the interrupt status, and write it back to clear the |
457 | * interrupt cause. Contrary to the UHCI specification, the | |
458 | * "HC Halted" status bit is persistent: it is RO, not R/WC. | |
1da177e4 | 459 | */ |
9faa091a | 460 | status = uhci_readw(uhci, USBSTS); |
014e73c9 AS |
461 | if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */ |
462 | return IRQ_NONE; | |
9faa091a | 463 | uhci_writew(uhci, status, USBSTS); /* Clear it */ |
014e73c9 | 464 | |
0f815a0a AS |
465 | spin_lock(&uhci->lock); |
466 | if (unlikely(!uhci->is_initialized)) /* not yet configured */ | |
467 | goto done; | |
468 | ||
014e73c9 AS |
469 | if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) { |
470 | if (status & USBSTS_HSE) | |
3171fcab CG |
471 | dev_err(uhci_dev(uhci), |
472 | "host system error, PCI problems?\n"); | |
014e73c9 | 473 | if (status & USBSTS_HCPE) |
3171fcab CG |
474 | dev_err(uhci_dev(uhci), |
475 | "host controller process error, something bad happened!\n"); | |
4daaa87c | 476 | if (status & USBSTS_HCH) { |
4daaa87c AS |
477 | if (uhci->rh_state >= UHCI_RH_RUNNING) { |
478 | dev_err(uhci_dev(uhci), | |
3171fcab | 479 | "host controller halted, very bad!\n"); |
8d402e1a AS |
480 | if (debug > 1 && errbuf) { |
481 | /* Print the schedule for debugging */ | |
13996ca7 CG |
482 | uhci_sprint_schedule(uhci, errbuf, |
483 | ERRBUF_LEN - EXTRA_SPACE); | |
8d402e1a AS |
484 | lprintk(errbuf); |
485 | } | |
e323de46 | 486 | uhci_hc_died(uhci); |
7d670a2e | 487 | usb_hc_died(hcd); |
1f09df8b AS |
488 | |
489 | /* Force a callback in case there are | |
490 | * pending unlinks */ | |
491 | mod_timer(&hcd->rh_timer, jiffies); | |
4daaa87c | 492 | } |
1da177e4 | 493 | } |
1da177e4 LT |
494 | } |
495 | ||
0f815a0a AS |
496 | if (status & USBSTS_RD) { |
497 | spin_unlock(&uhci->lock); | |
6c1b445c | 498 | usb_hcd_poll_rh_status(hcd); |
0f815a0a | 499 | } else { |
7d12e780 | 500 | uhci_scan_schedule(uhci); |
0f815a0a | 501 | done: |
442258e2 | 502 | spin_unlock(&uhci->lock); |
1f09df8b | 503 | } |
1da177e4 | 504 | |
014e73c9 AS |
505 | return IRQ_HANDLED; |
506 | } | |
1da177e4 | 507 | |
014e73c9 AS |
508 | /* |
509 | * Store the current frame number in uhci->frame_number if the controller | |
06125beb | 510 | * is running. Expand from 11 bits (of which we use only 10) to a |
c4334726 AS |
511 | * full-sized integer. |
512 | * | |
513 | * Like many other parts of the driver, this code relies on being polled | |
514 | * more than once per second as long as the controller is running. | |
014e73c9 AS |
515 | */ |
516 | static void uhci_get_current_frame_number(struct uhci_hcd *uhci) | |
517 | { | |
c4334726 AS |
518 | if (!uhci->is_stopped) { |
519 | unsigned delta; | |
520 | ||
9faa091a | 521 | delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) & |
c4334726 AS |
522 | (UHCI_NUMFRAMES - 1); |
523 | uhci->frame_number += delta; | |
524 | } | |
1da177e4 LT |
525 | } |
526 | ||
527 | /* | |
528 | * De-allocate all resources | |
529 | */ | |
530 | static void release_uhci(struct uhci_hcd *uhci) | |
531 | { | |
532 | int i; | |
533 | ||
8d402e1a | 534 | |
cadb3756 ON |
535 | spin_lock_irq(&uhci->lock); |
536 | uhci->is_initialized = 0; | |
537 | spin_unlock_irq(&uhci->lock); | |
538 | ||
539 | debugfs_remove(uhci->dentry); | |
8d402e1a | 540 | |
1da177e4 | 541 | for (i = 0; i < UHCI_NUM_SKELQH; i++) |
8b4cd421 | 542 | uhci_free_qh(uhci, uhci->skelqh[i]); |
1da177e4 | 543 | |
8b4cd421 | 544 | uhci_free_td(uhci, uhci->term_td); |
1da177e4 | 545 | |
8b4cd421 | 546 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 | 547 | |
8b4cd421 | 548 | dma_pool_destroy(uhci->td_pool); |
1da177e4 | 549 | |
a1d59ce8 AS |
550 | kfree(uhci->frame_cpu); |
551 | ||
552 | dma_free_coherent(uhci_dev(uhci), | |
553 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
554 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 LT |
555 | } |
556 | ||
1da177e4 LT |
557 | /* |
558 | * Allocate a frame list, and then setup the skeleton | |
559 | * | |
560 | * The hardware doesn't really know any difference | |
561 | * in the queues, but the order does matter for the | |
17230acd AS |
562 | * protocols higher up. The order in which the queues |
563 | * are encountered by the hardware is: | |
1da177e4 | 564 | * |
17230acd | 565 | * - All isochronous events are handled before any |
1da177e4 LT |
566 | * of the queues. We don't do that here, because |
567 | * we'll create the actual TD entries on demand. | |
17230acd AS |
568 | * - The first queue is the high-period interrupt queue. |
569 | * - The second queue is the period-1 interrupt and async | |
570 | * (low-speed control, full-speed control, then bulk) queue. | |
571 | * - The third queue is the terminating bandwidth reclamation queue, | |
572 | * which contains no members, loops back to itself, and is present | |
573 | * only when FSBR is on and there are no full-speed control or bulk QHs. | |
1da177e4 LT |
574 | */ |
575 | static int uhci_start(struct usb_hcd *hcd) | |
576 | { | |
577 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
578 | int retval = -EBUSY; | |
c074b416 | 579 | int i; |
b409214c | 580 | struct dentry __maybe_unused *dentry; |
1da177e4 | 581 | |
6c1b445c | 582 | hcd->uses_new_polling = 1; |
2851784f SAS |
583 | /* Accept arbitrarily long scatter-gather lists */ |
584 | if (!(hcd->driver->flags & HCD_LOCAL_MEM)) | |
585 | hcd->self.sg_tablesize = ~0; | |
1da177e4 | 586 | |
1da177e4 | 587 | spin_lock_init(&uhci->lock); |
e99e88a9 | 588 | timer_setup(&uhci->fsbr_timer, uhci_fsbr_timeout, 0); |
dccf4a48 | 589 | INIT_LIST_HEAD(&uhci->idle_qh_list); |
1da177e4 LT |
590 | init_waitqueue_head(&uhci->waitqh); |
591 | ||
b409214c AS |
592 | #ifdef UHCI_DEBUG_OPS |
593 | dentry = debugfs_create_file(hcd->self.bus_name, | |
594 | S_IFREG|S_IRUGO|S_IWUSR, uhci_debugfs_root, | |
595 | uhci, &uhci_debug_operations); | |
596 | if (!dentry) { | |
597 | dev_err(uhci_dev(uhci), "couldn't create uhci debugfs entry\n"); | |
598 | return -ENOMEM; | |
8d402e1a | 599 | } |
b409214c AS |
600 | uhci->dentry = dentry; |
601 | #endif | |
8d402e1a | 602 | |
a1d59ce8 AS |
603 | uhci->frame = dma_alloc_coherent(uhci_dev(uhci), |
604 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
f589b3e0 | 605 | &uhci->frame_dma_handle, GFP_KERNEL); |
a1d59ce8 | 606 | if (!uhci->frame) { |
3171fcab CG |
607 | dev_err(uhci_dev(uhci), |
608 | "unable to allocate consistent memory for frame list\n"); | |
a1d59ce8 | 609 | goto err_alloc_frame; |
1da177e4 | 610 | } |
a1d59ce8 | 611 | memset(uhci->frame, 0, UHCI_NUMFRAMES * sizeof(*uhci->frame)); |
1da177e4 | 612 | |
a1d59ce8 AS |
613 | uhci->frame_cpu = kcalloc(UHCI_NUMFRAMES, sizeof(*uhci->frame_cpu), |
614 | GFP_KERNEL); | |
314e6725 | 615 | if (!uhci->frame_cpu) |
a1d59ce8 | 616 | goto err_alloc_frame_cpu; |
1da177e4 LT |
617 | |
618 | uhci->td_pool = dma_pool_create("uhci_td", uhci_dev(uhci), | |
619 | sizeof(struct uhci_td), 16, 0); | |
620 | if (!uhci->td_pool) { | |
621 | dev_err(uhci_dev(uhci), "unable to create td dma_pool\n"); | |
622 | goto err_create_td_pool; | |
623 | } | |
624 | ||
625 | uhci->qh_pool = dma_pool_create("uhci_qh", uhci_dev(uhci), | |
626 | sizeof(struct uhci_qh), 16, 0); | |
627 | if (!uhci->qh_pool) { | |
628 | dev_err(uhci_dev(uhci), "unable to create qh dma_pool\n"); | |
629 | goto err_create_qh_pool; | |
630 | } | |
631 | ||
2532178a | 632 | uhci->term_td = uhci_alloc_td(uhci); |
1da177e4 LT |
633 | if (!uhci->term_td) { |
634 | dev_err(uhci_dev(uhci), "unable to allocate terminating TD\n"); | |
635 | goto err_alloc_term_td; | |
636 | } | |
637 | ||
638 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { | |
dccf4a48 | 639 | uhci->skelqh[i] = uhci_alloc_qh(uhci, NULL, NULL); |
1da177e4 LT |
640 | if (!uhci->skelqh[i]) { |
641 | dev_err(uhci_dev(uhci), "unable to allocate QH\n"); | |
642 | goto err_alloc_skelqh; | |
643 | } | |
644 | } | |
645 | ||
646 | /* | |
17230acd | 647 | * 8 Interrupt queues; link all higher int queues to int1 = async |
1da177e4 | 648 | */ |
17230acd | 649 | for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i) |
51e2f62f JA |
650 | uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh); |
651 | uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci); | |
652 | uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh); | |
1da177e4 LT |
653 | |
654 | /* This dummy TD is to work around a bug in Intel PIIX controllers */ | |
51e2f62f | 655 | uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) | |
17230acd | 656 | (0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0); |
51e2f62f | 657 | uhci->term_td->link = UHCI_PTR_TERM(uhci); |
17230acd | 658 | uhci->skel_async_qh->element = uhci->skel_term_qh->element = |
51e2f62f | 659 | LINK_TO_TD(uhci, uhci->term_td); |
1da177e4 LT |
660 | |
661 | /* | |
662 | * Fill the frame list: make all entries point to the proper | |
663 | * interrupt queue. | |
1da177e4 LT |
664 | */ |
665 | for (i = 0; i < UHCI_NUMFRAMES; i++) { | |
1da177e4 LT |
666 | |
667 | /* Only place we don't use the frame list routines */ | |
f3fe239b | 668 | uhci->frame[i] = uhci_frame_skel_link(uhci, i); |
1da177e4 LT |
669 | } |
670 | ||
671 | /* | |
672 | * Some architectures require a full mb() to enforce completion of | |
a8bed8b6 | 673 | * the memory writes above before the I/O transfers in configure_hc(). |
1da177e4 LT |
674 | */ |
675 | mb(); | |
a8bed8b6 | 676 | |
0f815a0a | 677 | spin_lock_irq(&uhci->lock); |
a8bed8b6 | 678 | configure_hc(uhci); |
8d402e1a | 679 | uhci->is_initialized = 1; |
a8bed8b6 | 680 | start_rh(uhci); |
ba297edd | 681 | spin_unlock_irq(&uhci->lock); |
1da177e4 LT |
682 | return 0; |
683 | ||
684 | /* | |
685 | * error exits: | |
686 | */ | |
1da177e4 | 687 | err_alloc_skelqh: |
8b4cd421 AS |
688 | for (i = 0; i < UHCI_NUM_SKELQH; i++) { |
689 | if (uhci->skelqh[i]) | |
1da177e4 | 690 | uhci_free_qh(uhci, uhci->skelqh[i]); |
8b4cd421 | 691 | } |
1da177e4 LT |
692 | |
693 | uhci_free_td(uhci, uhci->term_td); | |
1da177e4 LT |
694 | |
695 | err_alloc_term_td: | |
1da177e4 | 696 | dma_pool_destroy(uhci->qh_pool); |
1da177e4 LT |
697 | |
698 | err_create_qh_pool: | |
699 | dma_pool_destroy(uhci->td_pool); | |
1da177e4 LT |
700 | |
701 | err_create_td_pool: | |
a1d59ce8 AS |
702 | kfree(uhci->frame_cpu); |
703 | ||
704 | err_alloc_frame_cpu: | |
705 | dma_free_coherent(uhci_dev(uhci), | |
706 | UHCI_NUMFRAMES * sizeof(*uhci->frame), | |
707 | uhci->frame, uhci->frame_dma_handle); | |
1da177e4 | 708 | |
a1d59ce8 | 709 | err_alloc_frame: |
1da177e4 | 710 | debugfs_remove(uhci->dentry); |
1da177e4 | 711 | |
1da177e4 LT |
712 | return retval; |
713 | } | |
714 | ||
715 | static void uhci_stop(struct usb_hcd *hcd) | |
716 | { | |
717 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
718 | ||
1da177e4 | 719 | spin_lock_irq(&uhci->lock); |
541c7d43 | 720 | if (HCD_HW_ACCESSIBLE(hcd) && !uhci->dead) |
e323de46 | 721 | uhci_hc_died(uhci); |
7d12e780 | 722 | uhci_scan_schedule(uhci); |
1da177e4 | 723 | spin_unlock_irq(&uhci->lock); |
d23356da | 724 | synchronize_irq(hcd->irq); |
6c1b445c | 725 | |
c5e3b741 | 726 | del_timer_sync(&uhci->fsbr_timer); |
1da177e4 LT |
727 | release_uhci(uhci); |
728 | } | |
729 | ||
730 | #ifdef CONFIG_PM | |
a8bed8b6 AS |
731 | static int uhci_rh_suspend(struct usb_hcd *hcd) |
732 | { | |
733 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
be3cbc5f | 734 | int rc = 0; |
a8bed8b6 AS |
735 | |
736 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 737 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 738 | rc = -ESHUTDOWN; |
cec3a53c AS |
739 | else if (uhci->dead) |
740 | ; /* Dead controllers tell no tales */ | |
741 | ||
742 | /* Once the controller is stopped, port resumes that are already | |
743 | * in progress won't complete. Hence if remote wakeup is enabled | |
744 | * for the root hub and any ports are in the middle of a resume or | |
745 | * remote wakeup, we must fail the suspend. | |
746 | */ | |
747 | else if (hcd->self.root_hub->do_remote_wakeup && | |
748 | uhci->resuming_ports) { | |
3171fcab CG |
749 | dev_dbg(uhci_dev(uhci), |
750 | "suspend failed because a port is resuming\n"); | |
cec3a53c AS |
751 | rc = -EBUSY; |
752 | } else | |
4daaa87c | 753 | suspend_rh(uhci, UHCI_RH_SUSPENDED); |
a8bed8b6 | 754 | spin_unlock_irq(&uhci->lock); |
be3cbc5f | 755 | return rc; |
a8bed8b6 AS |
756 | } |
757 | ||
758 | static int uhci_rh_resume(struct usb_hcd *hcd) | |
759 | { | |
760 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
4daaa87c | 761 | int rc = 0; |
a8bed8b6 AS |
762 | |
763 | spin_lock_irq(&uhci->lock); | |
541c7d43 | 764 | if (!HCD_HW_ACCESSIBLE(hcd)) |
be3cbc5f | 765 | rc = -ESHUTDOWN; |
cfa59dab | 766 | else if (!uhci->dead) |
4daaa87c | 767 | wakeup_rh(uhci); |
a8bed8b6 | 768 | spin_unlock_irq(&uhci->lock); |
4daaa87c | 769 | return rc; |
a8bed8b6 AS |
770 | } |
771 | ||
1da177e4 LT |
772 | #endif |
773 | ||
dccf4a48 | 774 | /* Wait until a particular device/endpoint's QH is idle, and free it */ |
1da177e4 | 775 | static void uhci_hcd_endpoint_disable(struct usb_hcd *hcd, |
dccf4a48 | 776 | struct usb_host_endpoint *hep) |
1da177e4 LT |
777 | { |
778 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
dccf4a48 AS |
779 | struct uhci_qh *qh; |
780 | ||
781 | spin_lock_irq(&uhci->lock); | |
782 | qh = (struct uhci_qh *) hep->hcpriv; | |
783 | if (qh == NULL) | |
784 | goto done; | |
1da177e4 | 785 | |
dccf4a48 AS |
786 | while (qh->state != QH_STATE_IDLE) { |
787 | ++uhci->num_waiting; | |
788 | spin_unlock_irq(&uhci->lock); | |
789 | wait_event_interruptible(uhci->waitqh, | |
790 | qh->state == QH_STATE_IDLE); | |
791 | spin_lock_irq(&uhci->lock); | |
792 | --uhci->num_waiting; | |
793 | } | |
794 | ||
795 | uhci_free_qh(uhci, qh); | |
796 | done: | |
797 | spin_unlock_irq(&uhci->lock); | |
1da177e4 LT |
798 | } |
799 | ||
800 | static int uhci_hcd_get_frame_number(struct usb_hcd *hcd) | |
801 | { | |
802 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
c4334726 AS |
803 | unsigned frame_number; |
804 | unsigned delta; | |
1da177e4 LT |
805 | |
806 | /* Minimize latency by avoiding the spinlock */ | |
c4334726 AS |
807 | frame_number = uhci->frame_number; |
808 | barrier(); | |
9faa091a | 809 | delta = (uhci_readw(uhci, USBFRNUM) - frame_number) & |
c4334726 AS |
810 | (UHCI_NUMFRAMES - 1); |
811 | return frame_number + delta; | |
1da177e4 LT |
812 | } |
813 | ||
c31a65f8 JA |
814 | /* Determines number of ports on controller */ |
815 | static int uhci_count_ports(struct usb_hcd *hcd) | |
816 | { | |
817 | struct uhci_hcd *uhci = hcd_to_uhci(hcd); | |
818 | unsigned io_size = (unsigned) hcd->rsrc_len; | |
819 | int port; | |
1da177e4 | 820 | |
c31a65f8 JA |
821 | /* The UHCI spec says devices must have 2 ports, and goes on to say |
822 | * they may have more but gives no way to determine how many there | |
823 | * are. However according to the UHCI spec, Bit 7 of the port | |
824 | * status and control register is always set to 1. So we try to | |
825 | * use this to our advantage. Another common failure mode when | |
826 | * a nonexistent register is addressed is to return all ones, so | |
827 | * we test for that also. | |
828 | */ | |
829 | for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) { | |
830 | unsigned int portstatus; | |
1da177e4 | 831 | |
9faa091a | 832 | portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2)); |
c31a65f8 JA |
833 | if (!(portstatus & 0x0080) || portstatus == 0xffff) |
834 | break; | |
835 | } | |
836 | if (debug) | |
837 | dev_info(uhci_dev(uhci), "detected %d ports\n", port); | |
1da177e4 | 838 | |
c31a65f8 JA |
839 | /* Anything greater than 7 is weird so we'll ignore it. */ |
840 | if (port > UHCI_RH_MAXCHILD) { | |
3171fcab CG |
841 | dev_info(uhci_dev(uhci), |
842 | "port count misdetected? forcing to 2 ports\n"); | |
c31a65f8 JA |
843 | port = 2; |
844 | } | |
1da177e4 | 845 | |
c31a65f8 JA |
846 | return port; |
847 | } | |
1da177e4 | 848 | |
c31a65f8 | 849 | static const char hcd_name[] = "uhci_hcd"; |
1da177e4 | 850 | |
2c93e790 | 851 | #ifdef CONFIG_USB_PCI |
c31a65f8 | 852 | #include "uhci-pci.c" |
3db7739c JA |
853 | #define PCI_DRIVER uhci_pci_driver |
854 | #endif | |
1da177e4 | 855 | |
3db7739c JA |
856 | #ifdef CONFIG_SPARC_LEON |
857 | #include "uhci-grlib.c" | |
858 | #define PLATFORM_DRIVER uhci_grlib_driver | |
859 | #endif | |
1da177e4 | 860 | |
100d4597 TP |
861 | #ifdef CONFIG_USB_UHCI_PLATFORM |
862 | #include "uhci-platform.c" | |
863 | #define PLATFORM_DRIVER uhci_platform_driver | |
864 | #endif | |
865 | ||
3db7739c JA |
866 | #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) |
867 | #error "missing bus glue for uhci-hcd" | |
abb30641 | 868 | #endif |
1da177e4 | 869 | |
1da177e4 LT |
870 | static int __init uhci_hcd_init(void) |
871 | { | |
872 | int retval = -ENOMEM; | |
873 | ||
1da177e4 LT |
874 | if (usb_disabled()) |
875 | return -ENODEV; | |
876 | ||
2b70f073 AS |
877 | printk(KERN_INFO "uhci_hcd: " DRIVER_DESC "%s\n", |
878 | ignore_oc ? ", overcurrent ignored" : ""); | |
9beeee65 | 879 | set_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
2b70f073 | 880 | |
1c20163d | 881 | #ifdef CONFIG_DYNAMIC_DEBUG |
cadb3756 ON |
882 | errbuf = kmalloc(ERRBUF_LEN, GFP_KERNEL); |
883 | if (!errbuf) | |
884 | goto errbuf_failed; | |
885 | uhci_debugfs_root = debugfs_create_dir("uhci", usb_debug_root); | |
886 | if (!uhci_debugfs_root) | |
887 | goto debug_failed; | |
888 | #endif | |
1da177e4 | 889 | |
1da177e4 | 890 | uhci_up_cachep = kmem_cache_create("uhci_urb_priv", |
20c2df83 | 891 | sizeof(struct urb_priv), 0, 0, NULL); |
1da177e4 LT |
892 | if (!uhci_up_cachep) |
893 | goto up_failed; | |
894 | ||
3db7739c JA |
895 | #ifdef PLATFORM_DRIVER |
896 | retval = platform_driver_register(&PLATFORM_DRIVER); | |
897 | if (retval < 0) | |
898 | goto clean0; | |
899 | #endif | |
900 | ||
901 | #ifdef PCI_DRIVER | |
902 | retval = pci_register_driver(&PCI_DRIVER); | |
903 | if (retval < 0) | |
904 | goto clean1; | |
905 | #endif | |
1da177e4 LT |
906 | |
907 | return 0; | |
908 | ||
3db7739c JA |
909 | #ifdef PCI_DRIVER |
910 | clean1: | |
911 | #endif | |
912 | #ifdef PLATFORM_DRIVER | |
913 | platform_driver_unregister(&PLATFORM_DRIVER); | |
914 | clean0: | |
915 | #endif | |
1a1d92c1 | 916 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 LT |
917 | |
918 | up_failed: | |
cadb3756 | 919 | #if defined(DEBUG) || defined(CONFIG_DYNAMIC_DEBUG) |
1da177e4 LT |
920 | debugfs_remove(uhci_debugfs_root); |
921 | ||
922 | debug_failed: | |
1bc3c9e1 | 923 | kfree(errbuf); |
1da177e4 LT |
924 | |
925 | errbuf_failed: | |
cadb3756 | 926 | #endif |
1da177e4 | 927 | |
9beeee65 | 928 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
929 | return retval; |
930 | } | |
931 | ||
932 | static void __exit uhci_hcd_cleanup(void) | |
933 | { | |
3db7739c JA |
934 | #ifdef PLATFORM_DRIVER |
935 | platform_driver_unregister(&PLATFORM_DRIVER); | |
936 | #endif | |
937 | #ifdef PCI_DRIVER | |
938 | pci_unregister_driver(&PCI_DRIVER); | |
939 | #endif | |
1a1d92c1 | 940 | kmem_cache_destroy(uhci_up_cachep); |
1da177e4 | 941 | debugfs_remove(uhci_debugfs_root); |
1c20163d | 942 | #ifdef CONFIG_DYNAMIC_DEBUG |
1bc3c9e1 | 943 | kfree(errbuf); |
cadb3756 | 944 | #endif |
9beeee65 | 945 | clear_bit(USB_UHCI_LOADED, &usb_hcds_loaded); |
1da177e4 LT |
946 | } |
947 | ||
948 | module_init(uhci_hcd_init); | |
949 | module_exit(uhci_hcd_cleanup); | |
950 | ||
951 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
952 | MODULE_DESCRIPTION(DRIVER_DESC); | |
953 | MODULE_LICENSE("GPL"); |