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net/mlx5: Fix mlx5_ifc_query_lag_out_bits
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
37e92a9d 150 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
7486216b 151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 241 MLX5_CMD_OP_MAX
e281682b
SM		 242};
243
244struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
19cc7524 248 u8 outer_ip_version[0x1];
e281682b
SM		 249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
a8ade55f 252 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
b4ff3a36 256 u8 reserved_at_b[0x1];
e281682b
SM		 257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
b4ff3a36 271 u8 reserved_at_1a[0x5];
e281682b
SM		 272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
19cc7524 277 u8 inner_ip_version[0x1];
e281682b
SM		 278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
b4ff3a36 281 u8 reserved_at_27[0x1];
e281682b
SM		 282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
b4ff3a36 285 u8 reserved_at_2b[0x1];
e281682b
SM		 286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
b4ff3a36 297 u8 reserved_at_37[0x9];
a550ddfc
YH		 298 u8 reserved_at_40[0x1a];
299 u8 bth_dst_qp[0x1];
e281682b 300
a550ddfc 301 u8 reserved_at_5b[0x25];
e281682b
SM		 302};
303
304struct mlx5_ifc_flow_table_prop_layout_bits {
305 u8 ft_support[0x1];
9dc0b289
AV		 306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
26a81453 308 u8 flow_modify_en[0x1];
2cc43b49 309 u8 modify_root[0x1];
34a40e68
MG		 310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
7adbde20
HHZ		 312 u8 encap[0x1];
313 u8 decap[0x1];
314 u8 reserved_at_9[0x17];
e281682b 315
b4ff3a36 316 u8 reserved_at_20[0x2];
e281682b 317 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
e281682b
SM		 320 u8 max_ft_level[0x8];
321
b4ff3a36 322 u8 reserved_at_40[0x20];
e281682b 323
b4ff3a36 324 u8 reserved_at_60[0x18];
e281682b
SM		 325 u8 log_max_ft_num[0x8];
326
b4ff3a36 327 u8 reserved_at_80[0x18];
e281682b
SM		 328 u8 log_max_destination[0x8];
329
16f1c5bb
RS		 330 u8 log_max_flow_counter[0x8];
331 u8 reserved_at_a8[0x10];
e281682b
SM		 332 u8 log_max_flow[0x8];
333
b4ff3a36 334 u8 reserved_at_c0[0x40];
e281682b
SM		 335
336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
337
338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
339};
340
341struct mlx5_ifc_odp_per_transport_service_cap_bits {
342 u8 send[0x1];
343 u8 receive[0x1];
344 u8 write[0x1];
345 u8 read[0x1];
17d2f88f 346 u8 atomic[0x1];
e281682b 347 u8 srq_receive[0x1];
b4ff3a36 348 u8 reserved_at_6[0x1a];
e281682b
SM		 349};
350
b4d1f032 351struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 352 u8 reserved_at_0[0x60];
b4d1f032
MG		 353
354 u8 ipv4[0x20];
355};
356
357struct mlx5_ifc_ipv6_layout_bits {
358 u8 ipv6[16][0x8];
359};
360
361union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 364 u8 reserved_at_0[0x80];
b4d1f032
MG		 365};
366
e281682b
SM		 367struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
368 u8 smac_47_16[0x20];
369
370 u8 smac_15_0[0x10];
371 u8 ethertype[0x10];
372
373 u8 dmac_47_16[0x20];
374
375 u8 dmac_15_0[0x10];
376 u8 first_prio[0x3];
377 u8 first_cfi[0x1];
378 u8 first_vid[0xc];
379
380 u8 ip_protocol[0x8];
381 u8 ip_dscp[0x6];
382 u8 ip_ecn[0x2];
10543365
MHY		 383 u8 cvlan_tag[0x1];
384 u8 svlan_tag[0x1];
e281682b 385 u8 frag[0x1];
19cc7524 386 u8 ip_version[0x4];
e281682b
SM		 387 u8 tcp_flags[0x9];
388
389 u8 tcp_sport[0x10];
390 u8 tcp_dport[0x10];
391
a8ade55f
OG		 392 u8 reserved_at_c0[0x18];
393 u8 ttl_hoplimit[0x8];
e281682b
SM		 394
395 u8 udp_sport[0x10];
396 u8 udp_dport[0x10];
397
b4d1f032 398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 399
b4d1f032 400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 401};
402
403struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 404 u8 reserved_at_0[0x8];
405 u8 source_sqn[0x18];
e281682b 406
b4ff3a36 407 u8 reserved_at_20[0x10];
e281682b
SM		 408 u8 source_port[0x10];
409
410 u8 outer_second_prio[0x3];
411 u8 outer_second_cfi[0x1];
412 u8 outer_second_vid[0xc];
413 u8 inner_second_prio[0x3];
414 u8 inner_second_cfi[0x1];
415 u8 inner_second_vid[0xc];
416
10543365
MHY		 417 u8 outer_second_cvlan_tag[0x1];
418 u8 inner_second_cvlan_tag[0x1];
419 u8 outer_second_svlan_tag[0x1];
420 u8 inner_second_svlan_tag[0x1];
421 u8 reserved_at_64[0xc];
e281682b
SM		 422 u8 gre_protocol[0x10];
423
424 u8 gre_key_h[0x18];
425 u8 gre_key_l[0x8];
426
427 u8 vxlan_vni[0x18];
b4ff3a36 428 u8 reserved_at_b8[0x8];
e281682b 429
b4ff3a36 430 u8 reserved_at_c0[0x20];
e281682b 431
b4ff3a36 432 u8 reserved_at_e0[0xc];
e281682b
SM		 433 u8 outer_ipv6_flow_label[0x14];
434
b4ff3a36 435 u8 reserved_at_100[0xc];
e281682b
SM		 436 u8 inner_ipv6_flow_label[0x14];
437
a550ddfc
YH		 438 u8 reserved_at_120[0x28];
439 u8 bth_dst_qp[0x18];
440 u8 reserved_at_160[0xa0];
e281682b
SM		 441};
442
443struct mlx5_ifc_cmd_pas_bits {
444 u8 pa_h[0x20];
445
446 u8 pa_l[0x14];
b4ff3a36 447 u8 reserved_at_34[0xc];
e281682b
SM		 448};
449
450struct mlx5_ifc_uint64_bits {
451 u8 hi[0x20];
452
453 u8 lo[0x20];
454};
455
456enum {
457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
459 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
460 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
461 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
462 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
463 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
464 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
465 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
466 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
467};
468
469struct mlx5_ifc_ads_bits {
470 u8 fl[0x1];
471 u8 free_ar[0x1];
b4ff3a36 472 u8 reserved_at_2[0xe];
e281682b
SM		 473 u8 pkey_index[0x10];
474
b4ff3a36 475 u8 reserved_at_20[0x8];
e281682b
SM		 476 u8 grh[0x1];
477 u8 mlid[0x7];
478 u8 rlid[0x10];
479
480 u8 ack_timeout[0x5];
b4ff3a36 481 u8 reserved_at_45[0x3];
e281682b 482 u8 src_addr_index[0x8];
b4ff3a36 483 u8 reserved_at_50[0x4];
e281682b
SM		 484 u8 stat_rate[0x4];
485 u8 hop_limit[0x8];
486
b4ff3a36 487 u8 reserved_at_60[0x4];
e281682b
SM		 488 u8 tclass[0x8];
489 u8 flow_label[0x14];
490
491 u8 rgid_rip[16][0x8];
492
b4ff3a36 493 u8 reserved_at_100[0x4];
e281682b
SM		 494 u8 f_dscp[0x1];
495 u8 f_ecn[0x1];
b4ff3a36 496 u8 reserved_at_106[0x1];
e281682b
SM		 497 u8 f_eth_prio[0x1];
498 u8 ecn[0x2];
499 u8 dscp[0x6];
500 u8 udp_sport[0x10];
501
502 u8 dei_cfi[0x1];
503 u8 eth_prio[0x3];
504 u8 sl[0x4];
505 u8 port[0x8];
506 u8 rmac_47_32[0x10];
507
508 u8 rmac_31_0[0x20];
509};
510
511struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 512 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 513 u8 nic_rx_multi_path_tirs_fts[0x1];
514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
515 u8 reserved_at_3[0x1fd];
e281682b
SM		 516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
518
b4ff3a36 519 u8 reserved_at_400[0x200];
e281682b
SM		 520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
522
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
524
b4ff3a36 525 u8 reserved_at_a00[0x200];
e281682b
SM		 526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
528
b4ff3a36 529 u8 reserved_at_e00[0x7200];
e281682b
SM		 530};
531
495716b1 532struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 533 u8 reserved_at_0[0x200];
495716b1
SM		 534
535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
538
539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
540
b4ff3a36 541 u8 reserved_at_800[0x7800];
495716b1
SM		 542};
543
d6666753
SM		 544struct mlx5_ifc_e_switch_cap_bits {
545 u8 vport_svlan_strip[0x1];
546 u8 vport_cvlan_strip[0x1];
547 u8 vport_svlan_insert[0x1];
548 u8 vport_cvlan_insert_if_not_exist[0x1];
549 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 550 u8 reserved_at_5[0x19];
551 u8 nic_vport_node_guid_modify[0x1];
552 u8 nic_vport_port_guid_modify[0x1];
d6666753 553
7adbde20
HHZ		 554 u8 vxlan_encap_decap[0x1];
555 u8 nvgre_encap_decap[0x1];
556 u8 reserved_at_22[0x9];
557 u8 log_max_encap_headers[0x5];
558 u8 reserved_2b[0x6];
559 u8 max_encap_header_size[0xa];
560
561 u8 reserved_40[0x7c0];
562
d6666753
SM		 563};
564
7486216b
SM		 565struct mlx5_ifc_qos_cap_bits {
566 u8 packet_pacing[0x1];
813f8540 567 u8 esw_scheduling[0x1];
c9497c98
MHY		 568 u8 esw_bw_share[0x1];
569 u8 esw_rate_limit[0x1];
570 u8 reserved_at_4[0x1c];
813f8540
MHY		 571
572 u8 reserved_at_20[0x20];
573
7486216b 574 u8 packet_pacing_max_rate[0x20];
813f8540 575
7486216b 576 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 577
578 u8 reserved_at_80[0x10];
7486216b 579 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 580
581 u8 esw_element_type[0x10];
582 u8 esw_tsar_type[0x10];
583
584 u8 reserved_at_c0[0x10];
585 u8 max_qos_para_vport[0x10];
586
587 u8 max_tsar_bw_share[0x20];
588
589 u8 reserved_at_100[0x700];
7486216b
SM		 590};
591
e281682b
SM		 592struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
593 u8 csum_cap[0x1];
594 u8 vlan_cap[0x1];
595 u8 lro_cap[0x1];
596 u8 lro_psh_flag[0x1];
597 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 598 u8 reserved_at_5[0x2];
599 u8 wqe_vlan_insert[0x1];
66189961 600 u8 self_lb_en_modifiable[0x1];
b4ff3a36 601 u8 reserved_at_9[0x2];
e281682b 602 u8 max_lso_cap[0x5];
c226dc22 603 u8 multi_pkt_send_wqe[0x2];
cff92d7c 604 u8 wqe_inline_mode[0x2];
e281682b 605 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 606 u8 reg_umr_sq[0x1];
607 u8 scatter_fcs[0x1];
050da902 608 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 609 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 610 u8 reserved_at_1c[0x2];
27299841 611 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 612 u8 tunnel_stateless_vxlan[0x1];
613
547eede0
IT		 614 u8 swp[0x1];
615 u8 swp_csum[0x1];
616 u8 swp_lso[0x1];
786fb87b
SM		 617 u8 cqe_checksum_full[0x1];
618 u8 reserved_at_24[0x1a];
4d350f1f
MG		 619 u8 max_geneve_opt_len[0x1];
620 u8 tunnel_stateless_geneve_rx[0x1];
e281682b 621
b4ff3a36 622 u8 reserved_at_40[0x10];
e281682b
SM		 623 u8 lro_min_mss_size[0x10];
624
b4ff3a36 625 u8 reserved_at_60[0x120];
e281682b
SM		 626
627 u8 lro_timer_supported_periods[4][0x20];
628
b4ff3a36 629 u8 reserved_at_200[0x600];
e281682b
SM		 630};
631
632struct mlx5_ifc_roce_cap_bits {
633 u8 roce_apm[0x1];
b4ff3a36 634 u8 reserved_at_1[0x1f];
e281682b 635
b4ff3a36 636 u8 reserved_at_20[0x60];
e281682b 637
b4ff3a36 638 u8 reserved_at_80[0xc];
e281682b 639 u8 l3_type[0x4];
b4ff3a36 640 u8 reserved_at_90[0x8];
e281682b
SM		 641 u8 roce_version[0x8];
642
b4ff3a36 643 u8 reserved_at_a0[0x10];
e281682b
SM		 644 u8 r_roce_dest_udp_port[0x10];
645
646 u8 r_roce_max_src_udp_port[0x10];
647 u8 r_roce_min_src_udp_port[0x10];
648
b4ff3a36 649 u8 reserved_at_e0[0x10];
e281682b
SM		 650 u8 roce_address_table_size[0x10];
651
b4ff3a36 652 u8 reserved_at_100[0x700];
e281682b
SM		 653};
654
655enum {
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
664 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
665};
666
667enum {
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
676 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
677};
678
679struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 680 u8 reserved_at_0[0x40];
e281682b 681
bd10838a 682 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 683 u8 reserved_at_42[0x4];
bd10838a 684 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 685
b4ff3a36 686 u8 reserved_at_47[0x19];
e281682b 687
b4ff3a36 688 u8 reserved_at_60[0x20];
e281682b 689
b4ff3a36 690 u8 reserved_at_80[0x10];
f91e6d89 691 u8 atomic_operations[0x10];
e281682b 692
b4ff3a36 693 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 694 u8 atomic_size_qp[0x10];
695
b4ff3a36 696 u8 reserved_at_c0[0x10];
e281682b
SM		 697 u8 atomic_size_dc[0x10];
698
b4ff3a36 699 u8 reserved_at_e0[0x720];
e281682b
SM		 700};
701
702struct mlx5_ifc_odp_cap_bits {
b4ff3a36 703 u8 reserved_at_0[0x40];
e281682b
SM		 704
705 u8 sig[0x1];
b4ff3a36 706 u8 reserved_at_41[0x1f];
e281682b 707
b4ff3a36 708 u8 reserved_at_60[0x20];
e281682b
SM		 709
710 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
711
712 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
713
714 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
715
b4ff3a36 716 u8 reserved_at_e0[0x720];
e281682b
SM		 717};
718
3f0393a5
SG		 719struct mlx5_ifc_calc_op {
720 u8 reserved_at_0[0x10];
721 u8 reserved_at_10[0x9];
722 u8 op_swap_endianness[0x1];
723 u8 op_min[0x1];
724 u8 op_xor[0x1];
725 u8 op_or[0x1];
726 u8 op_and[0x1];
727 u8 op_max[0x1];
728 u8 op_add[0x1];
729};
730
731struct mlx5_ifc_vector_calc_cap_bits {
732 u8 calc_matrix[0x1];
733 u8 reserved_at_1[0x1f];
734 u8 reserved_at_20[0x8];
735 u8 max_vec_count[0x8];
736 u8 reserved_at_30[0xd];
737 u8 max_chunk_size[0x3];
738 struct mlx5_ifc_calc_op calc0;
739 struct mlx5_ifc_calc_op calc1;
740 struct mlx5_ifc_calc_op calc2;
741 struct mlx5_ifc_calc_op calc3;
742
743 u8 reserved_at_e0[0x720];
744};
745
e281682b
SM		 746enum {
747 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
748 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 749 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
ccc87087 750 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
e281682b
SM		 751};
752
753enum {
754 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
755 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
756};
757
758enum {
759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
760 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
761 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
762 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
763 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
764};
765
766enum {
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
769 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
770 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
771 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
772 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
773};
774
775enum {
776 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
777 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
778};
779
780enum {
781 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
782 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
783 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
784};
785
786enum {
787 MLX5_CAP_PORT_TYPE_IB = 0x0,
788 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 789};
790
1410a90a
MG		 791enum {
792 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
793 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
794 MLX5_CAP_UMR_FENCE_NONE = 0x2,
795};
796
b775516b 797struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 798 u8 reserved_at_0[0x80];
b775516b
EC		 799
800 u8 log_max_srq_sz[0x8];
801 u8 log_max_qp_sz[0x8];
b4ff3a36 802 u8 reserved_at_90[0xb];
b775516b
EC		 803 u8 log_max_qp[0x5];
804
b4ff3a36 805 u8 reserved_at_a0[0xb];
e281682b 806 u8 log_max_srq[0x5];
b4ff3a36 807 u8 reserved_at_b0[0x10];
b775516b 808
b4ff3a36 809 u8 reserved_at_c0[0x8];
b775516b 810 u8 log_max_cq_sz[0x8];
b4ff3a36 811 u8 reserved_at_d0[0xb];
b775516b
EC		 812 u8 log_max_cq[0x5];
813
814 u8 log_max_eq_sz[0x8];
b4ff3a36 815 u8 reserved_at_e8[0x2];
b775516b 816 u8 log_max_mkey[0x6];
b4ff3a36 817 u8 reserved_at_f0[0xc];
b775516b
EC		 818 u8 log_max_eq[0x4];
819
820 u8 max_indirection[0x8];
bcda1aca 821 u8 fixed_buffer_size[0x1];
b775516b 822 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 823 u8 force_teardown[0x1];
824 u8 reserved_at_111[0x1];
b775516b 825 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 826 u8 umr_extended_translation_offset[0x1];
827 u8 null_mkey[0x1];
b775516b
EC		 828 u8 log_max_klm_list_size[0x6];
829
b4ff3a36 830 u8 reserved_at_120[0xa];
b775516b 831 u8 log_max_ra_req_dc[0x6];
b4ff3a36 832 u8 reserved_at_130[0xa];
b775516b
EC		 833 u8 log_max_ra_res_dc[0x6];
834
b4ff3a36 835 u8 reserved_at_140[0xa];
b775516b 836 u8 log_max_ra_req_qp[0x6];
b4ff3a36 837 u8 reserved_at_150[0xa];
b775516b
EC		 838 u8 log_max_ra_res_qp[0x6];
839
f32f5bd2 840 u8 end_pad[0x1];
b775516b
EC		 841 u8 cc_query_allowed[0x1];
842 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 843 u8 start_pad[0x1];
844 u8 cache_line_128byte[0x1];
c02762eb
HN		 845 u8 reserved_at_165[0xa];
846 u8 qcam_reg[0x1];
e281682b 847 u8 gid_table_size[0x10];
b775516b 848
e281682b
SM		 849 u8 out_of_seq_cnt[0x1];
850 u8 vport_counters[0x1];
7486216b 851 u8 retransmission_q_counters[0x1];
83b502a1
AV		 852 u8 reserved_at_183[0x1];
853 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 854 u8 rq_delay_drop[0x1];
b775516b
EC		 855 u8 max_qp_cnt[0xa];
856 u8 pkey_table_size[0x10];
857
e281682b
SM		 858 u8 vport_group_manager[0x1];
859 u8 vhca_group_manager[0x1];
860 u8 ib_virt[0x1];
861 u8 eth_virt[0x1];
b4ff3a36 862 u8 reserved_at_1a4[0x1];
e281682b
SM		 863 u8 ets[0x1];
864 u8 nic_flow_table[0x1];
05c52228 865 u8 eswitch_manager[0x1];
e1c9c62b 866 u8 early_vf_enable[0x1];
cfdcbcea
GP		 867 u8 mcam_reg[0x1];
868 u8 pcam_reg[0x1];
b775516b 869 u8 local_ca_ack_delay[0x5];
4ce3bf2f 870 u8 port_module_event[0x1];
58dcb60a 871 u8 enhanced_error_q_counters[0x1];
7d5e1423 872 u8 ports_check[0x1];
7b13558f 873 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 874 u8 disable_link_up[0x1];
875 u8 beacon_led[0x1];
e281682b 876 u8 port_type[0x2];
b775516b
EC		 877 u8 num_ports[0x8];
878
f9a1ef72
EE		 879 u8 reserved_at_1c0[0x1];
880 u8 pps[0x1];
881 u8 pps_modify[0x1];
b775516b 882 u8 log_max_msg[0x5];
e1c9c62b 883 u8 reserved_at_1c8[0x4];
4f3961ee 884 u8 max_tc[0x4];
7486216b
SM		 885 u8 reserved_at_1d0[0x1];
886 u8 dcbx[0x1];
246ac981
MG		 887 u8 general_notification_event[0x1];
888 u8 reserved_at_1d3[0x2];
e29341fb 889 u8 fpga[0x1];
928cfe87
TT		 890 u8 rol_s[0x1];
891 u8 rol_g[0x1];
e1c9c62b 892 u8 reserved_at_1d8[0x1];
928cfe87
TT		 893 u8 wol_s[0x1];
894 u8 wol_g[0x1];
895 u8 wol_a[0x1];
896 u8 wol_b[0x1];
897 u8 wol_m[0x1];
898 u8 wol_u[0x1];
899 u8 wol_p[0x1];
b775516b
EC		 900
901 u8 stat_rate_support[0x10];
e1c9c62b 902 u8 reserved_at_1f0[0xc];
e281682b 903 u8 cqe_version[0x4];
b775516b 904
e281682b 905 u8 compact_address_vector[0x1];
7d5e1423 906 u8 striding_rq[0x1];
500a3d0d
ES		 907 u8 reserved_at_202[0x1];
908 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 909 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 910 u8 reserved_at_205[0x5];
911 u8 umr_fence[0x2];
912 u8 reserved_at_20c[0x3];
e281682b 913 u8 drain_sigerr[0x1];
b775516b
EC		 914 u8 cmdif_checksum[0x2];
915 u8 sigerr_cqe[0x1];
e1c9c62b 916 u8 reserved_at_213[0x1];
b775516b
EC		 917 u8 wq_signature[0x1];
918 u8 sctr_data_cqe[0x1];
e1c9c62b 919 u8 reserved_at_216[0x1];
b775516b
EC		 920 u8 sho[0x1];
921 u8 tph[0x1];
922 u8 rf[0x1];
e281682b 923 u8 dct[0x1];
7486216b 924 u8 qos[0x1];
e281682b 925 u8 eth_net_offloads[0x1];
b775516b
EC		 926 u8 roce[0x1];
927 u8 atomic[0x1];
e1c9c62b 928 u8 reserved_at_21f[0x1];
b775516b
EC		 929
930 u8 cq_oi[0x1];
931 u8 cq_resize[0x1];
932 u8 cq_moderation[0x1];
e1c9c62b 933 u8 reserved_at_223[0x3];
e281682b 934 u8 cq_eq_remap[0x1];
b775516b
EC		 935 u8 pg[0x1];
936 u8 block_lb_mc[0x1];
e1c9c62b 937 u8 reserved_at_229[0x1];
e281682b 938 u8 scqe_break_moderation[0x1];
7d5e1423 939 u8 cq_period_start_from_cqe[0x1];
b775516b 940 u8 cd[0x1];
e1c9c62b 941 u8 reserved_at_22d[0x1];
b775516b 942 u8 apm[0x1];
3f0393a5 943 u8 vector_calc[0x1];
7d5e1423 944 u8 umr_ptr_rlky[0x1];
d2370e0a 945 u8 imaicl[0x1];
e1c9c62b 946 u8 reserved_at_232[0x4];
b775516b
EC		 947 u8 qkv[0x1];
948 u8 pkv[0x1];
b11a4f9c
HE		 949 u8 set_deth_sqpn[0x1];
950 u8 reserved_at_239[0x3];
b775516b
EC		 951 u8 xrc[0x1];
952 u8 ud[0x1];
953 u8 uc[0x1];
954 u8 rc[0x1];
955
a6d51b68
EC		 956 u8 uar_4k[0x1];
957 u8 reserved_at_241[0x9];
b775516b 958 u8 uar_sz[0x6];
e1c9c62b 959 u8 reserved_at_250[0x8];
b775516b
EC		 960 u8 log_pg_sz[0x8];
961
962 u8 bf[0x1];
0dbc6fe0 963 u8 driver_version[0x1];
e281682b 964 u8 pad_tx_eth_packet[0x1];
e1c9c62b 965 u8 reserved_at_263[0x8];
b775516b 966 u8 log_bf_reg_size[0x5];
84df61eb
AH		 967
968 u8 reserved_at_270[0xb];
969 u8 lag_master[0x1];
970 u8 num_lag_ports[0x4];
b775516b 971
e1c9c62b 972 u8 reserved_at_280[0x10];
b775516b
EC		 973 u8 max_wqe_sz_sq[0x10];
974
e1c9c62b 975 u8 reserved_at_2a0[0x10];
b775516b
EC		 976 u8 max_wqe_sz_rq[0x10];
977
a8ffcc74 978 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 979 u8 max_wqe_sz_sq_dc[0x10];
980
e1c9c62b 981 u8 reserved_at_2e0[0x7];
b775516b
EC		 982 u8 max_qp_mcg[0x19];
983
e1c9c62b 984 u8 reserved_at_300[0x18];
b775516b
EC		 985 u8 log_max_mcg[0x8];
986
e1c9c62b 987 u8 reserved_at_320[0x3];
e281682b 988 u8 log_max_transport_domain[0x5];
e1c9c62b 989 u8 reserved_at_328[0x3];
b775516b 990 u8 log_max_pd[0x5];
e1c9c62b 991 u8 reserved_at_330[0xb];
b775516b
EC		 992 u8 log_max_xrcd[0x5];
993
a351a1b0
AV		 994 u8 reserved_at_340[0x8];
995 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 996 u8 max_flow_counter_15_0[0x10];
a351a1b0 997
b775516b 998
e1c9c62b 999 u8 reserved_at_360[0x3];
b775516b 1000 u8 log_max_rq[0x5];
e1c9c62b 1001 u8 reserved_at_368[0x3];
b775516b 1002 u8 log_max_sq[0x5];
e1c9c62b 1003 u8 reserved_at_370[0x3];
b775516b 1004 u8 log_max_tir[0x5];
e1c9c62b 1005 u8 reserved_at_378[0x3];
b775516b
EC		 1006 u8 log_max_tis[0x5];
1007
e281682b 1008 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1009 u8 reserved_at_381[0x2];
e281682b 1010 u8 log_max_rmp[0x5];
e1c9c62b 1011 u8 reserved_at_388[0x3];
e281682b 1012 u8 log_max_rqt[0x5];
e1c9c62b 1013 u8 reserved_at_390[0x3];
e281682b 1014 u8 log_max_rqt_size[0x5];
e1c9c62b 1015 u8 reserved_at_398[0x3];
b775516b
EC		 1016 u8 log_max_tis_per_sq[0x5];
1017
e1c9c62b 1018 u8 reserved_at_3a0[0x3];
e281682b 1019 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1020 u8 reserved_at_3a8[0x3];
e281682b 1021 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1022 u8 reserved_at_3b0[0x3];
e281682b 1023 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1024 u8 reserved_at_3b8[0x3];
e281682b
SM		 1025 u8 log_min_stride_sz_sq[0x5];
1026
e1c9c62b 1027 u8 reserved_at_3c0[0x1b];
e281682b
SM		 1028 u8 log_max_wq_sz[0x5];
1029
54f0a411 1030 u8 nic_vport_change_event[0x1];
8978cc92
EBE		 1031 u8 disable_local_lb_uc[0x1];
1032 u8 disable_local_lb_mc[0x1];
1033 u8 reserved_at_3e3[0x8];
54f0a411 1034 u8 log_max_vlan_list[0x5];
e1c9c62b 1035 u8 reserved_at_3f0[0x3];
54f0a411 1036 u8 log_max_current_mc_list[0x5];
e1c9c62b 1037 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1038 u8 log_max_current_uc_list[0x5];
1039
e1c9c62b 1040 u8 reserved_at_400[0x80];
54f0a411 1041
e1c9c62b 1042 u8 reserved_at_480[0x3];
e281682b 1043 u8 log_max_l2_table[0x5];
e1c9c62b 1044 u8 reserved_at_488[0x8];
b775516b
EC		 1045 u8 log_uar_page_sz[0x10];
1046
e1c9c62b 1047 u8 reserved_at_4a0[0x20];
048ccca8 1048 u8 device_frequency_mhz[0x20];
b0844444 1049 u8 device_frequency_khz[0x20];
e1c9c62b 1050
a6d51b68
EC		 1051 u8 reserved_at_500[0x20];
1052 u8 num_of_uars_per_page[0x20];
1053 u8 reserved_at_540[0x40];
e1c9c62b 1054
0ff8e79c
GL		 1055 u8 reserved_at_580[0x3d];
1056 u8 cqe_128_always[0x1];
1057 u8 cqe_compression_128[0x1];
7d5e1423 1058 u8 cqe_compression[0x1];
b775516b 1059
7d5e1423
SM		 1060 u8 cqe_compression_timeout[0x10];
1061 u8 cqe_compression_max_num[0x10];
b775516b 1062
7486216b
SM		 1063 u8 reserved_at_5e0[0x10];
1064 u8 tag_matching[0x1];
1065 u8 rndv_offload_rc[0x1];
1066 u8 rndv_offload_dc[0x1];
1067 u8 log_tag_matching_list_sz[0x5];
7b13558f 1068 u8 reserved_at_5f8[0x3];
7486216b
SM		 1069 u8 log_max_xrq[0x5];
1070
7b13558f 1071 u8 reserved_at_600[0x200];
b775516b
EC		 1072};
1073
81848731
SM		 1074enum mlx5_flow_destination_type {
1075 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1076 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1077 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1078
1079 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1080};
b775516b 1081
e281682b
SM		 1082struct mlx5_ifc_dest_format_struct_bits {
1083 u8 destination_type[0x8];
1084 u8 destination_id[0x18];
b775516b 1085
b4ff3a36 1086 u8 reserved_at_20[0x20];
e281682b
SM		 1087};
1088
9dc0b289 1089struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1090 u8 flow_counter_id[0x20];
9dc0b289
AV		 1091
1092 u8 reserved_at_20[0x20];
1093};
1094
1095union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1096 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1097 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1098 u8 reserved_at_0[0x40];
1099};
1100
e281682b
SM		 1101struct mlx5_ifc_fte_match_param_bits {
1102 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1103
1104 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1105
1106 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1107
b4ff3a36 1108 u8 reserved_at_600[0xa00];
b775516b
EC		 1109};
1110
e281682b
SM		 1111enum {
1112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1115 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1116 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1117};
b775516b 1118
e281682b
SM		 1119struct mlx5_ifc_rx_hash_field_select_bits {
1120 u8 l3_prot_type[0x1];
1121 u8 l4_prot_type[0x1];
1122 u8 selected_fields[0x1e];
1123};
b775516b 1124
e281682b
SM		 1125enum {
1126 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1127 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1128};
1129
e281682b
SM		 1130enum {
1131 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1132 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1133};
1134
1135struct mlx5_ifc_wq_bits {
1136 u8 wq_type[0x4];
1137 u8 wq_signature[0x1];
1138 u8 end_padding_mode[0x2];
1139 u8 cd_slave[0x1];
b4ff3a36 1140 u8 reserved_at_8[0x18];
b775516b 1141
e281682b
SM		 1142 u8 hds_skip_first_sge[0x1];
1143 u8 log2_hds_buf_size[0x3];
b4ff3a36 1144 u8 reserved_at_24[0x7];
e281682b
SM		 1145 u8 page_offset[0x5];
1146 u8 lwm[0x10];
b775516b 1147
b4ff3a36 1148 u8 reserved_at_40[0x8];
e281682b
SM		 1149 u8 pd[0x18];
1150
b4ff3a36 1151 u8 reserved_at_60[0x8];
e281682b
SM		 1152 u8 uar_page[0x18];
1153
1154 u8 dbr_addr[0x40];
1155
1156 u8 hw_counter[0x20];
1157
1158 u8 sw_counter[0x20];
1159
b4ff3a36 1160 u8 reserved_at_100[0xc];
e281682b 1161 u8 log_wq_stride[0x4];
b4ff3a36 1162 u8 reserved_at_110[0x3];
e281682b 1163 u8 log_wq_pg_sz[0x5];
b4ff3a36 1164 u8 reserved_at_118[0x3];
e281682b
SM		 1165 u8 log_wq_sz[0x5];
1166
7d5e1423
SM		 1167 u8 reserved_at_120[0x15];
1168 u8 log_wqe_num_of_strides[0x3];
1169 u8 two_byte_shift_en[0x1];
1170 u8 reserved_at_139[0x4];
1171 u8 log_wqe_stride_size[0x3];
1172
1173 u8 reserved_at_140[0x4c0];
b775516b 1174
e281682b 1175 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1176};
1177
e281682b 1178struct mlx5_ifc_rq_num_bits {
b4ff3a36 1179 u8 reserved_at_0[0x8];
e281682b
SM		 1180 u8 rq_num[0x18];
1181};
b775516b 1182
e281682b 1183struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1184 u8 reserved_at_0[0x10];
e281682b 1185 u8 mac_addr_47_32[0x10];
b775516b 1186
e281682b
SM		 1187 u8 mac_addr_31_0[0x20];
1188};
1189
c0046cf7 1190struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1191 u8 reserved_at_0[0x14];
c0046cf7
SM		 1192 u8 vlan[0x0c];
1193
b4ff3a36 1194 u8 reserved_at_20[0x20];
c0046cf7
SM		 1195};
1196
e281682b 1197struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1198 u8 reserved_at_0[0xa0];
e281682b
SM		 1199
1200 u8 min_time_between_cnps[0x20];
1201
b4ff3a36 1202 u8 reserved_at_c0[0x12];
e281682b 1203 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1204 u8 reserved_at_d8[0x4];
1205 u8 cnp_prio_mode[0x1];
e281682b
SM		 1206 u8 cnp_802p_prio[0x3];
1207
b4ff3a36 1208 u8 reserved_at_e0[0x720];
e281682b
SM		 1209};
1210
1211struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1212 u8 reserved_at_0[0x60];
e281682b 1213
b4ff3a36 1214 u8 reserved_at_60[0x4];
e281682b 1215 u8 clamp_tgt_rate[0x1];
b4ff3a36 1216 u8 reserved_at_65[0x3];
e281682b 1217 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1218 u8 reserved_at_69[0x17];
e281682b 1219
b4ff3a36 1220 u8 reserved_at_80[0x20];
e281682b
SM		 1221
1222 u8 rpg_time_reset[0x20];
1223
1224 u8 rpg_byte_reset[0x20];
1225
1226 u8 rpg_threshold[0x20];
1227
1228 u8 rpg_max_rate[0x20];
1229
1230 u8 rpg_ai_rate[0x20];
1231
1232 u8 rpg_hai_rate[0x20];
1233
1234 u8 rpg_gd[0x20];
1235
1236 u8 rpg_min_dec_fac[0x20];
1237
1238 u8 rpg_min_rate[0x20];
1239
b4ff3a36 1240 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1241
1242 u8 rate_to_set_on_first_cnp[0x20];
1243
1244 u8 dce_tcp_g[0x20];
1245
1246 u8 dce_tcp_rtt[0x20];
1247
1248 u8 rate_reduce_monitor_period[0x20];
1249
b4ff3a36 1250 u8 reserved_at_320[0x20];
e281682b
SM		 1251
1252 u8 initial_alpha_value[0x20];
1253
b4ff3a36 1254 u8 reserved_at_360[0x4a0];
e281682b
SM		 1255};
1256
1257struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1258 u8 reserved_at_0[0x80];
e281682b
SM		 1259
1260 u8 rppp_max_rps[0x20];
1261
1262 u8 rpg_time_reset[0x20];
1263
1264 u8 rpg_byte_reset[0x20];
1265
1266 u8 rpg_threshold[0x20];
1267
1268 u8 rpg_max_rate[0x20];
1269
1270 u8 rpg_ai_rate[0x20];
1271
1272 u8 rpg_hai_rate[0x20];
1273
1274 u8 rpg_gd[0x20];
1275
1276 u8 rpg_min_dec_fac[0x20];
1277
1278 u8 rpg_min_rate[0x20];
1279
b4ff3a36 1280 u8 reserved_at_1c0[0x640];
e281682b
SM		 1281};
1282
1283enum {
1284 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1285 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1286 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1287};
1288
1289struct mlx5_ifc_resize_field_select_bits {
1290 u8 resize_field_select[0x20];
1291};
1292
1293enum {
1294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1296 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1297 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1298};
1299
1300struct mlx5_ifc_modify_field_select_bits {
1301 u8 modify_field_select[0x20];
1302};
1303
1304struct mlx5_ifc_field_select_r_roce_np_bits {
1305 u8 field_select_r_roce_np[0x20];
1306};
1307
1308struct mlx5_ifc_field_select_r_roce_rp_bits {
1309 u8 field_select_r_roce_rp[0x20];
1310};
1311
1312enum {
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1323};
1324
1325struct mlx5_ifc_field_select_802_1qau_rp_bits {
1326 u8 field_select_8021qaurp[0x20];
1327};
1328
1329struct mlx5_ifc_phys_layer_cntrs_bits {
1330 u8 time_since_last_clear_high[0x20];
1331
1332 u8 time_since_last_clear_low[0x20];
1333
1334 u8 symbol_errors_high[0x20];
1335
1336 u8 symbol_errors_low[0x20];
1337
1338 u8 sync_headers_errors_high[0x20];
1339
1340 u8 sync_headers_errors_low[0x20];
1341
1342 u8 edpl_bip_errors_lane0_high[0x20];
1343
1344 u8 edpl_bip_errors_lane0_low[0x20];
1345
1346 u8 edpl_bip_errors_lane1_high[0x20];
1347
1348 u8 edpl_bip_errors_lane1_low[0x20];
1349
1350 u8 edpl_bip_errors_lane2_high[0x20];
1351
1352 u8 edpl_bip_errors_lane2_low[0x20];
1353
1354 u8 edpl_bip_errors_lane3_high[0x20];
1355
1356 u8 edpl_bip_errors_lane3_low[0x20];
1357
1358 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1359
1360 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1361
1362 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1363
1364 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1365
1366 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1367
1368 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1369
1370 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1371
1372 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1373
1374 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1375
1376 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1377
1378 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1379
1380 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1381
1382 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1383
1384 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1385
1386 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1387
1388 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1389
1390 u8 rs_fec_corrected_blocks_high[0x20];
1391
1392 u8 rs_fec_corrected_blocks_low[0x20];
1393
1394 u8 rs_fec_uncorrectable_blocks_high[0x20];
1395
1396 u8 rs_fec_uncorrectable_blocks_low[0x20];
1397
1398 u8 rs_fec_no_errors_blocks_high[0x20];
1399
1400 u8 rs_fec_no_errors_blocks_low[0x20];
1401
1402 u8 rs_fec_single_error_blocks_high[0x20];
1403
1404 u8 rs_fec_single_error_blocks_low[0x20];
1405
1406 u8 rs_fec_corrected_symbols_total_high[0x20];
1407
1408 u8 rs_fec_corrected_symbols_total_low[0x20];
1409
1410 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1411
1412 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1413
1414 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1415
1416 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1417
1418 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1419
1420 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1421
1422 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1423
1424 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1425
1426 u8 link_down_events[0x20];
1427
1428 u8 successful_recovery_events[0x20];
1429
b4ff3a36 1430 u8 reserved_at_640[0x180];
e281682b
SM		 1431};
1432
d8dc0508
GP		 1433struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1434 u8 time_since_last_clear_high[0x20];
1435
1436 u8 time_since_last_clear_low[0x20];
1437
1438 u8 phy_received_bits_high[0x20];
1439
1440 u8 phy_received_bits_low[0x20];
1441
1442 u8 phy_symbol_errors_high[0x20];
1443
1444 u8 phy_symbol_errors_low[0x20];
1445
1446 u8 phy_corrected_bits_high[0x20];
1447
1448 u8 phy_corrected_bits_low[0x20];
1449
1450 u8 phy_corrected_bits_lane0_high[0x20];
1451
1452 u8 phy_corrected_bits_lane0_low[0x20];
1453
1454 u8 phy_corrected_bits_lane1_high[0x20];
1455
1456 u8 phy_corrected_bits_lane1_low[0x20];
1457
1458 u8 phy_corrected_bits_lane2_high[0x20];
1459
1460 u8 phy_corrected_bits_lane2_low[0x20];
1461
1462 u8 phy_corrected_bits_lane3_high[0x20];
1463
1464 u8 phy_corrected_bits_lane3_low[0x20];
1465
1466 u8 reserved_at_200[0x5c0];
1467};
1468
1c64bf6f
MY		 1469struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1470 u8 symbol_error_counter[0x10];
1471
1472 u8 link_error_recovery_counter[0x8];
1473
1474 u8 link_downed_counter[0x8];
1475
1476 u8 port_rcv_errors[0x10];
1477
1478 u8 port_rcv_remote_physical_errors[0x10];
1479
1480 u8 port_rcv_switch_relay_errors[0x10];
1481
1482 u8 port_xmit_discards[0x10];
1483
1484 u8 port_xmit_constraint_errors[0x8];
1485
1486 u8 port_rcv_constraint_errors[0x8];
1487
1488 u8 reserved_at_70[0x8];
1489
1490 u8 link_overrun_errors[0x8];
1491
1492 u8 reserved_at_80[0x10];
1493
1494 u8 vl_15_dropped[0x10];
1495
133bea04
TW		 1496 u8 reserved_at_a0[0x80];
1497
1498 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1499};
1500
e281682b
SM		 1501struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1502 u8 transmit_queue_high[0x20];
1503
1504 u8 transmit_queue_low[0x20];
1505
b4ff3a36 1506 u8 reserved_at_40[0x780];
e281682b
SM		 1507};
1508
1509struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1510 u8 rx_octets_high[0x20];
1511
1512 u8 rx_octets_low[0x20];
1513
b4ff3a36 1514 u8 reserved_at_40[0xc0];
e281682b
SM		 1515
1516 u8 rx_frames_high[0x20];
1517
1518 u8 rx_frames_low[0x20];
1519
1520 u8 tx_octets_high[0x20];
1521
1522 u8 tx_octets_low[0x20];
1523
b4ff3a36 1524 u8 reserved_at_180[0xc0];
e281682b
SM		 1525
1526 u8 tx_frames_high[0x20];
1527
1528 u8 tx_frames_low[0x20];
1529
1530 u8 rx_pause_high[0x20];
1531
1532 u8 rx_pause_low[0x20];
1533
1534 u8 rx_pause_duration_high[0x20];
1535
1536 u8 rx_pause_duration_low[0x20];
1537
1538 u8 tx_pause_high[0x20];
1539
1540 u8 tx_pause_low[0x20];
1541
1542 u8 tx_pause_duration_high[0x20];
1543
1544 u8 tx_pause_duration_low[0x20];
1545
1546 u8 rx_pause_transition_high[0x20];
1547
1548 u8 rx_pause_transition_low[0x20];
1549
b4ff3a36 1550 u8 reserved_at_3c0[0x400];
e281682b
SM		 1551};
1552
1553struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1554 u8 port_transmit_wait_high[0x20];
1555
1556 u8 port_transmit_wait_low[0x20];
1557
2dba0797
GP		 1558 u8 reserved_at_40[0x100];
1559
1560 u8 rx_buffer_almost_full_high[0x20];
1561
1562 u8 rx_buffer_almost_full_low[0x20];
1563
1564 u8 rx_buffer_full_high[0x20];
1565
1566 u8 rx_buffer_full_low[0x20];
1567
1568 u8 reserved_at_1c0[0x600];
e281682b
SM		 1569};
1570
1571struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1572 u8 dot3stats_alignment_errors_high[0x20];
1573
1574 u8 dot3stats_alignment_errors_low[0x20];
1575
1576 u8 dot3stats_fcs_errors_high[0x20];
1577
1578 u8 dot3stats_fcs_errors_low[0x20];
1579
1580 u8 dot3stats_single_collision_frames_high[0x20];
1581
1582 u8 dot3stats_single_collision_frames_low[0x20];
1583
1584 u8 dot3stats_multiple_collision_frames_high[0x20];
1585
1586 u8 dot3stats_multiple_collision_frames_low[0x20];
1587
1588 u8 dot3stats_sqe_test_errors_high[0x20];
1589
1590 u8 dot3stats_sqe_test_errors_low[0x20];
1591
1592 u8 dot3stats_deferred_transmissions_high[0x20];
1593
1594 u8 dot3stats_deferred_transmissions_low[0x20];
1595
1596 u8 dot3stats_late_collisions_high[0x20];
1597
1598 u8 dot3stats_late_collisions_low[0x20];
1599
1600 u8 dot3stats_excessive_collisions_high[0x20];
1601
1602 u8 dot3stats_excessive_collisions_low[0x20];
1603
1604 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1605
1606 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1607
1608 u8 dot3stats_carrier_sense_errors_high[0x20];
1609
1610 u8 dot3stats_carrier_sense_errors_low[0x20];
1611
1612 u8 dot3stats_frame_too_longs_high[0x20];
1613
1614 u8 dot3stats_frame_too_longs_low[0x20];
1615
1616 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1617
1618 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1619
1620 u8 dot3stats_symbol_errors_high[0x20];
1621
1622 u8 dot3stats_symbol_errors_low[0x20];
1623
1624 u8 dot3control_in_unknown_opcodes_high[0x20];
1625
1626 u8 dot3control_in_unknown_opcodes_low[0x20];
1627
1628 u8 dot3in_pause_frames_high[0x20];
1629
1630 u8 dot3in_pause_frames_low[0x20];
1631
1632 u8 dot3out_pause_frames_high[0x20];
1633
1634 u8 dot3out_pause_frames_low[0x20];
1635
b4ff3a36 1636 u8 reserved_at_400[0x3c0];
e281682b
SM		 1637};
1638
1639struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1640 u8 ether_stats_drop_events_high[0x20];
1641
1642 u8 ether_stats_drop_events_low[0x20];
1643
1644 u8 ether_stats_octets_high[0x20];
1645
1646 u8 ether_stats_octets_low[0x20];
1647
1648 u8 ether_stats_pkts_high[0x20];
1649
1650 u8 ether_stats_pkts_low[0x20];
1651
1652 u8 ether_stats_broadcast_pkts_high[0x20];
1653
1654 u8 ether_stats_broadcast_pkts_low[0x20];
1655
1656 u8 ether_stats_multicast_pkts_high[0x20];
1657
1658 u8 ether_stats_multicast_pkts_low[0x20];
1659
1660 u8 ether_stats_crc_align_errors_high[0x20];
1661
1662 u8 ether_stats_crc_align_errors_low[0x20];
1663
1664 u8 ether_stats_undersize_pkts_high[0x20];
1665
1666 u8 ether_stats_undersize_pkts_low[0x20];
1667
1668 u8 ether_stats_oversize_pkts_high[0x20];
1669
1670 u8 ether_stats_oversize_pkts_low[0x20];
1671
1672 u8 ether_stats_fragments_high[0x20];
1673
1674 u8 ether_stats_fragments_low[0x20];
1675
1676 u8 ether_stats_jabbers_high[0x20];
1677
1678 u8 ether_stats_jabbers_low[0x20];
1679
1680 u8 ether_stats_collisions_high[0x20];
1681
1682 u8 ether_stats_collisions_low[0x20];
1683
1684 u8 ether_stats_pkts64octets_high[0x20];
1685
1686 u8 ether_stats_pkts64octets_low[0x20];
1687
1688 u8 ether_stats_pkts65to127octets_high[0x20];
1689
1690 u8 ether_stats_pkts65to127octets_low[0x20];
1691
1692 u8 ether_stats_pkts128to255octets_high[0x20];
1693
1694 u8 ether_stats_pkts128to255octets_low[0x20];
1695
1696 u8 ether_stats_pkts256to511octets_high[0x20];
1697
1698 u8 ether_stats_pkts256to511octets_low[0x20];
1699
1700 u8 ether_stats_pkts512to1023octets_high[0x20];
1701
1702 u8 ether_stats_pkts512to1023octets_low[0x20];
1703
1704 u8 ether_stats_pkts1024to1518octets_high[0x20];
1705
1706 u8 ether_stats_pkts1024to1518octets_low[0x20];
1707
1708 u8 ether_stats_pkts1519to2047octets_high[0x20];
1709
1710 u8 ether_stats_pkts1519to2047octets_low[0x20];
1711
1712 u8 ether_stats_pkts2048to4095octets_high[0x20];
1713
1714 u8 ether_stats_pkts2048to4095octets_low[0x20];
1715
1716 u8 ether_stats_pkts4096to8191octets_high[0x20];
1717
1718 u8 ether_stats_pkts4096to8191octets_low[0x20];
1719
1720 u8 ether_stats_pkts8192to10239octets_high[0x20];
1721
1722 u8 ether_stats_pkts8192to10239octets_low[0x20];
1723
b4ff3a36 1724 u8 reserved_at_540[0x280];
e281682b
SM		 1725};
1726
1727struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1728 u8 if_in_octets_high[0x20];
1729
1730 u8 if_in_octets_low[0x20];
1731
1732 u8 if_in_ucast_pkts_high[0x20];
1733
1734 u8 if_in_ucast_pkts_low[0x20];
1735
1736 u8 if_in_discards_high[0x20];
1737
1738 u8 if_in_discards_low[0x20];
1739
1740 u8 if_in_errors_high[0x20];
1741
1742 u8 if_in_errors_low[0x20];
1743
1744 u8 if_in_unknown_protos_high[0x20];
1745
1746 u8 if_in_unknown_protos_low[0x20];
1747
1748 u8 if_out_octets_high[0x20];
1749
1750 u8 if_out_octets_low[0x20];
1751
1752 u8 if_out_ucast_pkts_high[0x20];
1753
1754 u8 if_out_ucast_pkts_low[0x20];
1755
1756 u8 if_out_discards_high[0x20];
1757
1758 u8 if_out_discards_low[0x20];
1759
1760 u8 if_out_errors_high[0x20];
1761
1762 u8 if_out_errors_low[0x20];
1763
1764 u8 if_in_multicast_pkts_high[0x20];
1765
1766 u8 if_in_multicast_pkts_low[0x20];
1767
1768 u8 if_in_broadcast_pkts_high[0x20];
1769
1770 u8 if_in_broadcast_pkts_low[0x20];
1771
1772 u8 if_out_multicast_pkts_high[0x20];
1773
1774 u8 if_out_multicast_pkts_low[0x20];
1775
1776 u8 if_out_broadcast_pkts_high[0x20];
1777
1778 u8 if_out_broadcast_pkts_low[0x20];
1779
b4ff3a36 1780 u8 reserved_at_340[0x480];
e281682b
SM		 1781};
1782
1783struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1784 u8 a_frames_transmitted_ok_high[0x20];
1785
1786 u8 a_frames_transmitted_ok_low[0x20];
1787
1788 u8 a_frames_received_ok_high[0x20];
1789
1790 u8 a_frames_received_ok_low[0x20];
1791
1792 u8 a_frame_check_sequence_errors_high[0x20];
1793
1794 u8 a_frame_check_sequence_errors_low[0x20];
1795
1796 u8 a_alignment_errors_high[0x20];
1797
1798 u8 a_alignment_errors_low[0x20];
1799
1800 u8 a_octets_transmitted_ok_high[0x20];
1801
1802 u8 a_octets_transmitted_ok_low[0x20];
1803
1804 u8 a_octets_received_ok_high[0x20];
1805
1806 u8 a_octets_received_ok_low[0x20];
1807
1808 u8 a_multicast_frames_xmitted_ok_high[0x20];
1809
1810 u8 a_multicast_frames_xmitted_ok_low[0x20];
1811
1812 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1813
1814 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1815
1816 u8 a_multicast_frames_received_ok_high[0x20];
1817
1818 u8 a_multicast_frames_received_ok_low[0x20];
1819
1820 u8 a_broadcast_frames_received_ok_high[0x20];
1821
1822 u8 a_broadcast_frames_received_ok_low[0x20];
1823
1824 u8 a_in_range_length_errors_high[0x20];
1825
1826 u8 a_in_range_length_errors_low[0x20];
1827
1828 u8 a_out_of_range_length_field_high[0x20];
1829
1830 u8 a_out_of_range_length_field_low[0x20];
1831
1832 u8 a_frame_too_long_errors_high[0x20];
1833
1834 u8 a_frame_too_long_errors_low[0x20];
1835
1836 u8 a_symbol_error_during_carrier_high[0x20];
1837
1838 u8 a_symbol_error_during_carrier_low[0x20];
1839
1840 u8 a_mac_control_frames_transmitted_high[0x20];
1841
1842 u8 a_mac_control_frames_transmitted_low[0x20];
1843
1844 u8 a_mac_control_frames_received_high[0x20];
1845
1846 u8 a_mac_control_frames_received_low[0x20];
1847
1848 u8 a_unsupported_opcodes_received_high[0x20];
1849
1850 u8 a_unsupported_opcodes_received_low[0x20];
1851
1852 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1853
1854 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1855
1856 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1857
1858 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1859
b4ff3a36 1860 u8 reserved_at_4c0[0x300];
e281682b
SM		 1861};
1862
8ed1a630
GP		 1863struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1864 u8 life_time_counter_high[0x20];
1865
1866 u8 life_time_counter_low[0x20];
1867
1868 u8 rx_errors[0x20];
1869
1870 u8 tx_errors[0x20];
1871
1872 u8 l0_to_recovery_eieos[0x20];
1873
1874 u8 l0_to_recovery_ts[0x20];
1875
1876 u8 l0_to_recovery_framing[0x20];
1877
1878 u8 l0_to_recovery_retrain[0x20];
1879
1880 u8 crc_error_dllp[0x20];
1881
1882 u8 crc_error_tlp[0x20];
1883
efae7f78
EBE		 1884 u8 tx_overflow_buffer_pkt_high[0x20];
1885
1886 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1887
1888 u8 outbound_stalled_reads[0x20];
1889
1890 u8 outbound_stalled_writes[0x20];
1891
1892 u8 outbound_stalled_reads_events[0x20];
1893
1894 u8 outbound_stalled_writes_events[0x20];
1895
1896 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1897};
1898
e281682b
SM		 1899struct mlx5_ifc_cmd_inter_comp_event_bits {
1900 u8 command_completion_vector[0x20];
1901
b4ff3a36 1902 u8 reserved_at_20[0xc0];
e281682b
SM		 1903};
1904
1905struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1906 u8 reserved_at_0[0x18];
e281682b 1907 u8 port_num[0x1];
b4ff3a36 1908 u8 reserved_at_19[0x3];
e281682b
SM		 1909 u8 vl[0x4];
1910
b4ff3a36 1911 u8 reserved_at_20[0xa0];
e281682b
SM		 1912};
1913
1914struct mlx5_ifc_db_bf_congestion_event_bits {
1915 u8 event_subtype[0x8];
b4ff3a36 1916 u8 reserved_at_8[0x8];
e281682b 1917 u8 congestion_level[0x8];
b4ff3a36 1918 u8 reserved_at_18[0x8];
e281682b 1919
b4ff3a36 1920 u8 reserved_at_20[0xa0];
e281682b
SM		 1921};
1922
1923struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1924 u8 reserved_at_0[0x60];
e281682b
SM		 1925
1926 u8 gpio_event_hi[0x20];
1927
1928 u8 gpio_event_lo[0x20];
1929
b4ff3a36 1930 u8 reserved_at_a0[0x40];
e281682b
SM		 1931};
1932
1933struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1934 u8 reserved_at_0[0x40];
e281682b
SM		 1935
1936 u8 port_num[0x4];
b4ff3a36 1937 u8 reserved_at_44[0x1c];
e281682b 1938
b4ff3a36 1939 u8 reserved_at_60[0x80];
e281682b
SM		 1940};
1941
1942struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1943 u8 reserved_at_0[0xe0];
e281682b
SM		 1944};
1945
1946enum {
1947 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1948 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1949};
1950
1951struct mlx5_ifc_cq_error_bits {
b4ff3a36 1952 u8 reserved_at_0[0x8];
e281682b
SM		 1953 u8 cqn[0x18];
1954
b4ff3a36 1955 u8 reserved_at_20[0x20];
e281682b 1956
b4ff3a36 1957 u8 reserved_at_40[0x18];
e281682b
SM		 1958 u8 syndrome[0x8];
1959
b4ff3a36 1960 u8 reserved_at_60[0x80];
e281682b
SM		 1961};
1962
1963struct mlx5_ifc_rdma_page_fault_event_bits {
1964 u8 bytes_committed[0x20];
1965
1966 u8 r_key[0x20];
1967
b4ff3a36 1968 u8 reserved_at_40[0x10];
e281682b
SM		 1969 u8 packet_len[0x10];
1970
1971 u8 rdma_op_len[0x20];
1972
1973 u8 rdma_va[0x40];
1974
b4ff3a36 1975 u8 reserved_at_c0[0x5];
e281682b
SM		 1976 u8 rdma[0x1];
1977 u8 write[0x1];
1978 u8 requestor[0x1];
1979 u8 qp_number[0x18];
1980};
1981
1982struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1983 u8 bytes_committed[0x20];
1984
b4ff3a36 1985 u8 reserved_at_20[0x10];
e281682b
SM		 1986 u8 wqe_index[0x10];
1987
b4ff3a36 1988 u8 reserved_at_40[0x10];
e281682b
SM		 1989 u8 len[0x10];
1990
b4ff3a36 1991 u8 reserved_at_60[0x60];
e281682b 1992
b4ff3a36 1993 u8 reserved_at_c0[0x5];
e281682b
SM		 1994 u8 rdma[0x1];
1995 u8 write_read[0x1];
1996 u8 requestor[0x1];
1997 u8 qpn[0x18];
1998};
1999
2000struct mlx5_ifc_qp_events_bits {
b4ff3a36 2001 u8 reserved_at_0[0xa0];
e281682b
SM		 2002
2003 u8 type[0x8];
b4ff3a36 2004 u8 reserved_at_a8[0x18];
e281682b 2005
b4ff3a36 2006 u8 reserved_at_c0[0x8];
e281682b
SM		 2007 u8 qpn_rqn_sqn[0x18];
2008};
2009
2010struct mlx5_ifc_dct_events_bits {
b4ff3a36 2011 u8 reserved_at_0[0xc0];
e281682b 2012
b4ff3a36 2013 u8 reserved_at_c0[0x8];
e281682b
SM		 2014 u8 dct_number[0x18];
2015};
2016
2017struct mlx5_ifc_comp_event_bits {
b4ff3a36 2018 u8 reserved_at_0[0xc0];
e281682b 2019
b4ff3a36 2020 u8 reserved_at_c0[0x8];
e281682b
SM		 2021 u8 cq_number[0x18];
2022};
2023
2024enum {
2025 MLX5_QPC_STATE_RST = 0x0,
2026 MLX5_QPC_STATE_INIT = 0x1,
2027 MLX5_QPC_STATE_RTR = 0x2,
2028 MLX5_QPC_STATE_RTS = 0x3,
2029 MLX5_QPC_STATE_SQER = 0x4,
2030 MLX5_QPC_STATE_ERR = 0x6,
2031 MLX5_QPC_STATE_SQD = 0x7,
2032 MLX5_QPC_STATE_SUSPENDED = 0x9,
2033};
2034
2035enum {
2036 MLX5_QPC_ST_RC = 0x0,
2037 MLX5_QPC_ST_UC = 0x1,
2038 MLX5_QPC_ST_UD = 0x2,
2039 MLX5_QPC_ST_XRC = 0x3,
2040 MLX5_QPC_ST_DCI = 0x5,
2041 MLX5_QPC_ST_QP0 = 0x7,
2042 MLX5_QPC_ST_QP1 = 0x8,
2043 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2044 MLX5_QPC_ST_REG_UMR = 0xc,
2045};
2046
2047enum {
2048 MLX5_QPC_PM_STATE_ARMED = 0x0,
2049 MLX5_QPC_PM_STATE_REARM = 0x1,
2050 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2051 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2052};
2053
6e44636a
AK		 2054enum {
2055 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2056};
2057
e281682b
SM		 2058enum {
2059 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2060 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2061};
2062
2063enum {
2064 MLX5_QPC_MTU_256_BYTES = 0x1,
2065 MLX5_QPC_MTU_512_BYTES = 0x2,
2066 MLX5_QPC_MTU_1K_BYTES = 0x3,
2067 MLX5_QPC_MTU_2K_BYTES = 0x4,
2068 MLX5_QPC_MTU_4K_BYTES = 0x5,
2069 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2070};
2071
2072enum {
2073 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2074 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2075 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2076 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2077 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2078 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2079 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2080 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2081};
2082
2083enum {
2084 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2085 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2086 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2087};
2088
2089enum {
2090 MLX5_QPC_CS_RES_DISABLE = 0x0,
2091 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2092 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2093};
2094
2095struct mlx5_ifc_qpc_bits {
2096 u8 state[0x4];
84df61eb 2097 u8 lag_tx_port_affinity[0x4];
e281682b 2098 u8 st[0x8];
b4ff3a36 2099 u8 reserved_at_10[0x3];
e281682b 2100 u8 pm_state[0x2];
6e44636a
AK		 2101 u8 reserved_at_15[0x3];
2102 u8 offload_type[0x4];
e281682b 2103 u8 end_padding_mode[0x2];
b4ff3a36 2104 u8 reserved_at_1e[0x2];
e281682b
SM		 2105
2106 u8 wq_signature[0x1];
2107 u8 block_lb_mc[0x1];
2108 u8 atomic_like_write_en[0x1];
2109 u8 latency_sensitive[0x1];
b4ff3a36 2110 u8 reserved_at_24[0x1];
e281682b 2111 u8 drain_sigerr[0x1];
b4ff3a36 2112 u8 reserved_at_26[0x2];
e281682b
SM		 2113 u8 pd[0x18];
2114
2115 u8 mtu[0x3];
2116 u8 log_msg_max[0x5];
b4ff3a36 2117 u8 reserved_at_48[0x1];
e281682b
SM		 2118 u8 log_rq_size[0x4];
2119 u8 log_rq_stride[0x3];
2120 u8 no_sq[0x1];
2121 u8 log_sq_size[0x4];
b4ff3a36 2122 u8 reserved_at_55[0x6];
e281682b 2123 u8 rlky[0x1];
1015c2e8 2124 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2125
2126 u8 counter_set_id[0x8];
2127 u8 uar_page[0x18];
2128
b4ff3a36 2129 u8 reserved_at_80[0x8];
e281682b
SM		 2130 u8 user_index[0x18];
2131
b4ff3a36 2132 u8 reserved_at_a0[0x3];
e281682b
SM		 2133 u8 log_page_size[0x5];
2134 u8 remote_qpn[0x18];
2135
2136 struct mlx5_ifc_ads_bits primary_address_path;
2137
2138 struct mlx5_ifc_ads_bits secondary_address_path;
2139
2140 u8 log_ack_req_freq[0x4];
b4ff3a36 2141 u8 reserved_at_384[0x4];
e281682b 2142 u8 log_sra_max[0x3];
b4ff3a36 2143 u8 reserved_at_38b[0x2];
e281682b
SM		 2144 u8 retry_count[0x3];
2145 u8 rnr_retry[0x3];
b4ff3a36 2146 u8 reserved_at_393[0x1];
e281682b
SM		 2147 u8 fre[0x1];
2148 u8 cur_rnr_retry[0x3];
2149 u8 cur_retry_count[0x3];
b4ff3a36 2150 u8 reserved_at_39b[0x5];
e281682b 2151
b4ff3a36 2152 u8 reserved_at_3a0[0x20];
e281682b 2153
b4ff3a36 2154 u8 reserved_at_3c0[0x8];
e281682b
SM		 2155 u8 next_send_psn[0x18];
2156
b4ff3a36 2157 u8 reserved_at_3e0[0x8];
e281682b
SM		 2158 u8 cqn_snd[0x18];
2159
09a7d9ec
SM		 2160 u8 reserved_at_400[0x8];
2161 u8 deth_sqpn[0x18];
2162
2163 u8 reserved_at_420[0x20];
e281682b 2164
b4ff3a36 2165 u8 reserved_at_440[0x8];
e281682b
SM		 2166 u8 last_acked_psn[0x18];
2167
b4ff3a36 2168 u8 reserved_at_460[0x8];
e281682b
SM		 2169 u8 ssn[0x18];
2170
b4ff3a36 2171 u8 reserved_at_480[0x8];
e281682b 2172 u8 log_rra_max[0x3];
b4ff3a36 2173 u8 reserved_at_48b[0x1];
e281682b
SM		 2174 u8 atomic_mode[0x4];
2175 u8 rre[0x1];
2176 u8 rwe[0x1];
2177 u8 rae[0x1];
b4ff3a36 2178 u8 reserved_at_493[0x1];
e281682b 2179 u8 page_offset[0x6];
b4ff3a36 2180 u8 reserved_at_49a[0x3];
e281682b
SM		 2181 u8 cd_slave_receive[0x1];
2182 u8 cd_slave_send[0x1];
2183 u8 cd_master[0x1];
2184
b4ff3a36 2185 u8 reserved_at_4a0[0x3];
e281682b
SM		 2186 u8 min_rnr_nak[0x5];
2187 u8 next_rcv_psn[0x18];
2188
b4ff3a36 2189 u8 reserved_at_4c0[0x8];
e281682b
SM		 2190 u8 xrcd[0x18];
2191
b4ff3a36 2192 u8 reserved_at_4e0[0x8];
e281682b
SM		 2193 u8 cqn_rcv[0x18];
2194
2195 u8 dbr_addr[0x40];
2196
2197 u8 q_key[0x20];
2198
b4ff3a36 2199 u8 reserved_at_560[0x5];
e281682b 2200 u8 rq_type[0x3];
7486216b 2201 u8 srqn_rmpn_xrqn[0x18];
e281682b 2202
b4ff3a36 2203 u8 reserved_at_580[0x8];
e281682b
SM		 2204 u8 rmsn[0x18];
2205
2206 u8 hw_sq_wqebb_counter[0x10];
2207 u8 sw_sq_wqebb_counter[0x10];
2208
2209 u8 hw_rq_counter[0x20];
2210
2211 u8 sw_rq_counter[0x20];
2212
b4ff3a36 2213 u8 reserved_at_600[0x20];
e281682b 2214
b4ff3a36 2215 u8 reserved_at_620[0xf];
e281682b
SM		 2216 u8 cgs[0x1];
2217 u8 cs_req[0x8];
2218 u8 cs_res[0x8];
2219
2220 u8 dc_access_key[0x40];
2221
b4ff3a36 2222 u8 reserved_at_680[0xc0];
e281682b
SM		 2223};
2224
2225struct mlx5_ifc_roce_addr_layout_bits {
2226 u8 source_l3_address[16][0x8];
2227
b4ff3a36 2228 u8 reserved_at_80[0x3];
e281682b
SM		 2229 u8 vlan_valid[0x1];
2230 u8 vlan_id[0xc];
2231 u8 source_mac_47_32[0x10];
2232
2233 u8 source_mac_31_0[0x20];
2234
b4ff3a36 2235 u8 reserved_at_c0[0x14];
e281682b
SM		 2236 u8 roce_l3_type[0x4];
2237 u8 roce_version[0x8];
2238
b4ff3a36 2239 u8 reserved_at_e0[0x20];
e281682b
SM		 2240};
2241
2242union mlx5_ifc_hca_cap_union_bits {
2243 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2244 struct mlx5_ifc_odp_cap_bits odp_cap;
2245 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2246 struct mlx5_ifc_roce_cap_bits roce_cap;
2247 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2248 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2249 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2250 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2251 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2252 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2253 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2254 u8 reserved_at_0[0x8000];
e281682b
SM		 2255};
2256
2257enum {
2258 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2259 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2260 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2261 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2262 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2263 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2264 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2265};
2266
2267struct mlx5_ifc_flow_context_bits {
b4ff3a36 2268 u8 reserved_at_0[0x20];
e281682b
SM		 2269
2270 u8 group_id[0x20];
2271
b4ff3a36 2272 u8 reserved_at_40[0x8];
e281682b
SM		 2273 u8 flow_tag[0x18];
2274
b4ff3a36 2275 u8 reserved_at_60[0x10];
e281682b
SM		 2276 u8 action[0x10];
2277
b4ff3a36 2278 u8 reserved_at_80[0x8];
e281682b
SM		 2279 u8 destination_list_size[0x18];
2280
9dc0b289
AV		 2281 u8 reserved_at_a0[0x8];
2282 u8 flow_counter_list_size[0x18];
2283
7adbde20
HHZ		 2284 u8 encap_id[0x20];
2285
2a69cb9f
OG		 2286 u8 modify_header_id[0x20];
2287
2288 u8 reserved_at_100[0x100];
e281682b
SM		 2289
2290 struct mlx5_ifc_fte_match_param_bits match_value;
2291
b4ff3a36 2292 u8 reserved_at_1200[0x600];
e281682b 2293
9dc0b289 2294 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2295};
2296
2297enum {
2298 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2299 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2300};
2301
2302struct mlx5_ifc_xrc_srqc_bits {
2303 u8 state[0x4];
2304 u8 log_xrc_srq_size[0x4];
b4ff3a36 2305 u8 reserved_at_8[0x18];
e281682b
SM		 2306
2307 u8 wq_signature[0x1];
2308 u8 cont_srq[0x1];
b4ff3a36 2309 u8 reserved_at_22[0x1];
e281682b
SM		 2310 u8 rlky[0x1];
2311 u8 basic_cyclic_rcv_wqe[0x1];
2312 u8 log_rq_stride[0x3];
2313 u8 xrcd[0x18];
2314
2315 u8 page_offset[0x6];
b4ff3a36 2316 u8 reserved_at_46[0x2];
e281682b
SM		 2317 u8 cqn[0x18];
2318
b4ff3a36 2319 u8 reserved_at_60[0x20];
e281682b
SM		 2320
2321 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2322 u8 reserved_at_81[0x1];
e281682b
SM		 2323 u8 log_page_size[0x6];
2324 u8 user_index[0x18];
2325
b4ff3a36 2326 u8 reserved_at_a0[0x20];
e281682b 2327
b4ff3a36 2328 u8 reserved_at_c0[0x8];
e281682b
SM		 2329 u8 pd[0x18];
2330
2331 u8 lwm[0x10];
2332 u8 wqe_cnt[0x10];
2333
b4ff3a36 2334 u8 reserved_at_100[0x40];
e281682b
SM		 2335
2336 u8 db_record_addr_h[0x20];
2337
2338 u8 db_record_addr_l[0x1e];
b4ff3a36 2339 u8 reserved_at_17e[0x2];
e281682b 2340
b4ff3a36 2341 u8 reserved_at_180[0x80];
e281682b
SM		 2342};
2343
2344struct mlx5_ifc_traffic_counter_bits {
2345 u8 packets[0x40];
2346
2347 u8 octets[0x40];
2348};
2349
2350struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2351 u8 strict_lag_tx_port_affinity[0x1];
2352 u8 reserved_at_1[0x3];
2353 u8 lag_tx_port_affinity[0x04];
2354
2355 u8 reserved_at_8[0x4];
e281682b 2356 u8 prio[0x4];
b4ff3a36 2357 u8 reserved_at_10[0x10];
e281682b 2358
b4ff3a36 2359 u8 reserved_at_20[0x100];
e281682b 2360
b4ff3a36 2361 u8 reserved_at_120[0x8];
e281682b
SM		 2362 u8 transport_domain[0x18];
2363
500a3d0d
ES		 2364 u8 reserved_at_140[0x8];
2365 u8 underlay_qpn[0x18];
2366 u8 reserved_at_160[0x3a0];
e281682b
SM		 2367};
2368
2369enum {
2370 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2371 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2372};
2373
2374enum {
2375 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2376 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2377};
2378
2379enum {
2be6967c
SM		 2380 MLX5_RX_HASH_FN_NONE = 0x0,
2381 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2382 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2383};
2384
2385enum {
2386 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2387 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2388};
2389
2390struct mlx5_ifc_tirc_bits {
b4ff3a36 2391 u8 reserved_at_0[0x20];
e281682b
SM		 2392
2393 u8 disp_type[0x4];
b4ff3a36 2394 u8 reserved_at_24[0x1c];
e281682b 2395
b4ff3a36 2396 u8 reserved_at_40[0x40];
e281682b 2397
b4ff3a36 2398 u8 reserved_at_80[0x4];
e281682b
SM		 2399 u8 lro_timeout_period_usecs[0x10];
2400 u8 lro_enable_mask[0x4];
2401 u8 lro_max_ip_payload_size[0x8];
2402
b4ff3a36 2403 u8 reserved_at_a0[0x40];
e281682b 2404
b4ff3a36 2405 u8 reserved_at_e0[0x8];
e281682b
SM		 2406 u8 inline_rqn[0x18];
2407
2408 u8 rx_hash_symmetric[0x1];
b4ff3a36 2409 u8 reserved_at_101[0x1];
e281682b 2410 u8 tunneled_offload_en[0x1];
b4ff3a36 2411 u8 reserved_at_103[0x5];
e281682b
SM		 2412 u8 indirect_table[0x18];
2413
2414 u8 rx_hash_fn[0x4];
b4ff3a36 2415 u8 reserved_at_124[0x2];
e281682b
SM		 2416 u8 self_lb_block[0x2];
2417 u8 transport_domain[0x18];
2418
2419 u8 rx_hash_toeplitz_key[10][0x20];
2420
2421 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2422
2423 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2424
b4ff3a36 2425 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2426};
2427
2428enum {
2429 MLX5_SRQC_STATE_GOOD = 0x0,
2430 MLX5_SRQC_STATE_ERROR = 0x1,
2431};
2432
2433struct mlx5_ifc_srqc_bits {
2434 u8 state[0x4];
2435 u8 log_srq_size[0x4];
b4ff3a36 2436 u8 reserved_at_8[0x18];
e281682b
SM		 2437
2438 u8 wq_signature[0x1];
2439 u8 cont_srq[0x1];
b4ff3a36 2440 u8 reserved_at_22[0x1];
e281682b 2441 u8 rlky[0x1];
b4ff3a36 2442 u8 reserved_at_24[0x1];
e281682b
SM		 2443 u8 log_rq_stride[0x3];
2444 u8 xrcd[0x18];
2445
2446 u8 page_offset[0x6];
b4ff3a36 2447 u8 reserved_at_46[0x2];
e281682b
SM		 2448 u8 cqn[0x18];
2449
b4ff3a36 2450 u8 reserved_at_60[0x20];
e281682b 2451
b4ff3a36 2452 u8 reserved_at_80[0x2];
e281682b 2453 u8 log_page_size[0x6];
b4ff3a36 2454 u8 reserved_at_88[0x18];
e281682b 2455
b4ff3a36 2456 u8 reserved_at_a0[0x20];
e281682b 2457
b4ff3a36 2458 u8 reserved_at_c0[0x8];
e281682b
SM		 2459 u8 pd[0x18];
2460
2461 u8 lwm[0x10];
2462 u8 wqe_cnt[0x10];
2463
b4ff3a36 2464 u8 reserved_at_100[0x40];
e281682b 2465
01949d01 2466 u8 dbr_addr[0x40];
e281682b 2467
b4ff3a36 2468 u8 reserved_at_180[0x80];
e281682b
SM		 2469};
2470
2471enum {
2472 MLX5_SQC_STATE_RST = 0x0,
2473 MLX5_SQC_STATE_RDY = 0x1,
2474 MLX5_SQC_STATE_ERR = 0x3,
2475};
2476
2477struct mlx5_ifc_sqc_bits {
2478 u8 rlky[0x1];
2479 u8 cd_master[0x1];
2480 u8 fre[0x1];
2481 u8 flush_in_error_en[0x1];
795b609c 2482 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2483 u8 min_wqe_inline_mode[0x3];
e281682b 2484 u8 state[0x4];
7d5e1423 2485 u8 reg_umr[0x1];
547eede0
IT		 2486 u8 allow_swp[0x1];
2487 u8 reserved_at_e[0x12];
e281682b 2488
b4ff3a36 2489 u8 reserved_at_20[0x8];
e281682b
SM		 2490 u8 user_index[0x18];
2491
b4ff3a36 2492 u8 reserved_at_40[0x8];
e281682b
SM		 2493 u8 cqn[0x18];
2494
7486216b 2495 u8 reserved_at_60[0x90];
e281682b 2496
7486216b 2497 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2498 u8 tis_lst_sz[0x10];
b4ff3a36 2499 u8 reserved_at_110[0x10];
e281682b 2500
b4ff3a36 2501 u8 reserved_at_120[0x40];
e281682b 2502
b4ff3a36 2503 u8 reserved_at_160[0x8];
e281682b
SM		 2504 u8 tis_num_0[0x18];
2505
2506 struct mlx5_ifc_wq_bits wq;
2507};
2508
813f8540
MHY		 2509enum {
2510 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2511 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2512 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2513 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2514};
2515
2516struct mlx5_ifc_scheduling_context_bits {
2517 u8 element_type[0x8];
2518 u8 reserved_at_8[0x18];
2519
2520 u8 element_attributes[0x20];
2521
2522 u8 parent_element_id[0x20];
2523
2524 u8 reserved_at_60[0x40];
2525
2526 u8 bw_share[0x20];
2527
2528 u8 max_average_bw[0x20];
2529
2530 u8 reserved_at_e0[0x120];
2531};
2532
e281682b 2533struct mlx5_ifc_rqtc_bits {
b4ff3a36 2534 u8 reserved_at_0[0xa0];
e281682b 2535
b4ff3a36 2536 u8 reserved_at_a0[0x10];
e281682b
SM		 2537 u8 rqt_max_size[0x10];
2538
b4ff3a36 2539 u8 reserved_at_c0[0x10];
e281682b
SM		 2540 u8 rqt_actual_size[0x10];
2541
b4ff3a36 2542 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2543
2544 struct mlx5_ifc_rq_num_bits rq_num[0];
2545};
2546
2547enum {
2548 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2549 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2550};
2551
2552enum {
2553 MLX5_RQC_STATE_RST = 0x0,
2554 MLX5_RQC_STATE_RDY = 0x1,
2555 MLX5_RQC_STATE_ERR = 0x3,
2556};
2557
2558struct mlx5_ifc_rqc_bits {
2559 u8 rlky[0x1];
03404e8a 2560 u8 delay_drop_en[0x1];
7d5e1423 2561 u8 scatter_fcs[0x1];
e281682b
SM		 2562 u8 vsd[0x1];
2563 u8 mem_rq_type[0x4];
2564 u8 state[0x4];
b4ff3a36 2565 u8 reserved_at_c[0x1];
e281682b 2566 u8 flush_in_error_en[0x1];
b4ff3a36 2567 u8 reserved_at_e[0x12];
e281682b 2568
b4ff3a36 2569 u8 reserved_at_20[0x8];
e281682b
SM		 2570 u8 user_index[0x18];
2571
b4ff3a36 2572 u8 reserved_at_40[0x8];
e281682b
SM		 2573 u8 cqn[0x18];
2574
2575 u8 counter_set_id[0x8];
b4ff3a36 2576 u8 reserved_at_68[0x18];
e281682b 2577
b4ff3a36 2578 u8 reserved_at_80[0x8];
e281682b
SM		 2579 u8 rmpn[0x18];
2580
b4ff3a36 2581 u8 reserved_at_a0[0xe0];
e281682b
SM		 2582
2583 struct mlx5_ifc_wq_bits wq;
2584};
2585
2586enum {
2587 MLX5_RMPC_STATE_RDY = 0x1,
2588 MLX5_RMPC_STATE_ERR = 0x3,
2589};
2590
2591struct mlx5_ifc_rmpc_bits {
b4ff3a36 2592 u8 reserved_at_0[0x8];
e281682b 2593 u8 state[0x4];
b4ff3a36 2594 u8 reserved_at_c[0x14];
e281682b
SM		 2595
2596 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2597 u8 reserved_at_21[0x1f];
e281682b 2598
b4ff3a36 2599 u8 reserved_at_40[0x140];
e281682b
SM		 2600
2601 struct mlx5_ifc_wq_bits wq;
2602};
2603
e281682b 2604struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2605 u8 reserved_at_0[0x5];
2606 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2607 u8 reserved_at_8[0x15];
2608 u8 disable_mc_local_lb[0x1];
2609 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2610 u8 roce_en[0x1];
2611
d82b7318 2612 u8 arm_change_event[0x1];
b4ff3a36 2613 u8 reserved_at_21[0x1a];
d82b7318
SM		 2614 u8 event_on_mtu[0x1];
2615 u8 event_on_promisc_change[0x1];
2616 u8 event_on_vlan_change[0x1];
2617 u8 event_on_mc_address_change[0x1];
2618 u8 event_on_uc_address_change[0x1];
e281682b 2619
b4ff3a36 2620 u8 reserved_at_40[0xf0];
d82b7318
SM		 2621
2622 u8 mtu[0x10];
2623
9efa7525
AS		 2624 u8 system_image_guid[0x40];
2625 u8 port_guid[0x40];
2626 u8 node_guid[0x40];
2627
b4ff3a36 2628 u8 reserved_at_200[0x140];
9efa7525 2629 u8 qkey_violation_counter[0x10];
b4ff3a36 2630 u8 reserved_at_350[0x430];
d82b7318
SM		 2631
2632 u8 promisc_uc[0x1];
2633 u8 promisc_mc[0x1];
2634 u8 promisc_all[0x1];
b4ff3a36 2635 u8 reserved_at_783[0x2];
e281682b 2636 u8 allowed_list_type[0x3];
b4ff3a36 2637 u8 reserved_at_788[0xc];
e281682b
SM		 2638 u8 allowed_list_size[0xc];
2639
2640 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2641
b4ff3a36 2642 u8 reserved_at_7e0[0x20];
e281682b
SM		 2643
2644 u8 current_uc_mac_address[0][0x40];
2645};
2646
2647enum {
2648 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2649 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2650 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2651 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2652};
2653
2654struct mlx5_ifc_mkc_bits {
b4ff3a36 2655 u8 reserved_at_0[0x1];
e281682b 2656 u8 free[0x1];
b4ff3a36 2657 u8 reserved_at_2[0xd];
e281682b
SM		 2658 u8 small_fence_on_rdma_read_response[0x1];
2659 u8 umr_en[0x1];
2660 u8 a[0x1];
2661 u8 rw[0x1];
2662 u8 rr[0x1];
2663 u8 lw[0x1];
2664 u8 lr[0x1];
2665 u8 access_mode[0x2];
b4ff3a36 2666 u8 reserved_at_18[0x8];
e281682b
SM		 2667
2668 u8 qpn[0x18];
2669 u8 mkey_7_0[0x8];
2670
b4ff3a36 2671 u8 reserved_at_40[0x20];
e281682b
SM		 2672
2673 u8 length64[0x1];
2674 u8 bsf_en[0x1];
2675 u8 sync_umr[0x1];
b4ff3a36 2676 u8 reserved_at_63[0x2];
e281682b 2677 u8 expected_sigerr_count[0x1];
b4ff3a36 2678 u8 reserved_at_66[0x1];
e281682b
SM		 2679 u8 en_rinval[0x1];
2680 u8 pd[0x18];
2681
2682 u8 start_addr[0x40];
2683
2684 u8 len[0x40];
2685
2686 u8 bsf_octword_size[0x20];
2687
b4ff3a36 2688 u8 reserved_at_120[0x80];
e281682b
SM		 2689
2690 u8 translations_octword_size[0x20];
2691
b4ff3a36 2692 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2693 u8 log_page_size[0x5];
2694
b4ff3a36 2695 u8 reserved_at_1e0[0x20];
e281682b
SM		 2696};
2697
2698struct mlx5_ifc_pkey_bits {
b4ff3a36 2699 u8 reserved_at_0[0x10];
e281682b
SM		 2700 u8 pkey[0x10];
2701};
2702
2703struct mlx5_ifc_array128_auto_bits {
2704 u8 array128_auto[16][0x8];
2705};
2706
2707struct mlx5_ifc_hca_vport_context_bits {
2708 u8 field_select[0x20];
2709
b4ff3a36 2710 u8 reserved_at_20[0xe0];
e281682b
SM		 2711
2712 u8 sm_virt_aware[0x1];
2713 u8 has_smi[0x1];
2714 u8 has_raw[0x1];
2715 u8 grh_required[0x1];
b4ff3a36 2716 u8 reserved_at_104[0xc];
707c4602
MD		 2717 u8 port_physical_state[0x4];
2718 u8 vport_state_policy[0x4];
2719 u8 port_state[0x4];
e281682b
SM		 2720 u8 vport_state[0x4];
2721
b4ff3a36 2722 u8 reserved_at_120[0x20];
707c4602
MD		 2723
2724 u8 system_image_guid[0x40];
e281682b
SM		 2725
2726 u8 port_guid[0x40];
2727
2728 u8 node_guid[0x40];
2729
2730 u8 cap_mask1[0x20];
2731
2732 u8 cap_mask1_field_select[0x20];
2733
2734 u8 cap_mask2[0x20];
2735
2736 u8 cap_mask2_field_select[0x20];
2737
b4ff3a36 2738 u8 reserved_at_280[0x80];
e281682b
SM		 2739
2740 u8 lid[0x10];
b4ff3a36 2741 u8 reserved_at_310[0x4];
e281682b
SM		 2742 u8 init_type_reply[0x4];
2743 u8 lmc[0x3];
2744 u8 subnet_timeout[0x5];
2745
2746 u8 sm_lid[0x10];
2747 u8 sm_sl[0x4];
b4ff3a36 2748 u8 reserved_at_334[0xc];
e281682b
SM		 2749
2750 u8 qkey_violation_counter[0x10];
2751 u8 pkey_violation_counter[0x10];
2752
b4ff3a36 2753 u8 reserved_at_360[0xca0];
e281682b
SM		 2754};
2755
d6666753 2756struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2757 u8 reserved_at_0[0x3];
d6666753
SM		 2758 u8 vport_svlan_strip[0x1];
2759 u8 vport_cvlan_strip[0x1];
2760 u8 vport_svlan_insert[0x1];
2761 u8 vport_cvlan_insert[0x2];
b4ff3a36 2762 u8 reserved_at_8[0x18];
d6666753 2763
b4ff3a36 2764 u8 reserved_at_20[0x20];
d6666753
SM		 2765
2766 u8 svlan_cfi[0x1];
2767 u8 svlan_pcp[0x3];
2768 u8 svlan_id[0xc];
2769 u8 cvlan_cfi[0x1];
2770 u8 cvlan_pcp[0x3];
2771 u8 cvlan_id[0xc];
2772
b4ff3a36 2773 u8 reserved_at_60[0x7a0];
d6666753
SM		 2774};
2775
e281682b
SM		 2776enum {
2777 MLX5_EQC_STATUS_OK = 0x0,
2778 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2779};
2780
2781enum {
2782 MLX5_EQC_ST_ARMED = 0x9,
2783 MLX5_EQC_ST_FIRED = 0xa,
2784};
2785
2786struct mlx5_ifc_eqc_bits {
2787 u8 status[0x4];
b4ff3a36 2788 u8 reserved_at_4[0x9];
e281682b
SM		 2789 u8 ec[0x1];
2790 u8 oi[0x1];
b4ff3a36 2791 u8 reserved_at_f[0x5];
e281682b 2792 u8 st[0x4];
b4ff3a36 2793 u8 reserved_at_18[0x8];
e281682b 2794
b4ff3a36 2795 u8 reserved_at_20[0x20];
e281682b 2796
b4ff3a36 2797 u8 reserved_at_40[0x14];
e281682b 2798 u8 page_offset[0x6];
b4ff3a36 2799 u8 reserved_at_5a[0x6];
e281682b 2800
b4ff3a36 2801 u8 reserved_at_60[0x3];
e281682b
SM		 2802 u8 log_eq_size[0x5];
2803 u8 uar_page[0x18];
2804
b4ff3a36 2805 u8 reserved_at_80[0x20];
e281682b 2806
b4ff3a36 2807 u8 reserved_at_a0[0x18];
e281682b
SM		 2808 u8 intr[0x8];
2809
b4ff3a36 2810 u8 reserved_at_c0[0x3];
e281682b 2811 u8 log_page_size[0x5];
b4ff3a36 2812 u8 reserved_at_c8[0x18];
e281682b 2813
b4ff3a36 2814 u8 reserved_at_e0[0x60];
e281682b 2815
b4ff3a36 2816 u8 reserved_at_140[0x8];
e281682b
SM		 2817 u8 consumer_counter[0x18];
2818
b4ff3a36 2819 u8 reserved_at_160[0x8];
e281682b
SM		 2820 u8 producer_counter[0x18];
2821
b4ff3a36 2822 u8 reserved_at_180[0x80];
e281682b
SM		 2823};
2824
2825enum {
2826 MLX5_DCTC_STATE_ACTIVE = 0x0,
2827 MLX5_DCTC_STATE_DRAINING = 0x1,
2828 MLX5_DCTC_STATE_DRAINED = 0x2,
2829};
2830
2831enum {
2832 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2833 MLX5_DCTC_CS_RES_NA = 0x1,
2834 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2835};
2836
2837enum {
2838 MLX5_DCTC_MTU_256_BYTES = 0x1,
2839 MLX5_DCTC_MTU_512_BYTES = 0x2,
2840 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2841 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2842 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2843};
2844
2845struct mlx5_ifc_dctc_bits {
b4ff3a36 2846 u8 reserved_at_0[0x4];
e281682b 2847 u8 state[0x4];
b4ff3a36 2848 u8 reserved_at_8[0x18];
e281682b 2849
b4ff3a36 2850 u8 reserved_at_20[0x8];
e281682b
SM		 2851 u8 user_index[0x18];
2852
b4ff3a36 2853 u8 reserved_at_40[0x8];
e281682b
SM		 2854 u8 cqn[0x18];
2855
2856 u8 counter_set_id[0x8];
2857 u8 atomic_mode[0x4];
2858 u8 rre[0x1];
2859 u8 rwe[0x1];
2860 u8 rae[0x1];
2861 u8 atomic_like_write_en[0x1];
2862 u8 latency_sensitive[0x1];
2863 u8 rlky[0x1];
2864 u8 free_ar[0x1];
b4ff3a36 2865 u8 reserved_at_73[0xd];
e281682b 2866
b4ff3a36 2867 u8 reserved_at_80[0x8];
e281682b 2868 u8 cs_res[0x8];
b4ff3a36 2869 u8 reserved_at_90[0x3];
e281682b 2870 u8 min_rnr_nak[0x5];
b4ff3a36 2871 u8 reserved_at_98[0x8];
e281682b 2872
b4ff3a36 2873 u8 reserved_at_a0[0x8];
7486216b 2874 u8 srqn_xrqn[0x18];
e281682b 2875
b4ff3a36 2876 u8 reserved_at_c0[0x8];
e281682b
SM		 2877 u8 pd[0x18];
2878
2879 u8 tclass[0x8];
b4ff3a36 2880 u8 reserved_at_e8[0x4];
e281682b
SM		 2881 u8 flow_label[0x14];
2882
2883 u8 dc_access_key[0x40];
2884
b4ff3a36 2885 u8 reserved_at_140[0x5];
e281682b
SM		 2886 u8 mtu[0x3];
2887 u8 port[0x8];
2888 u8 pkey_index[0x10];
2889
b4ff3a36 2890 u8 reserved_at_160[0x8];
e281682b 2891 u8 my_addr_index[0x8];
b4ff3a36 2892 u8 reserved_at_170[0x8];
e281682b
SM		 2893 u8 hop_limit[0x8];
2894
2895 u8 dc_access_key_violation_count[0x20];
2896
b4ff3a36 2897 u8 reserved_at_1a0[0x14];
e281682b
SM		 2898 u8 dei_cfi[0x1];
2899 u8 eth_prio[0x3];
2900 u8 ecn[0x2];
2901 u8 dscp[0x6];
2902
b4ff3a36 2903 u8 reserved_at_1c0[0x40];
e281682b
SM		 2904};
2905
2906enum {
2907 MLX5_CQC_STATUS_OK = 0x0,
2908 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2909 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2910};
2911
2912enum {
2913 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2914 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2915};
2916
2917enum {
2918 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2919 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2920 MLX5_CQC_ST_FIRED = 0xa,
2921};
2922
7d5e1423
SM		 2923enum {
2924 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2925 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2926 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2927};
2928
e281682b
SM		 2929struct mlx5_ifc_cqc_bits {
2930 u8 status[0x4];
b4ff3a36 2931 u8 reserved_at_4[0x4];
e281682b
SM		 2932 u8 cqe_sz[0x3];
2933 u8 cc[0x1];
b4ff3a36 2934 u8 reserved_at_c[0x1];
e281682b
SM		 2935 u8 scqe_break_moderation_en[0x1];
2936 u8 oi[0x1];
7d5e1423
SM		 2937 u8 cq_period_mode[0x2];
2938 u8 cqe_comp_en[0x1];
e281682b
SM		 2939 u8 mini_cqe_res_format[0x2];
2940 u8 st[0x4];
b4ff3a36 2941 u8 reserved_at_18[0x8];
e281682b 2942
b4ff3a36 2943 u8 reserved_at_20[0x20];
e281682b 2944
b4ff3a36 2945 u8 reserved_at_40[0x14];
e281682b 2946 u8 page_offset[0x6];
b4ff3a36 2947 u8 reserved_at_5a[0x6];
e281682b 2948
b4ff3a36 2949 u8 reserved_at_60[0x3];
e281682b
SM		 2950 u8 log_cq_size[0x5];
2951 u8 uar_page[0x18];
2952
b4ff3a36 2953 u8 reserved_at_80[0x4];
e281682b
SM		 2954 u8 cq_period[0xc];
2955 u8 cq_max_count[0x10];
2956
b4ff3a36 2957 u8 reserved_at_a0[0x18];
e281682b
SM		 2958 u8 c_eqn[0x8];
2959
b4ff3a36 2960 u8 reserved_at_c0[0x3];
e281682b 2961 u8 log_page_size[0x5];
b4ff3a36 2962 u8 reserved_at_c8[0x18];
e281682b 2963
b4ff3a36 2964 u8 reserved_at_e0[0x20];
e281682b 2965
b4ff3a36 2966 u8 reserved_at_100[0x8];
e281682b
SM		 2967 u8 last_notified_index[0x18];
2968
b4ff3a36 2969 u8 reserved_at_120[0x8];
e281682b
SM		 2970 u8 last_solicit_index[0x18];
2971
b4ff3a36 2972 u8 reserved_at_140[0x8];
e281682b
SM		 2973 u8 consumer_counter[0x18];
2974
b4ff3a36 2975 u8 reserved_at_160[0x8];
e281682b
SM		 2976 u8 producer_counter[0x18];
2977
b4ff3a36 2978 u8 reserved_at_180[0x40];
e281682b
SM		 2979
2980 u8 dbr_addr[0x40];
2981};
2982
2983union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2984 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2985 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2986 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2987 u8 reserved_at_0[0x800];
e281682b
SM		 2988};
2989
2990struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2991 u8 reserved_at_0[0xc0];
e281682b 2992
b4ff3a36 2993 u8 reserved_at_c0[0x8];
211e6c80
MD		 2994 u8 ieee_vendor_id[0x18];
2995
b4ff3a36 2996 u8 reserved_at_e0[0x10];
e281682b
SM		 2997 u8 vsd_vendor_id[0x10];
2998
2999 u8 vsd[208][0x8];
3000
3001 u8 vsd_contd_psid[16][0x8];
3002};
3003
7486216b
SM		 3004enum {
3005 MLX5_XRQC_STATE_GOOD = 0x0,
3006 MLX5_XRQC_STATE_ERROR = 0x1,
3007};
3008
3009enum {
3010 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3011 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3012};
3013
3014enum {
3015 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3016};
3017
3018struct mlx5_ifc_tag_matching_topology_context_bits {
3019 u8 log_matching_list_sz[0x4];
3020 u8 reserved_at_4[0xc];
3021 u8 append_next_index[0x10];
3022
3023 u8 sw_phase_cnt[0x10];
3024 u8 hw_phase_cnt[0x10];
3025
3026 u8 reserved_at_40[0x40];
3027};
3028
3029struct mlx5_ifc_xrqc_bits {
3030 u8 state[0x4];
3031 u8 rlkey[0x1];
3032 u8 reserved_at_5[0xf];
3033 u8 topology[0x4];
3034 u8 reserved_at_18[0x4];
3035 u8 offload[0x4];
3036
3037 u8 reserved_at_20[0x8];
3038 u8 user_index[0x18];
3039
3040 u8 reserved_at_40[0x8];
3041 u8 cqn[0x18];
3042
3043 u8 reserved_at_60[0xa0];
3044
3045 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3046
6e44636a 3047 u8 reserved_at_180[0x280];
7486216b
SM		 3048
3049 struct mlx5_ifc_wq_bits wq;
3050};
3051
e281682b
SM		 3052union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3053 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3054 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3055 u8 reserved_at_0[0x20];
e281682b
SM		 3056};
3057
3058union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3059 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3060 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3061 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3062 u8 reserved_at_0[0x20];
e281682b
SM		 3063};
3064
3065union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3066 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3067 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3068 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3069 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3070 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3071 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3072 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3073 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3074 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3075 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3076 u8 reserved_at_0[0x7c0];
e281682b
SM		 3077};
3078
8ed1a630
GP		 3079union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3080 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3081 u8 reserved_at_0[0x7c0];
3082};
3083
e281682b
SM		 3084union mlx5_ifc_event_auto_bits {
3085 struct mlx5_ifc_comp_event_bits comp_event;
3086 struct mlx5_ifc_dct_events_bits dct_events;
3087 struct mlx5_ifc_qp_events_bits qp_events;
3088 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3089 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3090 struct mlx5_ifc_cq_error_bits cq_error;
3091 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3092 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3093 struct mlx5_ifc_gpio_event_bits gpio_event;
3094 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3095 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3096 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3097 u8 reserved_at_0[0xe0];
e281682b
SM		 3098};
3099
3100struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3101 u8 reserved_at_0[0x100];
e281682b
SM		 3102
3103 u8 assert_existptr[0x20];
3104
3105 u8 assert_callra[0x20];
3106
b4ff3a36 3107 u8 reserved_at_140[0x40];
e281682b
SM		 3108
3109 u8 fw_version[0x20];
3110
3111 u8 hw_id[0x20];
3112
b4ff3a36 3113 u8 reserved_at_1c0[0x20];
e281682b
SM		 3114
3115 u8 irisc_index[0x8];
3116 u8 synd[0x8];
3117 u8 ext_synd[0x10];
3118};
3119
3120struct mlx5_ifc_register_loopback_control_bits {
3121 u8 no_lb[0x1];
b4ff3a36 3122 u8 reserved_at_1[0x7];
e281682b 3123 u8 port[0x8];
b4ff3a36 3124 u8 reserved_at_10[0x10];
e281682b 3125
b4ff3a36 3126 u8 reserved_at_20[0x60];
e281682b
SM		 3127};
3128
813f8540
MHY		 3129struct mlx5_ifc_vport_tc_element_bits {
3130 u8 traffic_class[0x4];
3131 u8 reserved_at_4[0xc];
3132 u8 vport_number[0x10];
3133};
3134
3135struct mlx5_ifc_vport_element_bits {
3136 u8 reserved_at_0[0x10];
3137 u8 vport_number[0x10];
3138};
3139
3140enum {
3141 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3142 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3143 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3144};
3145
3146struct mlx5_ifc_tsar_element_bits {
3147 u8 reserved_at_0[0x8];
3148 u8 tsar_type[0x8];
3149 u8 reserved_at_10[0x10];
3150};
3151
8812c24d
MD		 3152enum {
3153 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3154 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3155};
3156
e281682b
SM		 3157struct mlx5_ifc_teardown_hca_out_bits {
3158 u8 status[0x8];
b4ff3a36 3159 u8 reserved_at_8[0x18];
e281682b
SM		 3160
3161 u8 syndrome[0x20];
3162
8812c24d
MD		 3163 u8 reserved_at_40[0x3f];
3164
3165 u8 force_state[0x1];
e281682b
SM		 3166};
3167
3168enum {
3169 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3170 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3171};
3172
3173struct mlx5_ifc_teardown_hca_in_bits {
3174 u8 opcode[0x10];
b4ff3a36 3175 u8 reserved_at_10[0x10];
e281682b 3176
b4ff3a36 3177 u8 reserved_at_20[0x10];
e281682b
SM		 3178 u8 op_mod[0x10];
3179
b4ff3a36 3180 u8 reserved_at_40[0x10];
e281682b
SM		 3181 u8 profile[0x10];
3182
b4ff3a36 3183 u8 reserved_at_60[0x20];
e281682b
SM		 3184};
3185
3186struct mlx5_ifc_sqerr2rts_qp_out_bits {
3187 u8 status[0x8];
b4ff3a36 3188 u8 reserved_at_8[0x18];
e281682b
SM		 3189
3190 u8 syndrome[0x20];
3191
b4ff3a36 3192 u8 reserved_at_40[0x40];
e281682b
SM		 3193};
3194
3195struct mlx5_ifc_sqerr2rts_qp_in_bits {
3196 u8 opcode[0x10];
b4ff3a36 3197 u8 reserved_at_10[0x10];
e281682b 3198
b4ff3a36 3199 u8 reserved_at_20[0x10];
e281682b
SM		 3200 u8 op_mod[0x10];
3201
b4ff3a36 3202 u8 reserved_at_40[0x8];
e281682b
SM		 3203 u8 qpn[0x18];
3204
b4ff3a36 3205 u8 reserved_at_60[0x20];
e281682b
SM		 3206
3207 u8 opt_param_mask[0x20];
3208
b4ff3a36 3209 u8 reserved_at_a0[0x20];
e281682b
SM		 3210
3211 struct mlx5_ifc_qpc_bits qpc;
3212
b4ff3a36 3213 u8 reserved_at_800[0x80];
e281682b
SM		 3214};
3215
3216struct mlx5_ifc_sqd2rts_qp_out_bits {
3217 u8 status[0x8];
b4ff3a36 3218 u8 reserved_at_8[0x18];
e281682b
SM		 3219
3220 u8 syndrome[0x20];
3221
b4ff3a36 3222 u8 reserved_at_40[0x40];
e281682b
SM		 3223};
3224
3225struct mlx5_ifc_sqd2rts_qp_in_bits {
3226 u8 opcode[0x10];
b4ff3a36 3227 u8 reserved_at_10[0x10];
e281682b 3228
b4ff3a36 3229 u8 reserved_at_20[0x10];
e281682b
SM		 3230 u8 op_mod[0x10];
3231
b4ff3a36 3232 u8 reserved_at_40[0x8];
e281682b
SM		 3233 u8 qpn[0x18];
3234
b4ff3a36 3235 u8 reserved_at_60[0x20];
e281682b
SM		 3236
3237 u8 opt_param_mask[0x20];
3238
b4ff3a36 3239 u8 reserved_at_a0[0x20];
e281682b
SM		 3240
3241 struct mlx5_ifc_qpc_bits qpc;
3242
b4ff3a36 3243 u8 reserved_at_800[0x80];
e281682b
SM		 3244};
3245
3246struct mlx5_ifc_set_roce_address_out_bits {
3247 u8 status[0x8];
b4ff3a36 3248 u8 reserved_at_8[0x18];
e281682b
SM		 3249
3250 u8 syndrome[0x20];
3251
b4ff3a36 3252 u8 reserved_at_40[0x40];
e281682b
SM		 3253};
3254
3255struct mlx5_ifc_set_roce_address_in_bits {
3256 u8 opcode[0x10];
b4ff3a36 3257 u8 reserved_at_10[0x10];
e281682b 3258
b4ff3a36 3259 u8 reserved_at_20[0x10];
e281682b
SM		 3260 u8 op_mod[0x10];
3261
3262 u8 roce_address_index[0x10];
b4ff3a36 3263 u8 reserved_at_50[0x10];
e281682b 3264
b4ff3a36 3265 u8 reserved_at_60[0x20];
e281682b
SM		 3266
3267 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3268};
3269
3270struct mlx5_ifc_set_mad_demux_out_bits {
3271 u8 status[0x8];
b4ff3a36 3272 u8 reserved_at_8[0x18];
e281682b
SM		 3273
3274 u8 syndrome[0x20];
3275
b4ff3a36 3276 u8 reserved_at_40[0x40];
e281682b
SM		 3277};
3278
3279enum {
3280 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3281 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3282};
3283
3284struct mlx5_ifc_set_mad_demux_in_bits {
3285 u8 opcode[0x10];
b4ff3a36 3286 u8 reserved_at_10[0x10];
e281682b 3287
b4ff3a36 3288 u8 reserved_at_20[0x10];
e281682b
SM		 3289 u8 op_mod[0x10];
3290
b4ff3a36 3291 u8 reserved_at_40[0x20];
e281682b 3292
b4ff3a36 3293 u8 reserved_at_60[0x6];
e281682b 3294 u8 demux_mode[0x2];
b4ff3a36 3295 u8 reserved_at_68[0x18];
e281682b
SM		 3296};
3297
3298struct mlx5_ifc_set_l2_table_entry_out_bits {
3299 u8 status[0x8];
b4ff3a36 3300 u8 reserved_at_8[0x18];
e281682b
SM		 3301
3302 u8 syndrome[0x20];
3303
b4ff3a36 3304 u8 reserved_at_40[0x40];
e281682b
SM		 3305};
3306
3307struct mlx5_ifc_set_l2_table_entry_in_bits {
3308 u8 opcode[0x10];
b4ff3a36 3309 u8 reserved_at_10[0x10];
e281682b 3310
b4ff3a36 3311 u8 reserved_at_20[0x10];
e281682b
SM		 3312 u8 op_mod[0x10];
3313
b4ff3a36 3314 u8 reserved_at_40[0x60];
e281682b 3315
b4ff3a36 3316 u8 reserved_at_a0[0x8];
e281682b
SM		 3317 u8 table_index[0x18];
3318
b4ff3a36 3319 u8 reserved_at_c0[0x20];
e281682b 3320
b4ff3a36 3321 u8 reserved_at_e0[0x13];
e281682b
SM		 3322 u8 vlan_valid[0x1];
3323 u8 vlan[0xc];
3324
3325 struct mlx5_ifc_mac_address_layout_bits mac_address;
3326
b4ff3a36 3327 u8 reserved_at_140[0xc0];
e281682b
SM		 3328};
3329
3330struct mlx5_ifc_set_issi_out_bits {
3331 u8 status[0x8];
b4ff3a36 3332 u8 reserved_at_8[0x18];
e281682b
SM		 3333
3334 u8 syndrome[0x20];
3335
b4ff3a36 3336 u8 reserved_at_40[0x40];
e281682b
SM		 3337};
3338
3339struct mlx5_ifc_set_issi_in_bits {
3340 u8 opcode[0x10];
b4ff3a36 3341 u8 reserved_at_10[0x10];
e281682b 3342
b4ff3a36 3343 u8 reserved_at_20[0x10];
e281682b
SM		 3344 u8 op_mod[0x10];
3345
b4ff3a36 3346 u8 reserved_at_40[0x10];
e281682b
SM		 3347 u8 current_issi[0x10];
3348
b4ff3a36 3349 u8 reserved_at_60[0x20];
e281682b
SM		 3350};
3351
3352struct mlx5_ifc_set_hca_cap_out_bits {
3353 u8 status[0x8];
b4ff3a36 3354 u8 reserved_at_8[0x18];
e281682b
SM		 3355
3356 u8 syndrome[0x20];
3357
b4ff3a36 3358 u8 reserved_at_40[0x40];
e281682b
SM		 3359};
3360
3361struct mlx5_ifc_set_hca_cap_in_bits {
3362 u8 opcode[0x10];
b4ff3a36 3363 u8 reserved_at_10[0x10];
e281682b 3364
b4ff3a36 3365 u8 reserved_at_20[0x10];
e281682b
SM		 3366 u8 op_mod[0x10];
3367
b4ff3a36 3368 u8 reserved_at_40[0x40];
e281682b
SM		 3369
3370 union mlx5_ifc_hca_cap_union_bits capability;
3371};
3372
26a81453
MG		 3373enum {
3374 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3375 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3376 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3377 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3378};
3379
e281682b
SM		 3380struct mlx5_ifc_set_fte_out_bits {
3381 u8 status[0x8];
b4ff3a36 3382 u8 reserved_at_8[0x18];
e281682b
SM		 3383
3384 u8 syndrome[0x20];
3385
b4ff3a36 3386 u8 reserved_at_40[0x40];
e281682b
SM		 3387};
3388
3389struct mlx5_ifc_set_fte_in_bits {
3390 u8 opcode[0x10];
b4ff3a36 3391 u8 reserved_at_10[0x10];
e281682b 3392
b4ff3a36 3393 u8 reserved_at_20[0x10];
e281682b
SM		 3394 u8 op_mod[0x10];
3395
7d5e1423
SM		 3396 u8 other_vport[0x1];
3397 u8 reserved_at_41[0xf];
3398 u8 vport_number[0x10];
3399
3400 u8 reserved_at_60[0x20];
e281682b
SM		 3401
3402 u8 table_type[0x8];
b4ff3a36 3403 u8 reserved_at_88[0x18];
e281682b 3404
b4ff3a36 3405 u8 reserved_at_a0[0x8];
e281682b
SM		 3406 u8 table_id[0x18];
3407
b4ff3a36 3408 u8 reserved_at_c0[0x18];
26a81453
MG		 3409 u8 modify_enable_mask[0x8];
3410
b4ff3a36 3411 u8 reserved_at_e0[0x20];
e281682b
SM		 3412
3413 u8 flow_index[0x20];
3414
b4ff3a36 3415 u8 reserved_at_120[0xe0];
e281682b
SM		 3416
3417 struct mlx5_ifc_flow_context_bits flow_context;
3418};
3419
3420struct mlx5_ifc_rts2rts_qp_out_bits {
3421 u8 status[0x8];
b4ff3a36 3422 u8 reserved_at_8[0x18];
e281682b
SM		 3423
3424 u8 syndrome[0x20];
3425
b4ff3a36 3426 u8 reserved_at_40[0x40];
e281682b
SM		 3427};
3428
3429struct mlx5_ifc_rts2rts_qp_in_bits {
3430 u8 opcode[0x10];
b4ff3a36 3431 u8 reserved_at_10[0x10];
e281682b 3432
b4ff3a36 3433 u8 reserved_at_20[0x10];
e281682b
SM		 3434 u8 op_mod[0x10];
3435
b4ff3a36 3436 u8 reserved_at_40[0x8];
e281682b
SM		 3437 u8 qpn[0x18];
3438
b4ff3a36 3439 u8 reserved_at_60[0x20];
e281682b
SM		 3440
3441 u8 opt_param_mask[0x20];
3442
b4ff3a36 3443 u8 reserved_at_a0[0x20];
e281682b
SM		 3444
3445 struct mlx5_ifc_qpc_bits qpc;
3446
b4ff3a36 3447 u8 reserved_at_800[0x80];
e281682b
SM		 3448};
3449
3450struct mlx5_ifc_rtr2rts_qp_out_bits {
3451 u8 status[0x8];
b4ff3a36 3452 u8 reserved_at_8[0x18];
e281682b
SM		 3453
3454 u8 syndrome[0x20];
3455
b4ff3a36 3456 u8 reserved_at_40[0x40];
e281682b
SM		 3457};
3458
3459struct mlx5_ifc_rtr2rts_qp_in_bits {
3460 u8 opcode[0x10];
b4ff3a36 3461 u8 reserved_at_10[0x10];
e281682b 3462
b4ff3a36 3463 u8 reserved_at_20[0x10];
e281682b
SM		 3464 u8 op_mod[0x10];
3465
b4ff3a36 3466 u8 reserved_at_40[0x8];
e281682b
SM		 3467 u8 qpn[0x18];
3468
b4ff3a36 3469 u8 reserved_at_60[0x20];
e281682b
SM		 3470
3471 u8 opt_param_mask[0x20];
3472
b4ff3a36 3473 u8 reserved_at_a0[0x20];
e281682b
SM		 3474
3475 struct mlx5_ifc_qpc_bits qpc;
3476
b4ff3a36 3477 u8 reserved_at_800[0x80];
e281682b
SM		 3478};
3479
3480struct mlx5_ifc_rst2init_qp_out_bits {
3481 u8 status[0x8];
b4ff3a36 3482 u8 reserved_at_8[0x18];
e281682b
SM		 3483
3484 u8 syndrome[0x20];
3485
b4ff3a36 3486 u8 reserved_at_40[0x40];
e281682b
SM		 3487};
3488
3489struct mlx5_ifc_rst2init_qp_in_bits {
3490 u8 opcode[0x10];
b4ff3a36 3491 u8 reserved_at_10[0x10];
e281682b 3492
b4ff3a36 3493 u8 reserved_at_20[0x10];
e281682b
SM		 3494 u8 op_mod[0x10];
3495
b4ff3a36 3496 u8 reserved_at_40[0x8];
e281682b
SM		 3497 u8 qpn[0x18];
3498
b4ff3a36 3499 u8 reserved_at_60[0x20];
e281682b
SM		 3500
3501 u8 opt_param_mask[0x20];
3502
b4ff3a36 3503 u8 reserved_at_a0[0x20];
e281682b
SM		 3504
3505 struct mlx5_ifc_qpc_bits qpc;
3506
b4ff3a36 3507 u8 reserved_at_800[0x80];
e281682b
SM		 3508};
3509
7486216b
SM		 3510struct mlx5_ifc_query_xrq_out_bits {
3511 u8 status[0x8];
3512 u8 reserved_at_8[0x18];
3513
3514 u8 syndrome[0x20];
3515
3516 u8 reserved_at_40[0x40];
3517
3518 struct mlx5_ifc_xrqc_bits xrq_context;
3519};
3520
3521struct mlx5_ifc_query_xrq_in_bits {
3522 u8 opcode[0x10];
3523 u8 reserved_at_10[0x10];
3524
3525 u8 reserved_at_20[0x10];
3526 u8 op_mod[0x10];
3527
3528 u8 reserved_at_40[0x8];
3529 u8 xrqn[0x18];
3530
3531 u8 reserved_at_60[0x20];
3532};
3533
e281682b
SM		 3534struct mlx5_ifc_query_xrc_srq_out_bits {
3535 u8 status[0x8];
b4ff3a36 3536 u8 reserved_at_8[0x18];
e281682b
SM		 3537
3538 u8 syndrome[0x20];
3539
b4ff3a36 3540 u8 reserved_at_40[0x40];
e281682b
SM		 3541
3542 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3543
b4ff3a36 3544 u8 reserved_at_280[0x600];
e281682b
SM		 3545
3546 u8 pas[0][0x40];
3547};
3548
3549struct mlx5_ifc_query_xrc_srq_in_bits {
3550 u8 opcode[0x10];
b4ff3a36 3551 u8 reserved_at_10[0x10];
e281682b 3552
b4ff3a36 3553 u8 reserved_at_20[0x10];
e281682b
SM		 3554 u8 op_mod[0x10];
3555
b4ff3a36 3556 u8 reserved_at_40[0x8];
e281682b
SM		 3557 u8 xrc_srqn[0x18];
3558
b4ff3a36 3559 u8 reserved_at_60[0x20];
e281682b
SM		 3560};
3561
3562enum {
3563 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3564 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3565};
3566
3567struct mlx5_ifc_query_vport_state_out_bits {
3568 u8 status[0x8];
b4ff3a36 3569 u8 reserved_at_8[0x18];
e281682b
SM		 3570
3571 u8 syndrome[0x20];
3572
b4ff3a36 3573 u8 reserved_at_40[0x20];
e281682b 3574
b4ff3a36 3575 u8 reserved_at_60[0x18];
e281682b
SM		 3576 u8 admin_state[0x4];
3577 u8 state[0x4];
3578};
3579
3580enum {
3581 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3582 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3583};
3584
3585struct mlx5_ifc_query_vport_state_in_bits {
3586 u8 opcode[0x10];
b4ff3a36 3587 u8 reserved_at_10[0x10];
e281682b 3588
b4ff3a36 3589 u8 reserved_at_20[0x10];
e281682b
SM		 3590 u8 op_mod[0x10];
3591
3592 u8 other_vport[0x1];
b4ff3a36 3593 u8 reserved_at_41[0xf];
e281682b
SM		 3594 u8 vport_number[0x10];
3595
b4ff3a36 3596 u8 reserved_at_60[0x20];
e281682b
SM		 3597};
3598
3599struct mlx5_ifc_query_vport_counter_out_bits {
3600 u8 status[0x8];
b4ff3a36 3601 u8 reserved_at_8[0x18];
e281682b
SM		 3602
3603 u8 syndrome[0x20];
3604
b4ff3a36 3605 u8 reserved_at_40[0x40];
e281682b
SM		 3606
3607 struct mlx5_ifc_traffic_counter_bits received_errors;
3608
3609 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3610
3611 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3612
3613 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3614
3615 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3616
3617 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3618
3619 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3620
3621 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3622
3623 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3624
3625 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3626
3627 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3628
3629 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3630
b4ff3a36 3631 u8 reserved_at_680[0xa00];
e281682b
SM		 3632};
3633
3634enum {
3635 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3636};
3637
3638struct mlx5_ifc_query_vport_counter_in_bits {
3639 u8 opcode[0x10];
b4ff3a36 3640 u8 reserved_at_10[0x10];
e281682b 3641
b4ff3a36 3642 u8 reserved_at_20[0x10];
e281682b
SM		 3643 u8 op_mod[0x10];
3644
3645 u8 other_vport[0x1];
b54ba277
MY		 3646 u8 reserved_at_41[0xb];
3647 u8 port_num[0x4];
e281682b
SM		 3648 u8 vport_number[0x10];
3649
b4ff3a36 3650 u8 reserved_at_60[0x60];
e281682b
SM		 3651
3652 u8 clear[0x1];
b4ff3a36 3653 u8 reserved_at_c1[0x1f];
e281682b 3654
b4ff3a36 3655 u8 reserved_at_e0[0x20];
e281682b
SM		 3656};
3657
3658struct mlx5_ifc_query_tis_out_bits {
3659 u8 status[0x8];
b4ff3a36 3660 u8 reserved_at_8[0x18];
e281682b
SM		 3661
3662 u8 syndrome[0x20];
3663
b4ff3a36 3664 u8 reserved_at_40[0x40];
e281682b
SM		 3665
3666 struct mlx5_ifc_tisc_bits tis_context;
3667};
3668
3669struct mlx5_ifc_query_tis_in_bits {
3670 u8 opcode[0x10];
b4ff3a36 3671 u8 reserved_at_10[0x10];
e281682b 3672
b4ff3a36 3673 u8 reserved_at_20[0x10];
e281682b
SM		 3674 u8 op_mod[0x10];
3675
b4ff3a36 3676 u8 reserved_at_40[0x8];
e281682b
SM		 3677 u8 tisn[0x18];
3678
b4ff3a36 3679 u8 reserved_at_60[0x20];
e281682b
SM		 3680};
3681
3682struct mlx5_ifc_query_tir_out_bits {
3683 u8 status[0x8];
b4ff3a36 3684 u8 reserved_at_8[0x18];
e281682b
SM		 3685
3686 u8 syndrome[0x20];
3687
b4ff3a36 3688 u8 reserved_at_40[0xc0];
e281682b
SM		 3689
3690 struct mlx5_ifc_tirc_bits tir_context;
3691};
3692
3693struct mlx5_ifc_query_tir_in_bits {
3694 u8 opcode[0x10];
b4ff3a36 3695 u8 reserved_at_10[0x10];
e281682b 3696
b4ff3a36 3697 u8 reserved_at_20[0x10];
e281682b
SM		 3698 u8 op_mod[0x10];
3699
b4ff3a36 3700 u8 reserved_at_40[0x8];
e281682b
SM		 3701 u8 tirn[0x18];
3702
b4ff3a36 3703 u8 reserved_at_60[0x20];
e281682b
SM		 3704};
3705
3706struct mlx5_ifc_query_srq_out_bits {
3707 u8 status[0x8];
b4ff3a36 3708 u8 reserved_at_8[0x18];
e281682b
SM		 3709
3710 u8 syndrome[0x20];
3711
b4ff3a36 3712 u8 reserved_at_40[0x40];
e281682b
SM		 3713
3714 struct mlx5_ifc_srqc_bits srq_context_entry;
3715
b4ff3a36 3716 u8 reserved_at_280[0x600];
e281682b
SM		 3717
3718 u8 pas[0][0x40];
3719};
3720
3721struct mlx5_ifc_query_srq_in_bits {
3722 u8 opcode[0x10];
b4ff3a36 3723 u8 reserved_at_10[0x10];
e281682b 3724
b4ff3a36 3725 u8 reserved_at_20[0x10];
e281682b
SM		 3726 u8 op_mod[0x10];
3727
b4ff3a36 3728 u8 reserved_at_40[0x8];
e281682b
SM		 3729 u8 srqn[0x18];
3730
b4ff3a36 3731 u8 reserved_at_60[0x20];
e281682b
SM		 3732};
3733
3734struct mlx5_ifc_query_sq_out_bits {
3735 u8 status[0x8];
b4ff3a36 3736 u8 reserved_at_8[0x18];
e281682b
SM		 3737
3738 u8 syndrome[0x20];
3739
b4ff3a36 3740 u8 reserved_at_40[0xc0];
e281682b
SM		 3741
3742 struct mlx5_ifc_sqc_bits sq_context;
3743};
3744
3745struct mlx5_ifc_query_sq_in_bits {
3746 u8 opcode[0x10];
b4ff3a36 3747 u8 reserved_at_10[0x10];
e281682b 3748
b4ff3a36 3749 u8 reserved_at_20[0x10];
e281682b
SM		 3750 u8 op_mod[0x10];
3751
b4ff3a36 3752 u8 reserved_at_40[0x8];
e281682b
SM		 3753 u8 sqn[0x18];
3754
b4ff3a36 3755 u8 reserved_at_60[0x20];
e281682b
SM		 3756};
3757
3758struct mlx5_ifc_query_special_contexts_out_bits {
3759 u8 status[0x8];
b4ff3a36 3760 u8 reserved_at_8[0x18];
e281682b
SM		 3761
3762 u8 syndrome[0x20];
3763
ec22eb53 3764 u8 dump_fill_mkey[0x20];
e281682b
SM		 3765
3766 u8 resd_lkey[0x20];
bcda1aca
AK		 3767
3768 u8 null_mkey[0x20];
3769
3770 u8 reserved_at_a0[0x60];
e281682b
SM		 3771};
3772
3773struct mlx5_ifc_query_special_contexts_in_bits {
3774 u8 opcode[0x10];
b4ff3a36 3775 u8 reserved_at_10[0x10];
e281682b 3776
b4ff3a36 3777 u8 reserved_at_20[0x10];
e281682b
SM		 3778 u8 op_mod[0x10];
3779
b4ff3a36 3780 u8 reserved_at_40[0x40];
e281682b
SM		 3781};
3782
813f8540
MHY		 3783struct mlx5_ifc_query_scheduling_element_out_bits {
3784 u8 opcode[0x10];
3785 u8 reserved_at_10[0x10];
3786
3787 u8 reserved_at_20[0x10];
3788 u8 op_mod[0x10];
3789
3790 u8 reserved_at_40[0xc0];
3791
3792 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3793
3794 u8 reserved_at_300[0x100];
3795};
3796
3797enum {
3798 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3799};
3800
3801struct mlx5_ifc_query_scheduling_element_in_bits {
3802 u8 opcode[0x10];
3803 u8 reserved_at_10[0x10];
3804
3805 u8 reserved_at_20[0x10];
3806 u8 op_mod[0x10];
3807
3808 u8 scheduling_hierarchy[0x8];
3809 u8 reserved_at_48[0x18];
3810
3811 u8 scheduling_element_id[0x20];
3812
3813 u8 reserved_at_80[0x180];
3814};
3815
e281682b
SM		 3816struct mlx5_ifc_query_rqt_out_bits {
3817 u8 status[0x8];
b4ff3a36 3818 u8 reserved_at_8[0x18];
e281682b
SM		 3819
3820 u8 syndrome[0x20];
3821
b4ff3a36 3822 u8 reserved_at_40[0xc0];
e281682b
SM		 3823
3824 struct mlx5_ifc_rqtc_bits rqt_context;
3825};
3826
3827struct mlx5_ifc_query_rqt_in_bits {
3828 u8 opcode[0x10];
b4ff3a36 3829 u8 reserved_at_10[0x10];
e281682b 3830
b4ff3a36 3831 u8 reserved_at_20[0x10];
e281682b
SM		 3832 u8 op_mod[0x10];
3833
b4ff3a36 3834 u8 reserved_at_40[0x8];
e281682b
SM		 3835 u8 rqtn[0x18];
3836
b4ff3a36 3837 u8 reserved_at_60[0x20];
e281682b
SM		 3838};
3839
3840struct mlx5_ifc_query_rq_out_bits {
3841 u8 status[0x8];
b4ff3a36 3842 u8 reserved_at_8[0x18];
e281682b
SM		 3843
3844 u8 syndrome[0x20];
3845
b4ff3a36 3846 u8 reserved_at_40[0xc0];
e281682b
SM		 3847
3848 struct mlx5_ifc_rqc_bits rq_context;
3849};
3850
3851struct mlx5_ifc_query_rq_in_bits {
3852 u8 opcode[0x10];
b4ff3a36 3853 u8 reserved_at_10[0x10];
e281682b 3854
b4ff3a36 3855 u8 reserved_at_20[0x10];
e281682b
SM		 3856 u8 op_mod[0x10];
3857
b4ff3a36 3858 u8 reserved_at_40[0x8];
e281682b
SM		 3859 u8 rqn[0x18];
3860
b4ff3a36 3861 u8 reserved_at_60[0x20];
e281682b
SM		 3862};
3863
3864struct mlx5_ifc_query_roce_address_out_bits {
3865 u8 status[0x8];
b4ff3a36 3866 u8 reserved_at_8[0x18];
e281682b
SM		 3867
3868 u8 syndrome[0x20];
3869
b4ff3a36 3870 u8 reserved_at_40[0x40];
e281682b
SM		 3871
3872 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3873};
3874
3875struct mlx5_ifc_query_roce_address_in_bits {
3876 u8 opcode[0x10];
b4ff3a36 3877 u8 reserved_at_10[0x10];
e281682b 3878
b4ff3a36 3879 u8 reserved_at_20[0x10];
e281682b
SM		 3880 u8 op_mod[0x10];
3881
3882 u8 roce_address_index[0x10];
b4ff3a36 3883 u8 reserved_at_50[0x10];
e281682b 3884
b4ff3a36 3885 u8 reserved_at_60[0x20];
e281682b
SM		 3886};
3887
3888struct mlx5_ifc_query_rmp_out_bits {
3889 u8 status[0x8];
b4ff3a36 3890 u8 reserved_at_8[0x18];
e281682b
SM		 3891
3892 u8 syndrome[0x20];
3893
b4ff3a36 3894 u8 reserved_at_40[0xc0];
e281682b
SM		 3895
3896 struct mlx5_ifc_rmpc_bits rmp_context;
3897};
3898
3899struct mlx5_ifc_query_rmp_in_bits {
3900 u8 opcode[0x10];
b4ff3a36 3901 u8 reserved_at_10[0x10];
e281682b 3902
b4ff3a36 3903 u8 reserved_at_20[0x10];
e281682b
SM		 3904 u8 op_mod[0x10];
3905
b4ff3a36 3906 u8 reserved_at_40[0x8];
e281682b
SM		 3907 u8 rmpn[0x18];
3908
b4ff3a36 3909 u8 reserved_at_60[0x20];
e281682b
SM		 3910};
3911
3912struct mlx5_ifc_query_qp_out_bits {
3913 u8 status[0x8];
b4ff3a36 3914 u8 reserved_at_8[0x18];
e281682b
SM		 3915
3916 u8 syndrome[0x20];
3917
b4ff3a36 3918 u8 reserved_at_40[0x40];
e281682b
SM		 3919
3920 u8 opt_param_mask[0x20];
3921
b4ff3a36 3922 u8 reserved_at_a0[0x20];
e281682b
SM		 3923
3924 struct mlx5_ifc_qpc_bits qpc;
3925
b4ff3a36 3926 u8 reserved_at_800[0x80];
e281682b
SM		 3927
3928 u8 pas[0][0x40];
3929};
3930
3931struct mlx5_ifc_query_qp_in_bits {
3932 u8 opcode[0x10];
b4ff3a36 3933 u8 reserved_at_10[0x10];
e281682b 3934
b4ff3a36 3935 u8 reserved_at_20[0x10];
e281682b
SM		 3936 u8 op_mod[0x10];
3937
b4ff3a36 3938 u8 reserved_at_40[0x8];
e281682b
SM		 3939 u8 qpn[0x18];
3940
b4ff3a36 3941 u8 reserved_at_60[0x20];
e281682b
SM		 3942};
3943
3944struct mlx5_ifc_query_q_counter_out_bits {
3945 u8 status[0x8];
b4ff3a36 3946 u8 reserved_at_8[0x18];
e281682b
SM		 3947
3948 u8 syndrome[0x20];
3949
b4ff3a36 3950 u8 reserved_at_40[0x40];
e281682b
SM		 3951
3952 u8 rx_write_requests[0x20];
3953
b4ff3a36 3954 u8 reserved_at_a0[0x20];
e281682b
SM		 3955
3956 u8 rx_read_requests[0x20];
3957
b4ff3a36 3958 u8 reserved_at_e0[0x20];
e281682b
SM		 3959
3960 u8 rx_atomic_requests[0x20];
3961
b4ff3a36 3962 u8 reserved_at_120[0x20];
e281682b
SM		 3963
3964 u8 rx_dct_connect[0x20];
3965
b4ff3a36 3966 u8 reserved_at_160[0x20];
e281682b
SM		 3967
3968 u8 out_of_buffer[0x20];
3969
b4ff3a36 3970 u8 reserved_at_1a0[0x20];
e281682b
SM		 3971
3972 u8 out_of_sequence[0x20];
3973
7486216b
SM		 3974 u8 reserved_at_1e0[0x20];
3975
3976 u8 duplicate_request[0x20];
3977
3978 u8 reserved_at_220[0x20];
3979
3980 u8 rnr_nak_retry_err[0x20];
3981
3982 u8 reserved_at_260[0x20];
3983
3984 u8 packet_seq_err[0x20];
3985
3986 u8 reserved_at_2a0[0x20];
3987
3988 u8 implied_nak_seq_err[0x20];
3989
3990 u8 reserved_at_2e0[0x20];
3991
3992 u8 local_ack_timeout_err[0x20];
3993
58dcb60a
PP		 3994 u8 reserved_at_320[0xa0];
3995
3996 u8 resp_local_length_error[0x20];
3997
3998 u8 req_local_length_error[0x20];
3999
4000 u8 resp_local_qp_error[0x20];
4001
4002 u8 local_operation_error[0x20];
4003
4004 u8 resp_local_protection[0x20];
4005
4006 u8 req_local_protection[0x20];
4007
4008 u8 resp_cqe_error[0x20];
4009
4010 u8 req_cqe_error[0x20];
4011
4012 u8 req_mw_binding[0x20];
4013
4014 u8 req_bad_response[0x20];
4015
4016 u8 req_remote_invalid_request[0x20];
4017
4018 u8 resp_remote_invalid_request[0x20];
4019
4020 u8 req_remote_access_errors[0x20];
4021
4022 u8 resp_remote_access_errors[0x20];
4023
4024 u8 req_remote_operation_errors[0x20];
4025
4026 u8 req_transport_retries_exceeded[0x20];
4027
4028 u8 cq_overflow[0x20];
4029
4030 u8 resp_cqe_flush_error[0x20];
4031
4032 u8 req_cqe_flush_error[0x20];
4033
4034 u8 reserved_at_620[0x1e0];
e281682b
SM		 4035};
4036
4037struct mlx5_ifc_query_q_counter_in_bits {
4038 u8 opcode[0x10];
b4ff3a36 4039 u8 reserved_at_10[0x10];
e281682b 4040
b4ff3a36 4041 u8 reserved_at_20[0x10];
e281682b
SM		 4042 u8 op_mod[0x10];
4043
b4ff3a36 4044 u8 reserved_at_40[0x80];
e281682b
SM		 4045
4046 u8 clear[0x1];
b4ff3a36 4047 u8 reserved_at_c1[0x1f];
e281682b 4048
b4ff3a36 4049 u8 reserved_at_e0[0x18];
e281682b
SM		 4050 u8 counter_set_id[0x8];
4051};
4052
4053struct mlx5_ifc_query_pages_out_bits {
4054 u8 status[0x8];
b4ff3a36 4055 u8 reserved_at_8[0x18];
e281682b
SM		 4056
4057 u8 syndrome[0x20];
4058
b4ff3a36 4059 u8 reserved_at_40[0x10];
e281682b
SM		 4060 u8 function_id[0x10];
4061
4062 u8 num_pages[0x20];
4063};
4064
4065enum {
4066 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4067 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4068 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4069};
4070
4071struct mlx5_ifc_query_pages_in_bits {
4072 u8 opcode[0x10];
b4ff3a36 4073 u8 reserved_at_10[0x10];
e281682b 4074
b4ff3a36 4075 u8 reserved_at_20[0x10];
e281682b
SM		 4076 u8 op_mod[0x10];
4077
b4ff3a36 4078 u8 reserved_at_40[0x10];
e281682b
SM		 4079 u8 function_id[0x10];
4080
b4ff3a36 4081 u8 reserved_at_60[0x20];
e281682b
SM		 4082};
4083
4084struct mlx5_ifc_query_nic_vport_context_out_bits {
4085 u8 status[0x8];
b4ff3a36 4086 u8 reserved_at_8[0x18];
e281682b
SM		 4087
4088 u8 syndrome[0x20];
4089
b4ff3a36 4090 u8 reserved_at_40[0x40];
e281682b
SM		 4091
4092 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4093};
4094
4095struct mlx5_ifc_query_nic_vport_context_in_bits {
4096 u8 opcode[0x10];
b4ff3a36 4097 u8 reserved_at_10[0x10];
e281682b 4098
b4ff3a36 4099 u8 reserved_at_20[0x10];
e281682b
SM		 4100 u8 op_mod[0x10];
4101
4102 u8 other_vport[0x1];
b4ff3a36 4103 u8 reserved_at_41[0xf];
e281682b
SM		 4104 u8 vport_number[0x10];
4105
b4ff3a36 4106 u8 reserved_at_60[0x5];
e281682b 4107 u8 allowed_list_type[0x3];
b4ff3a36 4108 u8 reserved_at_68[0x18];
e281682b
SM		 4109};
4110
4111struct mlx5_ifc_query_mkey_out_bits {
4112 u8 status[0x8];
b4ff3a36 4113 u8 reserved_at_8[0x18];
e281682b
SM		 4114
4115 u8 syndrome[0x20];
4116
b4ff3a36 4117 u8 reserved_at_40[0x40];
e281682b
SM		 4118
4119 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4120
b4ff3a36 4121 u8 reserved_at_280[0x600];
e281682b
SM		 4122
4123 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4124
4125 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4126};
4127
4128struct mlx5_ifc_query_mkey_in_bits {
4129 u8 opcode[0x10];
b4ff3a36 4130 u8 reserved_at_10[0x10];
e281682b 4131
b4ff3a36 4132 u8 reserved_at_20[0x10];
e281682b
SM		 4133 u8 op_mod[0x10];
4134
b4ff3a36 4135 u8 reserved_at_40[0x8];
e281682b
SM		 4136 u8 mkey_index[0x18];
4137
4138 u8 pg_access[0x1];
b4ff3a36 4139 u8 reserved_at_61[0x1f];
e281682b
SM		 4140};
4141
4142struct mlx5_ifc_query_mad_demux_out_bits {
4143 u8 status[0x8];
b4ff3a36 4144 u8 reserved_at_8[0x18];
e281682b
SM		 4145
4146 u8 syndrome[0x20];
4147
b4ff3a36 4148 u8 reserved_at_40[0x40];
e281682b
SM		 4149
4150 u8 mad_dumux_parameters_block[0x20];
4151};
4152
4153struct mlx5_ifc_query_mad_demux_in_bits {
4154 u8 opcode[0x10];
b4ff3a36 4155 u8 reserved_at_10[0x10];
e281682b 4156
b4ff3a36 4157 u8 reserved_at_20[0x10];
e281682b
SM		 4158 u8 op_mod[0x10];
4159
b4ff3a36 4160 u8 reserved_at_40[0x40];
e281682b
SM		 4161};
4162
4163struct mlx5_ifc_query_l2_table_entry_out_bits {
4164 u8 status[0x8];
b4ff3a36 4165 u8 reserved_at_8[0x18];
e281682b
SM		 4166
4167 u8 syndrome[0x20];
4168
b4ff3a36 4169 u8 reserved_at_40[0xa0];
e281682b 4170
b4ff3a36 4171 u8 reserved_at_e0[0x13];
e281682b
SM		 4172 u8 vlan_valid[0x1];
4173 u8 vlan[0xc];
4174
4175 struct mlx5_ifc_mac_address_layout_bits mac_address;
4176
b4ff3a36 4177 u8 reserved_at_140[0xc0];
e281682b
SM		 4178};
4179
4180struct mlx5_ifc_query_l2_table_entry_in_bits {
4181 u8 opcode[0x10];
b4ff3a36 4182 u8 reserved_at_10[0x10];
e281682b 4183
b4ff3a36 4184 u8 reserved_at_20[0x10];
e281682b
SM		 4185 u8 op_mod[0x10];
4186
b4ff3a36 4187 u8 reserved_at_40[0x60];
e281682b 4188
b4ff3a36 4189 u8 reserved_at_a0[0x8];
e281682b
SM		 4190 u8 table_index[0x18];
4191
b4ff3a36 4192 u8 reserved_at_c0[0x140];
e281682b
SM		 4193};
4194
4195struct mlx5_ifc_query_issi_out_bits {
4196 u8 status[0x8];
b4ff3a36 4197 u8 reserved_at_8[0x18];
e281682b
SM		 4198
4199 u8 syndrome[0x20];
4200
b4ff3a36 4201 u8 reserved_at_40[0x10];
e281682b
SM		 4202 u8 current_issi[0x10];
4203
b4ff3a36 4204 u8 reserved_at_60[0xa0];
e281682b 4205
b4ff3a36 4206 u8 reserved_at_100[76][0x8];
e281682b
SM		 4207 u8 supported_issi_dw0[0x20];
4208};
4209
4210struct mlx5_ifc_query_issi_in_bits {
4211 u8 opcode[0x10];
b4ff3a36 4212 u8 reserved_at_10[0x10];
e281682b 4213
b4ff3a36 4214 u8 reserved_at_20[0x10];
e281682b
SM		 4215 u8 op_mod[0x10];
4216
b4ff3a36 4217 u8 reserved_at_40[0x40];
e281682b
SM		 4218};
4219
0dbc6fe0
SM		 4220struct mlx5_ifc_set_driver_version_out_bits {
4221 u8 status[0x8];
4222 u8 reserved_0[0x18];
4223
4224 u8 syndrome[0x20];
4225 u8 reserved_1[0x40];
4226};
4227
4228struct mlx5_ifc_set_driver_version_in_bits {
4229 u8 opcode[0x10];
4230 u8 reserved_0[0x10];
4231
4232 u8 reserved_1[0x10];
4233 u8 op_mod[0x10];
4234
4235 u8 reserved_2[0x40];
4236 u8 driver_version[64][0x8];
4237};
4238
e281682b
SM		 4239struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4240 u8 status[0x8];
b4ff3a36 4241 u8 reserved_at_8[0x18];
e281682b
SM		 4242
4243 u8 syndrome[0x20];
4244
b4ff3a36 4245 u8 reserved_at_40[0x40];
e281682b
SM		 4246
4247 struct mlx5_ifc_pkey_bits pkey[0];
4248};
4249
4250struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4251 u8 opcode[0x10];
b4ff3a36 4252 u8 reserved_at_10[0x10];
e281682b 4253
b4ff3a36 4254 u8 reserved_at_20[0x10];
e281682b
SM		 4255 u8 op_mod[0x10];
4256
4257 u8 other_vport[0x1];
b4ff3a36 4258 u8 reserved_at_41[0xb];
707c4602 4259 u8 port_num[0x4];
e281682b
SM		 4260 u8 vport_number[0x10];
4261
b4ff3a36 4262 u8 reserved_at_60[0x10];
e281682b
SM		 4263 u8 pkey_index[0x10];
4264};
4265
eff901d3
EC		 4266enum {
4267 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4268 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4269 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4270};
4271
e281682b
SM		 4272struct mlx5_ifc_query_hca_vport_gid_out_bits {
4273 u8 status[0x8];
b4ff3a36 4274 u8 reserved_at_8[0x18];
e281682b
SM		 4275
4276 u8 syndrome[0x20];
4277
b4ff3a36 4278 u8 reserved_at_40[0x20];
e281682b
SM		 4279
4280 u8 gids_num[0x10];
b4ff3a36 4281 u8 reserved_at_70[0x10];
e281682b
SM		 4282
4283 struct mlx5_ifc_array128_auto_bits gid[0];
4284};
4285
4286struct mlx5_ifc_query_hca_vport_gid_in_bits {
4287 u8 opcode[0x10];
b4ff3a36 4288 u8 reserved_at_10[0x10];
e281682b 4289
b4ff3a36 4290 u8 reserved_at_20[0x10];
e281682b
SM		 4291 u8 op_mod[0x10];
4292
4293 u8 other_vport[0x1];
b4ff3a36 4294 u8 reserved_at_41[0xb];
707c4602 4295 u8 port_num[0x4];
e281682b
SM		 4296 u8 vport_number[0x10];
4297
b4ff3a36 4298 u8 reserved_at_60[0x10];
e281682b
SM		 4299 u8 gid_index[0x10];
4300};
4301
4302struct mlx5_ifc_query_hca_vport_context_out_bits {
4303 u8 status[0x8];
b4ff3a36 4304 u8 reserved_at_8[0x18];
e281682b
SM		 4305
4306 u8 syndrome[0x20];
4307
b4ff3a36 4308 u8 reserved_at_40[0x40];
e281682b
SM		 4309
4310 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4311};
4312
4313struct mlx5_ifc_query_hca_vport_context_in_bits {
4314 u8 opcode[0x10];
b4ff3a36 4315 u8 reserved_at_10[0x10];
e281682b 4316
b4ff3a36 4317 u8 reserved_at_20[0x10];
e281682b
SM		 4318 u8 op_mod[0x10];
4319
4320 u8 other_vport[0x1];
b4ff3a36 4321 u8 reserved_at_41[0xb];
707c4602 4322 u8 port_num[0x4];
e281682b
SM		 4323 u8 vport_number[0x10];
4324
b4ff3a36 4325 u8 reserved_at_60[0x20];
e281682b
SM		 4326};
4327
4328struct mlx5_ifc_query_hca_cap_out_bits {
4329 u8 status[0x8];
b4ff3a36 4330 u8 reserved_at_8[0x18];
e281682b
SM		 4331
4332 u8 syndrome[0x20];
4333
b4ff3a36 4334 u8 reserved_at_40[0x40];
e281682b
SM		 4335
4336 union mlx5_ifc_hca_cap_union_bits capability;
4337};
4338
4339struct mlx5_ifc_query_hca_cap_in_bits {
4340 u8 opcode[0x10];
b4ff3a36 4341 u8 reserved_at_10[0x10];
e281682b 4342
b4ff3a36 4343 u8 reserved_at_20[0x10];
e281682b
SM		 4344 u8 op_mod[0x10];
4345
b4ff3a36 4346 u8 reserved_at_40[0x40];
e281682b
SM		 4347};
4348
4349struct mlx5_ifc_query_flow_table_out_bits {
4350 u8 status[0x8];
b4ff3a36 4351 u8 reserved_at_8[0x18];
e281682b
SM		 4352
4353 u8 syndrome[0x20];
4354
b4ff3a36 4355 u8 reserved_at_40[0x80];
e281682b 4356
b4ff3a36 4357 u8 reserved_at_c0[0x8];
e281682b 4358 u8 level[0x8];
b4ff3a36 4359 u8 reserved_at_d0[0x8];
e281682b
SM		 4360 u8 log_size[0x8];
4361
b4ff3a36 4362 u8 reserved_at_e0[0x120];
e281682b
SM		 4363};
4364
4365struct mlx5_ifc_query_flow_table_in_bits {
4366 u8 opcode[0x10];
b4ff3a36 4367 u8 reserved_at_10[0x10];
e281682b 4368
b4ff3a36 4369 u8 reserved_at_20[0x10];
e281682b
SM		 4370 u8 op_mod[0x10];
4371
b4ff3a36 4372 u8 reserved_at_40[0x40];
e281682b
SM		 4373
4374 u8 table_type[0x8];
b4ff3a36 4375 u8 reserved_at_88[0x18];
e281682b 4376
b4ff3a36 4377 u8 reserved_at_a0[0x8];
e281682b
SM		 4378 u8 table_id[0x18];
4379
b4ff3a36 4380 u8 reserved_at_c0[0x140];
e281682b
SM		 4381};
4382
4383struct mlx5_ifc_query_fte_out_bits {
4384 u8 status[0x8];
b4ff3a36 4385 u8 reserved_at_8[0x18];
e281682b
SM		 4386
4387 u8 syndrome[0x20];
4388
b4ff3a36 4389 u8 reserved_at_40[0x1c0];
e281682b
SM		 4390
4391 struct mlx5_ifc_flow_context_bits flow_context;
4392};
4393
4394struct mlx5_ifc_query_fte_in_bits {
4395 u8 opcode[0x10];
b4ff3a36 4396 u8 reserved_at_10[0x10];
e281682b 4397
b4ff3a36 4398 u8 reserved_at_20[0x10];
e281682b
SM		 4399 u8 op_mod[0x10];
4400
b4ff3a36 4401 u8 reserved_at_40[0x40];
e281682b
SM		 4402
4403 u8 table_type[0x8];
b4ff3a36 4404 u8 reserved_at_88[0x18];
e281682b 4405
b4ff3a36 4406 u8 reserved_at_a0[0x8];
e281682b
SM		 4407 u8 table_id[0x18];
4408
b4ff3a36 4409 u8 reserved_at_c0[0x40];
e281682b
SM		 4410
4411 u8 flow_index[0x20];
4412
b4ff3a36 4413 u8 reserved_at_120[0xe0];
e281682b
SM		 4414};
4415
4416enum {
4417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4418 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4419 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4420};
4421
4422struct mlx5_ifc_query_flow_group_out_bits {
4423 u8 status[0x8];
b4ff3a36 4424 u8 reserved_at_8[0x18];
e281682b
SM		 4425
4426 u8 syndrome[0x20];
4427
b4ff3a36 4428 u8 reserved_at_40[0xa0];
e281682b
SM		 4429
4430 u8 start_flow_index[0x20];
4431
b4ff3a36 4432 u8 reserved_at_100[0x20];
e281682b
SM		 4433
4434 u8 end_flow_index[0x20];
4435
b4ff3a36 4436 u8 reserved_at_140[0xa0];
e281682b 4437
b4ff3a36 4438 u8 reserved_at_1e0[0x18];
e281682b
SM		 4439 u8 match_criteria_enable[0x8];
4440
4441 struct mlx5_ifc_fte_match_param_bits match_criteria;
4442
b4ff3a36 4443 u8 reserved_at_1200[0xe00];
e281682b
SM		 4444};
4445
4446struct mlx5_ifc_query_flow_group_in_bits {
4447 u8 opcode[0x10];
b4ff3a36 4448 u8 reserved_at_10[0x10];
e281682b 4449
b4ff3a36 4450 u8 reserved_at_20[0x10];
e281682b
SM		 4451 u8 op_mod[0x10];
4452
b4ff3a36 4453 u8 reserved_at_40[0x40];
e281682b
SM		 4454
4455 u8 table_type[0x8];
b4ff3a36 4456 u8 reserved_at_88[0x18];
e281682b 4457
b4ff3a36 4458 u8 reserved_at_a0[0x8];
e281682b
SM		 4459 u8 table_id[0x18];
4460
4461 u8 group_id[0x20];
4462
b4ff3a36 4463 u8 reserved_at_e0[0x120];
e281682b
SM		 4464};
4465
9dc0b289
AV		 4466struct mlx5_ifc_query_flow_counter_out_bits {
4467 u8 status[0x8];
4468 u8 reserved_at_8[0x18];
4469
4470 u8 syndrome[0x20];
4471
4472 u8 reserved_at_40[0x40];
4473
4474 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4475};
4476
4477struct mlx5_ifc_query_flow_counter_in_bits {
4478 u8 opcode[0x10];
4479 u8 reserved_at_10[0x10];
4480
4481 u8 reserved_at_20[0x10];
4482 u8 op_mod[0x10];
4483
4484 u8 reserved_at_40[0x80];
4485
4486 u8 clear[0x1];
4487 u8 reserved_at_c1[0xf];
4488 u8 num_of_counters[0x10];
4489
a8ffcc74 4490 u8 flow_counter_id[0x20];
9dc0b289
AV		 4491};
4492
d6666753
SM		 4493struct mlx5_ifc_query_esw_vport_context_out_bits {
4494 u8 status[0x8];
b4ff3a36 4495 u8 reserved_at_8[0x18];
d6666753
SM		 4496
4497 u8 syndrome[0x20];
4498
b4ff3a36 4499 u8 reserved_at_40[0x40];
d6666753
SM		 4500
4501 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4502};
4503
4504struct mlx5_ifc_query_esw_vport_context_in_bits {
4505 u8 opcode[0x10];
b4ff3a36 4506 u8 reserved_at_10[0x10];
d6666753 4507
b4ff3a36 4508 u8 reserved_at_20[0x10];
d6666753
SM		 4509 u8 op_mod[0x10];
4510
4511 u8 other_vport[0x1];
b4ff3a36 4512 u8 reserved_at_41[0xf];
d6666753
SM		 4513 u8 vport_number[0x10];
4514
b4ff3a36 4515 u8 reserved_at_60[0x20];
d6666753
SM		 4516};
4517
4518struct mlx5_ifc_modify_esw_vport_context_out_bits {
4519 u8 status[0x8];
b4ff3a36 4520 u8 reserved_at_8[0x18];
d6666753
SM		 4521
4522 u8 syndrome[0x20];
4523
b4ff3a36 4524 u8 reserved_at_40[0x40];
d6666753
SM		 4525};
4526
4527struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4528 u8 reserved_at_0[0x1c];
d6666753
SM		 4529 u8 vport_cvlan_insert[0x1];
4530 u8 vport_svlan_insert[0x1];
4531 u8 vport_cvlan_strip[0x1];
4532 u8 vport_svlan_strip[0x1];
4533};
4534
4535struct mlx5_ifc_modify_esw_vport_context_in_bits {
4536 u8 opcode[0x10];
b4ff3a36 4537 u8 reserved_at_10[0x10];
d6666753 4538
b4ff3a36 4539 u8 reserved_at_20[0x10];
d6666753
SM		 4540 u8 op_mod[0x10];
4541
4542 u8 other_vport[0x1];
b4ff3a36 4543 u8 reserved_at_41[0xf];
d6666753
SM		 4544 u8 vport_number[0x10];
4545
4546 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4547
4548 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4549};
4550
e281682b
SM		 4551struct mlx5_ifc_query_eq_out_bits {
4552 u8 status[0x8];
b4ff3a36 4553 u8 reserved_at_8[0x18];
e281682b
SM		 4554
4555 u8 syndrome[0x20];
4556
b4ff3a36 4557 u8 reserved_at_40[0x40];
e281682b
SM		 4558
4559 struct mlx5_ifc_eqc_bits eq_context_entry;
4560
b4ff3a36 4561 u8 reserved_at_280[0x40];
e281682b
SM		 4562
4563 u8 event_bitmask[0x40];
4564
b4ff3a36 4565 u8 reserved_at_300[0x580];
e281682b
SM		 4566
4567 u8 pas[0][0x40];
4568};
4569
4570struct mlx5_ifc_query_eq_in_bits {
4571 u8 opcode[0x10];
b4ff3a36 4572 u8 reserved_at_10[0x10];
e281682b 4573
b4ff3a36 4574 u8 reserved_at_20[0x10];
e281682b
SM		 4575 u8 op_mod[0x10];
4576
b4ff3a36 4577 u8 reserved_at_40[0x18];
e281682b
SM		 4578 u8 eq_number[0x8];
4579
b4ff3a36 4580 u8 reserved_at_60[0x20];
e281682b
SM		 4581};
4582
7adbde20
HHZ		 4583struct mlx5_ifc_encap_header_in_bits {
4584 u8 reserved_at_0[0x5];
4585 u8 header_type[0x3];
4586 u8 reserved_at_8[0xe];
4587 u8 encap_header_size[0xa];
4588
4589 u8 reserved_at_20[0x10];
4590 u8 encap_header[2][0x8];
4591
4592 u8 more_encap_header[0][0x8];
4593};
4594
4595struct mlx5_ifc_query_encap_header_out_bits {
4596 u8 status[0x8];
4597 u8 reserved_at_8[0x18];
4598
4599 u8 syndrome[0x20];
4600
4601 u8 reserved_at_40[0xa0];
4602
4603 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4604};
4605
4606struct mlx5_ifc_query_encap_header_in_bits {
4607 u8 opcode[0x10];
4608 u8 reserved_at_10[0x10];
4609
4610 u8 reserved_at_20[0x10];
4611 u8 op_mod[0x10];
4612
4613 u8 encap_id[0x20];
4614
4615 u8 reserved_at_60[0xa0];
4616};
4617
4618struct mlx5_ifc_alloc_encap_header_out_bits {
4619 u8 status[0x8];
4620 u8 reserved_at_8[0x18];
4621
4622 u8 syndrome[0x20];
4623
4624 u8 encap_id[0x20];
4625
4626 u8 reserved_at_60[0x20];
4627};
4628
4629struct mlx5_ifc_alloc_encap_header_in_bits {
4630 u8 opcode[0x10];
4631 u8 reserved_at_10[0x10];
4632
4633 u8 reserved_at_20[0x10];
4634 u8 op_mod[0x10];
4635
4636 u8 reserved_at_40[0xa0];
4637
4638 struct mlx5_ifc_encap_header_in_bits encap_header;
4639};
4640
4641struct mlx5_ifc_dealloc_encap_header_out_bits {
4642 u8 status[0x8];
4643 u8 reserved_at_8[0x18];
4644
4645 u8 syndrome[0x20];
4646
4647 u8 reserved_at_40[0x40];
4648};
4649
4650struct mlx5_ifc_dealloc_encap_header_in_bits {
4651 u8 opcode[0x10];
4652 u8 reserved_at_10[0x10];
4653
4654 u8 reserved_20[0x10];
4655 u8 op_mod[0x10];
4656
4657 u8 encap_id[0x20];
4658
4659 u8 reserved_60[0x20];
4660};
4661
2a69cb9f
OG		 4662struct mlx5_ifc_set_action_in_bits {
4663 u8 action_type[0x4];
4664 u8 field[0xc];
4665 u8 reserved_at_10[0x3];
4666 u8 offset[0x5];
4667 u8 reserved_at_18[0x3];
4668 u8 length[0x5];
4669
4670 u8 data[0x20];
4671};
4672
4673struct mlx5_ifc_add_action_in_bits {
4674 u8 action_type[0x4];
4675 u8 field[0xc];
4676 u8 reserved_at_10[0x10];
4677
4678 u8 data[0x20];
4679};
4680
4681union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4682 struct mlx5_ifc_set_action_in_bits set_action_in;
4683 struct mlx5_ifc_add_action_in_bits add_action_in;
4684 u8 reserved_at_0[0x40];
4685};
4686
4687enum {
4688 MLX5_ACTION_TYPE_SET = 0x1,
4689 MLX5_ACTION_TYPE_ADD = 0x2,
4690};
4691
4692enum {
4693 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4694 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4695 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4696 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4697 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4698 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4699 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4700 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4701 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4702 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4703 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4704 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4705 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4706 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4707 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4708 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4709 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4710 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4711 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4712 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4713 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4714 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4715 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4716};
4717
4718struct mlx5_ifc_alloc_modify_header_context_out_bits {
4719 u8 status[0x8];
4720 u8 reserved_at_8[0x18];
4721
4722 u8 syndrome[0x20];
4723
4724 u8 modify_header_id[0x20];
4725
4726 u8 reserved_at_60[0x20];
4727};
4728
4729struct mlx5_ifc_alloc_modify_header_context_in_bits {
4730 u8 opcode[0x10];
4731 u8 reserved_at_10[0x10];
4732
4733 u8 reserved_at_20[0x10];
4734 u8 op_mod[0x10];
4735
4736 u8 reserved_at_40[0x20];
4737
4738 u8 table_type[0x8];
4739 u8 reserved_at_68[0x10];
4740 u8 num_of_actions[0x8];
4741
4742 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4743};
4744
4745struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4746 u8 status[0x8];
4747 u8 reserved_at_8[0x18];
4748
4749 u8 syndrome[0x20];
4750
4751 u8 reserved_at_40[0x40];
4752};
4753
4754struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4755 u8 opcode[0x10];
4756 u8 reserved_at_10[0x10];
4757
4758 u8 reserved_at_20[0x10];
4759 u8 op_mod[0x10];
4760
4761 u8 modify_header_id[0x20];
4762
4763 u8 reserved_at_60[0x20];
4764};
4765
e281682b
SM		 4766struct mlx5_ifc_query_dct_out_bits {
4767 u8 status[0x8];
b4ff3a36 4768 u8 reserved_at_8[0x18];
e281682b
SM		 4769
4770 u8 syndrome[0x20];
4771
b4ff3a36 4772 u8 reserved_at_40[0x40];
e281682b
SM		 4773
4774 struct mlx5_ifc_dctc_bits dct_context_entry;
4775
b4ff3a36 4776 u8 reserved_at_280[0x180];
e281682b
SM		 4777};
4778
4779struct mlx5_ifc_query_dct_in_bits {
4780 u8 opcode[0x10];
b4ff3a36 4781 u8 reserved_at_10[0x10];
e281682b 4782
b4ff3a36 4783 u8 reserved_at_20[0x10];
e281682b
SM		 4784 u8 op_mod[0x10];
4785
b4ff3a36 4786 u8 reserved_at_40[0x8];
e281682b
SM		 4787 u8 dctn[0x18];
4788
b4ff3a36 4789 u8 reserved_at_60[0x20];
e281682b
SM		 4790};
4791
4792struct mlx5_ifc_query_cq_out_bits {
4793 u8 status[0x8];
b4ff3a36 4794 u8 reserved_at_8[0x18];
e281682b
SM		 4795
4796 u8 syndrome[0x20];
4797
b4ff3a36 4798 u8 reserved_at_40[0x40];
e281682b
SM		 4799
4800 struct mlx5_ifc_cqc_bits cq_context;
4801
b4ff3a36 4802 u8 reserved_at_280[0x600];
e281682b
SM		 4803
4804 u8 pas[0][0x40];
4805};
4806
4807struct mlx5_ifc_query_cq_in_bits {
4808 u8 opcode[0x10];
b4ff3a36 4809 u8 reserved_at_10[0x10];
e281682b 4810
b4ff3a36 4811 u8 reserved_at_20[0x10];
e281682b
SM		 4812 u8 op_mod[0x10];
4813
b4ff3a36 4814 u8 reserved_at_40[0x8];
e281682b
SM		 4815 u8 cqn[0x18];
4816
b4ff3a36 4817 u8 reserved_at_60[0x20];
e281682b
SM		 4818};
4819
4820struct mlx5_ifc_query_cong_status_out_bits {
4821 u8 status[0x8];
b4ff3a36 4822 u8 reserved_at_8[0x18];
e281682b
SM		 4823
4824 u8 syndrome[0x20];
4825
b4ff3a36 4826 u8 reserved_at_40[0x20];
e281682b
SM		 4827
4828 u8 enable[0x1];
4829 u8 tag_enable[0x1];
b4ff3a36 4830 u8 reserved_at_62[0x1e];
e281682b
SM		 4831};
4832
4833struct mlx5_ifc_query_cong_status_in_bits {
4834 u8 opcode[0x10];
b4ff3a36 4835 u8 reserved_at_10[0x10];
e281682b 4836
b4ff3a36 4837 u8 reserved_at_20[0x10];
e281682b
SM		 4838 u8 op_mod[0x10];
4839
b4ff3a36 4840 u8 reserved_at_40[0x18];
e281682b
SM		 4841 u8 priority[0x4];
4842 u8 cong_protocol[0x4];
4843
b4ff3a36 4844 u8 reserved_at_60[0x20];
e281682b
SM		 4845};
4846
4847struct mlx5_ifc_query_cong_statistics_out_bits {
4848 u8 status[0x8];
b4ff3a36 4849 u8 reserved_at_8[0x18];
e281682b
SM		 4850
4851 u8 syndrome[0x20];
4852
b4ff3a36 4853 u8 reserved_at_40[0x40];
e281682b 4854
e1f24a79 4855 u8 rp_cur_flows[0x20];
e281682b
SM		 4856
4857 u8 sum_flows[0x20];
4858
e1f24a79 4859 u8 rp_cnp_ignored_high[0x20];
e281682b 4860
e1f24a79 4861 u8 rp_cnp_ignored_low[0x20];
e281682b 4862
e1f24a79 4863 u8 rp_cnp_handled_high[0x20];
e281682b 4864
e1f24a79 4865 u8 rp_cnp_handled_low[0x20];
e281682b 4866
b4ff3a36 4867 u8 reserved_at_140[0x100];
e281682b
SM		 4868
4869 u8 time_stamp_high[0x20];
4870
4871 u8 time_stamp_low[0x20];
4872
4873 u8 accumulators_period[0x20];
4874
e1f24a79 4875 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 4876
e1f24a79 4877 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 4878
e1f24a79 4879 u8 np_cnp_sent_high[0x20];
e281682b 4880
e1f24a79 4881 u8 np_cnp_sent_low[0x20];
e281682b 4882
b4ff3a36 4883 u8 reserved_at_320[0x560];
e281682b
SM		 4884};
4885
4886struct mlx5_ifc_query_cong_statistics_in_bits {
4887 u8 opcode[0x10];
b4ff3a36 4888 u8 reserved_at_10[0x10];
e281682b 4889
b4ff3a36 4890 u8 reserved_at_20[0x10];
e281682b
SM		 4891 u8 op_mod[0x10];
4892
4893 u8 clear[0x1];
b4ff3a36 4894 u8 reserved_at_41[0x1f];
e281682b 4895
b4ff3a36 4896 u8 reserved_at_60[0x20];
e281682b
SM		 4897};
4898
4899struct mlx5_ifc_query_cong_params_out_bits {
4900 u8 status[0x8];
b4ff3a36 4901 u8 reserved_at_8[0x18];
e281682b
SM		 4902
4903 u8 syndrome[0x20];
4904
b4ff3a36 4905 u8 reserved_at_40[0x40];
e281682b
SM		 4906
4907 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4908};
4909
4910struct mlx5_ifc_query_cong_params_in_bits {
4911 u8 opcode[0x10];
b4ff3a36 4912 u8 reserved_at_10[0x10];
e281682b 4913
b4ff3a36 4914 u8 reserved_at_20[0x10];
e281682b
SM		 4915 u8 op_mod[0x10];
4916
b4ff3a36 4917 u8 reserved_at_40[0x1c];
e281682b
SM		 4918 u8 cong_protocol[0x4];
4919
b4ff3a36 4920 u8 reserved_at_60[0x20];
e281682b
SM		 4921};
4922
4923struct mlx5_ifc_query_adapter_out_bits {
4924 u8 status[0x8];
b4ff3a36 4925 u8 reserved_at_8[0x18];
e281682b
SM		 4926
4927 u8 syndrome[0x20];
4928
b4ff3a36 4929 u8 reserved_at_40[0x40];
e281682b
SM		 4930
4931 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4932};
4933
4934struct mlx5_ifc_query_adapter_in_bits {
4935 u8 opcode[0x10];
b4ff3a36 4936 u8 reserved_at_10[0x10];
e281682b 4937
b4ff3a36 4938 u8 reserved_at_20[0x10];
e281682b
SM		 4939 u8 op_mod[0x10];
4940
b4ff3a36 4941 u8 reserved_at_40[0x40];
e281682b
SM		 4942};
4943
4944struct mlx5_ifc_qp_2rst_out_bits {
4945 u8 status[0x8];
b4ff3a36 4946 u8 reserved_at_8[0x18];
e281682b
SM		 4947
4948 u8 syndrome[0x20];
4949
b4ff3a36 4950 u8 reserved_at_40[0x40];
e281682b
SM		 4951};
4952
4953struct mlx5_ifc_qp_2rst_in_bits {
4954 u8 opcode[0x10];
b4ff3a36 4955 u8 reserved_at_10[0x10];
e281682b 4956
b4ff3a36 4957 u8 reserved_at_20[0x10];
e281682b
SM		 4958 u8 op_mod[0x10];
4959
b4ff3a36 4960 u8 reserved_at_40[0x8];
e281682b
SM		 4961 u8 qpn[0x18];
4962
b4ff3a36 4963 u8 reserved_at_60[0x20];
e281682b
SM		 4964};
4965
4966struct mlx5_ifc_qp_2err_out_bits {
4967 u8 status[0x8];
b4ff3a36 4968 u8 reserved_at_8[0x18];
e281682b
SM		 4969
4970 u8 syndrome[0x20];
4971
b4ff3a36 4972 u8 reserved_at_40[0x40];
e281682b
SM		 4973};
4974
4975struct mlx5_ifc_qp_2err_in_bits {
4976 u8 opcode[0x10];
b4ff3a36 4977 u8 reserved_at_10[0x10];
e281682b 4978
b4ff3a36 4979 u8 reserved_at_20[0x10];
e281682b
SM		 4980 u8 op_mod[0x10];
4981
b4ff3a36 4982 u8 reserved_at_40[0x8];
e281682b
SM		 4983 u8 qpn[0x18];
4984
b4ff3a36 4985 u8 reserved_at_60[0x20];
e281682b
SM		 4986};
4987
4988struct mlx5_ifc_page_fault_resume_out_bits {
4989 u8 status[0x8];
b4ff3a36 4990 u8 reserved_at_8[0x18];
e281682b
SM		 4991
4992 u8 syndrome[0x20];
4993
b4ff3a36 4994 u8 reserved_at_40[0x40];
e281682b
SM		 4995};
4996
4997struct mlx5_ifc_page_fault_resume_in_bits {
4998 u8 opcode[0x10];
b4ff3a36 4999 u8 reserved_at_10[0x10];
e281682b 5000
b4ff3a36 5001 u8 reserved_at_20[0x10];
e281682b
SM		 5002 u8 op_mod[0x10];
5003
5004 u8 error[0x1];
b4ff3a36 5005 u8 reserved_at_41[0x4];
223cdc72
AK		 5006 u8 page_fault_type[0x3];
5007 u8 wq_number[0x18];
e281682b 5008
223cdc72
AK		 5009 u8 reserved_at_60[0x8];
5010 u8 token[0x18];
e281682b
SM		 5011};
5012
5013struct mlx5_ifc_nop_out_bits {
5014 u8 status[0x8];
b4ff3a36 5015 u8 reserved_at_8[0x18];
e281682b
SM		 5016
5017 u8 syndrome[0x20];
5018
b4ff3a36 5019 u8 reserved_at_40[0x40];
e281682b
SM		 5020};
5021
5022struct mlx5_ifc_nop_in_bits {
5023 u8 opcode[0x10];
b4ff3a36 5024 u8 reserved_at_10[0x10];
e281682b 5025
b4ff3a36 5026 u8 reserved_at_20[0x10];
e281682b
SM		 5027 u8 op_mod[0x10];
5028
b4ff3a36 5029 u8 reserved_at_40[0x40];
e281682b
SM		 5030};
5031
5032struct mlx5_ifc_modify_vport_state_out_bits {
5033 u8 status[0x8];
b4ff3a36 5034 u8 reserved_at_8[0x18];
e281682b
SM		 5035
5036 u8 syndrome[0x20];
5037
b4ff3a36 5038 u8 reserved_at_40[0x40];
e281682b
SM		 5039};
5040
5041struct mlx5_ifc_modify_vport_state_in_bits {
5042 u8 opcode[0x10];
b4ff3a36 5043 u8 reserved_at_10[0x10];
e281682b 5044
b4ff3a36 5045 u8 reserved_at_20[0x10];
e281682b
SM		 5046 u8 op_mod[0x10];
5047
5048 u8 other_vport[0x1];
b4ff3a36 5049 u8 reserved_at_41[0xf];
e281682b
SM		 5050 u8 vport_number[0x10];
5051
b4ff3a36 5052 u8 reserved_at_60[0x18];
e281682b 5053 u8 admin_state[0x4];
b4ff3a36 5054 u8 reserved_at_7c[0x4];
e281682b
SM		 5055};
5056
5057struct mlx5_ifc_modify_tis_out_bits {
5058 u8 status[0x8];
b4ff3a36 5059 u8 reserved_at_8[0x18];
e281682b
SM		 5060
5061 u8 syndrome[0x20];
5062
b4ff3a36 5063 u8 reserved_at_40[0x40];
e281682b
SM		 5064};
5065
75850d0b 5066struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5067 u8 reserved_at_0[0x20];
75850d0b 5068
84df61eb
AH		 5069 u8 reserved_at_20[0x1d];
5070 u8 lag_tx_port_affinity[0x1];
5071 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5072 u8 prio[0x1];
5073};
5074
e281682b
SM		 5075struct mlx5_ifc_modify_tis_in_bits {
5076 u8 opcode[0x10];
b4ff3a36 5077 u8 reserved_at_10[0x10];
e281682b 5078
b4ff3a36 5079 u8 reserved_at_20[0x10];
e281682b
SM		 5080 u8 op_mod[0x10];
5081
b4ff3a36 5082 u8 reserved_at_40[0x8];
e281682b
SM		 5083 u8 tisn[0x18];
5084
b4ff3a36 5085 u8 reserved_at_60[0x20];
e281682b 5086
75850d0b 5087 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5088
b4ff3a36 5089 u8 reserved_at_c0[0x40];
e281682b
SM		 5090
5091 struct mlx5_ifc_tisc_bits ctx;
5092};
5093
d9eea403 5094struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5095 u8 reserved_at_0[0x20];
d9eea403 5096
b4ff3a36 5097 u8 reserved_at_20[0x1b];
66189961 5098 u8 self_lb_en[0x1];
bdfc028d
TT		 5099 u8 reserved_at_3c[0x1];
5100 u8 hash[0x1];
5101 u8 reserved_at_3e[0x1];
d9eea403
AS		 5102 u8 lro[0x1];
5103};
5104
e281682b
SM		 5105struct mlx5_ifc_modify_tir_out_bits {
5106 u8 status[0x8];
b4ff3a36 5107 u8 reserved_at_8[0x18];
e281682b
SM		 5108
5109 u8 syndrome[0x20];
5110
b4ff3a36 5111 u8 reserved_at_40[0x40];
e281682b
SM		 5112};
5113
5114struct mlx5_ifc_modify_tir_in_bits {
5115 u8 opcode[0x10];
b4ff3a36 5116 u8 reserved_at_10[0x10];
e281682b 5117
b4ff3a36 5118 u8 reserved_at_20[0x10];
e281682b
SM		 5119 u8 op_mod[0x10];
5120
b4ff3a36 5121 u8 reserved_at_40[0x8];
e281682b
SM		 5122 u8 tirn[0x18];
5123
b4ff3a36 5124 u8 reserved_at_60[0x20];
e281682b 5125
d9eea403 5126 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5127
b4ff3a36 5128 u8 reserved_at_c0[0x40];
e281682b
SM		 5129
5130 struct mlx5_ifc_tirc_bits ctx;
5131};
5132
5133struct mlx5_ifc_modify_sq_out_bits {
5134 u8 status[0x8];
b4ff3a36 5135 u8 reserved_at_8[0x18];
e281682b
SM		 5136
5137 u8 syndrome[0x20];
5138
b4ff3a36 5139 u8 reserved_at_40[0x40];
e281682b
SM		 5140};
5141
5142struct mlx5_ifc_modify_sq_in_bits {
5143 u8 opcode[0x10];
b4ff3a36 5144 u8 reserved_at_10[0x10];
e281682b 5145
b4ff3a36 5146 u8 reserved_at_20[0x10];
e281682b
SM		 5147 u8 op_mod[0x10];
5148
5149 u8 sq_state[0x4];
b4ff3a36 5150 u8 reserved_at_44[0x4];
e281682b
SM		 5151 u8 sqn[0x18];
5152
b4ff3a36 5153 u8 reserved_at_60[0x20];
e281682b
SM		 5154
5155 u8 modify_bitmask[0x40];
5156
b4ff3a36 5157 u8 reserved_at_c0[0x40];
e281682b
SM		 5158
5159 struct mlx5_ifc_sqc_bits ctx;
5160};
5161
813f8540
MHY		 5162struct mlx5_ifc_modify_scheduling_element_out_bits {
5163 u8 status[0x8];
5164 u8 reserved_at_8[0x18];
5165
5166 u8 syndrome[0x20];
5167
5168 u8 reserved_at_40[0x1c0];
5169};
5170
5171enum {
5172 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5173 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5174};
5175
5176struct mlx5_ifc_modify_scheduling_element_in_bits {
5177 u8 opcode[0x10];
5178 u8 reserved_at_10[0x10];
5179
5180 u8 reserved_at_20[0x10];
5181 u8 op_mod[0x10];
5182
5183 u8 scheduling_hierarchy[0x8];
5184 u8 reserved_at_48[0x18];
5185
5186 u8 scheduling_element_id[0x20];
5187
5188 u8 reserved_at_80[0x20];
5189
5190 u8 modify_bitmask[0x20];
5191
5192 u8 reserved_at_c0[0x40];
5193
5194 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5195
5196 u8 reserved_at_300[0x100];
5197};
5198
e281682b
SM		 5199struct mlx5_ifc_modify_rqt_out_bits {
5200 u8 status[0x8];
b4ff3a36 5201 u8 reserved_at_8[0x18];
e281682b
SM		 5202
5203 u8 syndrome[0x20];
5204
b4ff3a36 5205 u8 reserved_at_40[0x40];
e281682b
SM		 5206};
5207
5c50368f 5208struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5209 u8 reserved_at_0[0x20];
5c50368f 5210
b4ff3a36 5211 u8 reserved_at_20[0x1f];
5c50368f
AS		 5212 u8 rqn_list[0x1];
5213};
5214
e281682b
SM		 5215struct mlx5_ifc_modify_rqt_in_bits {
5216 u8 opcode[0x10];
b4ff3a36 5217 u8 reserved_at_10[0x10];
e281682b 5218
b4ff3a36 5219 u8 reserved_at_20[0x10];
e281682b
SM		 5220 u8 op_mod[0x10];
5221
b4ff3a36 5222 u8 reserved_at_40[0x8];
e281682b
SM		 5223 u8 rqtn[0x18];
5224
b4ff3a36 5225 u8 reserved_at_60[0x20];
e281682b 5226
5c50368f 5227 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5228
b4ff3a36 5229 u8 reserved_at_c0[0x40];
e281682b
SM		 5230
5231 struct mlx5_ifc_rqtc_bits ctx;
5232};
5233
5234struct mlx5_ifc_modify_rq_out_bits {
5235 u8 status[0x8];
b4ff3a36 5236 u8 reserved_at_8[0x18];
e281682b
SM		 5237
5238 u8 syndrome[0x20];
5239
b4ff3a36 5240 u8 reserved_at_40[0x40];
e281682b
SM		 5241};
5242
83b502a1
AV		 5243enum {
5244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5245 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5246 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5247};
5248
e281682b
SM		 5249struct mlx5_ifc_modify_rq_in_bits {
5250 u8 opcode[0x10];
b4ff3a36 5251 u8 reserved_at_10[0x10];
e281682b 5252
b4ff3a36 5253 u8 reserved_at_20[0x10];
e281682b
SM		 5254 u8 op_mod[0x10];
5255
5256 u8 rq_state[0x4];
b4ff3a36 5257 u8 reserved_at_44[0x4];
e281682b
SM		 5258 u8 rqn[0x18];
5259
b4ff3a36 5260 u8 reserved_at_60[0x20];
e281682b
SM		 5261
5262 u8 modify_bitmask[0x40];
5263
b4ff3a36 5264 u8 reserved_at_c0[0x40];
e281682b
SM		 5265
5266 struct mlx5_ifc_rqc_bits ctx;
5267};
5268
5269struct mlx5_ifc_modify_rmp_out_bits {
5270 u8 status[0x8];
b4ff3a36 5271 u8 reserved_at_8[0x18];
e281682b
SM		 5272
5273 u8 syndrome[0x20];
5274
b4ff3a36 5275 u8 reserved_at_40[0x40];
e281682b
SM		 5276};
5277
01949d01 5278struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5279 u8 reserved_at_0[0x20];
01949d01 5280
b4ff3a36 5281 u8 reserved_at_20[0x1f];
01949d01
HA		 5282 u8 lwm[0x1];
5283};
5284
e281682b
SM		 5285struct mlx5_ifc_modify_rmp_in_bits {
5286 u8 opcode[0x10];
b4ff3a36 5287 u8 reserved_at_10[0x10];
e281682b 5288
b4ff3a36 5289 u8 reserved_at_20[0x10];
e281682b
SM		 5290 u8 op_mod[0x10];
5291
5292 u8 rmp_state[0x4];
b4ff3a36 5293 u8 reserved_at_44[0x4];
e281682b
SM		 5294 u8 rmpn[0x18];
5295
b4ff3a36 5296 u8 reserved_at_60[0x20];
e281682b 5297
01949d01 5298 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5299
b4ff3a36 5300 u8 reserved_at_c0[0x40];
e281682b
SM		 5301
5302 struct mlx5_ifc_rmpc_bits ctx;
5303};
5304
5305struct mlx5_ifc_modify_nic_vport_context_out_bits {
5306 u8 status[0x8];
b4ff3a36 5307 u8 reserved_at_8[0x18];
e281682b
SM		 5308
5309 u8 syndrome[0x20];
5310
b4ff3a36 5311 u8 reserved_at_40[0x40];
e281682b
SM		 5312};
5313
5314struct mlx5_ifc_modify_nic_vport_field_select_bits {
bded747b
HN		 5315 u8 reserved_at_0[0x14];
5316 u8 disable_uc_local_lb[0x1];
5317 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5318 u8 node_guid[0x1];
5319 u8 port_guid[0x1];
9def7121 5320 u8 min_inline[0x1];
d82b7318
SM		 5321 u8 mtu[0x1];
5322 u8 change_event[0x1];
5323 u8 promisc[0x1];
e281682b
SM		 5324 u8 permanent_address[0x1];
5325 u8 addresses_list[0x1];
5326 u8 roce_en[0x1];
b4ff3a36 5327 u8 reserved_at_1f[0x1];
e281682b
SM		 5328};
5329
5330struct mlx5_ifc_modify_nic_vport_context_in_bits {
5331 u8 opcode[0x10];
b4ff3a36 5332 u8 reserved_at_10[0x10];
e281682b 5333
b4ff3a36 5334 u8 reserved_at_20[0x10];
e281682b
SM		 5335 u8 op_mod[0x10];
5336
5337 u8 other_vport[0x1];
b4ff3a36 5338 u8 reserved_at_41[0xf];
e281682b
SM		 5339 u8 vport_number[0x10];
5340
5341 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5342
b4ff3a36 5343 u8 reserved_at_80[0x780];
e281682b
SM		 5344
5345 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5346};
5347
5348struct mlx5_ifc_modify_hca_vport_context_out_bits {
5349 u8 status[0x8];
b4ff3a36 5350 u8 reserved_at_8[0x18];
e281682b
SM		 5351
5352 u8 syndrome[0x20];
5353
b4ff3a36 5354 u8 reserved_at_40[0x40];
e281682b
SM		 5355};
5356
5357struct mlx5_ifc_modify_hca_vport_context_in_bits {
5358 u8 opcode[0x10];
b4ff3a36 5359 u8 reserved_at_10[0x10];
e281682b 5360
b4ff3a36 5361 u8 reserved_at_20[0x10];
e281682b
SM		 5362 u8 op_mod[0x10];
5363
5364 u8 other_vport[0x1];
b4ff3a36 5365 u8 reserved_at_41[0xb];
707c4602 5366 u8 port_num[0x4];
e281682b
SM		 5367 u8 vport_number[0x10];
5368
b4ff3a36 5369 u8 reserved_at_60[0x20];
e281682b
SM		 5370
5371 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5372};
5373
5374struct mlx5_ifc_modify_cq_out_bits {
5375 u8 status[0x8];
b4ff3a36 5376 u8 reserved_at_8[0x18];
e281682b
SM		 5377
5378 u8 syndrome[0x20];
5379
b4ff3a36 5380 u8 reserved_at_40[0x40];
e281682b
SM		 5381};
5382
5383enum {
5384 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5385 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5386};
5387
5388struct mlx5_ifc_modify_cq_in_bits {
5389 u8 opcode[0x10];
b4ff3a36 5390 u8 reserved_at_10[0x10];
e281682b 5391
b4ff3a36 5392 u8 reserved_at_20[0x10];
e281682b
SM		 5393 u8 op_mod[0x10];
5394
b4ff3a36 5395 u8 reserved_at_40[0x8];
e281682b
SM		 5396 u8 cqn[0x18];
5397
5398 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5399
5400 struct mlx5_ifc_cqc_bits cq_context;
5401
014db75d
ES		 5402 u8 reserved_at_280[0x60];
5403
5404 u8 cq_umem_valid[0x1];
5405 u8 reserved_at_2e1[0x1f];
5406
5407 u8 reserved_at_300[0x580];
e281682b
SM		 5408
5409 u8 pas[0][0x40];
5410};
5411
5412struct mlx5_ifc_modify_cong_status_out_bits {
5413 u8 status[0x8];
b4ff3a36 5414 u8 reserved_at_8[0x18];
e281682b
SM		 5415
5416 u8 syndrome[0x20];
5417
b4ff3a36 5418 u8 reserved_at_40[0x40];
e281682b
SM		 5419};
5420
5421struct mlx5_ifc_modify_cong_status_in_bits {
5422 u8 opcode[0x10];
b4ff3a36 5423 u8 reserved_at_10[0x10];
e281682b 5424
b4ff3a36 5425 u8 reserved_at_20[0x10];
e281682b
SM		 5426 u8 op_mod[0x10];
5427
b4ff3a36 5428 u8 reserved_at_40[0x18];
e281682b
SM		 5429 u8 priority[0x4];
5430 u8 cong_protocol[0x4];
5431
5432 u8 enable[0x1];
5433 u8 tag_enable[0x1];
b4ff3a36 5434 u8 reserved_at_62[0x1e];
e281682b
SM		 5435};
5436
5437struct mlx5_ifc_modify_cong_params_out_bits {
5438 u8 status[0x8];
b4ff3a36 5439 u8 reserved_at_8[0x18];
e281682b
SM		 5440
5441 u8 syndrome[0x20];
5442
b4ff3a36 5443 u8 reserved_at_40[0x40];
e281682b
SM		 5444};
5445
5446struct mlx5_ifc_modify_cong_params_in_bits {
5447 u8 opcode[0x10];
b4ff3a36 5448 u8 reserved_at_10[0x10];
e281682b 5449
b4ff3a36 5450 u8 reserved_at_20[0x10];
e281682b
SM		 5451 u8 op_mod[0x10];
5452
b4ff3a36 5453 u8 reserved_at_40[0x1c];
e281682b
SM		 5454 u8 cong_protocol[0x4];
5455
5456 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5457
b4ff3a36 5458 u8 reserved_at_80[0x80];
e281682b
SM		 5459
5460 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5461};
5462
5463struct mlx5_ifc_manage_pages_out_bits {
5464 u8 status[0x8];
b4ff3a36 5465 u8 reserved_at_8[0x18];
e281682b
SM		 5466
5467 u8 syndrome[0x20];
5468
5469 u8 output_num_entries[0x20];
5470
b4ff3a36 5471 u8 reserved_at_60[0x20];
e281682b
SM		 5472
5473 u8 pas[0][0x40];
5474};
5475
5476enum {
5477 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5478 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5479 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5480};
5481
5482struct mlx5_ifc_manage_pages_in_bits {
5483 u8 opcode[0x10];
b4ff3a36 5484 u8 reserved_at_10[0x10];
e281682b 5485
b4ff3a36 5486 u8 reserved_at_20[0x10];
e281682b
SM		 5487 u8 op_mod[0x10];
5488
b4ff3a36 5489 u8 reserved_at_40[0x10];
e281682b
SM		 5490 u8 function_id[0x10];
5491
5492 u8 input_num_entries[0x20];
5493
5494 u8 pas[0][0x40];
5495};
5496
5497struct mlx5_ifc_mad_ifc_out_bits {
5498 u8 status[0x8];
b4ff3a36 5499 u8 reserved_at_8[0x18];
e281682b
SM		 5500
5501 u8 syndrome[0x20];
5502
b4ff3a36 5503 u8 reserved_at_40[0x40];
e281682b
SM		 5504
5505 u8 response_mad_packet[256][0x8];
5506};
5507
5508struct mlx5_ifc_mad_ifc_in_bits {
5509 u8 opcode[0x10];
b4ff3a36 5510 u8 reserved_at_10[0x10];
e281682b 5511
b4ff3a36 5512 u8 reserved_at_20[0x10];
e281682b
SM		 5513 u8 op_mod[0x10];
5514
5515 u8 remote_lid[0x10];
b4ff3a36 5516 u8 reserved_at_50[0x8];
e281682b
SM		 5517 u8 port[0x8];
5518
b4ff3a36 5519 u8 reserved_at_60[0x20];
e281682b
SM		 5520
5521 u8 mad[256][0x8];
5522};
5523
5524struct mlx5_ifc_init_hca_out_bits {
5525 u8 status[0x8];
b4ff3a36 5526 u8 reserved_at_8[0x18];
e281682b
SM		 5527
5528 u8 syndrome[0x20];
5529
b4ff3a36 5530 u8 reserved_at_40[0x40];
e281682b
SM		 5531};
5532
5533struct mlx5_ifc_init_hca_in_bits {
5534 u8 opcode[0x10];
b4ff3a36 5535 u8 reserved_at_10[0x10];
e281682b 5536
b4ff3a36 5537 u8 reserved_at_20[0x10];
e281682b
SM		 5538 u8 op_mod[0x10];
5539
b4ff3a36 5540 u8 reserved_at_40[0x40];
e281682b
SM		 5541};
5542
5543struct mlx5_ifc_init2rtr_qp_out_bits {
5544 u8 status[0x8];
b4ff3a36 5545 u8 reserved_at_8[0x18];
e281682b
SM		 5546
5547 u8 syndrome[0x20];
5548
b4ff3a36 5549 u8 reserved_at_40[0x40];
e281682b
SM		 5550};
5551
5552struct mlx5_ifc_init2rtr_qp_in_bits {
5553 u8 opcode[0x10];
b4ff3a36 5554 u8 reserved_at_10[0x10];
e281682b 5555
b4ff3a36 5556 u8 reserved_at_20[0x10];
e281682b
SM		 5557 u8 op_mod[0x10];
5558
b4ff3a36 5559 u8 reserved_at_40[0x8];
e281682b
SM		 5560 u8 qpn[0x18];
5561
b4ff3a36 5562 u8 reserved_at_60[0x20];
e281682b
SM		 5563
5564 u8 opt_param_mask[0x20];
5565
b4ff3a36 5566 u8 reserved_at_a0[0x20];
e281682b
SM		 5567
5568 struct mlx5_ifc_qpc_bits qpc;
5569
b4ff3a36 5570 u8 reserved_at_800[0x80];
e281682b
SM		 5571};
5572
5573struct mlx5_ifc_init2init_qp_out_bits {
5574 u8 status[0x8];
b4ff3a36 5575 u8 reserved_at_8[0x18];
e281682b
SM		 5576
5577 u8 syndrome[0x20];
5578
b4ff3a36 5579 u8 reserved_at_40[0x40];
e281682b
SM		 5580};
5581
5582struct mlx5_ifc_init2init_qp_in_bits {
5583 u8 opcode[0x10];
b4ff3a36 5584 u8 reserved_at_10[0x10];
e281682b 5585
b4ff3a36 5586 u8 reserved_at_20[0x10];
e281682b
SM		 5587 u8 op_mod[0x10];
5588
b4ff3a36 5589 u8 reserved_at_40[0x8];
e281682b
SM		 5590 u8 qpn[0x18];
5591
b4ff3a36 5592 u8 reserved_at_60[0x20];
e281682b
SM		 5593
5594 u8 opt_param_mask[0x20];
5595
b4ff3a36 5596 u8 reserved_at_a0[0x20];
e281682b
SM		 5597
5598 struct mlx5_ifc_qpc_bits qpc;
5599
b4ff3a36 5600 u8 reserved_at_800[0x80];
e281682b
SM		 5601};
5602
5603struct mlx5_ifc_get_dropped_packet_log_out_bits {
5604 u8 status[0x8];
b4ff3a36 5605 u8 reserved_at_8[0x18];
e281682b
SM		 5606
5607 u8 syndrome[0x20];
5608
b4ff3a36 5609 u8 reserved_at_40[0x40];
e281682b
SM		 5610
5611 u8 packet_headers_log[128][0x8];
5612
5613 u8 packet_syndrome[64][0x8];
5614};
5615
5616struct mlx5_ifc_get_dropped_packet_log_in_bits {
5617 u8 opcode[0x10];
b4ff3a36 5618 u8 reserved_at_10[0x10];
e281682b 5619
b4ff3a36 5620 u8 reserved_at_20[0x10];
e281682b
SM		 5621 u8 op_mod[0x10];
5622
b4ff3a36 5623 u8 reserved_at_40[0x40];
e281682b
SM		 5624};
5625
5626struct mlx5_ifc_gen_eqe_in_bits {
5627 u8 opcode[0x10];
b4ff3a36 5628 u8 reserved_at_10[0x10];
e281682b 5629
b4ff3a36 5630 u8 reserved_at_20[0x10];
e281682b
SM		 5631 u8 op_mod[0x10];
5632
b4ff3a36 5633 u8 reserved_at_40[0x18];
e281682b
SM		 5634 u8 eq_number[0x8];
5635
b4ff3a36 5636 u8 reserved_at_60[0x20];
e281682b
SM		 5637
5638 u8 eqe[64][0x8];
5639};
5640
5641struct mlx5_ifc_gen_eq_out_bits {
5642 u8 status[0x8];
b4ff3a36 5643 u8 reserved_at_8[0x18];
e281682b
SM		 5644
5645 u8 syndrome[0x20];
5646
b4ff3a36 5647 u8 reserved_at_40[0x40];
e281682b
SM		 5648};
5649
5650struct mlx5_ifc_enable_hca_out_bits {
5651 u8 status[0x8];
b4ff3a36 5652 u8 reserved_at_8[0x18];
e281682b
SM		 5653
5654 u8 syndrome[0x20];
5655
b4ff3a36 5656 u8 reserved_at_40[0x20];
e281682b
SM		 5657};
5658
5659struct mlx5_ifc_enable_hca_in_bits {
5660 u8 opcode[0x10];
b4ff3a36 5661 u8 reserved_at_10[0x10];
e281682b 5662
b4ff3a36 5663 u8 reserved_at_20[0x10];
e281682b
SM		 5664 u8 op_mod[0x10];
5665
b4ff3a36 5666 u8 reserved_at_40[0x10];
e281682b
SM		 5667 u8 function_id[0x10];
5668
b4ff3a36 5669 u8 reserved_at_60[0x20];
e281682b
SM		 5670};
5671
5672struct mlx5_ifc_drain_dct_out_bits {
5673 u8 status[0x8];
b4ff3a36 5674 u8 reserved_at_8[0x18];
e281682b
SM		 5675
5676 u8 syndrome[0x20];
5677
b4ff3a36 5678 u8 reserved_at_40[0x40];
e281682b
SM		 5679};
5680
5681struct mlx5_ifc_drain_dct_in_bits {
5682 u8 opcode[0x10];
b4ff3a36 5683 u8 reserved_at_10[0x10];
e281682b 5684
b4ff3a36 5685 u8 reserved_at_20[0x10];
e281682b
SM		 5686 u8 op_mod[0x10];
5687
b4ff3a36 5688 u8 reserved_at_40[0x8];
e281682b
SM		 5689 u8 dctn[0x18];
5690
b4ff3a36 5691 u8 reserved_at_60[0x20];
e281682b
SM		 5692};
5693
5694struct mlx5_ifc_disable_hca_out_bits {
5695 u8 status[0x8];
b4ff3a36 5696 u8 reserved_at_8[0x18];
e281682b
SM		 5697
5698 u8 syndrome[0x20];
5699
b4ff3a36 5700 u8 reserved_at_40[0x20];
e281682b
SM		 5701};
5702
5703struct mlx5_ifc_disable_hca_in_bits {
5704 u8 opcode[0x10];
b4ff3a36 5705 u8 reserved_at_10[0x10];
e281682b 5706
b4ff3a36 5707 u8 reserved_at_20[0x10];
e281682b
SM		 5708 u8 op_mod[0x10];
5709
b4ff3a36 5710 u8 reserved_at_40[0x10];
e281682b
SM		 5711 u8 function_id[0x10];
5712
b4ff3a36 5713 u8 reserved_at_60[0x20];
e281682b
SM		 5714};
5715
5716struct mlx5_ifc_detach_from_mcg_out_bits {
5717 u8 status[0x8];
b4ff3a36 5718 u8 reserved_at_8[0x18];
e281682b
SM		 5719
5720 u8 syndrome[0x20];
5721
b4ff3a36 5722 u8 reserved_at_40[0x40];
e281682b
SM		 5723};
5724
5725struct mlx5_ifc_detach_from_mcg_in_bits {
5726 u8 opcode[0x10];
b4ff3a36 5727 u8 reserved_at_10[0x10];
e281682b 5728
b4ff3a36 5729 u8 reserved_at_20[0x10];
e281682b
SM		 5730 u8 op_mod[0x10];
5731
b4ff3a36 5732 u8 reserved_at_40[0x8];
e281682b
SM		 5733 u8 qpn[0x18];
5734
b4ff3a36 5735 u8 reserved_at_60[0x20];
e281682b
SM		 5736
5737 u8 multicast_gid[16][0x8];
5738};
5739
7486216b
SM		 5740struct mlx5_ifc_destroy_xrq_out_bits {
5741 u8 status[0x8];
5742 u8 reserved_at_8[0x18];
5743
5744 u8 syndrome[0x20];
5745
5746 u8 reserved_at_40[0x40];
5747};
5748
5749struct mlx5_ifc_destroy_xrq_in_bits {
5750 u8 opcode[0x10];
5751 u8 reserved_at_10[0x10];
5752
5753 u8 reserved_at_20[0x10];
5754 u8 op_mod[0x10];
5755
5756 u8 reserved_at_40[0x8];
5757 u8 xrqn[0x18];
5758
5759 u8 reserved_at_60[0x20];
5760};
5761
e281682b
SM		 5762struct mlx5_ifc_destroy_xrc_srq_out_bits {
5763 u8 status[0x8];
b4ff3a36 5764 u8 reserved_at_8[0x18];
e281682b
SM		 5765
5766 u8 syndrome[0x20];
5767
b4ff3a36 5768 u8 reserved_at_40[0x40];
e281682b
SM		 5769};
5770
5771struct mlx5_ifc_destroy_xrc_srq_in_bits {
5772 u8 opcode[0x10];
b4ff3a36 5773 u8 reserved_at_10[0x10];
e281682b 5774
b4ff3a36 5775 u8 reserved_at_20[0x10];
e281682b
SM		 5776 u8 op_mod[0x10];
5777
b4ff3a36 5778 u8 reserved_at_40[0x8];
e281682b
SM		 5779 u8 xrc_srqn[0x18];
5780
b4ff3a36 5781 u8 reserved_at_60[0x20];
e281682b
SM		 5782};
5783
5784struct mlx5_ifc_destroy_tis_out_bits {
5785 u8 status[0x8];
b4ff3a36 5786 u8 reserved_at_8[0x18];
e281682b
SM		 5787
5788 u8 syndrome[0x20];
5789
b4ff3a36 5790 u8 reserved_at_40[0x40];
e281682b
SM		 5791};
5792
5793struct mlx5_ifc_destroy_tis_in_bits {
5794 u8 opcode[0x10];
b4ff3a36 5795 u8 reserved_at_10[0x10];
e281682b 5796
b4ff3a36 5797 u8 reserved_at_20[0x10];
e281682b
SM		 5798 u8 op_mod[0x10];
5799
b4ff3a36 5800 u8 reserved_at_40[0x8];
e281682b
SM		 5801 u8 tisn[0x18];
5802
b4ff3a36 5803 u8 reserved_at_60[0x20];
e281682b
SM		 5804};
5805
5806struct mlx5_ifc_destroy_tir_out_bits {
5807 u8 status[0x8];
b4ff3a36 5808 u8 reserved_at_8[0x18];
e281682b
SM		 5809
5810 u8 syndrome[0x20];
5811
b4ff3a36 5812 u8 reserved_at_40[0x40];
e281682b
SM		 5813};
5814
5815struct mlx5_ifc_destroy_tir_in_bits {
5816 u8 opcode[0x10];
b4ff3a36 5817 u8 reserved_at_10[0x10];
e281682b 5818
b4ff3a36 5819 u8 reserved_at_20[0x10];
e281682b
SM		 5820 u8 op_mod[0x10];
5821
b4ff3a36 5822 u8 reserved_at_40[0x8];
e281682b
SM		 5823 u8 tirn[0x18];
5824
b4ff3a36 5825 u8 reserved_at_60[0x20];
e281682b
SM		 5826};
5827
5828struct mlx5_ifc_destroy_srq_out_bits {
5829 u8 status[0x8];
b4ff3a36 5830 u8 reserved_at_8[0x18];
e281682b
SM		 5831
5832 u8 syndrome[0x20];
5833
b4ff3a36 5834 u8 reserved_at_40[0x40];
e281682b
SM		 5835};
5836
5837struct mlx5_ifc_destroy_srq_in_bits {
5838 u8 opcode[0x10];
b4ff3a36 5839 u8 reserved_at_10[0x10];
e281682b 5840
b4ff3a36 5841 u8 reserved_at_20[0x10];
e281682b
SM		 5842 u8 op_mod[0x10];
5843
b4ff3a36 5844 u8 reserved_at_40[0x8];
e281682b
SM		 5845 u8 srqn[0x18];
5846
b4ff3a36 5847 u8 reserved_at_60[0x20];
e281682b
SM		 5848};
5849
5850struct mlx5_ifc_destroy_sq_out_bits {
5851 u8 status[0x8];
b4ff3a36 5852 u8 reserved_at_8[0x18];
e281682b
SM		 5853
5854 u8 syndrome[0x20];
5855
b4ff3a36 5856 u8 reserved_at_40[0x40];
e281682b
SM		 5857};
5858
5859struct mlx5_ifc_destroy_sq_in_bits {
5860 u8 opcode[0x10];
b4ff3a36 5861 u8 reserved_at_10[0x10];
e281682b 5862
b4ff3a36 5863 u8 reserved_at_20[0x10];
e281682b
SM		 5864 u8 op_mod[0x10];
5865
b4ff3a36 5866 u8 reserved_at_40[0x8];
e281682b
SM		 5867 u8 sqn[0x18];
5868
b4ff3a36 5869 u8 reserved_at_60[0x20];
e281682b
SM		 5870};
5871
813f8540
MHY		 5872struct mlx5_ifc_destroy_scheduling_element_out_bits {
5873 u8 status[0x8];
5874 u8 reserved_at_8[0x18];
5875
5876 u8 syndrome[0x20];
5877
5878 u8 reserved_at_40[0x1c0];
5879};
5880
5881struct mlx5_ifc_destroy_scheduling_element_in_bits {
5882 u8 opcode[0x10];
5883 u8 reserved_at_10[0x10];
5884
5885 u8 reserved_at_20[0x10];
5886 u8 op_mod[0x10];
5887
5888 u8 scheduling_hierarchy[0x8];
5889 u8 reserved_at_48[0x18];
5890
5891 u8 scheduling_element_id[0x20];
5892
5893 u8 reserved_at_80[0x180];
5894};
5895
e281682b
SM		 5896struct mlx5_ifc_destroy_rqt_out_bits {
5897 u8 status[0x8];
b4ff3a36 5898 u8 reserved_at_8[0x18];
e281682b
SM		 5899
5900 u8 syndrome[0x20];
5901
b4ff3a36 5902 u8 reserved_at_40[0x40];
e281682b
SM		 5903};
5904
5905struct mlx5_ifc_destroy_rqt_in_bits {
5906 u8 opcode[0x10];
b4ff3a36 5907 u8 reserved_at_10[0x10];
e281682b 5908
b4ff3a36 5909 u8 reserved_at_20[0x10];
e281682b
SM		 5910 u8 op_mod[0x10];
5911
b4ff3a36 5912 u8 reserved_at_40[0x8];
e281682b
SM		 5913 u8 rqtn[0x18];
5914
b4ff3a36 5915 u8 reserved_at_60[0x20];
e281682b
SM		 5916};
5917
5918struct mlx5_ifc_destroy_rq_out_bits {
5919 u8 status[0x8];
b4ff3a36 5920 u8 reserved_at_8[0x18];
e281682b
SM		 5921
5922 u8 syndrome[0x20];
5923
b4ff3a36 5924 u8 reserved_at_40[0x40];
e281682b
SM		 5925};
5926
5927struct mlx5_ifc_destroy_rq_in_bits {
5928 u8 opcode[0x10];
b4ff3a36 5929 u8 reserved_at_10[0x10];
e281682b 5930
b4ff3a36 5931 u8 reserved_at_20[0x10];
e281682b
SM		 5932 u8 op_mod[0x10];
5933
b4ff3a36 5934 u8 reserved_at_40[0x8];
e281682b
SM		 5935 u8 rqn[0x18];
5936
b4ff3a36 5937 u8 reserved_at_60[0x20];
e281682b
SM		 5938};
5939
c1e0bfc1
MG		 5940struct mlx5_ifc_set_delay_drop_params_in_bits {
5941 u8 opcode[0x10];
5942 u8 reserved_at_10[0x10];
5943
5944 u8 reserved_at_20[0x10];
5945 u8 op_mod[0x10];
5946
5947 u8 reserved_at_40[0x20];
5948
5949 u8 reserved_at_60[0x10];
5950 u8 delay_drop_timeout[0x10];
5951};
5952
5953struct mlx5_ifc_set_delay_drop_params_out_bits {
5954 u8 status[0x8];
5955 u8 reserved_at_8[0x18];
5956
5957 u8 syndrome[0x20];
5958
5959 u8 reserved_at_40[0x40];
5960};
5961
e281682b
SM		 5962struct mlx5_ifc_destroy_rmp_out_bits {
5963 u8 status[0x8];
b4ff3a36 5964 u8 reserved_at_8[0x18];
e281682b
SM		 5965
5966 u8 syndrome[0x20];
5967
b4ff3a36 5968 u8 reserved_at_40[0x40];
e281682b
SM		 5969};
5970
5971struct mlx5_ifc_destroy_rmp_in_bits {
5972 u8 opcode[0x10];
b4ff3a36 5973 u8 reserved_at_10[0x10];
e281682b 5974
b4ff3a36 5975 u8 reserved_at_20[0x10];
e281682b
SM		 5976 u8 op_mod[0x10];
5977
b4ff3a36 5978 u8 reserved_at_40[0x8];
e281682b
SM		 5979 u8 rmpn[0x18];
5980
b4ff3a36 5981 u8 reserved_at_60[0x20];
e281682b
SM		 5982};
5983
5984struct mlx5_ifc_destroy_qp_out_bits {
5985 u8 status[0x8];
b4ff3a36 5986 u8 reserved_at_8[0x18];
e281682b
SM		 5987
5988 u8 syndrome[0x20];
5989
b4ff3a36 5990 u8 reserved_at_40[0x40];
e281682b
SM		 5991};
5992
5993struct mlx5_ifc_destroy_qp_in_bits {
5994 u8 opcode[0x10];
b4ff3a36 5995 u8 reserved_at_10[0x10];
e281682b 5996
b4ff3a36 5997 u8 reserved_at_20[0x10];
e281682b
SM		 5998 u8 op_mod[0x10];
5999
b4ff3a36 6000 u8 reserved_at_40[0x8];
e281682b
SM		 6001 u8 qpn[0x18];
6002
b4ff3a36 6003 u8 reserved_at_60[0x20];
e281682b
SM		 6004};
6005
6006struct mlx5_ifc_destroy_psv_out_bits {
6007 u8 status[0x8];
b4ff3a36 6008 u8 reserved_at_8[0x18];
e281682b
SM		 6009
6010 u8 syndrome[0x20];
6011
b4ff3a36 6012 u8 reserved_at_40[0x40];
e281682b
SM		 6013};
6014
6015struct mlx5_ifc_destroy_psv_in_bits {
6016 u8 opcode[0x10];
b4ff3a36 6017 u8 reserved_at_10[0x10];
e281682b 6018
b4ff3a36 6019 u8 reserved_at_20[0x10];
e281682b
SM		 6020 u8 op_mod[0x10];
6021
b4ff3a36 6022 u8 reserved_at_40[0x8];
e281682b
SM		 6023 u8 psvn[0x18];
6024
b4ff3a36 6025 u8 reserved_at_60[0x20];
e281682b
SM		 6026};
6027
6028struct mlx5_ifc_destroy_mkey_out_bits {
6029 u8 status[0x8];
b4ff3a36 6030 u8 reserved_at_8[0x18];
e281682b
SM		 6031
6032 u8 syndrome[0x20];
6033
b4ff3a36 6034 u8 reserved_at_40[0x40];
e281682b
SM		 6035};
6036
6037struct mlx5_ifc_destroy_mkey_in_bits {
6038 u8 opcode[0x10];
b4ff3a36 6039 u8 reserved_at_10[0x10];
e281682b 6040
b4ff3a36 6041 u8 reserved_at_20[0x10];
e281682b
SM		 6042 u8 op_mod[0x10];
6043
b4ff3a36 6044 u8 reserved_at_40[0x8];
e281682b
SM		 6045 u8 mkey_index[0x18];
6046
b4ff3a36 6047 u8 reserved_at_60[0x20];
e281682b
SM		 6048};
6049
6050struct mlx5_ifc_destroy_flow_table_out_bits {
6051 u8 status[0x8];
b4ff3a36 6052 u8 reserved_at_8[0x18];
e281682b
SM		 6053
6054 u8 syndrome[0x20];
6055
b4ff3a36 6056 u8 reserved_at_40[0x40];
e281682b
SM		 6057};
6058
6059struct mlx5_ifc_destroy_flow_table_in_bits {
6060 u8 opcode[0x10];
b4ff3a36 6061 u8 reserved_at_10[0x10];
e281682b 6062
b4ff3a36 6063 u8 reserved_at_20[0x10];
e281682b
SM		 6064 u8 op_mod[0x10];
6065
7d5e1423
SM		 6066 u8 other_vport[0x1];
6067 u8 reserved_at_41[0xf];
6068 u8 vport_number[0x10];
6069
6070 u8 reserved_at_60[0x20];
e281682b
SM		 6071
6072 u8 table_type[0x8];
b4ff3a36 6073 u8 reserved_at_88[0x18];
e281682b 6074
b4ff3a36 6075 u8 reserved_at_a0[0x8];
e281682b
SM		 6076 u8 table_id[0x18];
6077
b4ff3a36 6078 u8 reserved_at_c0[0x140];
e281682b
SM		 6079};
6080
6081struct mlx5_ifc_destroy_flow_group_out_bits {
6082 u8 status[0x8];
b4ff3a36 6083 u8 reserved_at_8[0x18];
e281682b
SM		 6084
6085 u8 syndrome[0x20];
6086
b4ff3a36 6087 u8 reserved_at_40[0x40];
e281682b
SM		 6088};
6089
6090struct mlx5_ifc_destroy_flow_group_in_bits {
6091 u8 opcode[0x10];
b4ff3a36 6092 u8 reserved_at_10[0x10];
e281682b 6093
b4ff3a36 6094 u8 reserved_at_20[0x10];
e281682b
SM		 6095 u8 op_mod[0x10];
6096
7d5e1423
SM		 6097 u8 other_vport[0x1];
6098 u8 reserved_at_41[0xf];
6099 u8 vport_number[0x10];
6100
6101 u8 reserved_at_60[0x20];
e281682b
SM		 6102
6103 u8 table_type[0x8];
b4ff3a36 6104 u8 reserved_at_88[0x18];
e281682b 6105
b4ff3a36 6106 u8 reserved_at_a0[0x8];
e281682b
SM		 6107 u8 table_id[0x18];
6108
6109 u8 group_id[0x20];
6110
b4ff3a36 6111 u8 reserved_at_e0[0x120];
e281682b
SM		 6112};
6113
6114struct mlx5_ifc_destroy_eq_out_bits {
6115 u8 status[0x8];
b4ff3a36 6116 u8 reserved_at_8[0x18];
e281682b
SM		 6117
6118 u8 syndrome[0x20];
6119
b4ff3a36 6120 u8 reserved_at_40[0x40];
e281682b
SM		 6121};
6122
6123struct mlx5_ifc_destroy_eq_in_bits {
6124 u8 opcode[0x10];
b4ff3a36 6125 u8 reserved_at_10[0x10];
e281682b 6126
b4ff3a36 6127 u8 reserved_at_20[0x10];
e281682b
SM		 6128 u8 op_mod[0x10];
6129
b4ff3a36 6130 u8 reserved_at_40[0x18];
e281682b
SM		 6131 u8 eq_number[0x8];
6132
b4ff3a36 6133 u8 reserved_at_60[0x20];
e281682b
SM		 6134};
6135
6136struct mlx5_ifc_destroy_dct_out_bits {
6137 u8 status[0x8];
b4ff3a36 6138 u8 reserved_at_8[0x18];
e281682b
SM		 6139
6140 u8 syndrome[0x20];
6141
b4ff3a36 6142 u8 reserved_at_40[0x40];
e281682b
SM		 6143};
6144
6145struct mlx5_ifc_destroy_dct_in_bits {
6146 u8 opcode[0x10];
b4ff3a36 6147 u8 reserved_at_10[0x10];
e281682b 6148
b4ff3a36 6149 u8 reserved_at_20[0x10];
e281682b
SM		 6150 u8 op_mod[0x10];
6151
b4ff3a36 6152 u8 reserved_at_40[0x8];
e281682b
SM		 6153 u8 dctn[0x18];
6154
b4ff3a36 6155 u8 reserved_at_60[0x20];
e281682b
SM		 6156};
6157
6158struct mlx5_ifc_destroy_cq_out_bits {
6159 u8 status[0x8];
b4ff3a36 6160 u8 reserved_at_8[0x18];
e281682b
SM		 6161
6162 u8 syndrome[0x20];
6163
b4ff3a36 6164 u8 reserved_at_40[0x40];
e281682b
SM		 6165};
6166
6167struct mlx5_ifc_destroy_cq_in_bits {
6168 u8 opcode[0x10];
b4ff3a36 6169 u8 reserved_at_10[0x10];
e281682b 6170
b4ff3a36 6171 u8 reserved_at_20[0x10];
e281682b
SM		 6172 u8 op_mod[0x10];
6173
b4ff3a36 6174 u8 reserved_at_40[0x8];
e281682b
SM		 6175 u8 cqn[0x18];
6176
b4ff3a36 6177 u8 reserved_at_60[0x20];
e281682b
SM		 6178};
6179
6180struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6181 u8 status[0x8];
b4ff3a36 6182 u8 reserved_at_8[0x18];
e281682b
SM		 6183
6184 u8 syndrome[0x20];
6185
b4ff3a36 6186 u8 reserved_at_40[0x40];
e281682b
SM		 6187};
6188
6189struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6190 u8 opcode[0x10];
b4ff3a36 6191 u8 reserved_at_10[0x10];
e281682b 6192
b4ff3a36 6193 u8 reserved_at_20[0x10];
e281682b
SM		 6194 u8 op_mod[0x10];
6195
b4ff3a36 6196 u8 reserved_at_40[0x20];
e281682b 6197
b4ff3a36 6198 u8 reserved_at_60[0x10];
e281682b
SM		 6199 u8 vxlan_udp_port[0x10];
6200};
6201
6202struct mlx5_ifc_delete_l2_table_entry_out_bits {
6203 u8 status[0x8];
b4ff3a36 6204 u8 reserved_at_8[0x18];
e281682b
SM		 6205
6206 u8 syndrome[0x20];
6207
b4ff3a36 6208 u8 reserved_at_40[0x40];
e281682b
SM		 6209};
6210
6211struct mlx5_ifc_delete_l2_table_entry_in_bits {
6212 u8 opcode[0x10];
b4ff3a36 6213 u8 reserved_at_10[0x10];
e281682b 6214
b4ff3a36 6215 u8 reserved_at_20[0x10];
e281682b
SM		 6216 u8 op_mod[0x10];
6217
b4ff3a36 6218 u8 reserved_at_40[0x60];
e281682b 6219
b4ff3a36 6220 u8 reserved_at_a0[0x8];
e281682b
SM		 6221 u8 table_index[0x18];
6222
b4ff3a36 6223 u8 reserved_at_c0[0x140];
e281682b
SM		 6224};
6225
6226struct mlx5_ifc_delete_fte_out_bits {
6227 u8 status[0x8];
b4ff3a36 6228 u8 reserved_at_8[0x18];
e281682b
SM		 6229
6230 u8 syndrome[0x20];
6231
b4ff3a36 6232 u8 reserved_at_40[0x40];
e281682b
SM		 6233};
6234
6235struct mlx5_ifc_delete_fte_in_bits {
6236 u8 opcode[0x10];
b4ff3a36 6237 u8 reserved_at_10[0x10];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_20[0x10];
e281682b
SM		 6240 u8 op_mod[0x10];
6241
7d5e1423
SM		 6242 u8 other_vport[0x1];
6243 u8 reserved_at_41[0xf];
6244 u8 vport_number[0x10];
6245
6246 u8 reserved_at_60[0x20];
e281682b
SM		 6247
6248 u8 table_type[0x8];
b4ff3a36 6249 u8 reserved_at_88[0x18];
e281682b 6250
b4ff3a36 6251 u8 reserved_at_a0[0x8];
e281682b
SM		 6252 u8 table_id[0x18];
6253
b4ff3a36 6254 u8 reserved_at_c0[0x40];
e281682b
SM		 6255
6256 u8 flow_index[0x20];
6257
b4ff3a36 6258 u8 reserved_at_120[0xe0];
e281682b
SM		 6259};
6260
6261struct mlx5_ifc_dealloc_xrcd_out_bits {
6262 u8 status[0x8];
b4ff3a36 6263 u8 reserved_at_8[0x18];
e281682b
SM		 6264
6265 u8 syndrome[0x20];
6266
b4ff3a36 6267 u8 reserved_at_40[0x40];
e281682b
SM		 6268};
6269
6270struct mlx5_ifc_dealloc_xrcd_in_bits {
6271 u8 opcode[0x10];
b4ff3a36 6272 u8 reserved_at_10[0x10];
e281682b 6273
b4ff3a36 6274 u8 reserved_at_20[0x10];
e281682b
SM		 6275 u8 op_mod[0x10];
6276
b4ff3a36 6277 u8 reserved_at_40[0x8];
e281682b
SM		 6278 u8 xrcd[0x18];
6279
b4ff3a36 6280 u8 reserved_at_60[0x20];
e281682b
SM		 6281};
6282
6283struct mlx5_ifc_dealloc_uar_out_bits {
6284 u8 status[0x8];
b4ff3a36 6285 u8 reserved_at_8[0x18];
e281682b
SM		 6286
6287 u8 syndrome[0x20];
6288
b4ff3a36 6289 u8 reserved_at_40[0x40];
e281682b
SM		 6290};
6291
6292struct mlx5_ifc_dealloc_uar_in_bits {
6293 u8 opcode[0x10];
b4ff3a36 6294 u8 reserved_at_10[0x10];
e281682b 6295
b4ff3a36 6296 u8 reserved_at_20[0x10];
e281682b
SM		 6297 u8 op_mod[0x10];
6298
b4ff3a36 6299 u8 reserved_at_40[0x8];
e281682b
SM		 6300 u8 uar[0x18];
6301
b4ff3a36 6302 u8 reserved_at_60[0x20];
e281682b
SM		 6303};
6304
6305struct mlx5_ifc_dealloc_transport_domain_out_bits {
6306 u8 status[0x8];
b4ff3a36 6307 u8 reserved_at_8[0x18];
e281682b
SM		 6308
6309 u8 syndrome[0x20];
6310
b4ff3a36 6311 u8 reserved_at_40[0x40];
e281682b
SM		 6312};
6313
6314struct mlx5_ifc_dealloc_transport_domain_in_bits {
6315 u8 opcode[0x10];
b4ff3a36 6316 u8 reserved_at_10[0x10];
e281682b 6317
b4ff3a36 6318 u8 reserved_at_20[0x10];
e281682b
SM		 6319 u8 op_mod[0x10];
6320
b4ff3a36 6321 u8 reserved_at_40[0x8];
e281682b
SM		 6322 u8 transport_domain[0x18];
6323
b4ff3a36 6324 u8 reserved_at_60[0x20];
e281682b
SM		 6325};
6326
6327struct mlx5_ifc_dealloc_q_counter_out_bits {
6328 u8 status[0x8];
b4ff3a36 6329 u8 reserved_at_8[0x18];
e281682b
SM		 6330
6331 u8 syndrome[0x20];
6332
b4ff3a36 6333 u8 reserved_at_40[0x40];
e281682b
SM		 6334};
6335
6336struct mlx5_ifc_dealloc_q_counter_in_bits {
6337 u8 opcode[0x10];
b4ff3a36 6338 u8 reserved_at_10[0x10];
e281682b 6339
b4ff3a36 6340 u8 reserved_at_20[0x10];
e281682b
SM		 6341 u8 op_mod[0x10];
6342
b4ff3a36 6343 u8 reserved_at_40[0x18];
e281682b
SM		 6344 u8 counter_set_id[0x8];
6345
b4ff3a36 6346 u8 reserved_at_60[0x20];
e281682b
SM		 6347};
6348
6349struct mlx5_ifc_dealloc_pd_out_bits {
6350 u8 status[0x8];
b4ff3a36 6351 u8 reserved_at_8[0x18];
e281682b
SM		 6352
6353 u8 syndrome[0x20];
6354
b4ff3a36 6355 u8 reserved_at_40[0x40];
e281682b
SM		 6356};
6357
6358struct mlx5_ifc_dealloc_pd_in_bits {
6359 u8 opcode[0x10];
b4ff3a36 6360 u8 reserved_at_10[0x10];
e281682b 6361
b4ff3a36 6362 u8 reserved_at_20[0x10];
e281682b
SM		 6363 u8 op_mod[0x10];
6364
b4ff3a36 6365 u8 reserved_at_40[0x8];
e281682b
SM		 6366 u8 pd[0x18];
6367
b4ff3a36 6368 u8 reserved_at_60[0x20];
e281682b
SM		 6369};
6370
9dc0b289
AV		 6371struct mlx5_ifc_dealloc_flow_counter_out_bits {
6372 u8 status[0x8];
6373 u8 reserved_at_8[0x18];
6374
6375 u8 syndrome[0x20];
6376
6377 u8 reserved_at_40[0x40];
6378};
6379
6380struct mlx5_ifc_dealloc_flow_counter_in_bits {
6381 u8 opcode[0x10];
6382 u8 reserved_at_10[0x10];
6383
6384 u8 reserved_at_20[0x10];
6385 u8 op_mod[0x10];
6386
a8ffcc74 6387 u8 flow_counter_id[0x20];
9dc0b289
AV		 6388
6389 u8 reserved_at_60[0x20];
6390};
6391
7486216b
SM		 6392struct mlx5_ifc_create_xrq_out_bits {
6393 u8 status[0x8];
6394 u8 reserved_at_8[0x18];
6395
6396 u8 syndrome[0x20];
6397
6398 u8 reserved_at_40[0x8];
6399 u8 xrqn[0x18];
6400
6401 u8 reserved_at_60[0x20];
6402};
6403
6404struct mlx5_ifc_create_xrq_in_bits {
6405 u8 opcode[0x10];
6406 u8 reserved_at_10[0x10];
6407
6408 u8 reserved_at_20[0x10];
6409 u8 op_mod[0x10];
6410
6411 u8 reserved_at_40[0x40];
6412
6413 struct mlx5_ifc_xrqc_bits xrq_context;
6414};
6415
e281682b
SM		 6416struct mlx5_ifc_create_xrc_srq_out_bits {
6417 u8 status[0x8];
b4ff3a36 6418 u8 reserved_at_8[0x18];
e281682b
SM		 6419
6420 u8 syndrome[0x20];
6421
b4ff3a36 6422 u8 reserved_at_40[0x8];
e281682b
SM		 6423 u8 xrc_srqn[0x18];
6424
b4ff3a36 6425 u8 reserved_at_60[0x20];
e281682b
SM		 6426};
6427
6428struct mlx5_ifc_create_xrc_srq_in_bits {
6429 u8 opcode[0x10];
b4ff3a36 6430 u8 reserved_at_10[0x10];
e281682b 6431
b4ff3a36 6432 u8 reserved_at_20[0x10];
e281682b
SM		 6433 u8 op_mod[0x10];
6434
b4ff3a36 6435 u8 reserved_at_40[0x40];
e281682b
SM		 6436
6437 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6438
b4ff3a36 6439 u8 reserved_at_280[0x600];
e281682b
SM		 6440
6441 u8 pas[0][0x40];
6442};
6443
6444struct mlx5_ifc_create_tis_out_bits {
6445 u8 status[0x8];
b4ff3a36 6446 u8 reserved_at_8[0x18];
e281682b
SM		 6447
6448 u8 syndrome[0x20];
6449
b4ff3a36 6450 u8 reserved_at_40[0x8];
e281682b
SM		 6451 u8 tisn[0x18];
6452
b4ff3a36 6453 u8 reserved_at_60[0x20];
e281682b
SM		 6454};
6455
6456struct mlx5_ifc_create_tis_in_bits {
6457 u8 opcode[0x10];
b4ff3a36 6458 u8 reserved_at_10[0x10];
e281682b 6459
b4ff3a36 6460 u8 reserved_at_20[0x10];
e281682b
SM		 6461 u8 op_mod[0x10];
6462
b4ff3a36 6463 u8 reserved_at_40[0xc0];
e281682b
SM		 6464
6465 struct mlx5_ifc_tisc_bits ctx;
6466};
6467
6468struct mlx5_ifc_create_tir_out_bits {
6469 u8 status[0x8];
b4ff3a36 6470 u8 reserved_at_8[0x18];
e281682b
SM		 6471
6472 u8 syndrome[0x20];
6473
b4ff3a36 6474 u8 reserved_at_40[0x8];
e281682b
SM		 6475 u8 tirn[0x18];
6476
b4ff3a36 6477 u8 reserved_at_60[0x20];
e281682b
SM		 6478};
6479
6480struct mlx5_ifc_create_tir_in_bits {
6481 u8 opcode[0x10];
b4ff3a36 6482 u8 reserved_at_10[0x10];
e281682b 6483
b4ff3a36 6484 u8 reserved_at_20[0x10];
e281682b
SM		 6485 u8 op_mod[0x10];
6486
b4ff3a36 6487 u8 reserved_at_40[0xc0];
e281682b
SM		 6488
6489 struct mlx5_ifc_tirc_bits ctx;
6490};
6491
6492struct mlx5_ifc_create_srq_out_bits {
6493 u8 status[0x8];
b4ff3a36 6494 u8 reserved_at_8[0x18];
e281682b
SM		 6495
6496 u8 syndrome[0x20];
6497
b4ff3a36 6498 u8 reserved_at_40[0x8];
e281682b
SM		 6499 u8 srqn[0x18];
6500
b4ff3a36 6501 u8 reserved_at_60[0x20];
e281682b
SM		 6502};
6503
6504struct mlx5_ifc_create_srq_in_bits {
6505 u8 opcode[0x10];
b4ff3a36 6506 u8 reserved_at_10[0x10];
e281682b 6507
b4ff3a36 6508 u8 reserved_at_20[0x10];
e281682b
SM		 6509 u8 op_mod[0x10];
6510
b4ff3a36 6511 u8 reserved_at_40[0x40];
e281682b
SM		 6512
6513 struct mlx5_ifc_srqc_bits srq_context_entry;
6514
b4ff3a36 6515 u8 reserved_at_280[0x600];
e281682b
SM		 6516
6517 u8 pas[0][0x40];
6518};
6519
6520struct mlx5_ifc_create_sq_out_bits {
6521 u8 status[0x8];
b4ff3a36 6522 u8 reserved_at_8[0x18];
e281682b
SM		 6523
6524 u8 syndrome[0x20];
6525
b4ff3a36 6526 u8 reserved_at_40[0x8];
e281682b
SM		 6527 u8 sqn[0x18];
6528
b4ff3a36 6529 u8 reserved_at_60[0x20];
e281682b
SM		 6530};
6531
6532struct mlx5_ifc_create_sq_in_bits {
6533 u8 opcode[0x10];
b4ff3a36 6534 u8 reserved_at_10[0x10];
e281682b 6535
b4ff3a36 6536 u8 reserved_at_20[0x10];
e281682b
SM		 6537 u8 op_mod[0x10];
6538
b4ff3a36 6539 u8 reserved_at_40[0xc0];
e281682b
SM		 6540
6541 struct mlx5_ifc_sqc_bits ctx;
6542};
6543
813f8540
MHY		 6544struct mlx5_ifc_create_scheduling_element_out_bits {
6545 u8 status[0x8];
6546 u8 reserved_at_8[0x18];
6547
6548 u8 syndrome[0x20];
6549
6550 u8 reserved_at_40[0x40];
6551
6552 u8 scheduling_element_id[0x20];
6553
6554 u8 reserved_at_a0[0x160];
6555};
6556
6557struct mlx5_ifc_create_scheduling_element_in_bits {
6558 u8 opcode[0x10];
6559 u8 reserved_at_10[0x10];
6560
6561 u8 reserved_at_20[0x10];
6562 u8 op_mod[0x10];
6563
6564 u8 scheduling_hierarchy[0x8];
6565 u8 reserved_at_48[0x18];
6566
6567 u8 reserved_at_60[0xa0];
6568
6569 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6570
6571 u8 reserved_at_300[0x100];
6572};
6573
e281682b
SM		 6574struct mlx5_ifc_create_rqt_out_bits {
6575 u8 status[0x8];
b4ff3a36 6576 u8 reserved_at_8[0x18];
e281682b
SM		 6577
6578 u8 syndrome[0x20];
6579
b4ff3a36 6580 u8 reserved_at_40[0x8];
e281682b
SM		 6581 u8 rqtn[0x18];
6582
b4ff3a36 6583 u8 reserved_at_60[0x20];
e281682b
SM		 6584};
6585
6586struct mlx5_ifc_create_rqt_in_bits {
6587 u8 opcode[0x10];
b4ff3a36 6588 u8 reserved_at_10[0x10];
e281682b 6589
b4ff3a36 6590 u8 reserved_at_20[0x10];
e281682b
SM		 6591 u8 op_mod[0x10];
6592
b4ff3a36 6593 u8 reserved_at_40[0xc0];
e281682b
SM		 6594
6595 struct mlx5_ifc_rqtc_bits rqt_context;
6596};
6597
6598struct mlx5_ifc_create_rq_out_bits {
6599 u8 status[0x8];
b4ff3a36 6600 u8 reserved_at_8[0x18];
e281682b
SM		 6601
6602 u8 syndrome[0x20];
6603
b4ff3a36 6604 u8 reserved_at_40[0x8];
e281682b
SM		 6605 u8 rqn[0x18];
6606
b4ff3a36 6607 u8 reserved_at_60[0x20];
e281682b
SM		 6608};
6609
6610struct mlx5_ifc_create_rq_in_bits {
6611 u8 opcode[0x10];
b4ff3a36 6612 u8 reserved_at_10[0x10];
e281682b 6613
b4ff3a36 6614 u8 reserved_at_20[0x10];
e281682b
SM		 6615 u8 op_mod[0x10];
6616
b4ff3a36 6617 u8 reserved_at_40[0xc0];
e281682b
SM		 6618
6619 struct mlx5_ifc_rqc_bits ctx;
6620};
6621
6622struct mlx5_ifc_create_rmp_out_bits {
6623 u8 status[0x8];
b4ff3a36 6624 u8 reserved_at_8[0x18];
e281682b
SM		 6625
6626 u8 syndrome[0x20];
6627
b4ff3a36 6628 u8 reserved_at_40[0x8];
e281682b
SM		 6629 u8 rmpn[0x18];
6630
b4ff3a36 6631 u8 reserved_at_60[0x20];
e281682b
SM		 6632};
6633
6634struct mlx5_ifc_create_rmp_in_bits {
6635 u8 opcode[0x10];
b4ff3a36 6636 u8 reserved_at_10[0x10];
e281682b 6637
b4ff3a36 6638 u8 reserved_at_20[0x10];
e281682b
SM		 6639 u8 op_mod[0x10];
6640
b4ff3a36 6641 u8 reserved_at_40[0xc0];
e281682b
SM		 6642
6643 struct mlx5_ifc_rmpc_bits ctx;
6644};
6645
6646struct mlx5_ifc_create_qp_out_bits {
6647 u8 status[0x8];
b4ff3a36 6648 u8 reserved_at_8[0x18];
e281682b
SM		 6649
6650 u8 syndrome[0x20];
6651
b4ff3a36 6652 u8 reserved_at_40[0x8];
e281682b
SM		 6653 u8 qpn[0x18];
6654
b4ff3a36 6655 u8 reserved_at_60[0x20];
e281682b
SM		 6656};
6657
6658struct mlx5_ifc_create_qp_in_bits {
6659 u8 opcode[0x10];
b4ff3a36 6660 u8 reserved_at_10[0x10];
e281682b 6661
b4ff3a36 6662 u8 reserved_at_20[0x10];
e281682b
SM		 6663 u8 op_mod[0x10];
6664
b4ff3a36 6665 u8 reserved_at_40[0x40];
e281682b
SM		 6666
6667 u8 opt_param_mask[0x20];
6668
b4ff3a36 6669 u8 reserved_at_a0[0x20];
e281682b
SM		 6670
6671 struct mlx5_ifc_qpc_bits qpc;
6672
b4ff3a36 6673 u8 reserved_at_800[0x80];
e281682b
SM		 6674
6675 u8 pas[0][0x40];
6676};
6677
6678struct mlx5_ifc_create_psv_out_bits {
6679 u8 status[0x8];
b4ff3a36 6680 u8 reserved_at_8[0x18];
e281682b
SM		 6681
6682 u8 syndrome[0x20];
6683
b4ff3a36 6684 u8 reserved_at_40[0x40];
e281682b 6685
b4ff3a36 6686 u8 reserved_at_80[0x8];
e281682b
SM		 6687 u8 psv0_index[0x18];
6688
b4ff3a36 6689 u8 reserved_at_a0[0x8];
e281682b
SM		 6690 u8 psv1_index[0x18];
6691
b4ff3a36 6692 u8 reserved_at_c0[0x8];
e281682b
SM		 6693 u8 psv2_index[0x18];
6694
b4ff3a36 6695 u8 reserved_at_e0[0x8];
e281682b
SM		 6696 u8 psv3_index[0x18];
6697};
6698
6699struct mlx5_ifc_create_psv_in_bits {
6700 u8 opcode[0x10];
b4ff3a36 6701 u8 reserved_at_10[0x10];
e281682b 6702
b4ff3a36 6703 u8 reserved_at_20[0x10];
e281682b
SM		 6704 u8 op_mod[0x10];
6705
6706 u8 num_psv[0x4];
b4ff3a36 6707 u8 reserved_at_44[0x4];
e281682b
SM		 6708 u8 pd[0x18];
6709
b4ff3a36 6710 u8 reserved_at_60[0x20];
e281682b
SM		 6711};
6712
6713struct mlx5_ifc_create_mkey_out_bits {
6714 u8 status[0x8];
b4ff3a36 6715 u8 reserved_at_8[0x18];
e281682b
SM		 6716
6717 u8 syndrome[0x20];
6718
b4ff3a36 6719 u8 reserved_at_40[0x8];
e281682b
SM		 6720 u8 mkey_index[0x18];
6721
b4ff3a36 6722 u8 reserved_at_60[0x20];
e281682b
SM		 6723};
6724
6725struct mlx5_ifc_create_mkey_in_bits {
6726 u8 opcode[0x10];
b4ff3a36 6727 u8 reserved_at_10[0x10];
e281682b 6728
b4ff3a36 6729 u8 reserved_at_20[0x10];
e281682b
SM		 6730 u8 op_mod[0x10];
6731
b4ff3a36 6732 u8 reserved_at_40[0x20];
e281682b
SM		 6733
6734 u8 pg_access[0x1];
b4ff3a36 6735 u8 reserved_at_61[0x1f];
e281682b
SM		 6736
6737 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6738
b4ff3a36 6739 u8 reserved_at_280[0x80];
e281682b
SM		 6740
6741 u8 translations_octword_actual_size[0x20];
6742
b4ff3a36 6743 u8 reserved_at_320[0x560];
e281682b
SM		 6744
6745 u8 klm_pas_mtt[0][0x20];
6746};
6747
6748struct mlx5_ifc_create_flow_table_out_bits {
6749 u8 status[0x8];
b4ff3a36 6750 u8 reserved_at_8[0x18];
e281682b
SM		 6751
6752 u8 syndrome[0x20];
6753
b4ff3a36 6754 u8 reserved_at_40[0x8];
e281682b
SM		 6755 u8 table_id[0x18];
6756
b4ff3a36 6757 u8 reserved_at_60[0x20];
e281682b
SM		 6758};
6759
0c90e9c6
MG		 6760struct mlx5_ifc_flow_table_context_bits {
6761 u8 encap_en[0x1];
6762 u8 decap_en[0x1];
6763 u8 reserved_at_2[0x2];
6764 u8 table_miss_action[0x4];
6765 u8 level[0x8];
6766 u8 reserved_at_10[0x8];
6767 u8 log_size[0x8];
6768
6769 u8 reserved_at_20[0x8];
6770 u8 table_miss_id[0x18];
6771
6772 u8 reserved_at_40[0x8];
6773 u8 lag_master_next_table_id[0x18];
6774
6775 u8 reserved_at_60[0xe0];
6776};
6777
e281682b
SM		 6778struct mlx5_ifc_create_flow_table_in_bits {
6779 u8 opcode[0x10];
b4ff3a36 6780 u8 reserved_at_10[0x10];
e281682b 6781
b4ff3a36 6782 u8 reserved_at_20[0x10];
e281682b
SM		 6783 u8 op_mod[0x10];
6784
7d5e1423
SM		 6785 u8 other_vport[0x1];
6786 u8 reserved_at_41[0xf];
6787 u8 vport_number[0x10];
6788
6789 u8 reserved_at_60[0x20];
e281682b
SM		 6790
6791 u8 table_type[0x8];
b4ff3a36 6792 u8 reserved_at_88[0x18];
e281682b 6793
b4ff3a36 6794 u8 reserved_at_a0[0x20];
e281682b 6795
0c90e9c6 6796 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6797};
6798
6799struct mlx5_ifc_create_flow_group_out_bits {
6800 u8 status[0x8];
b4ff3a36 6801 u8 reserved_at_8[0x18];
e281682b
SM		 6802
6803 u8 syndrome[0x20];
6804
b4ff3a36 6805 u8 reserved_at_40[0x8];
e281682b
SM		 6806 u8 group_id[0x18];
6807
b4ff3a36 6808 u8 reserved_at_60[0x20];
e281682b
SM		 6809};
6810
6811enum {
6812 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6813 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6814 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6815};
6816
6817struct mlx5_ifc_create_flow_group_in_bits {
6818 u8 opcode[0x10];
b4ff3a36 6819 u8 reserved_at_10[0x10];
e281682b 6820
b4ff3a36 6821 u8 reserved_at_20[0x10];
e281682b
SM		 6822 u8 op_mod[0x10];
6823
7d5e1423
SM		 6824 u8 other_vport[0x1];
6825 u8 reserved_at_41[0xf];
6826 u8 vport_number[0x10];
6827
6828 u8 reserved_at_60[0x20];
e281682b
SM		 6829
6830 u8 table_type[0x8];
b4ff3a36 6831 u8 reserved_at_88[0x18];
e281682b 6832
b4ff3a36 6833 u8 reserved_at_a0[0x8];
e281682b
SM		 6834 u8 table_id[0x18];
6835
b4ff3a36 6836 u8 reserved_at_c0[0x20];
e281682b
SM		 6837
6838 u8 start_flow_index[0x20];
6839
b4ff3a36 6840 u8 reserved_at_100[0x20];
e281682b
SM		 6841
6842 u8 end_flow_index[0x20];
6843
b4ff3a36 6844 u8 reserved_at_140[0xa0];
e281682b 6845
b4ff3a36 6846 u8 reserved_at_1e0[0x18];
e281682b
SM		 6847 u8 match_criteria_enable[0x8];
6848
6849 struct mlx5_ifc_fte_match_param_bits match_criteria;
6850
b4ff3a36 6851 u8 reserved_at_1200[0xe00];
e281682b
SM		 6852};
6853
6854struct mlx5_ifc_create_eq_out_bits {
6855 u8 status[0x8];
b4ff3a36 6856 u8 reserved_at_8[0x18];
e281682b
SM		 6857
6858 u8 syndrome[0x20];
6859
b4ff3a36 6860 u8 reserved_at_40[0x18];
e281682b
SM		 6861 u8 eq_number[0x8];
6862
b4ff3a36 6863 u8 reserved_at_60[0x20];
e281682b
SM		 6864};
6865
6866struct mlx5_ifc_create_eq_in_bits {
6867 u8 opcode[0x10];
b4ff3a36 6868 u8 reserved_at_10[0x10];
e281682b 6869
b4ff3a36 6870 u8 reserved_at_20[0x10];
e281682b
SM		 6871 u8 op_mod[0x10];
6872
b4ff3a36 6873 u8 reserved_at_40[0x40];
e281682b
SM		 6874
6875 struct mlx5_ifc_eqc_bits eq_context_entry;
6876
b4ff3a36 6877 u8 reserved_at_280[0x40];
e281682b
SM		 6878
6879 u8 event_bitmask[0x40];
6880
b4ff3a36 6881 u8 reserved_at_300[0x580];
e281682b
SM		 6882
6883 u8 pas[0][0x40];
6884};
6885
6886struct mlx5_ifc_create_dct_out_bits {
6887 u8 status[0x8];
b4ff3a36 6888 u8 reserved_at_8[0x18];
e281682b
SM		 6889
6890 u8 syndrome[0x20];
6891
b4ff3a36 6892 u8 reserved_at_40[0x8];
e281682b
SM		 6893 u8 dctn[0x18];
6894
b4ff3a36 6895 u8 reserved_at_60[0x20];
e281682b
SM		 6896};
6897
6898struct mlx5_ifc_create_dct_in_bits {
6899 u8 opcode[0x10];
b4ff3a36 6900 u8 reserved_at_10[0x10];
e281682b 6901
b4ff3a36 6902 u8 reserved_at_20[0x10];
e281682b
SM		 6903 u8 op_mod[0x10];
6904
b4ff3a36 6905 u8 reserved_at_40[0x40];
e281682b
SM		 6906
6907 struct mlx5_ifc_dctc_bits dct_context_entry;
6908
b4ff3a36 6909 u8 reserved_at_280[0x180];
e281682b
SM		 6910};
6911
6912struct mlx5_ifc_create_cq_out_bits {
6913 u8 status[0x8];
b4ff3a36 6914 u8 reserved_at_8[0x18];
e281682b
SM		 6915
6916 u8 syndrome[0x20];
6917
b4ff3a36 6918 u8 reserved_at_40[0x8];
e281682b
SM		 6919 u8 cqn[0x18];
6920
b4ff3a36 6921 u8 reserved_at_60[0x20];
e281682b
SM		 6922};
6923
6924struct mlx5_ifc_create_cq_in_bits {
6925 u8 opcode[0x10];
b4ff3a36 6926 u8 reserved_at_10[0x10];
e281682b 6927
b4ff3a36 6928 u8 reserved_at_20[0x10];
e281682b
SM		 6929 u8 op_mod[0x10];
6930
b4ff3a36 6931 u8 reserved_at_40[0x40];
e281682b
SM		 6932
6933 struct mlx5_ifc_cqc_bits cq_context;
6934
b4ff3a36 6935 u8 reserved_at_280[0x600];
e281682b
SM		 6936
6937 u8 pas[0][0x40];
6938};
6939
6940struct mlx5_ifc_config_int_moderation_out_bits {
6941 u8 status[0x8];
b4ff3a36 6942 u8 reserved_at_8[0x18];
e281682b
SM		 6943
6944 u8 syndrome[0x20];
6945
b4ff3a36 6946 u8 reserved_at_40[0x4];
e281682b
SM		 6947 u8 min_delay[0xc];
6948 u8 int_vector[0x10];
6949
b4ff3a36 6950 u8 reserved_at_60[0x20];
e281682b
SM		 6951};
6952
6953enum {
6954 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6955 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6956};
6957
6958struct mlx5_ifc_config_int_moderation_in_bits {
6959 u8 opcode[0x10];
b4ff3a36 6960 u8 reserved_at_10[0x10];
e281682b 6961
b4ff3a36 6962 u8 reserved_at_20[0x10];
e281682b
SM		 6963 u8 op_mod[0x10];
6964
b4ff3a36 6965 u8 reserved_at_40[0x4];
e281682b
SM		 6966 u8 min_delay[0xc];
6967 u8 int_vector[0x10];
6968
b4ff3a36 6969 u8 reserved_at_60[0x20];
e281682b
SM		 6970};
6971
6972struct mlx5_ifc_attach_to_mcg_out_bits {
6973 u8 status[0x8];
b4ff3a36 6974 u8 reserved_at_8[0x18];
e281682b
SM		 6975
6976 u8 syndrome[0x20];
6977
b4ff3a36 6978 u8 reserved_at_40[0x40];
e281682b
SM		 6979};
6980
6981struct mlx5_ifc_attach_to_mcg_in_bits {
6982 u8 opcode[0x10];
b4ff3a36 6983 u8 reserved_at_10[0x10];
e281682b 6984
b4ff3a36 6985 u8 reserved_at_20[0x10];
e281682b
SM		 6986 u8 op_mod[0x10];
6987
b4ff3a36 6988 u8 reserved_at_40[0x8];
e281682b
SM		 6989 u8 qpn[0x18];
6990
b4ff3a36 6991 u8 reserved_at_60[0x20];
e281682b
SM		 6992
6993 u8 multicast_gid[16][0x8];
6994};
6995
7486216b
SM		 6996struct mlx5_ifc_arm_xrq_out_bits {
6997 u8 status[0x8];
6998 u8 reserved_at_8[0x18];
6999
7000 u8 syndrome[0x20];
7001
7002 u8 reserved_at_40[0x40];
7003};
7004
7005struct mlx5_ifc_arm_xrq_in_bits {
7006 u8 opcode[0x10];
7007 u8 reserved_at_10[0x10];
7008
7009 u8 reserved_at_20[0x10];
7010 u8 op_mod[0x10];
7011
7012 u8 reserved_at_40[0x8];
7013 u8 xrqn[0x18];
7014
7015 u8 reserved_at_60[0x10];
7016 u8 lwm[0x10];
7017};
7018
e281682b
SM		 7019struct mlx5_ifc_arm_xrc_srq_out_bits {
7020 u8 status[0x8];
b4ff3a36 7021 u8 reserved_at_8[0x18];
e281682b
SM		 7022
7023 u8 syndrome[0x20];
7024
b4ff3a36 7025 u8 reserved_at_40[0x40];
e281682b
SM		 7026};
7027
7028enum {
7029 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7030};
7031
7032struct mlx5_ifc_arm_xrc_srq_in_bits {
7033 u8 opcode[0x10];
b4ff3a36 7034 u8 reserved_at_10[0x10];
e281682b 7035
b4ff3a36 7036 u8 reserved_at_20[0x10];
e281682b
SM		 7037 u8 op_mod[0x10];
7038
b4ff3a36 7039 u8 reserved_at_40[0x8];
e281682b
SM		 7040 u8 xrc_srqn[0x18];
7041
b4ff3a36 7042 u8 reserved_at_60[0x10];
e281682b
SM		 7043 u8 lwm[0x10];
7044};
7045
7046struct mlx5_ifc_arm_rq_out_bits {
7047 u8 status[0x8];
b4ff3a36 7048 u8 reserved_at_8[0x18];
e281682b
SM		 7049
7050 u8 syndrome[0x20];
7051
b4ff3a36 7052 u8 reserved_at_40[0x40];
e281682b
SM		 7053};
7054
7055enum {
7486216b
SM		 7056 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7057 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7058};
7059
7060struct mlx5_ifc_arm_rq_in_bits {
7061 u8 opcode[0x10];
b4ff3a36 7062 u8 reserved_at_10[0x10];
e281682b 7063
b4ff3a36 7064 u8 reserved_at_20[0x10];
e281682b
SM		 7065 u8 op_mod[0x10];
7066
b4ff3a36 7067 u8 reserved_at_40[0x8];
e281682b
SM		 7068 u8 srq_number[0x18];
7069
b4ff3a36 7070 u8 reserved_at_60[0x10];
e281682b
SM		 7071 u8 lwm[0x10];
7072};
7073
7074struct mlx5_ifc_arm_dct_out_bits {
7075 u8 status[0x8];
b4ff3a36 7076 u8 reserved_at_8[0x18];
e281682b
SM		 7077
7078 u8 syndrome[0x20];
7079
b4ff3a36 7080 u8 reserved_at_40[0x40];
e281682b
SM		 7081};
7082
7083struct mlx5_ifc_arm_dct_in_bits {
7084 u8 opcode[0x10];
b4ff3a36 7085 u8 reserved_at_10[0x10];
e281682b 7086
b4ff3a36 7087 u8 reserved_at_20[0x10];
e281682b
SM		 7088 u8 op_mod[0x10];
7089
b4ff3a36 7090 u8 reserved_at_40[0x8];
e281682b
SM		 7091 u8 dct_number[0x18];
7092
b4ff3a36 7093 u8 reserved_at_60[0x20];
e281682b
SM		 7094};
7095
7096struct mlx5_ifc_alloc_xrcd_out_bits {
7097 u8 status[0x8];
b4ff3a36 7098 u8 reserved_at_8[0x18];
e281682b
SM		 7099
7100 u8 syndrome[0x20];
7101
b4ff3a36 7102 u8 reserved_at_40[0x8];
e281682b
SM		 7103 u8 xrcd[0x18];
7104
b4ff3a36 7105 u8 reserved_at_60[0x20];
e281682b
SM		 7106};
7107
7108struct mlx5_ifc_alloc_xrcd_in_bits {
7109 u8 opcode[0x10];
b4ff3a36 7110 u8 reserved_at_10[0x10];
e281682b 7111
b4ff3a36 7112 u8 reserved_at_20[0x10];
e281682b
SM		 7113 u8 op_mod[0x10];
7114
b4ff3a36 7115 u8 reserved_at_40[0x40];
e281682b
SM		 7116};
7117
7118struct mlx5_ifc_alloc_uar_out_bits {
7119 u8 status[0x8];
b4ff3a36 7120 u8 reserved_at_8[0x18];
e281682b
SM		 7121
7122 u8 syndrome[0x20];
7123
b4ff3a36 7124 u8 reserved_at_40[0x8];
e281682b
SM		 7125 u8 uar[0x18];
7126
b4ff3a36 7127 u8 reserved_at_60[0x20];
e281682b
SM		 7128};
7129
7130struct mlx5_ifc_alloc_uar_in_bits {
7131 u8 opcode[0x10];
b4ff3a36 7132 u8 reserved_at_10[0x10];
e281682b 7133
b4ff3a36 7134 u8 reserved_at_20[0x10];
e281682b
SM		 7135 u8 op_mod[0x10];
7136
b4ff3a36 7137 u8 reserved_at_40[0x40];
e281682b
SM		 7138};
7139
7140struct mlx5_ifc_alloc_transport_domain_out_bits {
7141 u8 status[0x8];
b4ff3a36 7142 u8 reserved_at_8[0x18];
e281682b
SM		 7143
7144 u8 syndrome[0x20];
7145
b4ff3a36 7146 u8 reserved_at_40[0x8];
e281682b
SM		 7147 u8 transport_domain[0x18];
7148
b4ff3a36 7149 u8 reserved_at_60[0x20];
e281682b
SM		 7150};
7151
7152struct mlx5_ifc_alloc_transport_domain_in_bits {
7153 u8 opcode[0x10];
b4ff3a36 7154 u8 reserved_at_10[0x10];
e281682b 7155
b4ff3a36 7156 u8 reserved_at_20[0x10];
e281682b
SM		 7157 u8 op_mod[0x10];
7158
b4ff3a36 7159 u8 reserved_at_40[0x40];
e281682b
SM		 7160};
7161
7162struct mlx5_ifc_alloc_q_counter_out_bits {
7163 u8 status[0x8];
b4ff3a36 7164 u8 reserved_at_8[0x18];
e281682b
SM		 7165
7166 u8 syndrome[0x20];
7167
b4ff3a36 7168 u8 reserved_at_40[0x18];
e281682b
SM		 7169 u8 counter_set_id[0x8];
7170
b4ff3a36 7171 u8 reserved_at_60[0x20];
e281682b
SM		 7172};
7173
7174struct mlx5_ifc_alloc_q_counter_in_bits {
7175 u8 opcode[0x10];
b4ff3a36 7176 u8 reserved_at_10[0x10];
e281682b 7177
b4ff3a36 7178 u8 reserved_at_20[0x10];
e281682b
SM		 7179 u8 op_mod[0x10];
7180
b4ff3a36 7181 u8 reserved_at_40[0x40];
e281682b
SM		 7182};
7183
7184struct mlx5_ifc_alloc_pd_out_bits {
7185 u8 status[0x8];
b4ff3a36 7186 u8 reserved_at_8[0x18];
e281682b
SM		 7187
7188 u8 syndrome[0x20];
7189
b4ff3a36 7190 u8 reserved_at_40[0x8];
e281682b
SM		 7191 u8 pd[0x18];
7192
b4ff3a36 7193 u8 reserved_at_60[0x20];
e281682b
SM		 7194};
7195
7196struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7197 u8 opcode[0x10];
7198 u8 reserved_at_10[0x10];
7199
7200 u8 reserved_at_20[0x10];
7201 u8 op_mod[0x10];
7202
7203 u8 reserved_at_40[0x40];
7204};
7205
7206struct mlx5_ifc_alloc_flow_counter_out_bits {
7207 u8 status[0x8];
7208 u8 reserved_at_8[0x18];
7209
7210 u8 syndrome[0x20];
7211
a8ffcc74 7212 u8 flow_counter_id[0x20];
9dc0b289
AV		 7213
7214 u8 reserved_at_60[0x20];
7215};
7216
7217struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7218 u8 opcode[0x10];
b4ff3a36 7219 u8 reserved_at_10[0x10];
e281682b 7220
b4ff3a36 7221 u8 reserved_at_20[0x10];
e281682b
SM		 7222 u8 op_mod[0x10];
7223
b4ff3a36 7224 u8 reserved_at_40[0x40];
e281682b
SM		 7225};
7226
7227struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7228 u8 status[0x8];
b4ff3a36 7229 u8 reserved_at_8[0x18];
e281682b
SM		 7230
7231 u8 syndrome[0x20];
7232
b4ff3a36 7233 u8 reserved_at_40[0x40];
e281682b
SM		 7234};
7235
7236struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7237 u8 opcode[0x10];
b4ff3a36 7238 u8 reserved_at_10[0x10];
e281682b 7239
b4ff3a36 7240 u8 reserved_at_20[0x10];
e281682b
SM		 7241 u8 op_mod[0x10];
7242
b4ff3a36 7243 u8 reserved_at_40[0x20];
e281682b 7244
b4ff3a36 7245 u8 reserved_at_60[0x10];
e281682b
SM		 7246 u8 vxlan_udp_port[0x10];
7247};
7248
37e92a9d 7249struct mlx5_ifc_set_pp_rate_limit_out_bits {
7486216b
SM		 7250 u8 status[0x8];
7251 u8 reserved_at_8[0x18];
7252
7253 u8 syndrome[0x20];
7254
7255 u8 reserved_at_40[0x40];
7256};
7257
37e92a9d 7258struct mlx5_ifc_set_pp_rate_limit_in_bits {
7486216b
SM		 7259 u8 opcode[0x10];
7260 u8 reserved_at_10[0x10];
7261
7262 u8 reserved_at_20[0x10];
7263 u8 op_mod[0x10];
7264
7265 u8 reserved_at_40[0x10];
7266 u8 rate_limit_index[0x10];
7267
7268 u8 reserved_at_60[0x20];
7269
7270 u8 rate_limit[0x20];
37e92a9d
EBE		 7271
7272 u8 reserved_at_a0[0x160];
7486216b
SM		 7273};
7274
e281682b
SM		 7275struct mlx5_ifc_access_register_out_bits {
7276 u8 status[0x8];
b4ff3a36 7277 u8 reserved_at_8[0x18];
e281682b
SM		 7278
7279 u8 syndrome[0x20];
7280
b4ff3a36 7281 u8 reserved_at_40[0x40];
e281682b
SM		 7282
7283 u8 register_data[0][0x20];
7284};
7285
7286enum {
7287 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7288 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7289};
7290
7291struct mlx5_ifc_access_register_in_bits {
7292 u8 opcode[0x10];
b4ff3a36 7293 u8 reserved_at_10[0x10];
e281682b 7294
b4ff3a36 7295 u8 reserved_at_20[0x10];
e281682b
SM		 7296 u8 op_mod[0x10];
7297
b4ff3a36 7298 u8 reserved_at_40[0x10];
e281682b
SM		 7299 u8 register_id[0x10];
7300
7301 u8 argument[0x20];
7302
7303 u8 register_data[0][0x20];
7304};
7305
7306struct mlx5_ifc_sltp_reg_bits {
7307 u8 status[0x4];
7308 u8 version[0x4];
7309 u8 local_port[0x8];
7310 u8 pnat[0x2];
b4ff3a36 7311 u8 reserved_at_12[0x2];
e281682b 7312 u8 lane[0x4];
b4ff3a36 7313 u8 reserved_at_18[0x8];
e281682b 7314
b4ff3a36 7315 u8 reserved_at_20[0x20];
e281682b 7316
b4ff3a36 7317 u8 reserved_at_40[0x7];
e281682b
SM		 7318 u8 polarity[0x1];
7319 u8 ob_tap0[0x8];
7320 u8 ob_tap1[0x8];
7321 u8 ob_tap2[0x8];
7322
b4ff3a36 7323 u8 reserved_at_60[0xc];
e281682b
SM		 7324 u8 ob_preemp_mode[0x4];
7325 u8 ob_reg[0x8];
7326 u8 ob_bias[0x8];
7327
b4ff3a36 7328 u8 reserved_at_80[0x20];
e281682b
SM		 7329};
7330
7331struct mlx5_ifc_slrg_reg_bits {
7332 u8 status[0x4];
7333 u8 version[0x4];
7334 u8 local_port[0x8];
7335 u8 pnat[0x2];
b4ff3a36 7336 u8 reserved_at_12[0x2];
e281682b 7337 u8 lane[0x4];
b4ff3a36 7338 u8 reserved_at_18[0x8];
e281682b
SM		 7339
7340 u8 time_to_link_up[0x10];
b4ff3a36 7341 u8 reserved_at_30[0xc];
e281682b
SM		 7342 u8 grade_lane_speed[0x4];
7343
7344 u8 grade_version[0x8];
7345 u8 grade[0x18];
7346
b4ff3a36 7347 u8 reserved_at_60[0x4];
e281682b
SM		 7348 u8 height_grade_type[0x4];
7349 u8 height_grade[0x18];
7350
7351 u8 height_dz[0x10];
7352 u8 height_dv[0x10];
7353
b4ff3a36 7354 u8 reserved_at_a0[0x10];
e281682b
SM		 7355 u8 height_sigma[0x10];
7356
b4ff3a36 7357 u8 reserved_at_c0[0x20];
e281682b 7358
b4ff3a36 7359 u8 reserved_at_e0[0x4];
e281682b
SM		 7360 u8 phase_grade_type[0x4];
7361 u8 phase_grade[0x18];
7362
b4ff3a36 7363 u8 reserved_at_100[0x8];
e281682b 7364 u8 phase_eo_pos[0x8];
b4ff3a36 7365 u8 reserved_at_110[0x8];
e281682b
SM		 7366 u8 phase_eo_neg[0x8];
7367
7368 u8 ffe_set_tested[0x10];
7369 u8 test_errors_per_lane[0x10];
7370};
7371
7372struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7373 u8 reserved_at_0[0x8];
e281682b 7374 u8 local_port[0x8];
b4ff3a36 7375 u8 reserved_at_10[0x10];
e281682b 7376
b4ff3a36 7377 u8 reserved_at_20[0x1c];
e281682b
SM		 7378 u8 vl_hw_cap[0x4];
7379
b4ff3a36 7380 u8 reserved_at_40[0x1c];
e281682b
SM		 7381 u8 vl_admin[0x4];
7382
b4ff3a36 7383 u8 reserved_at_60[0x1c];
e281682b
SM		 7384 u8 vl_operational[0x4];
7385};
7386
7387struct mlx5_ifc_pude_reg_bits {
7388 u8 swid[0x8];
7389 u8 local_port[0x8];
b4ff3a36 7390 u8 reserved_at_10[0x4];
e281682b 7391 u8 admin_status[0x4];
b4ff3a36 7392 u8 reserved_at_18[0x4];
e281682b
SM		 7393 u8 oper_status[0x4];
7394
b4ff3a36 7395 u8 reserved_at_20[0x60];
e281682b
SM		 7396};
7397
7398struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7399 u8 reserved_at_0[0x1];
7486216b 7400 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7401 u8 an_disable_cap[0x1];
7402 u8 reserved_at_3[0x5];
e281682b 7403 u8 local_port[0x8];
b4ff3a36 7404 u8 reserved_at_10[0xd];
e281682b
SM		 7405 u8 proto_mask[0x3];
7406
7486216b
SM		 7407 u8 an_status[0x4];
7408 u8 reserved_at_24[0x3c];
e281682b
SM		 7409
7410 u8 eth_proto_capability[0x20];
7411
7412 u8 ib_link_width_capability[0x10];
7413 u8 ib_proto_capability[0x10];
7414
b4ff3a36 7415 u8 reserved_at_a0[0x20];
e281682b
SM		 7416
7417 u8 eth_proto_admin[0x20];
7418
7419 u8 ib_link_width_admin[0x10];
7420 u8 ib_proto_admin[0x10];
7421
b4ff3a36 7422 u8 reserved_at_100[0x20];
e281682b
SM		 7423
7424 u8 eth_proto_oper[0x20];
7425
7426 u8 ib_link_width_oper[0x10];
7427 u8 ib_proto_oper[0x10];
7428
5b4793f8
EBE		 7429 u8 reserved_at_160[0x1c];
7430 u8 connector_type[0x4];
e281682b
SM		 7431
7432 u8 eth_proto_lp_advertise[0x20];
7433
b4ff3a36 7434 u8 reserved_at_1a0[0x60];
e281682b
SM		 7435};
7436
7d5e1423
SM		 7437struct mlx5_ifc_mlcr_reg_bits {
7438 u8 reserved_at_0[0x8];
7439 u8 local_port[0x8];
7440 u8 reserved_at_10[0x20];
7441
7442 u8 beacon_duration[0x10];
7443 u8 reserved_at_40[0x10];
7444
7445 u8 beacon_remain[0x10];
7446};
7447
e281682b 7448struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7449 u8 reserved_at_0[0x20];
e281682b
SM		 7450
7451 u8 algorithm_options[0x10];
b4ff3a36 7452 u8 reserved_at_30[0x4];
e281682b
SM		 7453 u8 repetitions_mode[0x4];
7454 u8 num_of_repetitions[0x8];
7455
7456 u8 grade_version[0x8];
7457 u8 height_grade_type[0x4];
7458 u8 phase_grade_type[0x4];
7459 u8 height_grade_weight[0x8];
7460 u8 phase_grade_weight[0x8];
7461
7462 u8 gisim_measure_bits[0x10];
7463 u8 adaptive_tap_measure_bits[0x10];
7464
7465 u8 ber_bath_high_error_threshold[0x10];
7466 u8 ber_bath_mid_error_threshold[0x10];
7467
7468 u8 ber_bath_low_error_threshold[0x10];
7469 u8 one_ratio_high_threshold[0x10];
7470
7471 u8 one_ratio_high_mid_threshold[0x10];
7472 u8 one_ratio_low_mid_threshold[0x10];
7473
7474 u8 one_ratio_low_threshold[0x10];
7475 u8 ndeo_error_threshold[0x10];
7476
7477 u8 mixer_offset_step_size[0x10];
b4ff3a36 7478 u8 reserved_at_110[0x8];
e281682b
SM		 7479 u8 mix90_phase_for_voltage_bath[0x8];
7480
7481 u8 mixer_offset_start[0x10];
7482 u8 mixer_offset_end[0x10];
7483
b4ff3a36 7484 u8 reserved_at_140[0x15];
e281682b
SM		 7485 u8 ber_test_time[0xb];
7486};
7487
7488struct mlx5_ifc_pspa_reg_bits {
7489 u8 swid[0x8];
7490 u8 local_port[0x8];
7491 u8 sub_port[0x8];
b4ff3a36 7492 u8 reserved_at_18[0x8];
e281682b 7493
b4ff3a36 7494 u8 reserved_at_20[0x20];
e281682b
SM		 7495};
7496
7497struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7498 u8 reserved_at_0[0x8];
e281682b 7499 u8 local_port[0x8];
b4ff3a36 7500 u8 reserved_at_10[0x5];
e281682b 7501 u8 prio[0x3];
b4ff3a36 7502 u8 reserved_at_18[0x6];
e281682b
SM		 7503 u8 mode[0x2];
7504
b4ff3a36 7505 u8 reserved_at_20[0x20];
e281682b 7506
b4ff3a36 7507 u8 reserved_at_40[0x10];
e281682b
SM		 7508 u8 min_threshold[0x10];
7509
b4ff3a36 7510 u8 reserved_at_60[0x10];
e281682b
SM		 7511 u8 max_threshold[0x10];
7512
b4ff3a36 7513 u8 reserved_at_80[0x10];
e281682b
SM		 7514 u8 mark_probability_denominator[0x10];
7515
b4ff3a36 7516 u8 reserved_at_a0[0x60];
e281682b
SM		 7517};
7518
7519struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7520 u8 reserved_at_0[0x8];
e281682b 7521 u8 local_port[0x8];
b4ff3a36 7522 u8 reserved_at_10[0x10];
e281682b 7523
b4ff3a36 7524 u8 reserved_at_20[0x60];
e281682b 7525
b4ff3a36 7526 u8 reserved_at_80[0x1c];
e281682b
SM		 7527 u8 wrps_admin[0x4];
7528
b4ff3a36 7529 u8 reserved_at_a0[0x1c];
e281682b
SM		 7530 u8 wrps_status[0x4];
7531
b4ff3a36 7532 u8 reserved_at_c0[0x8];
e281682b 7533 u8 up_threshold[0x8];
b4ff3a36 7534 u8 reserved_at_d0[0x8];
e281682b
SM		 7535 u8 down_threshold[0x8];
7536
b4ff3a36 7537 u8 reserved_at_e0[0x20];
e281682b 7538
b4ff3a36 7539 u8 reserved_at_100[0x1c];
e281682b
SM		 7540 u8 srps_admin[0x4];
7541
b4ff3a36 7542 u8 reserved_at_120[0x1c];
e281682b
SM		 7543 u8 srps_status[0x4];
7544
b4ff3a36 7545 u8 reserved_at_140[0x40];
e281682b
SM		 7546};
7547
7548struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7549 u8 reserved_at_0[0x8];
e281682b 7550 u8 local_port[0x8];
b4ff3a36 7551 u8 reserved_at_10[0x10];
e281682b 7552
b4ff3a36 7553 u8 reserved_at_20[0x8];
e281682b 7554 u8 lb_cap[0x8];
b4ff3a36 7555 u8 reserved_at_30[0x8];
e281682b
SM		 7556 u8 lb_en[0x8];
7557};
7558
7559struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7560 u8 reserved_at_0[0x8];
e281682b 7561 u8 local_port[0x8];
b4ff3a36 7562 u8 reserved_at_10[0x10];
e281682b 7563
b4ff3a36 7564 u8 reserved_at_20[0x20];
e281682b
SM		 7565
7566 u8 port_profile_mode[0x8];
7567 u8 static_port_profile[0x8];
7568 u8 active_port_profile[0x8];
b4ff3a36 7569 u8 reserved_at_58[0x8];
e281682b
SM		 7570
7571 u8 retransmission_active[0x8];
7572 u8 fec_mode_active[0x18];
7573
b4ff3a36 7574 u8 reserved_at_80[0x20];
e281682b
SM		 7575};
7576
7577struct mlx5_ifc_ppcnt_reg_bits {
7578 u8 swid[0x8];
7579 u8 local_port[0x8];
7580 u8 pnat[0x2];
b4ff3a36 7581 u8 reserved_at_12[0x8];
e281682b
SM		 7582 u8 grp[0x6];
7583
7584 u8 clr[0x1];
b4ff3a36 7585 u8 reserved_at_21[0x1c];
e281682b
SM		 7586 u8 prio_tc[0x3];
7587
7588 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7589};
7590
8ed1a630
GP		 7591struct mlx5_ifc_mpcnt_reg_bits {
7592 u8 reserved_at_0[0x8];
7593 u8 pcie_index[0x8];
7594 u8 reserved_at_10[0xa];
7595 u8 grp[0x6];
7596
7597 u8 clr[0x1];
7598 u8 reserved_at_21[0x1f];
7599
7600 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7601};
7602
e281682b 7603struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7604 u8 reserved_at_0[0x3];
e281682b 7605 u8 single_mac[0x1];
b4ff3a36 7606 u8 reserved_at_4[0x4];
e281682b
SM		 7607 u8 local_port[0x8];
7608 u8 mac_47_32[0x10];
7609
7610 u8 mac_31_0[0x20];
7611
b4ff3a36 7612 u8 reserved_at_40[0x40];
e281682b
SM		 7613};
7614
7615struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7616 u8 reserved_at_0[0x8];
e281682b 7617 u8 local_port[0x8];
b4ff3a36 7618 u8 reserved_at_10[0x10];
e281682b
SM		 7619
7620 u8 max_mtu[0x10];
b4ff3a36 7621 u8 reserved_at_30[0x10];
e281682b
SM		 7622
7623 u8 admin_mtu[0x10];
b4ff3a36 7624 u8 reserved_at_50[0x10];
e281682b
SM		 7625
7626 u8 oper_mtu[0x10];
b4ff3a36 7627 u8 reserved_at_70[0x10];
e281682b
SM		 7628};
7629
7630struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7631 u8 reserved_at_0[0x8];
e281682b 7632 u8 module[0x8];
b4ff3a36 7633 u8 reserved_at_10[0x10];
e281682b 7634
b4ff3a36 7635 u8 reserved_at_20[0x18];
e281682b
SM		 7636 u8 attenuation_5g[0x8];
7637
b4ff3a36 7638 u8 reserved_at_40[0x18];
e281682b
SM		 7639 u8 attenuation_7g[0x8];
7640
b4ff3a36 7641 u8 reserved_at_60[0x18];
e281682b
SM		 7642 u8 attenuation_12g[0x8];
7643};
7644
7645struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7646 u8 reserved_at_0[0x8];
e281682b 7647 u8 module[0x8];
b4ff3a36 7648 u8 reserved_at_10[0xc];
e281682b
SM		 7649 u8 module_status[0x4];
7650
b4ff3a36 7651 u8 reserved_at_20[0x60];
e281682b
SM		 7652};
7653
7654struct mlx5_ifc_pmpc_reg_bits {
7655 u8 module_state_updated[32][0x8];
7656};
7657
7658struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7659 u8 reserved_at_0[0x4];
e281682b
SM		 7660 u8 mlpn_status[0x4];
7661 u8 local_port[0x8];
b4ff3a36 7662 u8 reserved_at_10[0x10];
e281682b
SM		 7663
7664 u8 e[0x1];
b4ff3a36 7665 u8 reserved_at_21[0x1f];
e281682b
SM		 7666};
7667
7668struct mlx5_ifc_pmlp_reg_bits {
7669 u8 rxtx[0x1];
b4ff3a36 7670 u8 reserved_at_1[0x7];
e281682b 7671 u8 local_port[0x8];
b4ff3a36 7672 u8 reserved_at_10[0x8];
e281682b
SM		 7673 u8 width[0x8];
7674
7675 u8 lane0_module_mapping[0x20];
7676
7677 u8 lane1_module_mapping[0x20];
7678
7679 u8 lane2_module_mapping[0x20];
7680
7681 u8 lane3_module_mapping[0x20];
7682
b4ff3a36 7683 u8 reserved_at_a0[0x160];
e281682b
SM		 7684};
7685
7686struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7687 u8 reserved_at_0[0x8];
e281682b 7688 u8 module[0x8];
b4ff3a36 7689 u8 reserved_at_10[0x4];
e281682b 7690 u8 admin_status[0x4];
b4ff3a36 7691 u8 reserved_at_18[0x4];
e281682b
SM		 7692 u8 oper_status[0x4];
7693
7694 u8 ase[0x1];
7695 u8 ee[0x1];
b4ff3a36 7696 u8 reserved_at_22[0x1c];
e281682b
SM		 7697 u8 e[0x2];
7698
b4ff3a36 7699 u8 reserved_at_40[0x40];
e281682b
SM		 7700};
7701
7702struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7703 u8 reserved_at_0[0x4];
e281682b 7704 u8 profile_id[0xc];
b4ff3a36 7705 u8 reserved_at_10[0x4];
e281682b 7706 u8 proto_mask[0x4];
b4ff3a36 7707 u8 reserved_at_18[0x8];
e281682b 7708
b4ff3a36 7709 u8 reserved_at_20[0x10];
e281682b
SM		 7710 u8 lane_speed[0x10];
7711
b4ff3a36 7712 u8 reserved_at_40[0x17];
e281682b
SM		 7713 u8 lpbf[0x1];
7714 u8 fec_mode_policy[0x8];
7715
7716 u8 retransmission_capability[0x8];
7717 u8 fec_mode_capability[0x18];
7718
7719 u8 retransmission_support_admin[0x8];
7720 u8 fec_mode_support_admin[0x18];
7721
7722 u8 retransmission_request_admin[0x8];
7723 u8 fec_mode_request_admin[0x18];
7724
b4ff3a36 7725 u8 reserved_at_c0[0x80];
e281682b
SM		 7726};
7727
7728struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7729 u8 reserved_at_0[0x8];
e281682b 7730 u8 local_port[0x8];
b4ff3a36 7731 u8 reserved_at_10[0x8];
e281682b
SM		 7732 u8 ib_port[0x8];
7733
b4ff3a36 7734 u8 reserved_at_20[0x60];
e281682b
SM		 7735};
7736
7737struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7738 u8 reserved_at_0[0x8];
e281682b 7739 u8 local_port[0x8];
b4ff3a36 7740 u8 reserved_at_10[0xd];
e281682b
SM		 7741 u8 lbf_mode[0x3];
7742
b4ff3a36 7743 u8 reserved_at_20[0x20];
e281682b
SM		 7744};
7745
7746struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7747 u8 reserved_at_0[0x8];
e281682b 7748 u8 local_port[0x8];
b4ff3a36 7749 u8 reserved_at_10[0x10];
e281682b
SM		 7750
7751 u8 dic[0x1];
b4ff3a36 7752 u8 reserved_at_21[0x19];
e281682b 7753 u8 ipg[0x4];
b4ff3a36 7754 u8 reserved_at_3e[0x2];
e281682b
SM		 7755};
7756
7757struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7758 u8 reserved_at_0[0x8];
e281682b 7759 u8 local_port[0x8];
b4ff3a36 7760 u8 reserved_at_10[0x10];
e281682b 7761
b4ff3a36 7762 u8 reserved_at_20[0xe0];
e281682b
SM		 7763
7764 u8 port_filter[8][0x20];
7765
7766 u8 port_filter_update_en[8][0x20];
7767};
7768
7769struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7770 u8 reserved_at_0[0x8];
e281682b 7771 u8 local_port[0x8];
b4ff3a36 7772 u8 reserved_at_10[0x10];
e281682b
SM		 7773
7774 u8 ppan[0x4];
b4ff3a36 7775 u8 reserved_at_24[0x4];
e281682b 7776 u8 prio_mask_tx[0x8];
b4ff3a36 7777 u8 reserved_at_30[0x8];
e281682b
SM		 7778 u8 prio_mask_rx[0x8];
7779
7780 u8 pptx[0x1];
7781 u8 aptx[0x1];
b4ff3a36 7782 u8 reserved_at_42[0x6];
e281682b 7783 u8 pfctx[0x8];
b4ff3a36 7784 u8 reserved_at_50[0x10];
e281682b
SM		 7785
7786 u8 pprx[0x1];
7787 u8 aprx[0x1];
b4ff3a36 7788 u8 reserved_at_62[0x6];
e281682b 7789 u8 pfcrx[0x8];
b4ff3a36 7790 u8 reserved_at_70[0x10];
e281682b 7791
b4ff3a36 7792 u8 reserved_at_80[0x80];
e281682b
SM		 7793};
7794
7795struct mlx5_ifc_pelc_reg_bits {
7796 u8 op[0x4];
b4ff3a36 7797 u8 reserved_at_4[0x4];
e281682b 7798 u8 local_port[0x8];
b4ff3a36 7799 u8 reserved_at_10[0x10];
e281682b
SM		 7800
7801 u8 op_admin[0x8];
7802 u8 op_capability[0x8];
7803 u8 op_request[0x8];
7804 u8 op_active[0x8];
7805
7806 u8 admin[0x40];
7807
7808 u8 capability[0x40];
7809
7810 u8 request[0x40];
7811
7812 u8 active[0x40];
7813
b4ff3a36 7814 u8 reserved_at_140[0x80];
e281682b
SM		 7815};
7816
7817struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7818 u8 reserved_at_0[0x8];
e281682b 7819 u8 local_port[0x8];
b4ff3a36 7820 u8 reserved_at_10[0x10];
e281682b 7821
b4ff3a36 7822 u8 reserved_at_20[0xc];
e281682b 7823 u8 error_count[0x4];
b4ff3a36 7824 u8 reserved_at_30[0x10];
e281682b 7825
b4ff3a36 7826 u8 reserved_at_40[0xc];
e281682b 7827 u8 lane[0x4];
b4ff3a36 7828 u8 reserved_at_50[0x8];
e281682b
SM		 7829 u8 error_type[0x8];
7830};
7831
cfdcbcea 7832struct mlx5_ifc_pcam_enhanced_features_bits {
2dba0797 7833 u8 reserved_at_0[0x7b];
cfdcbcea 7834
2dba0797 7835 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 7836 u8 ptys_connector_type[0x1];
7837 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7838 u8 ppcnt_discard_group[0x1];
7839 u8 ppcnt_statistical_group[0x1];
7840};
7841
7842struct mlx5_ifc_pcam_reg_bits {
7843 u8 reserved_at_0[0x8];
7844 u8 feature_group[0x8];
7845 u8 reserved_at_10[0x8];
7846 u8 access_reg_group[0x8];
7847
7848 u8 reserved_at_20[0x20];
7849
7850 union {
7851 u8 reserved_at_0[0x80];
7852 } port_access_reg_cap_mask;
7853
7854 u8 reserved_at_c0[0x80];
7855
7856 union {
7857 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7858 u8 reserved_at_0[0x80];
7859 } feature_cap_mask;
7860
7861 u8 reserved_at_1c0[0xc0];
7862};
7863
7864struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 7865 u8 reserved_at_0[0x7b];
7866 u8 pcie_outbound_stalled[0x1];
efae7f78 7867 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 7868 u8 mtpps_enh_out_per_adj[0x1];
7869 u8 mtpps_fs[0x1];
cfdcbcea
GP		 7870 u8 pcie_performance_group[0x1];
7871};
7872
0ab87743
OG		 7873struct mlx5_ifc_mcam_access_reg_bits {
7874 u8 reserved_at_0[0x1c];
7875 u8 mcda[0x1];
7876 u8 mcc[0x1];
7877 u8 mcqi[0x1];
7878 u8 reserved_at_1f[0x1];
7879
7880 u8 regs_95_to_64[0x20];
7881 u8 regs_63_to_32[0x20];
7882 u8 regs_31_to_0[0x20];
7883};
7884
cfdcbcea
GP		 7885struct mlx5_ifc_mcam_reg_bits {
7886 u8 reserved_at_0[0x8];
7887 u8 feature_group[0x8];
7888 u8 reserved_at_10[0x8];
7889 u8 access_reg_group[0x8];
7890
7891 u8 reserved_at_20[0x20];
7892
7893 union {
0ab87743 7894 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 7895 u8 reserved_at_0[0x80];
7896 } mng_access_reg_cap_mask;
7897
7898 u8 reserved_at_c0[0x80];
7899
7900 union {
7901 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7902 u8 reserved_at_0[0x80];
7903 } mng_feature_cap_mask;
7904
7905 u8 reserved_at_1c0[0x80];
7906};
7907
c02762eb
HN		 7908struct mlx5_ifc_qcam_access_reg_cap_mask {
7909 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7910 u8 qpdpm[0x1];
7911 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7912 u8 qdpm[0x1];
7913 u8 qpts[0x1];
7914 u8 qcap[0x1];
7915 u8 qcam_access_reg_cap_mask_0[0x1];
7916};
7917
7918struct mlx5_ifc_qcam_qos_feature_cap_mask {
7919 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7920 u8 qpts_trust_both[0x1];
7921};
7922
7923struct mlx5_ifc_qcam_reg_bits {
7924 u8 reserved_at_0[0x8];
7925 u8 feature_group[0x8];
7926 u8 reserved_at_10[0x8];
7927 u8 access_reg_group[0x8];
7928 u8 reserved_at_20[0x20];
7929
7930 union {
7931 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7932 u8 reserved_at_0[0x80];
7933 } qos_access_reg_cap_mask;
7934
7935 u8 reserved_at_c0[0x80];
7936
7937 union {
7938 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7939 u8 reserved_at_0[0x80];
7940 } qos_feature_cap_mask;
7941
7942 u8 reserved_at_1c0[0x80];
7943};
7944
e281682b 7945struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7946 u8 reserved_at_0[0x8];
e281682b 7947 u8 local_port[0x8];
b4ff3a36 7948 u8 reserved_at_10[0x10];
e281682b
SM		 7949
7950 u8 port_capability_mask[4][0x20];
7951};
7952
7953struct mlx5_ifc_paos_reg_bits {
7954 u8 swid[0x8];
7955 u8 local_port[0x8];
b4ff3a36 7956 u8 reserved_at_10[0x4];
e281682b 7957 u8 admin_status[0x4];
b4ff3a36 7958 u8 reserved_at_18[0x4];
e281682b
SM		 7959 u8 oper_status[0x4];
7960
7961 u8 ase[0x1];
7962 u8 ee[0x1];
b4ff3a36 7963 u8 reserved_at_22[0x1c];
e281682b
SM		 7964 u8 e[0x2];
7965
b4ff3a36 7966 u8 reserved_at_40[0x40];
e281682b
SM		 7967};
7968
7969struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7970 u8 reserved_at_0[0x8];
e281682b 7971 u8 opamp_group[0x8];
b4ff3a36 7972 u8 reserved_at_10[0xc];
e281682b
SM		 7973 u8 opamp_group_type[0x4];
7974
7975 u8 start_index[0x10];
b4ff3a36 7976 u8 reserved_at_30[0x4];
e281682b
SM		 7977 u8 num_of_indices[0xc];
7978
7979 u8 index_data[18][0x10];
7980};
7981
7d5e1423
SM		 7982struct mlx5_ifc_pcmr_reg_bits {
7983 u8 reserved_at_0[0x8];
7984 u8 local_port[0x8];
7985 u8 reserved_at_10[0x2e];
7986 u8 fcs_cap[0x1];
7987 u8 reserved_at_3f[0x1f];
7988 u8 fcs_chk[0x1];
7989 u8 reserved_at_5f[0x1];
7990};
7991
e281682b 7992struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7993 u8 reserved_at_0[0x6];
e281682b 7994 u8 rx_lane[0x2];
b4ff3a36 7995 u8 reserved_at_8[0x6];
e281682b 7996 u8 tx_lane[0x2];
b4ff3a36 7997 u8 reserved_at_10[0x8];
e281682b
SM		 7998 u8 module[0x8];
7999};
8000
8001struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 8002 u8 reserved_at_0[0x6];
e281682b
SM		 8003 u8 lossy[0x1];
8004 u8 epsb[0x1];
b4ff3a36 8005 u8 reserved_at_8[0xc];
e281682b
SM		 8006 u8 size[0xc];
8007
8008 u8 xoff_threshold[0x10];
8009 u8 xon_threshold[0x10];
8010};
8011
8012struct mlx5_ifc_set_node_in_bits {
8013 u8 node_description[64][0x8];
8014};
8015
8016struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8017 u8 reserved_at_0[0x18];
e281682b
SM		 8018 u8 power_settings_level[0x8];
8019
b4ff3a36 8020 u8 reserved_at_20[0x60];
e281682b
SM		 8021};
8022
8023struct mlx5_ifc_register_host_endianness_bits {
8024 u8 he[0x1];
b4ff3a36 8025 u8 reserved_at_1[0x1f];
e281682b 8026
b4ff3a36 8027 u8 reserved_at_20[0x60];
e281682b
SM		 8028};
8029
8030struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8031 u8 reserved_at_0[0x20];
e281682b
SM		 8032
8033 u8 mkey[0x20];
8034
8035 u8 addressh_63_32[0x20];
8036
8037 u8 addressl_31_0[0x20];
8038};
8039
8040struct mlx5_ifc_ud_adrs_vector_bits {
8041 u8 dc_key[0x40];
8042
8043 u8 ext[0x1];
b4ff3a36 8044 u8 reserved_at_41[0x7];
e281682b
SM		 8045 u8 destination_qp_dct[0x18];
8046
8047 u8 static_rate[0x4];
8048 u8 sl_eth_prio[0x4];
8049 u8 fl[0x1];
8050 u8 mlid[0x7];
8051 u8 rlid_udp_sport[0x10];
8052
b4ff3a36 8053 u8 reserved_at_80[0x20];
e281682b
SM		 8054
8055 u8 rmac_47_16[0x20];
8056
8057 u8 rmac_15_0[0x10];
8058 u8 tclass[0x8];
8059 u8 hop_limit[0x8];
8060
b4ff3a36 8061 u8 reserved_at_e0[0x1];
e281682b 8062 u8 grh[0x1];
b4ff3a36 8063 u8 reserved_at_e2[0x2];
e281682b
SM		 8064 u8 src_addr_index[0x8];
8065 u8 flow_label[0x14];
8066
8067 u8 rgid_rip[16][0x8];
8068};
8069
8070struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8071 u8 reserved_at_0[0x10];
e281682b
SM		 8072 u8 function_id[0x10];
8073
8074 u8 num_pages[0x20];
8075
b4ff3a36 8076 u8 reserved_at_40[0xa0];
e281682b
SM		 8077};
8078
8079struct mlx5_ifc_eqe_bits {
b4ff3a36 8080 u8 reserved_at_0[0x8];
e281682b 8081 u8 event_type[0x8];
b4ff3a36 8082 u8 reserved_at_10[0x8];
e281682b
SM		 8083 u8 event_sub_type[0x8];
8084
b4ff3a36 8085 u8 reserved_at_20[0xe0];
e281682b
SM		 8086
8087 union mlx5_ifc_event_auto_bits event_data;
8088
b4ff3a36 8089 u8 reserved_at_1e0[0x10];
e281682b 8090 u8 signature[0x8];
b4ff3a36 8091 u8 reserved_at_1f8[0x7];
e281682b
SM		 8092 u8 owner[0x1];
8093};
8094
8095enum {
8096 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8097};
8098
8099struct mlx5_ifc_cmd_queue_entry_bits {
8100 u8 type[0x8];
b4ff3a36 8101 u8 reserved_at_8[0x18];
e281682b
SM		 8102
8103 u8 input_length[0x20];
8104
8105 u8 input_mailbox_pointer_63_32[0x20];
8106
8107 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8108 u8 reserved_at_77[0x9];
e281682b
SM		 8109
8110 u8 command_input_inline_data[16][0x8];
8111
8112 u8 command_output_inline_data[16][0x8];
8113
8114 u8 output_mailbox_pointer_63_32[0x20];
8115
8116 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8117 u8 reserved_at_1b7[0x9];
e281682b
SM		 8118
8119 u8 output_length[0x20];
8120
8121 u8 token[0x8];
8122 u8 signature[0x8];
b4ff3a36 8123 u8 reserved_at_1f0[0x8];
e281682b
SM		 8124 u8 status[0x7];
8125 u8 ownership[0x1];
8126};
8127
8128struct mlx5_ifc_cmd_out_bits {
8129 u8 status[0x8];
b4ff3a36 8130 u8 reserved_at_8[0x18];
e281682b
SM		 8131
8132 u8 syndrome[0x20];
8133
8134 u8 command_output[0x20];
8135};
8136
8137struct mlx5_ifc_cmd_in_bits {
8138 u8 opcode[0x10];
b4ff3a36 8139 u8 reserved_at_10[0x10];
e281682b 8140
b4ff3a36 8141 u8 reserved_at_20[0x10];
e281682b
SM		 8142 u8 op_mod[0x10];
8143
8144 u8 command[0][0x20];
8145};
8146
8147struct mlx5_ifc_cmd_if_box_bits {
8148 u8 mailbox_data[512][0x8];
8149
b4ff3a36 8150 u8 reserved_at_1000[0x180];
e281682b
SM		 8151
8152 u8 next_pointer_63_32[0x20];
8153
8154 u8 next_pointer_31_10[0x16];
b4ff3a36 8155 u8 reserved_at_11b6[0xa];
e281682b
SM		 8156
8157 u8 block_number[0x20];
8158
b4ff3a36 8159 u8 reserved_at_11e0[0x8];
e281682b
SM		 8160 u8 token[0x8];
8161 u8 ctrl_signature[0x8];
8162 u8 signature[0x8];
8163};
8164
8165struct mlx5_ifc_mtt_bits {
8166 u8 ptag_63_32[0x20];
8167
8168 u8 ptag_31_8[0x18];
b4ff3a36 8169 u8 reserved_at_38[0x6];
e281682b
SM		 8170 u8 wr_en[0x1];
8171 u8 rd_en[0x1];
8172};
8173
928cfe87
TT		 8174struct mlx5_ifc_query_wol_rol_out_bits {
8175 u8 status[0x8];
8176 u8 reserved_at_8[0x18];
8177
8178 u8 syndrome[0x20];
8179
8180 u8 reserved_at_40[0x10];
8181 u8 rol_mode[0x8];
8182 u8 wol_mode[0x8];
8183
8184 u8 reserved_at_60[0x20];
8185};
8186
8187struct mlx5_ifc_query_wol_rol_in_bits {
8188 u8 opcode[0x10];
8189 u8 reserved_at_10[0x10];
8190
8191 u8 reserved_at_20[0x10];
8192 u8 op_mod[0x10];
8193
8194 u8 reserved_at_40[0x40];
8195};
8196
8197struct mlx5_ifc_set_wol_rol_out_bits {
8198 u8 status[0x8];
8199 u8 reserved_at_8[0x18];
8200
8201 u8 syndrome[0x20];
8202
8203 u8 reserved_at_40[0x40];
8204};
8205
8206struct mlx5_ifc_set_wol_rol_in_bits {
8207 u8 opcode[0x10];
8208 u8 reserved_at_10[0x10];
8209
8210 u8 reserved_at_20[0x10];
8211 u8 op_mod[0x10];
8212
8213 u8 rol_mode_valid[0x1];
8214 u8 wol_mode_valid[0x1];
8215 u8 reserved_at_42[0xe];
8216 u8 rol_mode[0x8];
8217 u8 wol_mode[0x8];
8218
8219 u8 reserved_at_60[0x20];
8220};
8221
e281682b
SM		 8222enum {
8223 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8224 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8225 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8226};
8227
8228enum {
8229 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8230 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8231 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8232};
8233
8234enum {
8235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8237 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8238 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8239 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8240 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8241 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8242 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8243 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8244 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8245 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8246};
8247
8248struct mlx5_ifc_initial_seg_bits {
8249 u8 fw_rev_minor[0x10];
8250 u8 fw_rev_major[0x10];
8251
8252 u8 cmd_interface_rev[0x10];
8253 u8 fw_rev_subminor[0x10];
8254
b4ff3a36 8255 u8 reserved_at_40[0x40];
e281682b
SM		 8256
8257 u8 cmdq_phy_addr_63_32[0x20];
8258
8259 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8260 u8 reserved_at_b4[0x2];
e281682b
SM		 8261 u8 nic_interface[0x2];
8262 u8 log_cmdq_size[0x4];
8263 u8 log_cmdq_stride[0x4];
8264
8265 u8 command_doorbell_vector[0x20];
8266
b4ff3a36 8267 u8 reserved_at_e0[0xf00];
e281682b
SM		 8268
8269 u8 initializing[0x1];
b4ff3a36 8270 u8 reserved_at_fe1[0x4];
e281682b 8271 u8 nic_interface_supported[0x3];
b4ff3a36 8272 u8 reserved_at_fe8[0x18];
e281682b
SM		 8273
8274 struct mlx5_ifc_health_buffer_bits health_buffer;
8275
8276 u8 no_dram_nic_offset[0x20];
8277
b4ff3a36 8278 u8 reserved_at_1220[0x6e40];
e281682b 8279
b4ff3a36 8280 u8 reserved_at_8060[0x1f];
e281682b
SM		 8281 u8 clear_int[0x1];
8282
8283 u8 health_syndrome[0x8];
8284 u8 health_counter[0x18];
8285
b4ff3a36 8286 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8287};
8288
f9a1ef72
EE		 8289struct mlx5_ifc_mtpps_reg_bits {
8290 u8 reserved_at_0[0xc];
8291 u8 cap_number_of_pps_pins[0x4];
8292 u8 reserved_at_10[0x4];
8293 u8 cap_max_num_of_pps_in_pins[0x4];
8294 u8 reserved_at_18[0x4];
8295 u8 cap_max_num_of_pps_out_pins[0x4];
8296
8297 u8 reserved_at_20[0x24];
8298 u8 cap_pin_3_mode[0x4];
8299 u8 reserved_at_48[0x4];
8300 u8 cap_pin_2_mode[0x4];
8301 u8 reserved_at_50[0x4];
8302 u8 cap_pin_1_mode[0x4];
8303 u8 reserved_at_58[0x4];
8304 u8 cap_pin_0_mode[0x4];
8305
8306 u8 reserved_at_60[0x4];
8307 u8 cap_pin_7_mode[0x4];
8308 u8 reserved_at_68[0x4];
8309 u8 cap_pin_6_mode[0x4];
8310 u8 reserved_at_70[0x4];
8311 u8 cap_pin_5_mode[0x4];
8312 u8 reserved_at_78[0x4];
8313 u8 cap_pin_4_mode[0x4];
8314
fa367688
EE		 8315 u8 field_select[0x20];
8316 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8317
8318 u8 enable[0x1];
8319 u8 reserved_at_101[0xb];
8320 u8 pattern[0x4];
8321 u8 reserved_at_110[0x4];
8322 u8 pin_mode[0x4];
8323 u8 pin[0x8];
8324
8325 u8 reserved_at_120[0x20];
8326
8327 u8 time_stamp[0x40];
8328
8329 u8 out_pulse_duration[0x10];
8330 u8 out_periodic_adjustment[0x10];
fa367688 8331 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8332
fa367688 8333 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8334};
8335
8336struct mlx5_ifc_mtppse_reg_bits {
8337 u8 reserved_at_0[0x18];
8338 u8 pin[0x8];
8339 u8 event_arm[0x1];
8340 u8 reserved_at_21[0x1b];
8341 u8 event_generation_mode[0x4];
8342 u8 reserved_at_40[0x40];
8343};
8344
47176289
OG		 8345struct mlx5_ifc_mcqi_cap_bits {
8346 u8 supported_info_bitmask[0x20];
8347
8348 u8 component_size[0x20];
8349
8350 u8 max_component_size[0x20];
8351
8352 u8 log_mcda_word_size[0x4];
8353 u8 reserved_at_64[0xc];
8354 u8 mcda_max_write_size[0x10];
8355
8356 u8 rd_en[0x1];
8357 u8 reserved_at_81[0x1];
8358 u8 match_chip_id[0x1];
8359 u8 match_psid[0x1];
8360 u8 check_user_timestamp[0x1];
8361 u8 match_base_guid_mac[0x1];
8362 u8 reserved_at_86[0x1a];
8363};
8364
8365struct mlx5_ifc_mcqi_reg_bits {
8366 u8 read_pending_component[0x1];
8367 u8 reserved_at_1[0xf];
8368 u8 component_index[0x10];
8369
8370 u8 reserved_at_20[0x20];
8371
8372 u8 reserved_at_40[0x1b];
8373 u8 info_type[0x5];
8374
8375 u8 info_size[0x20];
8376
8377 u8 offset[0x20];
8378
8379 u8 reserved_at_a0[0x10];
8380 u8 data_size[0x10];
8381
8382 u8 data[0][0x20];
8383};
8384
8385struct mlx5_ifc_mcc_reg_bits {
8386 u8 reserved_at_0[0x4];
8387 u8 time_elapsed_since_last_cmd[0xc];
8388 u8 reserved_at_10[0x8];
8389 u8 instruction[0x8];
8390
8391 u8 reserved_at_20[0x10];
8392 u8 component_index[0x10];
8393
8394 u8 reserved_at_40[0x8];
8395 u8 update_handle[0x18];
8396
8397 u8 handle_owner_type[0x4];
8398 u8 handle_owner_host_id[0x4];
8399 u8 reserved_at_68[0x1];
8400 u8 control_progress[0x7];
8401 u8 error_code[0x8];
8402 u8 reserved_at_78[0x4];
8403 u8 control_state[0x4];
8404
8405 u8 component_size[0x20];
8406
8407 u8 reserved_at_a0[0x60];
8408};
8409
8410struct mlx5_ifc_mcda_reg_bits {
8411 u8 reserved_at_0[0x8];
8412 u8 update_handle[0x18];
8413
8414 u8 offset[0x20];
8415
8416 u8 reserved_at_40[0x10];
8417 u8 size[0x10];
8418
8419 u8 reserved_at_60[0x20];
8420
8421 u8 data[0][0x20];
8422};
8423
e281682b
SM		 8424union mlx5_ifc_ports_control_registers_document_bits {
8425 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8426 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8427 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8428 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8429 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8430 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8431 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8432 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8433 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8434 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8435 struct mlx5_ifc_paos_reg_bits paos_reg;
8436 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8437 struct mlx5_ifc_peir_reg_bits peir_reg;
8438 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8439 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8440 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8441 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8442 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8443 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8444 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8445 struct mlx5_ifc_plib_reg_bits plib_reg;
8446 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8447 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8448 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8449 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8450 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8451 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8452 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8453 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8454 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8455 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8456 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8457 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8458 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8459 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8460 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8461 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8462 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8463 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8464 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8465 struct mlx5_ifc_pude_reg_bits pude_reg;
8466 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8467 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8468 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8469 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8470 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8471 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8472 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8473 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8474 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8475 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8476 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8477 u8 reserved_at_0[0x60e0];
e281682b
SM		 8478};
8479
8480union mlx5_ifc_debug_enhancements_document_bits {
8481 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8482 u8 reserved_at_0[0x200];
e281682b
SM		 8483};
8484
8485union mlx5_ifc_uplink_pci_interface_document_bits {
8486 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8487 u8 reserved_at_0[0x20060];
b775516b
EC		 8488};
8489
2cc43b49
MG		 8490struct mlx5_ifc_set_flow_table_root_out_bits {
8491 u8 status[0x8];
b4ff3a36 8492 u8 reserved_at_8[0x18];
2cc43b49
MG		 8493
8494 u8 syndrome[0x20];
8495
b4ff3a36 8496 u8 reserved_at_40[0x40];
2cc43b49
MG		 8497};
8498
8499struct mlx5_ifc_set_flow_table_root_in_bits {
8500 u8 opcode[0x10];
b4ff3a36 8501 u8 reserved_at_10[0x10];
2cc43b49 8502
b4ff3a36 8503 u8 reserved_at_20[0x10];
2cc43b49
MG		 8504 u8 op_mod[0x10];
8505
7d5e1423
SM		 8506 u8 other_vport[0x1];
8507 u8 reserved_at_41[0xf];
8508 u8 vport_number[0x10];
8509
8510 u8 reserved_at_60[0x20];
2cc43b49
MG		 8511
8512 u8 table_type[0x8];
b4ff3a36 8513 u8 reserved_at_88[0x18];
2cc43b49 8514
b4ff3a36 8515 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8516 u8 table_id[0x18];
8517
500a3d0d
ES		 8518 u8 reserved_at_c0[0x8];
8519 u8 underlay_qpn[0x18];
8520 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8521};
8522
34a40e68 8523enum {
84df61eb
AH		 8524 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8525 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8526};
8527
8528struct mlx5_ifc_modify_flow_table_out_bits {
8529 u8 status[0x8];
b4ff3a36 8530 u8 reserved_at_8[0x18];
34a40e68
MG		 8531
8532 u8 syndrome[0x20];
8533
b4ff3a36 8534 u8 reserved_at_40[0x40];
34a40e68
MG		 8535};
8536
8537struct mlx5_ifc_modify_flow_table_in_bits {
8538 u8 opcode[0x10];
b4ff3a36 8539 u8 reserved_at_10[0x10];
34a40e68 8540
b4ff3a36 8541 u8 reserved_at_20[0x10];
34a40e68
MG		 8542 u8 op_mod[0x10];
8543
7d5e1423
SM		 8544 u8 other_vport[0x1];
8545 u8 reserved_at_41[0xf];
8546 u8 vport_number[0x10];
34a40e68 8547
b4ff3a36 8548 u8 reserved_at_60[0x10];
34a40e68
MG		 8549 u8 modify_field_select[0x10];
8550
8551 u8 table_type[0x8];
b4ff3a36 8552 u8 reserved_at_88[0x18];
34a40e68 8553
b4ff3a36 8554 u8 reserved_at_a0[0x8];
34a40e68
MG		 8555 u8 table_id[0x18];
8556
0c90e9c6 8557 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8558};
8559
4f3961ee
SM		 8560struct mlx5_ifc_ets_tcn_config_reg_bits {
8561 u8 g[0x1];
8562 u8 b[0x1];
8563 u8 r[0x1];
8564 u8 reserved_at_3[0x9];
8565 u8 group[0x4];
8566 u8 reserved_at_10[0x9];
8567 u8 bw_allocation[0x7];
8568
8569 u8 reserved_at_20[0xc];
8570 u8 max_bw_units[0x4];
8571 u8 reserved_at_30[0x8];
8572 u8 max_bw_value[0x8];
8573};
8574
8575struct mlx5_ifc_ets_global_config_reg_bits {
8576 u8 reserved_at_0[0x2];
8577 u8 r[0x1];
8578 u8 reserved_at_3[0x1d];
8579
8580 u8 reserved_at_20[0xc];
8581 u8 max_bw_units[0x4];
8582 u8 reserved_at_30[0x8];
8583 u8 max_bw_value[0x8];
8584};
8585
8586struct mlx5_ifc_qetc_reg_bits {
8587 u8 reserved_at_0[0x8];
8588 u8 port_number[0x8];
8589 u8 reserved_at_10[0x30];
8590
8591 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8592 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8593};
8594
415a64aa
HN		 8595struct mlx5_ifc_qpdpm_dscp_reg_bits {
8596 u8 e[0x1];
8597 u8 reserved_at_01[0x0b];
8598 u8 prio[0x04];
8599};
8600
8601struct mlx5_ifc_qpdpm_reg_bits {
8602 u8 reserved_at_0[0x8];
8603 u8 local_port[0x8];
8604 u8 reserved_at_10[0x10];
8605 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8606};
8607
8608struct mlx5_ifc_qpts_reg_bits {
8609 u8 reserved_at_0[0x8];
8610 u8 local_port[0x8];
8611 u8 reserved_at_10[0x2d];
8612 u8 trust_state[0x3];
8613};
8614
4f3961ee
SM		 8615struct mlx5_ifc_qtct_reg_bits {
8616 u8 reserved_at_0[0x8];
8617 u8 port_number[0x8];
8618 u8 reserved_at_10[0xd];
8619 u8 prio[0x3];
8620
8621 u8 reserved_at_20[0x1d];
8622 u8 tclass[0x3];
8623};
8624
7d5e1423
SM		 8625struct mlx5_ifc_mcia_reg_bits {
8626 u8 l[0x1];
8627 u8 reserved_at_1[0x7];
8628 u8 module[0x8];
8629 u8 reserved_at_10[0x8];
8630 u8 status[0x8];
8631
8632 u8 i2c_device_address[0x8];
8633 u8 page_number[0x8];
8634 u8 device_address[0x10];
8635
8636 u8 reserved_at_40[0x10];
8637 u8 size[0x10];
8638
8639 u8 reserved_at_60[0x20];
8640
8641 u8 dword_0[0x20];
8642 u8 dword_1[0x20];
8643 u8 dword_2[0x20];
8644 u8 dword_3[0x20];
8645 u8 dword_4[0x20];
8646 u8 dword_5[0x20];
8647 u8 dword_6[0x20];
8648 u8 dword_7[0x20];
8649 u8 dword_8[0x20];
8650 u8 dword_9[0x20];
8651 u8 dword_10[0x20];
8652 u8 dword_11[0x20];
8653};
8654
7486216b
SM		 8655struct mlx5_ifc_dcbx_param_bits {
8656 u8 dcbx_cee_cap[0x1];
8657 u8 dcbx_ieee_cap[0x1];
8658 u8 dcbx_standby_cap[0x1];
8659 u8 reserved_at_0[0x5];
8660 u8 port_number[0x8];
8661 u8 reserved_at_10[0xa];
8662 u8 max_application_table_size[6];
8663 u8 reserved_at_20[0x15];
8664 u8 version_oper[0x3];
8665 u8 reserved_at_38[5];
8666 u8 version_admin[0x3];
8667 u8 willing_admin[0x1];
8668 u8 reserved_at_41[0x3];
8669 u8 pfc_cap_oper[0x4];
8670 u8 reserved_at_48[0x4];
8671 u8 pfc_cap_admin[0x4];
8672 u8 reserved_at_50[0x4];
8673 u8 num_of_tc_oper[0x4];
8674 u8 reserved_at_58[0x4];
8675 u8 num_of_tc_admin[0x4];
8676 u8 remote_willing[0x1];
8677 u8 reserved_at_61[3];
8678 u8 remote_pfc_cap[4];
8679 u8 reserved_at_68[0x14];
8680 u8 remote_num_of_tc[0x4];
8681 u8 reserved_at_80[0x18];
8682 u8 error[0x8];
8683 u8 reserved_at_a0[0x160];
8684};
84df61eb
AH		 8685
8686struct mlx5_ifc_lagc_bits {
8687 u8 reserved_at_0[0x1d];
8688 u8 lag_state[0x3];
8689
8690 u8 reserved_at_20[0x14];
8691 u8 tx_remap_affinity_2[0x4];
8692 u8 reserved_at_38[0x4];
8693 u8 tx_remap_affinity_1[0x4];
8694};
8695
8696struct mlx5_ifc_create_lag_out_bits {
8697 u8 status[0x8];
8698 u8 reserved_at_8[0x18];
8699
8700 u8 syndrome[0x20];
8701
8702 u8 reserved_at_40[0x40];
8703};
8704
8705struct mlx5_ifc_create_lag_in_bits {
8706 u8 opcode[0x10];
8707 u8 reserved_at_10[0x10];
8708
8709 u8 reserved_at_20[0x10];
8710 u8 op_mod[0x10];
8711
8712 struct mlx5_ifc_lagc_bits ctx;
8713};
8714
8715struct mlx5_ifc_modify_lag_out_bits {
8716 u8 status[0x8];
8717 u8 reserved_at_8[0x18];
8718
8719 u8 syndrome[0x20];
8720
8721 u8 reserved_at_40[0x40];
8722};
8723
8724struct mlx5_ifc_modify_lag_in_bits {
8725 u8 opcode[0x10];
8726 u8 reserved_at_10[0x10];
8727
8728 u8 reserved_at_20[0x10];
8729 u8 op_mod[0x10];
8730
8731 u8 reserved_at_40[0x20];
8732 u8 field_select[0x20];
8733
8734 struct mlx5_ifc_lagc_bits ctx;
8735};
8736
8737struct mlx5_ifc_query_lag_out_bits {
8738 u8 status[0x8];
8739 u8 reserved_at_8[0x18];
8740
8741 u8 syndrome[0x20];
8742
84df61eb
AH		 8743 struct mlx5_ifc_lagc_bits ctx;
8744};
8745
8746struct mlx5_ifc_query_lag_in_bits {
8747 u8 opcode[0x10];
8748 u8 reserved_at_10[0x10];
8749
8750 u8 reserved_at_20[0x10];
8751 u8 op_mod[0x10];
8752
8753 u8 reserved_at_40[0x40];
8754};
8755
8756struct mlx5_ifc_destroy_lag_out_bits {
8757 u8 status[0x8];
8758 u8 reserved_at_8[0x18];
8759
8760 u8 syndrome[0x20];
8761
8762 u8 reserved_at_40[0x40];
8763};
8764
8765struct mlx5_ifc_destroy_lag_in_bits {
8766 u8 opcode[0x10];
8767 u8 reserved_at_10[0x10];
8768
8769 u8 reserved_at_20[0x10];
8770 u8 op_mod[0x10];
8771
8772 u8 reserved_at_40[0x40];
8773};
8774
8775struct mlx5_ifc_create_vport_lag_out_bits {
8776 u8 status[0x8];
8777 u8 reserved_at_8[0x18];
8778
8779 u8 syndrome[0x20];
8780
8781 u8 reserved_at_40[0x40];
8782};
8783
8784struct mlx5_ifc_create_vport_lag_in_bits {
8785 u8 opcode[0x10];
8786 u8 reserved_at_10[0x10];
8787
8788 u8 reserved_at_20[0x10];
8789 u8 op_mod[0x10];
8790
8791 u8 reserved_at_40[0x40];
8792};
8793
8794struct mlx5_ifc_destroy_vport_lag_out_bits {
8795 u8 status[0x8];
8796 u8 reserved_at_8[0x18];
8797
8798 u8 syndrome[0x20];
8799
8800 u8 reserved_at_40[0x40];
8801};
8802
8803struct mlx5_ifc_destroy_vport_lag_in_bits {
8804 u8 opcode[0x10];
8805 u8 reserved_at_10[0x10];
8806
8807 u8 reserved_at_20[0x10];
8808 u8 op_mod[0x10];
8809
8810 u8 reserved_at_40[0x40];
8811};
8812
d29b796a 8813#endif /* MLX5_IFC_H */
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