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b2441318 1// SPDX-License-Identifier: GPL-2.0
1da177e4
LT
2/*
3 * Implement the default iomap interfaces
4 *
5 * (C) Copyright 2004 Linus Torvalds
6 */
7#include <linux/pci.h>
9ac7849e
TH
8#include <linux/io.h>
9
8bc3bcc9 10#include <linux/export.h>
1da177e4
LT
11
12/*
13 * Read/write from/to an (offsettable) iomem cookie. It might be a PIO
14 * access or a MMIO access, these functions don't care. The info is
15 * encoded in the hardware mapping set up by the mapping functions
16 * (or the cookie itself, depending on implementation and hw).
17 *
18 * The generic routines don't assume any hardware mappings, and just
19 * encode the PIO/MMIO as part of the cookie. They coldly assume that
20 * the MMIO IO mappings are not in the low address range.
21 *
22 * Architectures for which this is not true can't use this generic
23 * implementation and should do their own copy.
24 */
25
26#ifndef HAVE_ARCH_PIO_SIZE
27/*
28 * We encode the physical PIO addresses (0-0xffff) into the
29 * pointer by offsetting them with a constant (0x10000) and
30 * assuming that all the low addresses are always PIO. That means
31 * we can do some sanity checks on the low bits, and don't
32 * need to just take things for granted.
33 */
34#define PIO_OFFSET 0x10000UL
35#define PIO_MASK 0x0ffffUL
36#define PIO_RESERVED 0x40000UL
37#endif
38
6cbf0c70
LT
39static void bad_io_access(unsigned long port, const char *access)
40{
41 static int count = 10;
42 if (count) {
43 count--;
5cd2b459 44 WARN(1, KERN_ERR "Bad IO access at port %#lx (%s)\n", port, access);
6cbf0c70
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45 }
46}
47
1da177e4
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48/*
49 * Ugly macros are a way of life.
50 */
1da177e4
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51#define IO_COND(addr, is_pio, is_mmio) do { \
52 unsigned long port = (unsigned long __force)addr; \
6cbf0c70
LT
53 if (port >= PIO_RESERVED) { \
54 is_mmio; \
55 } else if (port > PIO_OFFSET) { \
1da177e4
LT
56 port &= PIO_MASK; \
57 is_pio; \
6cbf0c70
LT
58 } else \
59 bad_io_access(port, #is_pio ); \
1da177e4
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60} while (0)
61
34ba8a5c
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62#ifndef pio_read16be
63#define pio_read16be(port) swab16(inw(port))
64#define pio_read32be(port) swab32(inl(port))
65#endif
66
67#ifndef mmio_read16be
68#define mmio_read16be(addr) be16_to_cpu(__raw_readw(addr))
69#define mmio_read32be(addr) be32_to_cpu(__raw_readl(addr))
70#endif
71
9f741cb8 72unsigned int ioread8(void __iomem *addr)
1da177e4
LT
73{
74 IO_COND(addr, return inb(port), return readb(addr));
6cbf0c70 75 return 0xff;
1da177e4 76}
9f741cb8 77unsigned int ioread16(void __iomem *addr)
1da177e4
LT
78{
79 IO_COND(addr, return inw(port), return readw(addr));
6cbf0c70 80 return 0xffff;
1da177e4 81}
9f741cb8 82unsigned int ioread16be(void __iomem *addr)
dae409a2 83{
34ba8a5c 84 IO_COND(addr, return pio_read16be(port), return mmio_read16be(addr));
6cbf0c70 85 return 0xffff;
dae409a2 86}
9f741cb8 87unsigned int ioread32(void __iomem *addr)
1da177e4
LT
88{
89 IO_COND(addr, return inl(port), return readl(addr));
6cbf0c70 90 return 0xffffffff;
1da177e4 91}
9f741cb8 92unsigned int ioread32be(void __iomem *addr)
dae409a2 93{
34ba8a5c 94 IO_COND(addr, return pio_read32be(port), return mmio_read32be(addr));
6cbf0c70 95 return 0xffffffff;
dae409a2 96}
1da177e4
LT
97EXPORT_SYMBOL(ioread8);
98EXPORT_SYMBOL(ioread16);
dae409a2 99EXPORT_SYMBOL(ioread16be);
1da177e4 100EXPORT_SYMBOL(ioread32);
dae409a2 101EXPORT_SYMBOL(ioread32be);
1da177e4 102
34ba8a5c
LT
103#ifndef pio_write16be
104#define pio_write16be(val,port) outw(swab16(val),port)
105#define pio_write32be(val,port) outl(swab32(val),port)
106#endif
107
108#ifndef mmio_write16be
109#define mmio_write16be(val,port) __raw_writew(be16_to_cpu(val),port)
110#define mmio_write32be(val,port) __raw_writel(be32_to_cpu(val),port)
111#endif
112
9f741cb8 113void iowrite8(u8 val, void __iomem *addr)
1da177e4
LT
114{
115 IO_COND(addr, outb(val,port), writeb(val, addr));
116}
9f741cb8 117void iowrite16(u16 val, void __iomem *addr)
1da177e4
LT
118{
119 IO_COND(addr, outw(val,port), writew(val, addr));
120}
9f741cb8 121void iowrite16be(u16 val, void __iomem *addr)
dae409a2 122{
34ba8a5c 123 IO_COND(addr, pio_write16be(val,port), mmio_write16be(val, addr));
dae409a2 124}
9f741cb8 125void iowrite32(u32 val, void __iomem *addr)
1da177e4
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126{
127 IO_COND(addr, outl(val,port), writel(val, addr));
128}
9f741cb8 129void iowrite32be(u32 val, void __iomem *addr)
dae409a2 130{
34ba8a5c 131 IO_COND(addr, pio_write32be(val,port), mmio_write32be(val, addr));
dae409a2 132}
1da177e4
LT
133EXPORT_SYMBOL(iowrite8);
134EXPORT_SYMBOL(iowrite16);
dae409a2 135EXPORT_SYMBOL(iowrite16be);
1da177e4 136EXPORT_SYMBOL(iowrite32);
dae409a2 137EXPORT_SYMBOL(iowrite32be);
1da177e4
LT
138
139/*
140 * These are the "repeat MMIO read/write" functions.
141 * Note the "__raw" accesses, since we don't want to
142 * convert to CPU byte order. We write in "IO byte
143 * order" (we also don't have IO barriers).
144 */
34ba8a5c 145#ifndef mmio_insb
1da177e4
LT
146static inline void mmio_insb(void __iomem *addr, u8 *dst, int count)
147{
148 while (--count >= 0) {
149 u8 data = __raw_readb(addr);
150 *dst = data;
151 dst++;
152 }
153}
154static inline void mmio_insw(void __iomem *addr, u16 *dst, int count)
155{
156 while (--count >= 0) {
157 u16 data = __raw_readw(addr);
158 *dst = data;
159 dst++;
160 }
161}
162static inline void mmio_insl(void __iomem *addr, u32 *dst, int count)
163{
164 while (--count >= 0) {
165 u32 data = __raw_readl(addr);
166 *dst = data;
167 dst++;
168 }
169}
34ba8a5c 170#endif
1da177e4 171
34ba8a5c 172#ifndef mmio_outsb
1da177e4
LT
173static inline void mmio_outsb(void __iomem *addr, const u8 *src, int count)
174{
175 while (--count >= 0) {
176 __raw_writeb(*src, addr);
177 src++;
178 }
179}
180static inline void mmio_outsw(void __iomem *addr, const u16 *src, int count)
181{
182 while (--count >= 0) {
183 __raw_writew(*src, addr);
184 src++;
185 }
186}
187static inline void mmio_outsl(void __iomem *addr, const u32 *src, int count)
188{
189 while (--count >= 0) {
190 __raw_writel(*src, addr);
191 src++;
192 }
193}
34ba8a5c 194#endif
1da177e4 195
9f741cb8 196void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
1da177e4
LT
197{
198 IO_COND(addr, insb(port,dst,count), mmio_insb(addr, dst, count));
199}
9f741cb8 200void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
1da177e4
LT
201{
202 IO_COND(addr, insw(port,dst,count), mmio_insw(addr, dst, count));
203}
9f741cb8 204void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
1da177e4
LT
205{
206 IO_COND(addr, insl(port,dst,count), mmio_insl(addr, dst, count));
207}
208EXPORT_SYMBOL(ioread8_rep);
209EXPORT_SYMBOL(ioread16_rep);
210EXPORT_SYMBOL(ioread32_rep);
211
9f741cb8 212void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
1da177e4
LT
213{
214 IO_COND(addr, outsb(port, src, count), mmio_outsb(addr, src, count));
215}
9f741cb8 216void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
1da177e4
LT
217{
218 IO_COND(addr, outsw(port, src, count), mmio_outsw(addr, src, count));
219}
9f741cb8 220void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
1da177e4
LT
221{
222 IO_COND(addr, outsl(port, src,count), mmio_outsl(addr, src, count));
223}
224EXPORT_SYMBOL(iowrite8_rep);
225EXPORT_SYMBOL(iowrite16_rep);
226EXPORT_SYMBOL(iowrite32_rep);
227
ce816fa8 228#ifdef CONFIG_HAS_IOPORT_MAP
1da177e4
LT
229/* Create a virtual mapping cookie for an IO port range */
230void __iomem *ioport_map(unsigned long port, unsigned int nr)
231{
232 if (port > PIO_MASK)
233 return NULL;
234 return (void __iomem *) (unsigned long) (port + PIO_OFFSET);
235}
236
237void ioport_unmap(void __iomem *addr)
238{
239 /* Nothing to do */
240}
241EXPORT_SYMBOL(ioport_map);
242EXPORT_SYMBOL(ioport_unmap);
ce816fa8 243#endif /* CONFIG_HAS_IOPORT_MAP */
1da177e4 244
82ed223c 245#ifdef CONFIG_PCI
66eab4df
MT
246/* Hide the details if this is a MMIO or PIO address space and just do what
247 * you expect in the correct way. */
1da177e4
LT
248void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
249{
250 IO_COND(addr, /* nothing */, iounmap(addr));
251}
1da177e4 252EXPORT_SYMBOL(pci_iounmap);
82ed223c 253#endif /* CONFIG_PCI */