]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/commit
clk: samsung: exynos5250: Fix PLL rates
authorAndrzej Hajda <a.hajda@samsung.com>
Fri, 16 Feb 2018 14:57:49 +0000 (15:57 +0100)
committerStefan Bader <stefan.bader@canonical.com>
Tue, 14 Aug 2018 10:29:32 +0000 (12:29 +0200)
commit222d21fdb1d0af04db4b4ca8a016ea5586652933
treea948440c35aa50c79df22101ff69b18504cdd579
parentaf2e4936ba0498860ba0c381d00d2342d9f67a80
clk: samsung: exynos5250: Fix PLL rates

BugLink: http://bugs.launchpad.net/bugs/1783418
[ Upstream commit 2ac051eeabaa411ef89ae7cd5bb8e60cb41ad780 ]

Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003. If we now attempt to set rate of a PLL's child divider
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is, the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Kamal Mostafa <kamal@canonical.com>
Signed-off-by: Khalid Elmously <khalid.elmously@canonical.com>
drivers/clk/samsung/clk-exynos5250.c