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MIPS: Netlogic: L1D cacheflush before thread enable on XLPII
authorYonghong Song <ysong@broadcom.com>
Sat, 21 Dec 2013 11:22:16 +0000 (16:52 +0530)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 24 Jan 2014 21:39:47 +0000 (22:39 +0100)
commited8dfc46e0099540cb923f61bca885b460f1365e
treed7856bf6134c31844729669663a8d8917e74c4aetree
parentd3b94285025732379df8a46c02416400c70daa85commit | diff
MIPS: Netlogic: L1D cacheflush before thread enable on XLPII

On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
arch/mips/netlogic/common/reset.S diff | blob | blame | history
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