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ARM: dts: am335x: replace gpio-key,wakeup with wakeup-source property
[mirror_ubuntu-zesty-kernel.git] / arch / arm / boot / dts / am335x-evm.dts
CommitLineData
32bb00e0
AC		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
eb33ef66 10#include "am33xx.dtsi"
52dfcbfc 11#include <dt-bindings/interrupt-controller/irq.h>
32bb00e0
AC		 12
13/ {
14 model = "TI AM335x EVM";
15 compatible = "ti,am335x-evm", "ti,am33xx";
16
efeedcf2
AC		 17 cpus {
18 cpu@0 {
19 cpu0-supply = <&vdd1_reg>;
20 };
21 };
22
32bb00e0
AC		 23 memory {
24 device_type = "memory";
25 reg = <0x80000000 0x10000000>; /* 256 MB */
26 };
53d91034 27
1b2a9702
AC		 28 vbat: fixedregulator@0 {
29 compatible = "regulator-fixed";
30 regulator-name = "vbat";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
33 regulator-boot-on;
34 };
492dd024
AC		 35
36 lis3_reg: fixedregulator@1 {
37 compatible = "regulator-fixed";
38 regulator-name = "lis3_reg";
39 regulator-boot-on;
40 };
2ca1d317 41
52dfcbfc
ER		 42 wlan_en_reg: fixedregulator@2 {
43 compatible = "regulator-fixed";
44 regulator-name = "wlan-en-regulator";
45 regulator-min-microvolt = <1800000>;
46 regulator-max-microvolt = <1800000>;
47
48 /* WLAN_EN GPIO for this board - Bank1, pin16 */
49 gpio = <&gpio1 16 0>;
50
51 /* WLAN card specific delay */
52 startup-delay-us = <70000>;
53 enable-active-high;
54 };
55
2ca1d317
AC		 56 matrix_keypad: matrix_keypad@0 {
57 compatible = "gpio-matrix-keypad";
58 debounce-delay-ms = <5>;
59 col-scan-delay-us = <2>;
60
e94233c2
FV		 61 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
62 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
63 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
2ca1d317 64
e94233c2
FV		 65 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
66 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
2ca1d317
AC		 67
68 linux,keymap = <0x0000008b /* MENU */
69 0x0100009e /* BACK */
70 0x02000069 /* LEFT */
71 0x0001006a /* RIGHT */
72 0x0101001c /* ENTER */
73 0x0201006c>; /* DOWN */
74 };
822c9936
AC		 75
76 gpio_keys: volume_keys@0 {
77 compatible = "gpio-keys";
78 #address-cells = <1>;
79 #size-cells = <0>;
80 autorepeat;
81
82 switch@9 {
83 label = "volume-up";
84 linux,code = <115>;
e94233c2 85 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
3efda001 86 wakeup-source;
822c9936
AC		 87 };
88
89 switch@10 {
90 label = "volume-down";
91 linux,code = <114>;
e94233c2 92 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
3efda001 93 wakeup-source;
822c9936
AC		 94 };
95 };
6993fd01
PA		 96
97 backlight {
98 compatible = "pwm-backlight";
99 pwms = <&ecap0 0 50000 0>;
100 brightness-levels = <0 51 53 56 62 75 101 152 255>;
101 default-brightness-level = <8>;
102 };
d6cfc1e2
BP		 103
104 panel {
105 compatible = "ti,tilcdc,panel";
106 status = "okay";
107 pinctrl-names = "default";
108 pinctrl-0 = <&lcd_pins_s0>;
109 panel-info {
110 ac-bias = <255>;
111 ac-bias-intrpt = <0>;
112 dma-burst-sz = <16>;
113 bpp = <32>;
114 fdd = <0x80>;
115 sync-edge = <0>;
116 sync-ctrl = <1>;
117 raster-order = <0>;
118 fifo-th = <0>;
119 };
120
121 display-timings {
122 800x480p62 {
123 clock-frequency = <30000000>;
124 hactive = <800>;
125 vactive = <480>;
126 hfront-porch = <39>;
127 hback-porch = <39>;
128 hsync-len = <47>;
129 vback-porch = <29>;
130 vfront-porch = <13>;
131 vsync-len = <2>;
132 hsync-active = <1>;
133 vsync-active = <1>;
134 };
135 };
136 };
f608f8dd
DE		 137
138 sound {
80edaaea
PU		 139 compatible = "simple-audio-card";
140 simple-audio-card,name = "AM335x-EVM";
141 simple-audio-card,widgets =
142 "Headphone", "Headphone Jack",
143 "Line", "Line In";
144 simple-audio-card,routing =
145 "Headphone Jack", "HPLOUT",
146 "Headphone Jack", "HPROUT",
147 "LINE1L", "Line In",
148 "LINE1R", "Line In";
149 simple-audio-card,format = "dsp_b";
150 simple-audio-card,bitclock-master = <&sound_master>;
151 simple-audio-card,frame-master = <&sound_master>;
152 simple-audio-card,bitclock-inversion;
153
154 simple-audio-card,cpu {
155 sound-dai = <&mcasp1>;
156 };
157
158 sound_master: simple-audio-card,codec {
159 sound-dai = <&tlv320aic3106>;
160 system-clock-frequency = <12000000>;
161 };
f608f8dd 162 };
1b2a9702
AC		 163};
164
82d75afc
JMC		 165&am33xx_pinmux {
166 pinctrl-names = "default";
167 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
168
169 matrix_keypad_s0: matrix_keypad_s0 {
170 pinctrl-single,pins = <
46bd10c8
JMC		 171 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
172 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
173 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
174 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
175 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
82d75afc
JMC		 176 >;
177 };
178
179 volume_keys_s0: volume_keys_s0 {
180 pinctrl-single,pins = <
46bd10c8
JMC		 181 AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
182 AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
82d75afc
JMC		 183 >;
184 };
185
186 i2c0_pins: pinmux_i2c0_pins {
187 pinctrl-single,pins = <
46bd10c8
JMC		 188 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
189 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
82d75afc
JMC		 190 >;
191 };
192
193 i2c1_pins: pinmux_i2c1_pins {
194 pinctrl-single,pins = <
46bd10c8
JMC		 195 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
196 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
82d75afc
JMC		 197 >;
198 };
199
200 uart0_pins: pinmux_uart0_pins {
201 pinctrl-single,pins = <
46bd10c8
JMC		 202 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
203 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
82d75afc
JMC		 204 >;
205 };
206
ab159d23
EP		 207 uart1_pins: pinmux_uart1_pins {
208 pinctrl-single,pins = <
46bd10c8
JMC		 209 AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
210 AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
211 AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
212 AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
ab159d23
EP		 213 >;
214 };
215
82d75afc
JMC		 216 clkout2_pin: pinmux_clkout2_pin {
217 pinctrl-single,pins = <
46bd10c8 218 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
82d75afc
JMC		 219 >;
220 };
221
222 nandflash_pins_s0: nandflash_pins_s0 {
223 pinctrl-single,pins = <
46bd10c8
JMC		 224 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
225 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
226 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
227 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
228 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
229 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
230 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
231 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
232 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
233 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
234 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
235 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
236 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
237 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
238 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
82d75afc
JMC		 239 >;
240 };
241
242 ecap0_pins: backlight_pins {
243 pinctrl-single,pins = <
46bd10c8 244 AM33XX_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
82d75afc
JMC		 245 >;
246 };
247
248 cpsw_default: cpsw_default {
249 pinctrl-single,pins = <
250 /* Slave 1 */
46bd10c8
JMC		 251 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
252 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
253 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
254 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
255 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
256 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
257 AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
258 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
259 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
260 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
261 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
262 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
82d75afc
JMC		 263 >;
264 };
265
266 cpsw_sleep: cpsw_sleep {
267 pinctrl-single,pins = <
268 /* Slave 1 reset value */
46bd10c8
JMC		 269 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
270 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
271 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
272 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
273 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
274 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
275 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
276 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
277 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
278 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
279 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
280 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
82d75afc
JMC		 281 >;
282 };
283
284 davinci_mdio_default: davinci_mdio_default {
285 pinctrl-single,pins = <
286 /* MDIO */
46bd10c8
JMC		 287 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
288 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
82d75afc
JMC		 289 >;
290 };
291
292 davinci_mdio_sleep: davinci_mdio_sleep {
293 pinctrl-single,pins = <
294 /* MDIO reset value */
46bd10c8
JMC		 295 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
296 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
82d75afc
JMC		 297 >;
298 };
d6cfc1e2 299
b6586cd7
B		 300 mmc1_pins: pinmux_mmc1_pins {
301 pinctrl-single,pins = <
46bd10c8 302 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
b6586cd7
B		 303 >;
304 };
305
52dfcbfc
ER		 306 mmc3_pins: pinmux_mmc3_pins {
307 pinctrl-single,pins = <
46bd10c8
JMC		 308 AM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */
309 AM33XX_IOPAD(0x848, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */
310 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */
311 AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */
312 AM33XX_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */
313 AM33XX_IOPAD(0x88c, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */
52dfcbfc
ER		 314 >;
315 };
316
317 wlan_pins: pinmux_wlan_pins {
318 pinctrl-single,pins = <
46bd10c8
JMC		 319 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.gpio1_16 */
320 AM33XX_IOPAD(0x99c, PIN_INPUT | MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */
321 AM33XX_IOPAD(0x9ac, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */
52dfcbfc
ER		 322 >;
323 };
324
d6cfc1e2
BP		 325 lcd_pins_s0: lcd_pins_s0 {
326 pinctrl-single,pins = <
46bd10c8
JMC		 327 AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
328 AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
329 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
330 AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
331 AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
332 AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
333 AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
334 AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
335 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
336 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
337 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
338 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
339 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
340 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
341 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
342 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
343 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
344 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
345 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
346 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
347 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
348 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
349 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
350 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
351 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
352 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
353 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
354 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
d6cfc1e2
BP		 355 >;
356 };
f608f8dd 357
11fd9a9b 358 mcasp1_pins: mcasp1_pins {
f608f8dd 359 pinctrl-single,pins = <
46bd10c8
JMC		 360 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
361 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
362 AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
363 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
f608f8dd
DE		 364 >;
365 };
f80ecaf5 366
e4e0b702
PU		 367 mcasp1_pins_sleep: mcasp1_pins_sleep {
368 pinctrl-single,pins = <
46bd10c8
JMC		 369 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
370 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
371 AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
372 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
e4e0b702
PU		 373 >;
374 };
375
f80ecaf5
RQ		 376 dcan1_pins_default: dcan1_pins_default {
377 pinctrl-single,pins = <
46bd10c8
JMC		 378 AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
379 AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
f80ecaf5
RQ		 380 >;
381 };
82d75afc
JMC		 382};
383
e0efaafb
JMC		 384&uart0 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_pins>;
387
388 status = "okay";
389};
390
ab159d23
EP		 391&uart1 {
392 pinctrl-names = "default";
393 pinctrl-0 = <&uart1_pins>;
394
395 status = "okay";
396};
397
e0efaafb
JMC		 398&i2c0 {
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2c0_pins>;
401
402 status = "okay";
403 clock-frequency = <400000>;
404
405 tps: tps@2d {
406 reg = <0x2d>;
407 };
408};
409
410&usb {
411 status = "okay";
bd6fdaf7 412};
e0efaafb 413
bd6fdaf7
GM		 414&usb_ctrl_mod {
415 status = "okay";
416};
e0efaafb 417
bd6fdaf7
GM		 418&usb0_phy {
419 status = "okay";
420};
e0efaafb 421
bd6fdaf7
GM		 422&usb1_phy {
423 status = "okay";
424};
e0efaafb 425
bd6fdaf7
GM		 426&usb0 {
427 status = "okay";
428};
e0efaafb 429
bd6fdaf7
GM		 430&usb1 {
431 status = "okay";
432 dr_mode = "host";
433};
e0efaafb 434
bd6fdaf7
GM		 435&cppi41dma {
436 status = "okay";
e0efaafb
JMC		 437};
438
439&i2c1 {
440 pinctrl-names = "default";
441 pinctrl-0 = <&i2c1_pins>;
442
443 status = "okay";
444 clock-frequency = <100000>;
445
446 lis331dlh: lis331dlh@18 {
447 compatible = "st,lis331dlh", "st,lis3lv02d";
448 reg = <0x18>;
449 Vdd-supply = <&lis3_reg>;
450 Vdd_IO-supply = <&lis3_reg>;
451
452 st,click-single-x;
453 st,click-single-y;
454 st,click-single-z;
455 st,click-thresh-x = <10>;
456 st,click-thresh-y = <10>;
457 st,click-thresh-z = <10>;
458 st,irq1-click;
459 st,irq2-click;
460 st,wakeup-x-lo;
461 st,wakeup-x-hi;
462 st,wakeup-y-lo;
463 st,wakeup-y-hi;
464 st,wakeup-z-lo;
465 st,wakeup-z-hi;
466 st,min-limit-x = <120>;
467 st,min-limit-y = <120>;
468 st,min-limit-z = <140>;
469 st,max-limit-x = <550>;
470 st,max-limit-y = <550>;
471 st,max-limit-z = <750>;
472 };
473
474 tsl2550: tsl2550@39 {
475 compatible = "taos,tsl2550";
476 reg = <0x39>;
477 };
478
479 tmp275: tmp275@48 {
480 compatible = "ti,tmp275";
481 reg = <0x48>;
482 };
f608f8dd
DE		 483
484 tlv320aic3106: tlv320aic3106@1b {
80edaaea 485 #sound-dai-cells = <0>;
f608f8dd
DE		 486 compatible = "ti,tlv320aic3106";
487 reg = <0x1b>;
488 status = "okay";
489
490 /* Regulators */
491 AVDD-supply = <&vaux2_reg>;
492 IOVDD-supply = <&vaux2_reg>;
493 DRVDD-supply = <&vaux2_reg>;
494 DVDD-supply = <&vbat>;
495 };
e0efaafb
JMC		 496};
497
d6cfc1e2
BP		 498&lcdc {
499 status = "okay";
500};
501
e0efaafb
JMC		 502&elm {
503 status = "okay";
504};
505
506&epwmss0 {
507 status = "okay";
508
509 ecap0: ecap@48300100 {
510 status = "okay";
511 pinctrl-names = "default";
512 pinctrl-0 = <&ecap0_pins>;
513 };
514};
515
516&gpmc {
517 status = "okay";
518 pinctrl-names = "default";
519 pinctrl-0 = <&nandflash_pins_s0>;
e2c5eb78 520 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
e0efaafb 521 nand@0,0 {
e2c5eb78 522 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
e0efaafb 523 ti,nand-ecc-opt = "bch8";
c06c5270
PG		 524 ti,elm-id = <&elm>;
525 nand-bus-width = <8>;
e0efaafb
JMC		 526 gpmc,device-width = <1>;
527 gpmc,sync-clk-ps = <0>;
528 gpmc,cs-on-ns = <0>;
529 gpmc,cs-rd-off-ns = <44>;
530 gpmc,cs-wr-off-ns = <44>;
531 gpmc,adv-on-ns = <6>;
532 gpmc,adv-rd-off-ns = <34>;
533 gpmc,adv-wr-off-ns = <44>;
534 gpmc,we-on-ns = <0>;
535 gpmc,we-off-ns = <40>;
536 gpmc,oe-on-ns = <0>;
537 gpmc,oe-off-ns = <54>;
538 gpmc,access-ns = <64>;
539 gpmc,rd-cycle-ns = <82>;
540 gpmc,wr-cycle-ns = <82>;
541 gpmc,wait-on-read = "true";
542 gpmc,wait-on-write = "true";
543 gpmc,bus-turnaround-ns = <0>;
544 gpmc,cycle2cycle-delay-ns = <0>;
545 gpmc,clk-activation-ns = <0>;
546 gpmc,wait-monitoring-ns = <0>;
547 gpmc,wr-access-ns = <40>;
548 gpmc,wr-data-mux-bus-ns = <0>;
e0efaafb 549 /* MTD partition table */
91994fac
PG		 550 /* All SPL-* partitions are sized to minimal length
551 * which can be independently programmable. For
552 * NAND flash this is equal to size of erase-block */
553 #address-cells = <1>;
554 #size-cells = <1>;
e0efaafb 555 partition@0 {
91994fac 556 label = "NAND.SPL";
e0efaafb
JMC		 557 reg = <0x00000000 0x000020000>;
558 };
e0efaafb 559 partition@1 {
91994fac 560 label = "NAND.SPL.backup1";
e0efaafb
JMC		 561 reg = <0x00020000 0x00020000>;
562 };
e0efaafb 563 partition@2 {
91994fac 564 label = "NAND.SPL.backup2";
e0efaafb
JMC		 565 reg = <0x00040000 0x00020000>;
566 };
e0efaafb 567 partition@3 {
91994fac 568 label = "NAND.SPL.backup3";
e0efaafb
JMC		 569 reg = <0x00060000 0x00020000>;
570 };
e0efaafb 571 partition@4 {
a8ead0ec 572 label = "NAND.u-boot-spl-os";
91994fac 573 reg = <0x00080000 0x00040000>;
e0efaafb 574 };
e0efaafb 575 partition@5 {
91994fac
PG		 576 label = "NAND.u-boot";
577 reg = <0x000C0000 0x00100000>;
e0efaafb 578 };
e0efaafb 579 partition@6 {
91994fac
PG		 580 label = "NAND.u-boot-env";
581 reg = <0x001C0000 0x00020000>;
e0efaafb 582 };
e0efaafb 583 partition@7 {
91994fac
PG		 584 label = "NAND.u-boot-env.backup1";
585 reg = <0x001E0000 0x00020000>;
586 };
587 partition@8 {
588 label = "NAND.kernel";
589 reg = <0x00200000 0x00800000>;
590 };
591 partition@9 {
592 label = "NAND.file-system";
593 reg = <0x00A00000 0x0F600000>;
e0efaafb
JMC		 594 };
595 };
596};
597
eb33ef66 598#include "tps65910.dtsi"
1b2a9702 599
f608f8dd 600&mcasp1 {
80edaaea 601 #sound-dai-cells = <0>;
e4e0b702 602 pinctrl-names = "default", "sleep";
11fd9a9b 603 pinctrl-0 = <&mcasp1_pins>;
e4e0b702 604 pinctrl-1 = <&mcasp1_pins_sleep>;
f608f8dd 605
a6ccad68 606 status = "okay";
f608f8dd 607
a6ccad68
PU		 608 op-mode = <0>; /* MCASP_IIS_MODE */
609 tdm-slots = <2>;
610 /* 4 serializers */
611 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
612 0 0 1 2
613 >;
614 tx-num-evt = <32>;
615 rx-num-evt = <32>;
f608f8dd
DE		 616};
617
1b2a9702
AC		 618&tps {
619 vcc1-supply = <&vbat>;
620 vcc2-supply = <&vbat>;
621 vcc3-supply = <&vbat>;
622 vcc4-supply = <&vbat>;
623 vcc5-supply = <&vbat>;
624 vcc6-supply = <&vbat>;
625 vcc7-supply = <&vbat>;
626 vccio-supply = <&vbat>;
627
628 regulators {
629 vrtc_reg: regulator@0 {
630 regulator-always-on;
631 };
632
633 vio_reg: regulator@1 {
634 regulator-always-on;
635 };
636
637 vdd1_reg: regulator@2 {
638 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
639 regulator-name = "vdd_mpu";
640 regulator-min-microvolt = <912500>;
641 regulator-max-microvolt = <1312500>;
642 regulator-boot-on;
643 regulator-always-on;
644 };
645
646 vdd2_reg: regulator@3 {
647 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
648 regulator-name = "vdd_core";
649 regulator-min-microvolt = <912500>;
650 regulator-max-microvolt = <1150000>;
651 regulator-boot-on;
652 regulator-always-on;
653 };
654
655 vdd3_reg: regulator@4 {
656 regulator-always-on;
657 };
658
659 vdig1_reg: regulator@5 {
660 regulator-always-on;
661 };
662
663 vdig2_reg: regulator@6 {
664 regulator-always-on;
665 };
666
667 vpll_reg: regulator@7 {
668 regulator-always-on;
669 };
670
671 vdac_reg: regulator@8 {
672 regulator-always-on;
673 };
674
675 vaux1_reg: regulator@9 {
676 regulator-always-on;
677 };
678
679 vaux2_reg: regulator@10 {
680 regulator-always-on;
681 };
682
683 vaux33_reg: regulator@11 {
684 regulator-always-on;
685 };
686
687 vmmc_reg: regulator@12 {
55b4452b
MP		 688 regulator-min-microvolt = <1800000>;
689 regulator-max-microvolt = <3300000>;
1b2a9702
AC		 690 regulator-always-on;
691 };
53d91034 692 };
32bb00e0 693};
1a39a65c 694
50c7d2bd
M		 695&mac {
696 pinctrl-names = "default", "sleep";
697 pinctrl-0 = <&cpsw_default>;
698 pinctrl-1 = <&cpsw_sleep>;
16c75a13 699 status = "okay";
50c7d2bd
M		 700};
701
702&davinci_mdio {
703 pinctrl-names = "default", "sleep";
704 pinctrl-0 = <&davinci_mdio_default>;
705 pinctrl-1 = <&davinci_mdio_sleep>;
16c75a13 706 status = "okay";
50c7d2bd
M		 707};
708
1a39a65c
M		 709&cpsw_emac0 {
710 phy_id = <&davinci_mdio>, <0>;
6d75afe2 711 phy-mode = "rgmii-txid";
1a39a65c
M		 712};
713
714&cpsw_emac1 {
715 phy_id = <&davinci_mdio>, <1>;
6d75afe2 716 phy-mode = "rgmii-txid";
1a39a65c 717};
a82279dd
PR		 718
719&tscadc {
720 status = "okay";
721 tsc {
722 ti,wires = <4>;
723 ti,x-plate-resistance = <200>;
c9aeb249 724 ti,coordinate-readouts = <5>;
a82279dd 725 ti,wire-config = <0x00 0x11 0x22 0x33>;
e6e4a0d1 726 ti,charge-delay = <0x400>;
a82279dd
PR		 727 };
728
729 adc {
18926ede 730 ti,adc-channels = <4 5 6 7>;
a82279dd
PR		 731 };
732};
55b4452b
MP		 733
734&mmc1 {
735 status = "okay";
736 vmmc-supply = <&vmmc_reg>;
0d8d40fc 737 bus-width = <4>;
b6586cd7
B		 738 pinctrl-names = "default";
739 pinctrl-0 = <&mmc1_pins>;
c7ce74bc 740 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
55b4452b 741};
f8302e1e 742
52dfcbfc
ER		 743&mmc3 {
744 /* these are on the crossbar and are outlined in the
745 xbar-event-map element */
b5e50906
PU		 746 dmas = <&edma_xbar 12 0 1
747 &edma_xbar 13 0 2>;
52dfcbfc
ER		 748 dma-names = "tx", "rx";
749 status = "okay";
750 vmmc-supply = <&wlan_en_reg>;
751 bus-width = <4>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&mmc3_pins &wlan_pins>;
754 ti,non-removable;
755 ti,needs-special-hs-handling;
756 cap-power-off-card;
757 keep-power-in-suspend;
758
759 #address-cells = <1>;
760 #size-cells = <0>;
761 wlcore: wlcore@0 {
762 compatible = "ti,wl1835";
763 reg = <2>;
764 interrupt-parent = <&gpio3>;
765 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
766 };
767};
768
f8302e1e
MG		 769&sham {
770 status = "okay";
771};
99919e5e
MG		 772
773&aes {
774 status = "okay";
775};
f80ecaf5
RQ		 776
777&dcan1 {
778 status = "disabled"; /* Enable only if Profile 1 is selected */
779 pinctrl-names = "default";
780 pinctrl-0 = <&dcan1_pins_default>;
781};
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