]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - arch/arm64/Kconfig
arm64: atomic64_dec_if_positive: fix incorrect branch condition
[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / Kconfig
CommitLineData
8c2c3df3
CM
1config ARM64
2 def_bool y
b6197b93 3 select ACPI_CCA_REQUIRED if ACPI
d8f4f161 4 select ACPI_GENERIC_GSI if ACPI
6933de0c 5 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8c2c3df3 6 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
2b68f6ca 7 select ARCH_HAS_ELF_RANDOMIZE
957e3fac 8 select ARCH_HAS_GCOV_PROFILE_ALL
308c09f1 9 select ARCH_HAS_SG_CHAIN
1f85008e 10 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
c63c8700 11 select ARCH_USE_CMPXCHG_LOCKREF
4badad35 12 select ARCH_SUPPORTS_ATOMIC_RMW
9170100e 13 select ARCH_WANT_OPTIONAL_GPIOLIB
6212a512 14 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
b6f35981 15 select ARCH_WANT_FRAME_POINTERS
25c92a37 16 select ARM_AMBA
1aee5d7a 17 select ARM_ARCH_TIMER
c4188edc 18 select ARM_GIC
875cbf3e 19 select AUDIT_ARCH_COMPAT_GENERIC
853a33ce 20 select ARM_GIC_V2M if PCI_MSI
021f6537 21 select ARM_GIC_V3
19812729 22 select ARM_GIC_V3_ITS if PCI_MSI
adace895 23 select BUILDTIME_EXTABLE_SORT
db2789b5 24 select CLONE_BACKWARDS
7ca2ef33 25 select COMMON_CLK
166936ba 26 select CPU_PM if (SUSPEND || CPU_IDLE)
7bc13fd3 27 select DCACHE_WORD_ACCESS
ef37566c 28 select EDAC_SUPPORT
d4932f9e 29 select GENERIC_ALLOCATOR
8c2c3df3 30 select GENERIC_CLOCKEVENTS
4b3dc967 31 select GENERIC_CLOCKEVENTS_BROADCAST
3be1a5c4 32 select GENERIC_CPU_AUTOPROBE
bf4b558e 33 select GENERIC_EARLY_IOREMAP
8c2c3df3
CM
34 select GENERIC_IRQ_PROBE
35 select GENERIC_IRQ_SHOW
6544e67b 36 select GENERIC_IRQ_SHOW_LEVEL
cb61f676 37 select GENERIC_PCI_IOMAP
65cd4f6c 38 select GENERIC_SCHED_CLOCK
8c2c3df3 39 select GENERIC_SMP_IDLE_THREAD
12a0ef7b
WD
40 select GENERIC_STRNCPY_FROM_USER
41 select GENERIC_STRNLEN_USER
8c2c3df3 42 select GENERIC_TIME_VSYSCALL
a1ddc74a 43 select HANDLE_DOMAIN_IRQ
8c2c3df3 44 select HARDIRQS_SW_RESEND
5284e1b4 45 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
875cbf3e 46 select HAVE_ARCH_AUDITSYSCALL
8e7a4cef 47 select HAVE_ARCH_BITREVERSE
9732cafd 48 select HAVE_ARCH_JUMP_LABEL
9529247d 49 select HAVE_ARCH_KGDB
a1ae65b2 50 select HAVE_ARCH_SECCOMP_FILTER
8c2c3df3 51 select HAVE_ARCH_TRACEHOOK
e54bcde3 52 select HAVE_BPF_JIT
af64d2aa 53 select HAVE_C_RECORDMCOUNT
c0c264ae 54 select HAVE_CC_STACKPROTECTOR
5284e1b4 55 select HAVE_CMPXCHG_DOUBLE
9b2a60c4 56 select HAVE_DEBUG_BUGVERBOSE
b69ec42b 57 select HAVE_DEBUG_KMEMLEAK
8c2c3df3
CM
58 select HAVE_DMA_API_DEBUG
59 select HAVE_DMA_ATTRS
6ac2104d 60 select HAVE_DMA_CONTIGUOUS
bd7d38db 61 select HAVE_DYNAMIC_FTRACE
50afc33a 62 select HAVE_EFFICIENT_UNALIGNED_ACCESS
af64d2aa 63 select HAVE_FTRACE_MCOUNT_RECORD
819e50e2
AT
64 select HAVE_FUNCTION_TRACER
65 select HAVE_FUNCTION_GRAPH_TRACER
8c2c3df3 66 select HAVE_GENERIC_DMA_COHERENT
8c2c3df3 67 select HAVE_HW_BREAKPOINT if PERF_EVENTS
8c2c3df3 68 select HAVE_MEMBLOCK
55834a77 69 select HAVE_PATA_PLATFORM
8c2c3df3 70 select HAVE_PERF_EVENTS
2ee0d7fd
JP
71 select HAVE_PERF_REGS
72 select HAVE_PERF_USER_STACK_DUMP
5e5f6dc1 73 select HAVE_RCU_TABLE_FREE
055b1212 74 select HAVE_SYSCALL_TRACEPOINTS
8c2c3df3 75 select IRQ_DOMAIN
e8557d1f 76 select IRQ_FORCED_THREADING
fea2acaa 77 select MODULES_USE_ELF_RELA
8c2c3df3
CM
78 select NO_BOOTMEM
79 select OF
80 select OF_EARLY_FLATTREE
9bf14b7c 81 select OF_RESERVED_MEM
8c2c3df3 82 select PERF_USE_VMALLOC
aa1e8ec1
CM
83 select POWER_RESET
84 select POWER_SUPPLY
8c2c3df3
CM
85 select RTC_LIB
86 select SPARSE_IRQ
7ac57a89 87 select SYSCTL_EXCEPTION_TRACE
6c81fe79 88 select HAVE_CONTEXT_TRACKING
8c2c3df3
CM
89 help
90 ARM 64-bit (AArch64) Linux support.
91
92config 64BIT
93 def_bool y
94
95config ARCH_PHYS_ADDR_T_64BIT
96 def_bool y
97
98config MMU
99 def_bool y
100
ce816fa8 101config NO_IOPORT_MAP
d1e6dc91 102 def_bool y if !PCI
8c2c3df3
CM
103
104config STACKTRACE_SUPPORT
105 def_bool y
106
107config LOCKDEP_SUPPORT
108 def_bool y
109
110config TRACE_IRQFLAGS_SUPPORT
111 def_bool y
112
c209f799 113config RWSEM_XCHGADD_ALGORITHM
8c2c3df3
CM
114 def_bool y
115
9fb7410f
DM
116config GENERIC_BUG
117 def_bool y
118 depends on BUG
119
120config GENERIC_BUG_RELATIVE_POINTERS
121 def_bool y
122 depends on GENERIC_BUG
123
8c2c3df3
CM
124config GENERIC_HWEIGHT
125 def_bool y
126
127config GENERIC_CSUM
128 def_bool y
129
130config GENERIC_CALIBRATE_DELAY
131 def_bool y
132
19e7640d 133config ZONE_DMA
8c2c3df3
CM
134 def_bool y
135
29e56940
SC
136config HAVE_GENERIC_RCU_GUP
137 def_bool y
138
8c2c3df3
CM
139config ARCH_DMA_ADDR_T_64BIT
140 def_bool y
141
142config NEED_DMA_MAP_STATE
143 def_bool y
144
145config NEED_SG_DMA_LENGTH
146 def_bool y
147
4b3dc967
WD
148config SMP
149 def_bool y
150
8c2c3df3
CM
151config SWIOTLB
152 def_bool y
153
154config IOMMU_HELPER
155 def_bool SWIOTLB
156
4cfb3613
AB
157config KERNEL_MODE_NEON
158 def_bool y
159
92cc15fc
RH
160config FIX_EARLYCON_MEM
161 def_bool y
162
9f25e6ad
KS
163config PGTABLE_LEVELS
164 int
165 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
166 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
167 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
168 default 4 if ARM64_4K_PAGES && ARM64_VA_BITS_48
169
8c2c3df3
CM
170source "init/Kconfig"
171
172source "kernel/Kconfig.freezer"
173
1ae90e79
CM
174menu "Platform selection"
175
6f56eef1
AA
176config ARCH_EXYNOS
177 bool
178 help
179 This enables support for Samsung Exynos SoC family
180
181config ARCH_EXYNOS7
182 bool "ARMv8 based Samsung Exynos7"
183 select ARCH_EXYNOS
184 select COMMON_CLK_SAMSUNG
185 select HAVE_S3C2410_WATCHDOG if WATCHDOG
186 select HAVE_S3C_RTC if RTC_CLASS
187 select PINCTRL
188 select PINCTRL_EXYNOS
189
190 help
191 This enables support for Samsung Exynos7 SoC family
192
5118a6a3
OJ
193config ARCH_FSL_LS2085A
194 bool "Freescale LS2085A SOC"
195 help
196 This enables support for Freescale LS2085A SOC.
197
85fe946e
BW
198config ARCH_HISI
199 bool "Hisilicon SoC Family"
200 help
201 This enables support for Hisilicon ARMv8 SoC family
202
4727a6f6
EH
203config ARCH_MEDIATEK
204 bool "Mediatek MT65xx & MT81xx ARMv8 SoC"
205 select ARM_GIC
0a233cdf 206 select PINCTRL
4727a6f6
EH
207 help
208 Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
209
d7f64a44
AK
210config ARCH_QCOM
211 bool "Qualcomm Platforms"
212 select PINCTRL
213 help
214 This enables support for the ARMv8 based Qualcomm chipsets.
215
41904360
SS
216config ARCH_SEATTLE
217 bool "AMD Seattle SoC Family"
218 help
219 This enables support for AMD Seattle SOC Family
220
d035fdfa
PW
221config ARCH_TEGRA
222 bool "NVIDIA Tegra SoC Family"
223 select ARCH_HAS_RESET_CONTROLLER
224 select ARCH_REQUIRE_GPIOLIB
225 select CLKDEV_LOOKUP
226 select CLKSRC_MMIO
227 select CLKSRC_OF
228 select GENERIC_CLOCKEVENTS
229 select HAVE_CLK
d035fdfa
PW
230 select PINCTRL
231 select RESET_CONTROLLER
232 help
233 This enables support for the NVIDIA Tegra SoC family.
234
235config ARCH_TEGRA_132_SOC
236 bool "NVIDIA Tegra132 SoC"
237 depends on ARCH_TEGRA
238 select PINCTRL_TEGRA124
d035fdfa
PW
239 select USB_ULPI if USB_PHY
240 select USB_ULPI_VIEWPORT if USB_PHY
241 help
242 Enable support for NVIDIA Tegra132 SoC, based on the Denver
243 ARMv8 CPU. The Tegra132 SoC is similar to the Tegra124 SoC,
244 but contains an NVIDIA Denver CPU complex in place of
245 Tegra124's "4+1" Cortex-A15 CPU complex.
246
c4bb7995
ZZ
247config ARCH_SPRD
248 bool "Spreadtrum SoC platform"
249 help
250 Support for Spreadtrum ARM based SoCs
251
28f7420d
RMC
252config ARCH_THUNDER
253 bool "Cavium Inc. Thunder SoC Family"
254 help
255 This enables support for Cavium's Thunder Family of SoCs.
256
1ae90e79
CM
257config ARCH_VEXPRESS
258 bool "ARMv8 software model (Versatile Express)"
259 select ARCH_REQUIRE_GPIOLIB
260 select COMMON_CLK_VERSATILE
aa1e8ec1 261 select POWER_RESET_VEXPRESS
1ae90e79
CM
262 select VEXPRESS_CONFIG
263 help
264 This enables support for the ARMv8 software model (Versatile
265 Express).
8c2c3df3 266
15942853
VK
267config ARCH_XGENE
268 bool "AppliedMicro X-Gene SOC Family"
269 help
270 This enables support for AppliedMicro X-Gene SOC Family
271
5d1b79d2
MS
272config ARCH_ZYNQMP
273 bool "Xilinx ZynqMP Family"
274 help
275 This enables support for Xilinx ZynqMP Family
276
8c2c3df3
CM
277endmenu
278
279menu "Bus support"
280
d1e6dc91
LD
281config PCI
282 bool "PCI support"
283 help
284 This feature enables support for PCI bus system. If you say Y
285 here, the kernel will include drivers and infrastructure code
286 to support PCI bus devices.
287
288config PCI_DOMAINS
289 def_bool PCI
290
291config PCI_DOMAINS_GENERIC
292 def_bool PCI
293
294config PCI_SYSCALL
295 def_bool PCI
296
297source "drivers/pci/Kconfig"
298source "drivers/pci/pcie/Kconfig"
299source "drivers/pci/hotplug/Kconfig"
300
8c2c3df3
CM
301endmenu
302
303menu "Kernel Features"
304
c0a01b84
AP
305menu "ARM errata workarounds via the alternatives framework"
306
307config ARM64_ERRATUM_826319
308 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
309 default y
310 help
311 This option adds an alternative code sequence to work around ARM
312 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
313 AXI master interface and an L2 cache.
314
315 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
316 and is unable to accept a certain write via this interface, it will
317 not progress on read data presented on the read data channel and the
318 system can deadlock.
319
320 The workaround promotes data cache clean instructions to
321 data cache clean-and-invalidate.
322 Please note that this does not necessarily enable the workaround,
323 as it depends on the alternative framework, which will only patch
324 the kernel if an affected CPU is detected.
325
326 If unsure, say Y.
327
328config ARM64_ERRATUM_827319
329 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
330 default y
331 help
332 This option adds an alternative code sequence to work around ARM
333 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
334 master interface and an L2 cache.
335
336 Under certain conditions this erratum can cause a clean line eviction
337 to occur at the same time as another transaction to the same address
338 on the AMBA 5 CHI interface, which can cause data corruption if the
339 interconnect reorders the two transactions.
340
341 The workaround promotes data cache clean instructions to
342 data cache clean-and-invalidate.
343 Please note that this does not necessarily enable the workaround,
344 as it depends on the alternative framework, which will only patch
345 the kernel if an affected CPU is detected.
346
347 If unsure, say Y.
348
349config ARM64_ERRATUM_824069
350 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
351 default y
352 help
353 This option adds an alternative code sequence to work around ARM
354 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
355 to a coherent interconnect.
356
357 If a Cortex-A53 processor is executing a store or prefetch for
358 write instruction at the same time as a processor in another
359 cluster is executing a cache maintenance operation to the same
360 address, then this erratum might cause a clean cache line to be
361 incorrectly marked as dirty.
362
363 The workaround promotes data cache clean instructions to
364 data cache clean-and-invalidate.
365 Please note that this option does not necessarily enable the
366 workaround, as it depends on the alternative framework, which will
367 only patch the kernel if an affected CPU is detected.
368
369 If unsure, say Y.
370
371config ARM64_ERRATUM_819472
372 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
373 default y
374 help
375 This option adds an alternative code sequence to work around ARM
376 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
377 present when it is connected to a coherent interconnect.
378
379 If the processor is executing a load and store exclusive sequence at
380 the same time as a processor in another cluster is executing a cache
381 maintenance operation to the same address, then this erratum might
382 cause data corruption.
383
384 The workaround promotes data cache clean instructions to
385 data cache clean-and-invalidate.
386 Please note that this does not necessarily enable the workaround,
387 as it depends on the alternative framework, which will only patch
388 the kernel if an affected CPU is detected.
389
390 If unsure, say Y.
391
392config ARM64_ERRATUM_832075
393 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
394 default y
395 help
396 This option adds an alternative code sequence to work around ARM
397 erratum 832075 on Cortex-A57 parts up to r1p2.
398
399 Affected Cortex-A57 parts might deadlock when exclusive load/store
400 instructions to Write-Back memory are mixed with Device loads.
401
402 The workaround is to promote device loads to use Load-Acquire
403 semantics.
404 Please note that this does not necessarily enable the workaround,
405 as it depends on the alternative framework, which will only patch
406 the kernel if an affected CPU is detected.
407
408 If unsure, say Y.
409
905e8c5d
WD
410config ARM64_ERRATUM_845719
411 bool "Cortex-A53: 845719: a load might read incorrect data"
412 depends on COMPAT
413 default y
414 help
415 This option adds an alternative code sequence to work around ARM
416 erratum 845719 on Cortex-A53 parts up to r0p4.
417
418 When running a compat (AArch32) userspace on an affected Cortex-A53
419 part, a load at EL0 from a virtual address that matches the bottom 32
420 bits of the virtual address used by a recent load at (AArch64) EL1
421 might return incorrect data.
422
423 The workaround is to write the contextidr_el1 register on exception
424 return to a 32-bit task.
425 Please note that this does not necessarily enable the workaround,
426 as it depends on the alternative framework, which will only patch
427 the kernel if an affected CPU is detected.
428
429 If unsure, say Y.
430
c0a01b84
AP
431endmenu
432
433
e41ceed0
JL
434choice
435 prompt "Page size"
436 default ARM64_4K_PAGES
437 help
438 Page size (translation granule) configuration.
439
440config ARM64_4K_PAGES
441 bool "4KB"
442 help
443 This feature enables 4KB pages support.
444
8c2c3df3 445config ARM64_64K_PAGES
e41ceed0 446 bool "64KB"
8c2c3df3
CM
447 help
448 This feature enables 64KB pages support (4KB by default)
449 allowing only two levels of page tables and faster TLB
450 look-up. AArch32 emulation is not available when this feature
451 is enabled.
452
e41ceed0
JL
453endchoice
454
455choice
456 prompt "Virtual address space size"
457 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
458 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
459 help
460 Allows choosing one of multiple possible virtual address
461 space sizes. The level of translation table is determined by
462 a combination of page size and virtual address space size.
463
464config ARM64_VA_BITS_39
465 bool "39-bit"
466 depends on ARM64_4K_PAGES
467
468config ARM64_VA_BITS_42
469 bool "42-bit"
470 depends on ARM64_64K_PAGES
471
c79b954b
JL
472config ARM64_VA_BITS_48
473 bool "48-bit"
c79b954b 474
e41ceed0
JL
475endchoice
476
477config ARM64_VA_BITS
478 int
479 default 39 if ARM64_VA_BITS_39
480 default 42 if ARM64_VA_BITS_42
c79b954b 481 default 48 if ARM64_VA_BITS_48
e41ceed0 482
2f4b829c
CM
483config ARM64_HW_AFDBM
484 bool "Support for hardware updates of the Access and Dirty page flags"
485 default y
486 help
487 The ARMv8.1 architecture extensions introduce support for
488 hardware updates of the access and dirty information in page
489 table entries. When enabled in TCR_EL1 (HA and HD bits) on
490 capable processors, accesses to pages with PTE_AF cleared will
491 set this bit instead of raising an access flag fault.
492 Similarly, writes to read-only pages with the DBM bit set will
493 clear the read-only bit (AP[2]) instead of raising a
494 permission fault.
495
496 Kernels built with this configuration option enabled continue
497 to work on pre-ARMv8.1 hardware and the performance impact is
498 minimal. If unsure, say Y.
499
a872013d
WD
500config CPU_BIG_ENDIAN
501 bool "Build big-endian kernel"
502 help
503 Say Y if you plan on running a kernel in big-endian mode.
504
f6e763b9
MB
505config SCHED_MC
506 bool "Multi-core scheduler support"
f6e763b9
MB
507 help
508 Multi-core scheduler support improves the CPU scheduler's decision
509 making when dealing with multi-core CPU chips at a cost of slightly
510 increased overhead in some places. If unsure say N here.
511
512config SCHED_SMT
513 bool "SMT scheduler support"
f6e763b9
MB
514 help
515 Improves the CPU scheduler's decision making when dealing with
516 MultiThreading at a cost of slightly increased overhead in some
517 places. If unsure say N here.
518
8c2c3df3 519config NR_CPUS
62aa9655
GK
520 int "Maximum number of CPUs (2-4096)"
521 range 2 4096
15942853 522 # These have to remain sorted largest to smallest
e3672649 523 default "64"
8c2c3df3 524
9327e2c6
MR
525config HOTPLUG_CPU
526 bool "Support for hot-pluggable CPUs"
9327e2c6
MR
527 help
528 Say Y here to experiment with turning CPUs off and on. CPUs
529 can be controlled through /sys/devices/system/cpu.
530
8c2c3df3
CM
531source kernel/Kconfig.preempt
532
533config HZ
534 int
535 default 100
536
537config ARCH_HAS_HOLES_MEMORYMODEL
538 def_bool y if SPARSEMEM
539
540config ARCH_SPARSEMEM_ENABLE
541 def_bool y
542 select SPARSEMEM_VMEMMAP_ENABLE
543
544config ARCH_SPARSEMEM_DEFAULT
545 def_bool ARCH_SPARSEMEM_ENABLE
546
547config ARCH_SELECT_MEMORY_MODEL
548 def_bool ARCH_SPARSEMEM_ENABLE
549
550config HAVE_ARCH_PFN_VALID
551 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
552
553config HW_PERF_EVENTS
554 bool "Enable hardware performance counter support for perf events"
555 depends on PERF_EVENTS
556 default y
557 help
558 Enable hardware performance counter support for perf events. If
559 disabled, perf events will use software events only.
560
084bd298
SC
561config SYS_SUPPORTS_HUGETLBFS
562 def_bool y
563
564config ARCH_WANT_GENERAL_HUGETLB
565 def_bool y
566
567config ARCH_WANT_HUGE_PMD_SHARE
568 def_bool y if !ARM64_64K_PAGES
569
af074848
SC
570config HAVE_ARCH_TRANSPARENT_HUGEPAGE
571 def_bool y
572
a41dc0e8
CM
573config ARCH_HAS_CACHE_LINE_SIZE
574 def_bool y
575
8c2c3df3
CM
576source "mm/Kconfig"
577
a1ae65b2
AT
578config SECCOMP
579 bool "Enable seccomp to safely compute untrusted bytecode"
580 ---help---
581 This kernel feature is useful for number crunching applications
582 that may need to compute untrusted bytecode during their
583 execution. By using pipes or other transports made available to
584 the process as file descriptors supporting the read/write
585 syscalls, it's possible to isolate those applications in
586 their own address space using seccomp. Once seccomp is
587 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
588 and the task is only allowed to execute a few safe syscalls
589 defined by each seccomp mode.
590
aa42aa13
SS
591config XEN_DOM0
592 def_bool y
593 depends on XEN
594
595config XEN
c2ba1f7d 596 bool "Xen guest support on ARM64"
aa42aa13 597 depends on ARM64 && OF
83862ccf 598 select SWIOTLB_XEN
aa42aa13
SS
599 help
600 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
601
d03bb145
SC
602config FORCE_MAX_ZONEORDER
603 int
604 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
605 default "11"
606
338d4f49
JM
607config ARM64_PAN
608 bool "Enable support for Privileged Access Never (PAN)"
609 default y
610 help
611 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
612 prevents the kernel or hypervisor from accessing user-space (EL0)
613 memory directly.
614
615 Choosing this option will cause any unprotected (not using
616 copy_to_user et al) memory access to fail with a permission fault.
617
618 The feature is detected at runtime, and will remain as a 'nop'
619 instruction if the cpu does not implement the feature.
620
c0385b24
WD
621config ARM64_LSE_ATOMICS
622 bool "ARMv8.1 atomic instructions"
623 help
624 As part of the Large System Extensions, ARMv8.1 introduces new
625 atomic instructions that are designed specifically to scale in
626 very large systems.
627
628 Say Y here to make use of these instructions for the in-kernel
629 atomic routines. This incurs a small overhead on CPUs that do
630 not support these instructions and requires the kernel to be
631 built with binutils >= 2.25.
632
1b907f46
WD
633menuconfig ARMV8_DEPRECATED
634 bool "Emulate deprecated/obsolete ARMv8 instructions"
635 depends on COMPAT
636 help
637 Legacy software support may require certain instructions
638 that have been deprecated or obsoleted in the architecture.
639
640 Enable this config to enable selective emulation of these
641 features.
642
643 If unsure, say Y
644
645if ARMV8_DEPRECATED
646
647config SWP_EMULATION
648 bool "Emulate SWP/SWPB instructions"
649 help
650 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
651 they are always undefined. Say Y here to enable software
652 emulation of these instructions for userspace using LDXR/STXR.
653
654 In some older versions of glibc [<=2.8] SWP is used during futex
655 trylock() operations with the assumption that the code will not
656 be preempted. This invalid assumption may be more likely to fail
657 with SWP emulation enabled, leading to deadlock of the user
658 application.
659
660 NOTE: when accessing uncached shared regions, LDXR/STXR rely
661 on an external transaction monitoring block called a global
662 monitor to maintain update atomicity. If your system does not
663 implement a global monitor, this option can cause programs that
664 perform SWP operations to uncached memory to deadlock.
665
666 If unsure, say Y
667
668config CP15_BARRIER_EMULATION
669 bool "Emulate CP15 Barrier instructions"
670 help
671 The CP15 barrier instructions - CP15ISB, CP15DSB, and
672 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
673 strongly recommended to use the ISB, DSB, and DMB
674 instructions instead.
675
676 Say Y here to enable software emulation of these
677 instructions for AArch32 userspace code. When this option is
678 enabled, CP15 barrier usage is traced which can help
679 identify software that needs updating.
680
681 If unsure, say Y
682
2d888f48
SP
683config SETEND_EMULATION
684 bool "Emulate SETEND instruction"
685 help
686 The SETEND instruction alters the data-endianness of the
687 AArch32 EL0, and is deprecated in ARMv8.
688
689 Say Y here to enable software emulation of the instruction
690 for AArch32 userspace code.
691
692 Note: All the cpus on the system must have mixed endian support at EL0
693 for this feature to be enabled. If a new CPU - which doesn't support mixed
694 endian - is hotplugged in after this feature has been enabled, there could
695 be unexpected results in the applications.
696
697 If unsure, say Y
1b907f46
WD
698endif
699
8c2c3df3
CM
700endmenu
701
702menu "Boot options"
703
704config CMDLINE
705 string "Default kernel command string"
706 default ""
707 help
708 Provide a set of default command-line options at build time by
709 entering them here. As a minimum, you should specify the the
710 root device (e.g. root=/dev/nfs).
711
712config CMDLINE_FORCE
713 bool "Always use the default kernel command string"
714 help
715 Always use the default kernel command string, even if the boot
716 loader passes other arguments to the kernel.
717 This is useful if you cannot or don't want to change the
718 command-line options your boot loader passes to the kernel.
719
f4f75ad5
AB
720config EFI_STUB
721 bool
722
f84d0275
MS
723config EFI
724 bool "UEFI runtime support"
725 depends on OF && !CPU_BIG_ENDIAN
726 select LIBFDT
727 select UCS2_STRING
728 select EFI_PARAMS_FROM_FDT
e15dd494 729 select EFI_RUNTIME_WRAPPERS
f4f75ad5
AB
730 select EFI_STUB
731 select EFI_ARMSTUB
f84d0275
MS
732 default y
733 help
734 This option provides support for runtime services provided
735 by UEFI firmware (such as non-volatile variables, realtime
3c7f2550
MS
736 clock, and platform reset). A UEFI stub is also provided to
737 allow the kernel to be booted as an EFI application. This
738 is only useful on systems that have UEFI firmware.
f84d0275 739
d1ae8c00
YL
740config DMI
741 bool "Enable support for SMBIOS (DMI) tables"
742 depends on EFI
743 default y
744 help
745 This enables SMBIOS/DMI feature for systems.
746
747 This option is only useful on systems that have UEFI firmware.
748 However, even with this option, the resultant kernel should
749 continue to boot on existing non-UEFI platforms.
750
8c2c3df3
CM
751endmenu
752
753menu "Userspace binary formats"
754
755source "fs/Kconfig.binfmt"
756
757config COMPAT
758 bool "Kernel support for 32-bit EL0"
a8fcd8b1 759 depends on !ARM64_64K_PAGES || EXPERT
8c2c3df3 760 select COMPAT_BINFMT_ELF
af1839eb 761 select HAVE_UID16
84b9e9b4 762 select OLD_SIGSUSPEND3
51682036 763 select COMPAT_OLD_SIGACTION
8c2c3df3
CM
764 help
765 This option enables support for a 32-bit EL0 running under a 64-bit
766 kernel at EL1. AArch32-specific components such as system calls,
767 the user helper functions, VFP support and the ptrace interface are
768 handled appropriately by the kernel.
769
a8fcd8b1
AG
770 If you also enabled CONFIG_ARM64_64K_PAGES, please be aware that you
771 will only be able to execute AArch32 binaries that were compiled with
772 64k aligned segments.
773
8c2c3df3
CM
774 If you want to execute 32-bit userspace applications, say Y.
775
776config SYSVIPC_COMPAT
777 def_bool y
778 depends on COMPAT && SYSVIPC
779
780endmenu
781
166936ba
LP
782menu "Power management options"
783
784source "kernel/power/Kconfig"
785
786config ARCH_SUSPEND_POSSIBLE
787 def_bool y
788
166936ba
LP
789endmenu
790
1307220d
LP
791menu "CPU Power Management"
792
793source "drivers/cpuidle/Kconfig"
794
52e7e816
RH
795source "drivers/cpufreq/Kconfig"
796
797endmenu
798
8c2c3df3
CM
799source "net/Kconfig"
800
801source "drivers/Kconfig"
802
f84d0275
MS
803source "drivers/firmware/Kconfig"
804
b6a02173
GG
805source "drivers/acpi/Kconfig"
806
8c2c3df3
CM
807source "fs/Kconfig"
808
c3eb5b14
MZ
809source "arch/arm64/kvm/Kconfig"
810
8c2c3df3
CM
811source "arch/arm64/Kconfig.debug"
812
813source "security/Kconfig"
814
815source "crypto/Kconfig"
2c98833a
AB
816if CRYPTO
817source "arch/arm64/crypto/Kconfig"
818endif
8c2c3df3
CM
819
820source "lib/Kconfig"