[mirror_ubuntu-zesty-kernel.git] / arch / arm64 / kvm / hyp / vgic-v3-sr.c

/*
 * Copyright (C) 2012-2015 - ARM Ltd
 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/compiler.h>
#include <linux/irqchip/arm-gic-v3.h>
#include <linux/kvm_host.h>

#include <asm/kvm_hyp.h>

#define vtr_to_max_lr_idx(v)		((v) & 0xf)
#define vtr_to_nr_pri_bits(v)		(((u32)(v) >> 29) + 1)

#define read_gicreg(r)							\
	({								\
		u64 reg;						\
		asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg));	\
		reg;							\
	})

#define write_gicreg(v,r)						\
	do {								\
		u64 __val = (v);					\
		asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
	} while (0)

static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
{
	switch (lr & 0xf) {
	case 0:
		return read_gicreg(ICH_LR0_EL2);
	case 1:
		return read_gicreg(ICH_LR1_EL2);
	case 2:
		return read_gicreg(ICH_LR2_EL2);
	case 3:
		return read_gicreg(ICH_LR3_EL2);
	case 4:
		return read_gicreg(ICH_LR4_EL2);
	case 5:
		return read_gicreg(ICH_LR5_EL2);
	case 6:
		return read_gicreg(ICH_LR6_EL2);
	case 7:
		return read_gicreg(ICH_LR7_EL2);
	case 8:
		return read_gicreg(ICH_LR8_EL2);
	case 9:
		return read_gicreg(ICH_LR9_EL2);
	case 10:
		return read_gicreg(ICH_LR10_EL2);
	case 11:
		return read_gicreg(ICH_LR11_EL2);
	case 12:
		return read_gicreg(ICH_LR12_EL2);
	case 13:
		return read_gicreg(ICH_LR13_EL2);
	case 14:
		return read_gicreg(ICH_LR14_EL2);
	case 15:
		return read_gicreg(ICH_LR15_EL2);
	}

	unreachable();
}

static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
{
	switch (lr & 0xf) {
	case 0:
		write_gicreg(val, ICH_LR0_EL2);
		break;
	case 1:
		write_gicreg(val, ICH_LR1_EL2);
		break;
	case 2:
		write_gicreg(val, ICH_LR2_EL2);
		break;
	case 3:
		write_gicreg(val, ICH_LR3_EL2);
		break;
	case 4:
		write_gicreg(val, ICH_LR4_EL2);
		break;
	case 5:
		write_gicreg(val, ICH_LR5_EL2);
		break;
	case 6:
		write_gicreg(val, ICH_LR6_EL2);
		break;
	case 7:
		write_gicreg(val, ICH_LR7_EL2);
		break;
	case 8:
		write_gicreg(val, ICH_LR8_EL2);
		break;
	case 9:
		write_gicreg(val, ICH_LR9_EL2);
		break;
	case 10:
		write_gicreg(val, ICH_LR10_EL2);
		break;
	case 11:
		write_gicreg(val, ICH_LR11_EL2);
		break;
	case 12:
		write_gicreg(val, ICH_LR12_EL2);
		break;
	case 13:
		write_gicreg(val, ICH_LR13_EL2);
		break;
	case 14:
		write_gicreg(val, ICH_LR14_EL2);
		break;
	case 15:
		write_gicreg(val, ICH_LR15_EL2);
		break;
	}
}

static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	int i;
	bool expect_mi;

	expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);

	for (i = 0; i < nr_lr; i++) {
		if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
				continue;

		expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
			      (cpu_if->vgic_lr[i] & ICH_LR_EOI));
	}

	if (expect_mi) {
		cpu_if->vgic_misr  = read_gicreg(ICH_MISR_EL2);

		if (cpu_if->vgic_misr & ICH_MISR_EOI)
			cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
		else
			cpu_if->vgic_eisr = 0;
	} else {
		cpu_if->vgic_misr = 0;
		cpu_if->vgic_eisr = 0;
	}
}

void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u64 val;

	/*
	 * Make sure stores to the GIC via the memory mapped interface
	 * are now visible to the system register interface.
	 */
	dsb(st);

	cpu_if->vgic_vmcr  = read_gicreg(ICH_VMCR_EL2);

	if (vcpu->arch.vgic_cpu.live_lrs) {
		int i;
		u32 max_lr_idx, nr_pri_bits;

		cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);

		write_gicreg(0, ICH_HCR_EL2);
		val = read_gicreg(ICH_VTR_EL2);
		max_lr_idx = vtr_to_max_lr_idx(val);
		nr_pri_bits = vtr_to_nr_pri_bits(val);

		save_maint_int_state(vcpu, max_lr_idx + 1);

		for (i = 0; i <= max_lr_idx; i++) {
			if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
				continue;

			if (cpu_if->vgic_elrsr & (1 << i)) {
				cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
				continue;
			}

			cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
		}

		switch (nr_pri_bits) {
		case 7:
			cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
			cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
		case 6:
			cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
		default:
			cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
		}

		switch (nr_pri_bits) {
		case 7:
			cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
			cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
		case 6:
			cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
		default:
			cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
		}

		vcpu->arch.vgic_cpu.live_lrs = 0;
	} else {
		cpu_if->vgic_misr  = 0;
		cpu_if->vgic_eisr  = 0;
		cpu_if->vgic_elrsr = 0xffff;
		cpu_if->vgic_ap0r[0] = 0;
		cpu_if->vgic_ap0r[1] = 0;
		cpu_if->vgic_ap0r[2] = 0;
		cpu_if->vgic_ap0r[3] = 0;
		cpu_if->vgic_ap1r[0] = 0;
		cpu_if->vgic_ap1r[1] = 0;
		cpu_if->vgic_ap1r[2] = 0;
		cpu_if->vgic_ap1r[3] = 0;
	}

	val = read_gicreg(ICC_SRE_EL2);
	write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
	isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
	write_gicreg(1, ICC_SRE_EL1);
}

void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
{
	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	u64 val;
	u32 max_lr_idx, nr_pri_bits;
	u16 live_lrs = 0;
	int i;

	/*
	 * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
	 * Group0 interrupt (as generated in GICv2 mode) to be
	 * delivered as a FIQ to the guest, with potentially fatal
	 * consequences. So we must make sure that ICC_SRE_EL1 has
	 * been actually programmed with the value we want before
	 * starting to mess with the rest of the GIC.
	 */
	write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
	isb();

	val = read_gicreg(ICH_VTR_EL2);
	max_lr_idx = vtr_to_max_lr_idx(val);
	nr_pri_bits = vtr_to_nr_pri_bits(val);

	for (i = 0; i <= max_lr_idx; i++) {
		if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
			live_lrs |= (1 << i);
	}

	write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);

	if (live_lrs) {
		write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);

		switch (nr_pri_bits) {
		case 7:
			write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
			write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
		case 6:
			write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
		default:
			write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
		}

		switch (nr_pri_bits) {
		case 7:
			write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
			write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
		case 6:
			write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
		default:
			write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
		}

		for (i = 0; i <= max_lr_idx; i++) {
			val = 0;

			if (live_lrs & (1 << i))
				val = cpu_if->vgic_lr[i];

			__gic_v3_set_lr(val, i);
		}
	}

	/*
	 * Ensures that the above will have reached the
	 * (re)distributors. This ensure the guest will read the
	 * correct values from the memory-mapped interface.
	 */
	isb();
	dsb(sy);
	vcpu->arch.vgic_cpu.live_lrs = live_lrs;

	/*
	 * Prevent the guest from touching the GIC system registers if
	 * SRE isn't enabled for GICv3 emulation.
	 */
	if (!cpu_if->vgic_sre) {
		write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
			     ICC_SRE_EL2);
	}
}

static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
{
	return read_gicreg(ICH_VTR_EL2);
}

__alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void);
Commit	Line	Data
f68d2b1b MZ	1	/*
	2	* Copyright (C) 2012-2015 - ARM Ltd
	3	* Author: Marc Zyngier <marc.zyngier@arm.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#include <linux/compiler.h>
	19	#include <linux/irqchip/arm-gic-v3.h>
	20	#include <linux/kvm_host.h>
	21
13720a56	22	#include <asm/kvm_hyp.h>
f68d2b1b MZ	23
	24	#define vtr_to_max_lr_idx(v) ((v) & 0xf)
	25	#define vtr_to_nr_pri_bits(v) (((u32)(v) >> 29) + 1)
	26
	27	#define read_gicreg(r) \
	28	({ \
	29	u64 reg; \
	30	asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
	31	reg; \
	32	})
	33
	34	#define write_gicreg(v,r) \
	35	do { \
	36	u64 __val = (v); \
	37	asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
	38	} while (0)
	39
1b8e83c0 MZ	40	static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
	41	{
	42	switch (lr & 0xf) {
	43	case 0:
	44	return read_gicreg(ICH_LR0_EL2);
	45	case 1:
	46	return read_gicreg(ICH_LR1_EL2);
	47	case 2:
	48	return read_gicreg(ICH_LR2_EL2);
	49	case 3:
	50	return read_gicreg(ICH_LR3_EL2);
	51	case 4:
	52	return read_gicreg(ICH_LR4_EL2);
	53	case 5:
	54	return read_gicreg(ICH_LR5_EL2);
	55	case 6:
	56	return read_gicreg(ICH_LR6_EL2);
	57	case 7:
	58	return read_gicreg(ICH_LR7_EL2);
	59	case 8:
	60	return read_gicreg(ICH_LR8_EL2);
	61	case 9:
	62	return read_gicreg(ICH_LR9_EL2);
	63	case 10:
	64	return read_gicreg(ICH_LR10_EL2);
	65	case 11:
	66	return read_gicreg(ICH_LR11_EL2);
	67	case 12:
	68	return read_gicreg(ICH_LR12_EL2);
	69	case 13:
	70	return read_gicreg(ICH_LR13_EL2);
	71	case 14:
	72	return read_gicreg(ICH_LR14_EL2);
	73	case 15:
	74	return read_gicreg(ICH_LR15_EL2);
	75	}
	76
	77	unreachable();
	78	}
	79
	80	static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
	81	{
	82	switch (lr & 0xf) {
	83	case 0:
	84	write_gicreg(val, ICH_LR0_EL2);
	85	break;
	86	case 1:
	87	write_gicreg(val, ICH_LR1_EL2);
	88	break;
	89	case 2:
	90	write_gicreg(val, ICH_LR2_EL2);
	91	break;
	92	case 3:
	93	write_gicreg(val, ICH_LR3_EL2);
	94	break;
	95	case 4:
	96	write_gicreg(val, ICH_LR4_EL2);
	97	break;
	98	case 5:
	99	write_gicreg(val, ICH_LR5_EL2);
	100	break;
	101	case 6:
	102	write_gicreg(val, ICH_LR6_EL2);
	103	break;
104	case 7:
105	write_gicreg(val, ICH_LR7_EL2);
106	break;
107	case 8:
108	write_gicreg(val, ICH_LR8_EL2);
109	break;
110	case 9:
111	write_gicreg(val, ICH_LR9_EL2);
112	break;
113	case 10:
114	write_gicreg(val, ICH_LR10_EL2);
115	break;
116	case 11:
117	write_gicreg(val, ICH_LR11_EL2);
118	break;
119	case 12:
120	write_gicreg(val, ICH_LR12_EL2);
121	break;
122	case 13:
123	write_gicreg(val, ICH_LR13_EL2);
124	break;
125	case 14:
126	write_gicreg(val, ICH_LR14_EL2);
127	break;
128	case 15:
129	write_gicreg(val, ICH_LR15_EL2);
130	break;
131	}
132	}
133
b4344545 MZ	134	static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr)
	135	{
	136	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	137	int i;
	138	bool expect_mi;
	139
	140	expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);
	141
	142	for (i = 0; i < nr_lr; i++) {
	143	if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
	144	continue;
	145
	146	expect_mi \|= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
	147	(cpu_if->vgic_lr[i] & ICH_LR_EOI));
	148	}
	149
	150	if (expect_mi) {
	151	cpu_if->vgic_misr = read_gicreg(ICH_MISR_EL2);
	152
	153	if (cpu_if->vgic_misr & ICH_MISR_EOI)
	154	cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
	155	else
	156	cpu_if->vgic_eisr = 0;
	157	} else {
	158	cpu_if->vgic_misr = 0;
	159	cpu_if->vgic_eisr = 0;
	160	}
	161	}
	162
f68d2b1b MZ	163	void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
	164	{
	165	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	166	u64 val;
f68d2b1b MZ	167
	168	/*
	169	* Make sure stores to the GIC via the memory mapped interface
	170	* are now visible to the system register interface.
	171	*/
	172	dsb(st);
	173
	174	cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2);
f68d2b1b	175
1b8e83c0 MZ	176	if (vcpu->arch.vgic_cpu.live_lrs) {
	177	int i;
	178	u32 max_lr_idx, nr_pri_bits;
f68d2b1b	179
1b8e83c0	180	cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
f68d2b1b	181
1b8e83c0 MZ	182	write_gicreg(0, ICH_HCR_EL2);
	183	val = read_gicreg(ICH_VTR_EL2);
	184	max_lr_idx = vtr_to_max_lr_idx(val);
	185	nr_pri_bits = vtr_to_nr_pri_bits(val);
f68d2b1b	186
b4344545 MZ	187	save_maint_int_state(vcpu, max_lr_idx + 1);
b4344545 MZ	188
1b8e83c0	189	for (i = 0; i <= max_lr_idx; i++) {
84e8b9c8 MZ	190	if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
	191	continue;
	192
	193	if (cpu_if->vgic_elrsr & (1 << i)) {
	194	cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
	195	continue;
	196	}
	197
	198	cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
1b8e83c0 MZ	199	}
	200
	201	switch (nr_pri_bits) {
	202	case 7:
	203	cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
	204	cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
	205	case 6:
	206	cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
	207	default:
	208	cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
	209	}
	210
	211	switch (nr_pri_bits) {
	212	case 7:
	213	cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
	214	cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
	215	case 6:
	216	cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
	217	default:
	218	cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
	219	}
	220
	221	vcpu->arch.vgic_cpu.live_lrs = 0;
	222	} else {
	223	cpu_if->vgic_misr = 0;
	224	cpu_if->vgic_eisr = 0;
	225	cpu_if->vgic_elrsr = 0xffff;
	226	cpu_if->vgic_ap0r[0] = 0;
	227	cpu_if->vgic_ap0r[1] = 0;
	228	cpu_if->vgic_ap0r[2] = 0;
	229	cpu_if->vgic_ap0r[3] = 0;
	230	cpu_if->vgic_ap1r[0] = 0;
	231	cpu_if->vgic_ap1r[1] = 0;
	232	cpu_if->vgic_ap1r[2] = 0;
	233	cpu_if->vgic_ap1r[3] = 0;
f68d2b1b MZ	234	}
	235
	236	val = read_gicreg(ICC_SRE_EL2);
	237	write_gicreg(val \| ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
	238	isb(); /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
	239	write_gicreg(1, ICC_SRE_EL1);
	240	}
	241
	242	void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
	243	{
	244	struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
	245	u64 val;
	246	u32 max_lr_idx, nr_pri_bits;
1b8e83c0 MZ	247	u16 live_lrs = 0;
1b8e83c0 MZ	248	int i;
f68d2b1b MZ	249
	250	/*
	251	* VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
	252	* Group0 interrupt (as generated in GICv2 mode) to be
	253	* delivered as a FIQ to the guest, with potentially fatal
	254	* consequences. So we must make sure that ICC_SRE_EL1 has
	255	* been actually programmed with the value we want before
	256	* starting to mess with the rest of the GIC.
	257	*/
	258	write_gicreg(cpu_if->vgic_sre, ICC_SRE_EL1);
	259	isb();
	260
f68d2b1b MZ	261	val = read_gicreg(ICH_VTR_EL2);
	262	max_lr_idx = vtr_to_max_lr_idx(val);
	263	nr_pri_bits = vtr_to_nr_pri_bits(val);
	264
1b8e83c0 MZ	265	for (i = 0; i <= max_lr_idx; i++) {
	266	if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
	267	live_lrs \|= (1 << i);
f68d2b1b MZ	268	}
f68d2b1b MZ	269
1b8e83c0	270	write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
fd451b90	271
1b8e83c0 MZ	272	if (live_lrs) {
	273	write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
	274
	275	switch (nr_pri_bits) {
	276	case 7:
	277	write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
	278	write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
	279	case 6:
	280	write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
	281	default:
	282	write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
	283	}
	284
	285	switch (nr_pri_bits) {
	286	case 7:
	287	write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
	288	write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
	289	case 6:
	290	write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
	291	default:
	292	write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
	293	}
	294
	295	for (i = 0; i <= max_lr_idx; i++) {
	296	val = 0;
	297
	298	if (live_lrs & (1 << i))
	299	val = cpu_if->vgic_lr[i];
	300
	301	__gic_v3_set_lr(val, i);
	302	}
f68d2b1b MZ	303	}
	304
	305	/*
	306	* Ensures that the above will have reached the
	307	* (re)distributors. This ensure the guest will read the
	308	* correct values from the memory-mapped interface.
	309	*/
	310	isb();
	311	dsb(sy);
1b8e83c0	312	vcpu->arch.vgic_cpu.live_lrs = live_lrs;
f68d2b1b MZ	313
	314	/*
	315	* Prevent the guest from touching the GIC system registers if
	316	* SRE isn't enabled for GICv3 emulation.
	317	*/
	318	if (!cpu_if->vgic_sre) {
	319	write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
	320	ICC_SRE_EL2);
	321	}
	322	}
	323
3ffa75cd	324	static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
f68d2b1b MZ	325	{
	326	return read_gicreg(ICH_VTR_EL2);
	327	}
044ac37d	328
3ffa75cd	329	__alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void);